1252068 九、發明說明： 【發明所屬之技術領域】 種在黾路板或半導體元 一種導電結構之製法，尤指一 件上形成銲墊之製造方法。 【先前技術】 抑屯子產品縮小化，已長久以來的發展趨勢，並且以往 早—功能型態的電子產品已無法再滿足消費者的需求，因 :必須：合多種功能的電子產品，如行動電話結合數位相 機+使侍打動電話具有數位相機的功能，並可將影像由行 動電話直接傳送，因此使得隨身型的電子產品不再僅有單 -使用功能。而具有多功能的電子產品之所以得結合多種 使用功能，係拜積體電路（integrated circuit)高度發展之 賜，使得電子產品可邁入多功能、高性能的研發方向。而 為滿足半導體封裝#高積集度（Integrati〇n)以及微型化 (Miniaturization)之需求，覆晶接合⑻化已成 目前的主要趨勢。 … 而覆晶接合技術之主要結構係在晶片&半導體封束件 (semiconductor package)之複數個輸出接點上各形成一連 接用的錫球⑽der ball)，得藉由該錫#以與外部電路連 接。而在晶片或半導體封裝件上形成錫球的製造方法，如 第3 A圖至第3 G圖所示之習知方法。 請參閱第3 A圖，係在一雷败^ $路板21上先形成有複數電 性連接墊211，圖式中所示之雷极 电性連接墊211即為電路板 21提供與1C晶另銲墊接著之電性連接墊。 18035 5 1252068 凊荃閱第3B圖，接著該電路板21 硬化之第一絕緣層22。 “-如可顯像 請參閱第3C圖，然後該第—絕緣層22先 (exposure)，再顯像（devel en 接塾2U上方的第一開口 221。）皁4成-位在電性連 請參閱第3D圖，再於第一絕緣層22上方廣人—μ _ 絕緣層23 ;同樣於該第二絕緣層 土 口弟— 像，以在第二絕緣層23上形成第二刻顯 口 221與第m31制在電性連接墊2 = 一開 形成一直通電性連接墊211的連貫開口 3〇。 ，而可 = 圖，之後於該連貫.％㈣以如印刷 I;層24,而該銲料層24係如低溶點之錫材。 °月ί閱弟3 F圖，接著該程相* js。/1 a .接者騎科層24作回銲（re-flow)加 先、，使该鋅料層24融成半球狀之凸塊24，。 請參閱帛3G圖，最後移除該第二絕緣層23，使該凸 塊24顯露出來，如此即在半導體封裝件之電路板/上 形成用以連接至外部電路的凸塊24，。 但在電性連接墊211上形成凸塊24, _，必須先在電 路板U上先塵合用以絕緣之第一絕緣層22，以及可移除 的第二絕緣層23。且該第一絕緣層22及第二絕緣層23必 須^別先經過光學曝光顯影之製程。由於該第一開口 221 第幵’ 231之孔從皆十分微細，故位準對位不易，使 該，第二開口 231不易對準第一開口 221之轴心，因此通常 h第-開d 231之孔徑力口大，藉以降低對位之困難度。惟 18035 6 χ252〇68 開口 231之孔禮’則無法達到細線路（fine route) 加大第 之要求 再者，該第一絕綾層”_ 經一次的處土 θ少 弟—絕緣層23必須分別各 的複雜卢使仔製程步驟增加’因而增加製程上 此::=製程步驟增加’使得生產速度緩慢，如 曝光顯影:增:二=二2乂:…_ 第-絕緣層22作對位，除了 fr:7:緣層23必須與 題。 “低生產成本’故成為業界所欲解決之課 【發明内容】 鑑於前述習知技術之缺失，本發明之 供一種導雷处播《V痴丨、1， 文曰的你在徒 裡V电結構之製法得簡化製程。 提高生本目的，録提供-種導電結構之製法得 本發明之再一目的，係在提供一 降低生產成本。 種令电結構之製法得 括:二二已』有：目的’本發明較佳之實施步驟係包 層，再於❹-絕緣層上形成 繁 連接墊的正上方之Μ , 家層，且位於電性 方之弟-、弟二絕緣層作開口製 18035 7 1252068 P^ess)，以在該電性連接墊上方的第—、第二絕緣層形成 幵口，之歧該開π内職—銲料層 鮮料層㈣成半球狀；最後移除該第二絕緣層/、口 W 该第-絕緣層形成在電路板上後再形成第二絕緣層， 直接進行開H使該電路板之電性連接塾可續 路出來，如此即可免除二次對位及二 而 得簡化製造程序，並可加快生產速度。w私因而 困難ΐ者，由於免除二次對位，如此即可避免重疊對位的 口難度，而可簡化程序以降低製造成本。 "又僅需一次開口製程’而可免除二次開口必 從之缺失，因此得以達到細線路之要求、= 接墊的數目。 乂運徒阿電性連 【實施方式】 4，：：係藉土特定的具體實施例說明本發明之實施方 :U此技蟄之人士可由本說明書所揭示之 瞭解本發明之其他優點與功效。本發 t易地 的具體實施例加以施行或應用，本說明書中不同 種修飾與變更。 在不W本發明之精神下進行各 以下之實施例係進一步詳細說明本發 非以任何觀點限制本發明之範疇。 點，但並 [弟一貫施例] 請參閱第1Α圖至第1G圖，係為本發明 電結構之製法之製法剖面示意圖。 i路一種導 18035 8 1252068 】ι上t =圖首先提供—電路板11，於該電路板 上之表面形成有導電層110a(c〇ndu 導電層U〇a表面形成一具有開口的阻層J )再㈣ 如乾膜及液態光阻苴中一者。接荖 曰 ^且層係 轳，、 者接者於該阻層10的開口内電 錄形成㈣個電性連接墊11G可供與W電性連接。 :了 1B圖所示，，然後移除阻層1Q，使該電 1 1 0顯露出來。 ％任！ 如弟1C圖所示，再移除未為電性連接塾^ 之導電層110a。 後孤 如第1D圖所示，接著在該電路板11上以壓合 (laminati〇n)、塗佈（_ing)或印刷（pdnting)等方式先形成 -弟-絕緣層12,並且覆蓋電性連接墊11〇，而該第— 緣層12係如有機防銲層（〇rganics〇ldermask)。 < 如第1Ε圖所示，再於該第—絕緣層12上方同樣以舞 合、塗佈或印刷等方式形成一第二絕緣層13;而該第二： 緣層13係如感光材料（photo image細心)之乾膜層⑹、 fUm)或防銲層（solder mask)，或係如非感光材料 image material)之PET塑膠或藍帶（blue tape)等，或如不占 錫物質之鈦、翻或鈦翻合金等。 如第1F圖所示，位於該電性連接墊11〇正上方之第 一絕緣層12及第二絕緣層π，以雷射開口（laser)或電漿 (electric plasma)專開 口製程（0peiling process)在第一絕緣 層12及弟一絕緣層13形成一開口 i4(〇pening)。 若該第一絕緣層12或第二絕緣層13之任一層係為感 18035 9 !252〇68 光材料，則先對該感光絕緣層進行強制曝光（expose)，再 =雷射開口（〗)或電漿（eWie pIasma)等技㈣成開口 反之，若該第一絕緣層12及第二絕緣層π同為非 感，材料，則無須進行曝光製程，直接以雷射開口（ι叫 或電漿（electric plasma)等技術以一次完成開口製程。 ^ 、如第]G圖所示，之後於該開口 14内以係如印刷方式 形成一銲料層15，而該銲料層15之材質可選自鉛、錫、" :二銅、鉍、銻、鋅、鎳、鍅、鎮、銦、碲、金以及鎵所 構成之組群之元素的混合物所構成之合金。 如第1H圖所示，然後該銲料層15作加熱回銲 ，使該銲料層丨5軟化並藉由表面張力（surface tension)及内聚力（c〇hesi〇n)而形成半球狀的金屬球B，。 :如第11圖所示，最後以化學剝離（chemical stripping) 或物理剝離（Physics stripping)移除該第二絕緣層13，如此 即可在電路板11之線路層的電性連接墊110上形成半球狀 的金屬球15，，當然本發明亦可移除該第二絕緣層13再 進行回銲。 由上述之製法，該第一絕緣層12係先形成在電路板 11上’然後即再疊置形成第二絕緣層13 ;之後直接進行開 口製程，而可在第一絕緣層12及第二絕緣層π上直接形 成上下連貫的開口 14，因此可免除習知構造分成兩次作 業’而必須作二次對位的製程，故可免除重置對位的複 度。 才、 再者’本發明僅作一次的開口製程，並免除二次對位， 10 18035 ί252〇68 :可化製程以提高生產速度，進而可降低製造成本。 [弟二實施例] 請參閱第2A圖至第21圖，係為本發明 ，剖面示意圖，與前-實施例不同處在於該電二 ^電性連接墊no上形成—導電柱，並可藉以增加連接 南度，完整步驟說明如下。 圖所示’首先提供一於表面已形成有複數個 电性連接墊1Η)的電路板u，於該電路板表面上 形成一阻層1 6，使該阻厚1 6目女魁+ 錄層16具有對應於該電性連接墊110 !:成有一開口 160。其中該電性連接墊no係可藉由一導 =110a以電鑛方式形成之，關於電路板形成導電層及電 ^接塾之製程技術乃業界所周知之製程技術，非本發明 之重點’故未再予贅述。 ♦如第2B圖所示，於該阻層16之開口 16〇内可藉 2 ll〇a做為電流傳導路徑，而於該開口内電鍍 電柱⑴’而該導電柱⑴係如船、錫、銀、銅、金、二 乐鋅、錄、錯、叙、銦、碲以或鎵等金屬。 < ϋ 2C ®所示’然後移除該阻層16及1252068 IX. Description of the invention: [Technical field to which the invention pertains] A method of manufacturing a conductive structure in a circuit board or a semiconductor element, especially a manufacturing method in which a solder pad is formed. [Prior Art] Suppression of scorpion products has been a long-term development trend, and the early-function type of electronic products can no longer meet the needs of consumers, because: must: multi-functional electronic products, such as mobile phones In combination with the digital camera + to enable the mobile phone to have the function of a digital camera, and the image can be directly transmitted by the mobile phone, so that the portable electronic products no longer have a single-use function. The combination of multi-functional electronic products and the use of a variety of functions is due to the high development of integrated circuits, enabling electronic products to enter the direction of multi-functional, high-performance research and development. In order to meet the needs of semiconductor package #Integrati〇n and Miniaturization, flip chip bonding has become a major trend. The main structure of the flip chip bonding technique is to form a solder ball (10) der ball on a plurality of output contacts of the wafer & semiconductor package, which can be externally connected with the tin Circuit connection. A method of manufacturing a solder ball on a wafer or a semiconductor package is a conventional method as shown in Figs. 3A to 3G. Referring to FIG. 3A, a plurality of electrical connection pads 211 are formed on a thunder circuit board 21, and the lightning pole electrical connection pads 211 shown in the figure provide the circuit board 21 with 1C crystal. Another pad is followed by an electrical connection pad. 18035 5 1252068 Referring to Figure 3B, the first insulating layer 22 is then cured by the circuit board 21. "- If you can see the image, please refer to the 3C picture, then the first - insulation layer 22 is (exposure), then re-image (devel en connected to the first opening 221 above 2U.) soap 4 into - position in the electrical connection Referring to FIG. 3D, a plurality of _ insulating layers 23 are further disposed over the first insulating layer 22; and the second insulating layer is formed on the second insulating layer 23 to form a second etched opening. 221 and m31 in the electrical connection pad 2 = open to form a continuous opening 3 一直 of the electrically conductive connection pad 211, and can be = figure, then in the continuity.% (four) to print as I; layer 24, and The solder layer 24 is like a tin material with a low melting point. ° Yue ί 弟 3 F F, then the process phase * js. / 1 a. Receiver riding layer 24 for re-flow plus (first), The zinc material layer 24 is fused into a hemispherical bump 24. Referring to the 帛3G diagram, the second insulating layer 23 is finally removed to expose the bump 24, thus being on the circuit board of the semiconductor package/ Forming a bump 24 for connecting to an external circuit, but forming a bump 24, _ on the electrical connection pad 211, must first dust the first insulating layer 22 for insulating on the circuit board U, And the second insulating layer 23 is removable. The first insulating layer 22 and the second insulating layer 23 must be subjected to an optical exposure development process. Since the first opening 221 is the same as the hole 231' Fine, so the alignment is not easy, so that the second opening 231 is not easy to align with the axis of the first opening 221, so usually the aperture opening of the h-opening d 231 is large, thereby reducing the difficulty of alignment. 18035 6 χ252〇68 Opening 231 hole 礼 ' can not reach the fine line (fine route) to increase the requirements of the first, the first 绫 layer _ once the soil θ younger brother - insulation layer 23 must be separately Each complex Lu makes the process steps increase 'thus increasing the process:: = process step increase' makes the production speed slow, such as exposure development: increase: two = two 2 乂: ... _ the first insulation layer 22 is aligned, except Fr:7: The edge layer 23 must be related to the title. "Low production cost" has become a course that the industry wants to solve [invention] In view of the lack of the aforementioned prior art, the present invention provides a guide for broadcasting "V idiots, 1, literary you are in the V The method of structure is simplified to simplify the process. To improve the purpose of the production, the method of producing the conductive structure is further aimed at reducing the production cost. The method for making the electrical structure is included: : OBJECTIVE 'The preferred implementation steps of the present invention are a cladding layer, and then the Μ-home layer is formed on the ❹-insulation layer directly above the connection pad, and is located in the electrical side of the brother-, and the second insulation layer is used as the opening system 18035 7 1252068 P^ess), the first and second insulating layers above the electrical connection pad form a mouth, and the π inner-solder layer fresh layer (4) is hemispherical; finally the second insulating layer is removed /, port W The first insulating layer is formed on the circuit board and then the second insulating layer is formed, and the H is directly opened to make the electrical connection of the circuit board extend, so that the secondary alignment and the second can be eliminated. Simplify the manufacturing process and speed up production w private and thus difficult, because the second alignment is eliminated, so that the difficulty of overlapping the alignment can be avoided, and the procedure can be simplified to reduce the manufacturing cost. "An open process only needs one time, and the secondary opening can be eliminated. It is missing, so it can meet the requirements of fine lines, = the number of pads. 乂运徒阿电连 [Embodiment] 4,:: The specific implementation of the specific embodiment of the invention illustrates the implementation of the present invention: U this Those skilled in the art can understand the other advantages and effects of the present invention as disclosed in the present specification. The specific embodiments of the present invention are implemented or applied, and various modifications and changes are made in the present specification. The following examples are given to further illustrate the scope of the present invention by any means. Point, but the same applies to the first embodiment to see the first embodiment of the present invention. Schematic diagram of the manufacturing method. i-way a guide 18035 8 1252068] ι on t = diagram first provided - circuit board 11, on the surface of the board is formed with a conductive layer 110a (c〇ndu conductive layer U〇a surface Forming a resist layer with an opening J) and then (4) one of a dry film and a liquid photoresist. The layer is connected to the layer, and the connector is electrically recorded in the opening of the resist layer 10 to form (four) electrical properties. The connection pad 11G can be electrically connected to W. : As shown in FIG. 1B, the resist layer 1Q is removed, and the electric 1 1 0 is exposed. %任! As shown in the figure 1C, the removal is not The conductive layer 110a is electrically connected to the conductive layer 110a. The latter is formed as shown in FIG. 1D, and then formed on the circuit board 11 by laminating, coating (ping) or printing (pdnting). The insulating layer 12 covers the electrical connection pads 11A, and the first edge layer 12 is an organic solder mask (〇rganics〇ldermask). < As shown in Fig. 1, a second insulating layer 13 is also formed by dancing, coating or printing on the first insulating layer 12; and the second: edge layer 13 is made of a photosensitive material ( Photo image carefully) dry film layer (6), fUm) or solder mask, or PET plastic or blue tape such as non-photosensitive image material, or titanium without tin content , turning or titanium alloy. As shown in FIG. 1F, the first insulating layer 12 and the second insulating layer π located directly above the electrical connection pad 11 are processed by a laser or electric plasma (0peiling process). An opening i4 is formed in the first insulating layer 12 and the first insulating layer 13. If any of the first insulating layer 12 or the second insulating layer 13 is a 18035 9 ! 252 〇 68 light material, the photosensitive insulating layer is first subjected to an exposure, and then a laser opening (〗) Or plasma (eWie pIasma) and other techniques (4) to open the opposite side, if the first insulating layer 12 and the second insulating layer π are non-inductive, the material, there is no need to perform an exposure process, directly with a laser opening (ι call or electricity) Techniques such as electric plasma complete the opening process at one time. ^, as shown in Fig. G, a solder layer 15 is formed in the opening 14 by printing, and the material of the solder layer 15 is selected from the group consisting of Lead, tin, " : an alloy of a mixture of elements of a group consisting of two copper, bismuth, antimony, zinc, nickel, antimony, bismuth, indium, antimony, gold, and gallium. As shown in Figure 1H, Then, the solder layer 15 is heated and reflowed to soften the solder layer 丨5 and form a hemispherical metal ball B by surface tension and cohesion (c〇hesi〇n). Shown, finally with chemical stripping or physical stripping (Physics stripping) The second insulating layer 13 can form a hemispherical metal ball 15 on the electrical connection pad 110 of the circuit layer of the circuit board 11. Of course, the second insulating layer 13 can be removed and reflowed. According to the above method, the first insulating layer 12 is first formed on the circuit board 11 and then stacked to form the second insulating layer 13; then the opening process is directly performed, and the first insulating layer 12 and the second layer are provided. The upper and lower continuous openings 14 are formed directly on the insulating layer π, so that the conventional structure can be eliminated from the two operations' and the secondary alignment process must be performed, so that the resetting of the resetting position can be dispensed with. Invented the opening process only once, and eliminates the secondary alignment, 10 18035 ί252〇68: the process can be increased to increase the production speed, thereby reducing the manufacturing cost. [Second Embodiment] Please refer to Figure 2A to Figure 21 The present invention is a schematic cross-sectional view. The difference from the previous embodiment is that a conductive pillar is formed on the electrical connection pad no, and the connection degree can be increased. The complete steps are as follows. Providing a surface that has been formed A circuit board u of a plurality of electrical connection pads 1 ) forms a resist layer 16 6 on the surface of the circuit board such that the thickness of the 16-mesh female recording layer 16 corresponds to the electrical connection pad 110 !: There is an opening 160. The electrical connection pad no can be formed by electro-mineralization by a guide=110a, and the process technology for forming a conductive layer and an electrical connection on a circuit board is a well-known process technology in the industry, which is not the focus of the present invention. Therefore, it will not be repeated. ♦ As shown in FIG. 2B, in the opening 16〇 of the resist layer 16, 2 〇 〇 a can be used as a current conduction path, and the electric column (1)′ is electroplated in the opening, and the conductive column (1) is like a ship, tin, Silver, copper, gold, Erle Zinc, recorded, wrong, Syrian, indium, antimony or gallium. < ϋ 2C ® shown 'and then remove the resist layer 16 and
電層110a，俾以在該電踗刼n t V 導電柱m。 板11之電性連接墊110上形成 如第2D圖所示，此後在該電路板11上形成-第— 緣層12，並覆蓋電性連純110及其上的導電柱m/巴 如第2E圖所示’再於該第—絕緣層^上 二絕緣層13。 乐 18035 11 1252068 如* 2F圖所示，相對於該導以主⑴正上方 f 蝝層12及第二絕緣層13作開口 、，、巴 及第—確螓层]。1 x牙壬’以在弟一絕緣層12 Γ/: 形成一位於該導電柱⑴正上方的Η 口 14, 俾㈣導電柱⑴可顯露出來。 方的開口 如弟2G圖所示，之後於該開口 Μ 15, 而該銲料層15之材質 / ―，旱料層 鋅、鎳、錄、鎖、銦、碲、金以:鎵=I錄、 的混合物所構成之合金。 斤構成之組群之元素 銲料層15作回鮮_^^ …如第=軟化而形成半球狀的金屬球15，。 如此二=最後以剝離移除該第二絕緣層… 上形成半球狀的金屬球15，。 負面的h柱111 由於該電性連接墊J J 〇先 此即可在電性連接㈣〇先=力二的導電柱⑴’如 柱⑴上形成金屬球15，，藉t加¥連電^山，再於導電 料之用量《防止銲錫材料之掉球:見象連。接而度’並減少辉 用以：’以上僅為本發明之較佳實施例而已’並非 成之技術實體或方法下，任何他人完 者係完全相同，亦或為同1效專利範圍所定義 此申請專利範圍中。 句將被視為涵蓋於 【圖式簡單說明】 18035 12 1252068 第1A圖至第II圖係為本發 法剖面示意圖； 月之導電結構之製法的製 圖 第2 Α圖至第21圖係為本發明之婁 一… 个知月之v電結構之製法的另 貫施製法剖面示意圖；以及 第3A圖至第3G圖係為習知導電結構之製法剖面示意 【主要元件符號說明】 11 Λ 21電路板 Π〇 11 〇a Πΐ 12 N 22 13、23 14 電性連接塾 導電層 導電柱 弟一絕緣層 第二絕緣層 開口 15、 24 15， 16、 10 16〇 211 221 231 24, 銲料層 金屬球 阻層 開口 電性連接墊 第一開口 第二開口 凸塊 連貫開口 18035 13 30The electric layer 110a is electrically connected to the conductive column m at the electric gate n t V . The electrical connection pad 110 of the board 11 is formed as shown in FIG. 2D, after which the -th-edge layer 12 is formed on the circuit board 11, and the electrically connected pure 110 and the conductive post m/baru 2E shows the second insulating layer 13 on the first insulating layer. Le 18035 11 1252068 As shown in the figure *2F, the opening, the bar, and the second layer of the second insulating layer 13 are directly above the main (1). 1 x 壬 以 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 。 。 。 。 。 。 。 。 。 。 The opening of the square is as shown in the 2G diagram, and then in the opening Μ 15, and the material of the solder layer 15 /, the dry layer of zinc, nickel, recording, lock, indium, antimony, gold to: gallium = I recorded, The alloy of the mixture. The element of the group consisting of the pounds is made of the solder layer 15 as a fresh metal _^^ ... as the first = softened to form a hemispherical metal ball 15. So two = finally remove the second insulating layer ... by peeling to form a hemispherical metal ball 15 . Negative h-pillar 111 Since the electrical connection pad JJ 〇 first can form a metal ball 15 on the conductive column (1) such as the column (1) electrically connected (4) 〇 first = force 2, by l plus ¥ connect electricity ^ mountain , and then the amount of conductive material "to prevent the solder material from falling off the ball: see the company. And the following is only for the preferred embodiment of the present invention. This patent application is covered. The sentence will be considered as covering the [Simple Description] 18035 12 1252068 1A to II is a schematic cross-sectional view of the method; the drawing of the conductive structure of the month is from the 2nd to the 21st The invention is a schematic diagram of a cross-section of another method for manufacturing the electrical structure of the moon; and FIGS. 3A to 3G are schematic diagrams of the manufacturing method of the conventional conductive structure [main symbol description] 11 Λ 21 circuit Π〇11 〇a Πΐ 12 N 22 13,23 14 Electrical connection 塾 Conductive layer Conductive pillars An insulating layer Second insulating layer opening 15, 24 15, 16, 10 16〇211 221 231 24, Solder layer metal ball Resistance layer opening electrical connection pad first opening second opening bump continuous opening 18035 13 30