1250565 玖、發明說明： 【發明所屬之技術領域】 本發明係與半導體有關，尤指一種半導體晶圓及其製 程，其中該端子墊（termianl pad)係沿一半導體晶圓之一切 割道（scribe line)置放，以擴大該類比積體電路 (integrated circuit ; 1C)晶片的使用面積。 【先前技術】 一傳統半導體晶圓包括一晶圓主體與在該晶圓主體 上間隔形成的複數個晶片，用於定義作為每兩個晶片之間 一界限的一切割道。因此，每一該等晶片（亦稱為一類二 IC晶片）為基於石夕基板所組成的一積體電路。 在將每一該等晶片切割成一單獨組件之前，必須執行 一晶圓測試，以確保每一該等晶片係在一最佳條件下發^ 作用二一般而言，每一該等晶片包括在該晶片内部間隔形 成的複數個焊墊（bond pad)與複數個端子墊，其中該等端^ 墊可為測試墊（test pad)，用於經由諸如探針卡或剪切墊 (trim pad)之一測量工具來測量該晶片的電壓，以調整該 片的參考電壓及其參考功能。 敕〃此，通常採用雷射切割與電調整兩種調整方法來調 正，等晶片。執行雷射切割來切割保險絲，使得一旦保險 文？切割、’晶片的性能會相應改變。然❿，雷射切割操 :昂貴又複雜，以致會大幅增加晶片的製造成本。此外， j作,射切割過程中，不能預測每-晶片的電壓，以致 不月匕使每一晶片的品質標準化。 12505651250565 玖, the invention description: [Technical field of the invention] The present invention relates to semiconductors, and more particularly to a semiconductor wafer and a process thereof, wherein the terminal pad is cut along one of the semiconductor wafers (scribe Line) is placed to expand the area of use of the integrated circuit (1C) wafer. [Prior Art] A conventional semiconductor wafer includes a wafer body and a plurality of wafers formed on the wafer body for defining a scribe line as a boundary between each two wafers. Therefore, each of the wafers (also referred to as a type of two IC wafers) is an integrated circuit based on the Si-Xi substrate. Before each of the wafers is diced into a single component, a wafer test must be performed to ensure that each of the wafers is functioning under optimal conditions. In general, each of the wafers is included in the a plurality of bond pads formed in the interior of the wafer and a plurality of terminal pads, wherein the pads can be test pads for use via, for example, a probe card or a trim pad A measurement tool measures the voltage of the wafer to adjust the reference voltage of the chip and its reference function. In this case, laser cutting and electrical adjustment are usually used to adjust and wait for the wafer. Perform a laser cut to cut the fuse so that once it is insured? The performance of the cut, 'wafer will change accordingly. Then, laser cutting operations are expensive and complicated, which can significantly increase the manufacturing cost of the wafer. In addition, during the laser cutting process, the voltage per wafer cannot be predicted so that the quality of each wafer is standardized. 1250565
另一調整方法係盐山+、. L 該等晶片上施加方式來執行，丨中在每- 控制該電流，故可有保險絲。由於可有選擇地 便產生該晶片的參考電壓及其參考功能。專“移除，以 此外，傳統半導體晶圓具有數個缺 置放於每-該等晶片内•，故該晶片之尺寸係 :便；：：匕端子墊以及保險絲保持於適當位置。因 的焊墊或是端子塾。：：：上；ί谷納-定數量 體晶圓的製片之尺寸，以致大幅增加該半導 此外，當將該等晶片從 子墊會保留在每一該等晶片 測量相應晶片之電壓或可程 後’端子墊便無用處。因此 晶片的有限空間。 半導體晶圓上切除時，該等端 之上。然而，端子墊係僅用於 式化剪切該保險絲。測量結束 ’該等端子塾會浪費每一該等 【發明内容】 本發明的一主要目的係提供一種半導體晶圓，其中該 等端子墊係沿一半導體晶圓之一切割道置放，並與該晶片 電連接，以便擴大晶片的使用面積。 本發明的另一目的係提供一種半導體晶圓，其中一導 電配置係從該切割道向該晶片延伸，以使該端子墊與該晶 1250565 =電連接’使得當將晶片從該晶圓主體切除後，僅藉由沿 该切割道切除該導電配置即可將端子墊從晶片上移除。 名轨，t明的另—目的係提供—種半導體晶®，其中該端 糸製作為一梳型形成，使一切割工具沿該切割道切除 :::時,，其可將保留在該切割工具切割尖端上的殘逢減 至最夕，從而加強晶片的切割操作。 石轨，&明的另—目的得、提供—種半導體晶圓，其中該端 該晶片移至晶圓主體之切割道，使得晶片的可使 :面積侍以擴大，且晶片中可加入更多積體電路以加強晶 本發明的另一目的係提供一種半導體晶圓，其中並未 1^7片f質的結構设計，從而可藉由任何現有剪切測 试來測試該半導體晶圓，將本發a月的製造成本減至最少。 ϋ明的另一目的係提供一種剪切保險絲半導體晶 /或^ Β其製程較簡單’即將該端子墊從該晶片内重新定 二=的切割道來置放’並經由導電配置將端子墊與 该：片電連接。因&，本發明中不需要額外的組件，可進 一步降低本發明的製造成本。 從而 其包括： 為實現上述目的，本發明提供一種半導體晶圓 晶圓主體； 1250565 複數個類比ic晶片，其間隔且對齊地形成於該晶圓 ，體之上，每兩個晶片間之一區域定義為一切割道，其中 每一晶片具有在其内部形成的内部電路以及沿該切割道形 成的至少一端子墊；以及 一導電配置，其包括形成於晶圓主體之上的至少一導 電元件，將端子墊與該晶片之内部電路電連接，使得舍产 切割道將晶片從晶圓主體上切除後，可將端子墊從該：片^ 中切除，而該内部電路保留在晶片中。 本案得藉由以下列圖示與詳細說明，俾得一更深入之 了解。 【實施方式】 參考該等圖式之第一圖，其係本案較佳具體實施例之 騁導體晶圓的上視圖。其中，該半導體晶圓包括一晶圓主 個10，以及間隔並對齊地形成於晶圓主體1〇之上的複數 類比1C晶片20，每兩個晶片20間之一區域定義為一切 j道/!。其中，每一該等晶片2〇具有在晶片内部形成的 内部電路21以及沿切割道丨丨形成的至少一端子墊22。 於曰3半導體晶圓進一步包括-導電配置30，其包括形成 22 Ik主體1〇之上的至少一導電元件31，以便將端子墊 從晶、内部電路21電連接，使得當沿切割道11將晶片20 j^曰，曰圓主體10上切除後，可將端子墊22從晶片20中切 $ ’使内部電路21保留在晶片2〇中。 1250565 本發明進-步提供一製造該半導體晶圓， 以下步驟： … 0) ^晶圓主體1G上間隔並對齊地形成該等類比ic 曰曰片20，母兩個晶片2〇間之一區域定義為一切割道η。 (2) >口者在鄰近個另丨总η — η上安置排列該端子…回主體10的切割道 熱22(^於Λ圓主體1〇上形成導電元件31，以便將端子 墊22與忒曰曰片20的内部電路21電連接。 (4) /σ切割道丨丨將晶片2〇從晶圓主體1 〇上切除，以 子由塾22從該晶片20移除，使該内部電路21保留在 晶月20中。 確性= Ϊ 實施例，每-該等晶片2G均可提供精 可以。同揭，/因此，每一該等晶# 20的電壓測量 P，’母一該等晶片20均得到剪切以可程式化 A曰日片20,以產生一參考電壓與一參考功能。 精由互相電連接的複數個積體電路來構造每一該等晶 片20 ’以形成内部電路21。i 元件31來與個別晶片20的内部電路21電連接係…電 一剪作為從該晶片20之積體電路處電延伸的 延伸的一保險絲23,以使個別二 口於男切以產生*女曰 座生4 Β日片2〇的參考電壓及參考功能。然而， 10 1250565 =，墊22可為一測試墊，用於與該測量工具電耦合，以測 里该晶片20的電壓。 山如第三圖所不，具有一梳狀的端子墊22，定義複數個 端子齒22 1，其間隔地形成於晶圓主體丨〇之切割道丨丨上。 ς中，導電元件3 1係從晶圓主體丨〇之切割道丨丨延伸至該 :片20，以使端子墊22的端子齒221與晶片2〇的内部電 路21電連接。 ^值得一提的是為將晶片20從晶圓主體10上切除，可 =用一切割工具（如具有鑽石頭的一切割裝置）沿晶圓主 體10之切割道11來切割，以便單獨將晶片20從晶圓主體 10上为開。然而，當该切割工具之切割尖端沿晶圓主體i 〇 之切割道U滑動切㈣，端子塾22的殘潰會保留在具有 鋸齒狀邊緣的切割工具之切割尖端上。因此，為防止端子 墊22的殘渣會殘留在具有鋸齒狀邊緣的切割工具之切割 尖端上，將端子墊22作為一梳狀結構。當切割工具之切割 尖端沿端子墊22的端子齒221滑動切割時，使殘留在該切 割工具之切割尖端上的殘渣減至最少。 由金屬層製成的該導電元件31從晶圓主體1〇之切判 道11延伸至晶片20,以使端子墊22與晶片2〇的内部電 路21電連接。另夕卜，導電元件31可由多晶層(ρ_ ia㈣ 製成，使端子墊22與晶片20的内部電路21電連接。 因此，當將端子墊22做為剪切墊時，該導電配置3〇 更包括從導電元件31向保險絲23電延伸的一辅助導電元 件32,使保險絲23適合於透過該輔助導電元件32藉由端 !25〇565 5 3 ϋ剪切墊來剪切。在晶片20剪切後，如第三圖所 不：^塾22做為的剪切墊從晶片20處移除。 ^外，值得一提的，保險絲23係置放於晶片2〇内部， 可：曰片2〇從晶圓主體1〇上切除之後，該保險絲23 割、ϊ 1 1 曰片2〇内部。此外，由於已沿晶圓主體10之切 二割= 主：10上切除’故可將晶圓主體 除。 上的V電兀•件3 1之一部分從晶片20中移 -承I::子塾22作為測試墊來具體化時，晶片20中不 : 將導電元件32從晶圓主體10之切割道11 :電路21電連接。因此，在測 做為測試塾的端子墊22從晶片2〇移除。電堅後將 質上：：：：墊22係沿晶圓主體10之切割道11置放，實 更多‘體雷：片：0的使用面積，從而可向晶片20中加入 比，：】=:曰子片墊::'f於”内部的傳統…^ 為測試墊來能。此外，當將端子墊22作 受不八體化時、或為剪切晶片20 ==體化時，可用端子墊22來測試晶片= 在调整或測試晶片20之後，端子墊22不會再為曰片 僅=壬=’：而可將端子墊22從晶片20移除而 在曰曰片20中保留内部電路21，以用於操作。 12 1250565 · 上述本發明之具體實施例與圖示係使熟知此技術之人 士所能瞭解，然而本專利之權利範圍並不侷限在上述實施 例。 、 因而可以看見，本發明之該等目的已經完全且有效實 現。基於解說本發明之功能與結構原理之目的而顯示及說 明本發明之具體實施例，並且可對該等具體實施例進行均 等變化，而不致脫離此類原理。因此，本發明專利範圍 括涵蓋於以下申請專利範圍之精神與範圍内之所有均等變Another adjustment method is performed on the wafers of Yanshan+, .L. The current is controlled in each case, so there is a fuse. The reference voltage of the wafer and its reference function can be selectively generated. Specifically, "Removal, in addition, the conventional semiconductor wafer has several defects placed in each of the wafers, so the size of the wafer is:;;: 匕 terminal pads and fuses are held in place. Solder pad or terminal 塾.:::上; ί谷纳 - the size of the wafer of the number of wafers, so that the semi-conductor is greatly increased. In addition, when the wafers are retained from the sub-pads, each of these After the wafer measures the voltage or the process of the corresponding wafer, the terminal pad is useless. Therefore, the limited space of the wafer. Above the semiconductor wafer is cut off. However, the terminal pad is only used to cut the fuse. The measurement ends [these terminals will waste each of them] SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor wafer in which the terminal pads are placed along one of the dicing streets of a semiconductor wafer, and Electrically connecting to the wafer to expand the area of use of the wafer. Another object of the present invention is to provide a semiconductor wafer in which a conductive arrangement extends from the scribe line to the wafer such that the terminal pad and the crystal 12 50565 = electrical connection 'so that after the wafer is removed from the wafer body, the terminal pads can be removed from the wafer only by cutting the conductive configuration along the scribe line. a semiconductor crystal®, wherein the end turns are formed in a comb shape such that when a cutting tool is cut along the cutting path::, it can reduce the residuals remaining on the cutting tip of the cutting tool to the last , thereby enhancing the cutting operation of the wafer. The rail, & another, the purpose of providing a semiconductor wafer, wherein the end of the wafer is moved to the scribe line of the wafer body, so that the wafer can be: Expanded, and more integrated circuits can be added to the wafer to enhance the crystal. Another object of the present invention is to provide a semiconductor wafer in which there is no structural design of the substrate, so that any existing shear can be used. Test to test the semiconductor wafer to minimize the manufacturing cost of the current month. Another purpose of the invention is to provide a shear fuse semiconductor crystal / or Β its process is relatively simple 'coming the terminal pad from the Re-defining the scribe line in the wafer The terminal pad is electrically connected to the: via a conductive configuration. Since no additional components are required in the present invention, the manufacturing cost of the present invention can be further reduced. Thus, the present invention includes: To achieve the above object, the present invention Providing a semiconductor wafer wafer body; 1250565 a plurality of analog ic wafers formed on the wafer, spaced apart and aligned, and a region between each two wafers is defined as a scribe line, wherein each wafer has An internal circuit formed therein and at least one terminal pad formed along the scribe line; and a conductive arrangement including at least one conductive element formed on the wafer body to electrically connect the terminal pad to an internal circuit of the wafer After the wafer is cut from the wafer body, the terminal pad can be cut off from the wafer, and the internal circuit remains in the wafer. The present invention is illustrated by the following illustration and detailed description. Have a deeper understanding. [Embodiment] Referring to the first drawing of the drawings, which is a top view of a conductor wafer of a preferred embodiment of the present invention. Wherein, the semiconductor wafer comprises a wafer main 10, and a plurality of analog 1C wafers 20 formed on the wafer main body 1 间隔 at intervals and aligned, and an area between each of the two wafers 20 is defined as all j channels/ !! Each of the wafers 2 has an internal circuit 21 formed inside the wafer and at least one terminal pad 22 formed along the scribe line. The semiconductor wafer further includes a conductive arrangement 30 including at least one conductive element 31 formed over the 22 Ik body 1 电 to electrically connect the terminal pads from the crystal, internal circuit 21 such that when along the scribe line 11 After the wafer 20 is cut away, the terminal pad 22 can be cut from the wafer 20 to leave the internal circuit 21 in the wafer 2A. 1250565 The present invention further provides a method of fabricating the semiconductor wafer, the following steps: ... 0) ^ The wafer body 1G is spaced and aligned to form the analog ic dies 20, one of the two wafers 2 Defined as a cutting path η. (2) < The mouth is arranged on the adjacent 丨 total η - η to arrange the terminal ... back to the scribe line heat 22 of the body 10 (^ forming a conductive element 31 on the round body 1 , to connect the terminal pad 22 with The internal circuit 21 of the cymbal piece 20 is electrically connected. (4) The / σ dicing track 切除 removes the wafer 2 〇 from the wafer body 1 ,, and the 子 22 is removed from the wafer 20 by the 塾 22, so that the internal circuit 21 is retained in the crystal moon 20. Authenticity = 实施 In the embodiment, each of the wafers 2G can provide fine. Similarly, /, therefore, the voltage measurement of each of the crystals # 20, 'mother one of the wafers 20 is sheared to program the A-day film 20 to generate a reference voltage and a reference function. Each of the wafers 20' is constructed by a plurality of integrated circuits electrically connected to each other to form an internal circuit 21. The i element 31 is electrically connected to the internal circuit 21 of the individual wafer 20. The electric component is electrically cut as a fuse 23 extending from the integrated circuit of the wafer 20 so that the individual two are cut to produce * The reference voltage and reference function of the 2 Β 片 2 〇 片 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 10 10 10 10 10 10 10 For electrically coupling with the measuring tool to measure the voltage of the wafer 20. As shown in the third figure, the mountain has a comb-shaped terminal pad 22 defining a plurality of terminal teeth 22 1 formed at intervals on the wafer. In the crucible, the conductive element 31 extends from the dicing turn of the wafer body 至 to the sheet 20 such that the terminal teeth 221 of the terminal pad 22 and the wafer 2 are The internal circuit 21 is electrically connected. It is worth mentioning that in order to cut the wafer 20 from the wafer main body 10, it is possible to use a cutting tool (such as a cutting device having a diamond head) along the cutting path 11 of the wafer main body 10. Cutting to separate the wafer 20 from the wafer body 10. However, when the cutting tip of the cutting tool slides along the cutting path U of the wafer body i (4), the residue of the terminal 22 remains in the sawtooth The edge of the cutting tool is cut on the cutting tip. Therefore, in order to prevent the residue of the terminal pad 22 from remaining on the cutting tip of the cutting tool having the serrated edge, the terminal pad 22 is used as a comb structure. Terminal teeth 221 along terminal pad 22 During dynamic cutting, the residue remaining on the cutting tip of the cutting tool is minimized. The conductive element 31 made of a metal layer extends from the wafer body 1 to the wafer 20 to make the terminal pad 22 is electrically connected to the internal circuit 21 of the wafer 2. Further, the conductive member 31 may be made of a polycrystalline layer (ρ_ ia (4) to electrically connect the terminal pad 22 to the internal circuit 21 of the wafer 20. Therefore, when the terminal pad 22 is to be used When used as a shear pad, the conductive arrangement further includes an auxiliary conductive element 32 electrically extending from the conductive element 31 to the fuse 23, so that the fuse 23 is adapted to pass through the auxiliary conductive element 32 by the end! 25 〇 565 5 3 ϋ Cut the mat to cut. After the wafer 20 is diced, the dicing pad, as shown in the third figure, is removed from the wafer 20. In addition, it is worth mentioning that the fuse 23 is placed inside the wafer 2, and after the cymbal 2 is removed from the wafer main body 1 , the fuse 23 is cut and ϊ 1 1 〇 2 〇 inside. In addition, the wafer body can be removed because it has been cut along the wafer body 10 = main: 10 is removed. When one of the upper V-electrode parts 3 1 is moved from the wafer 20 and the I:: sub-tray 22 is embodied as a test pad, the wafer 20 is not: the conductive element 32 is cut from the wafer body 10 : Circuit 21 is electrically connected. Therefore, the terminal pad 22, which is measured as a test cartridge, is removed from the wafer 2A. After the electric hardening, the :::: mat 22 is placed along the cutting path 11 of the wafer main body 10, and more "body mine: sheet: 0 use area, so that the ratio can be added to the wafer 20, :] =: 曰子片垫::'f in the internal tradition...^ is the test pad. In addition, when the terminal pad 22 is subjected to the occlusion, or when the wafer 20 is modified, The terminal pad 22 can be used to test the wafer = after the wafer 20 is adjusted or tested, the terminal pad 22 will no longer be a die = ': the terminal pad 22 can be removed from the wafer 20 to remain in the die 20 The internal circuit 21 is for operation. 12 1250565 · The specific embodiments and illustrations of the present invention are known to those skilled in the art, but the scope of the patent is not limited to the above embodiments. The specific embodiments of the present invention have been shown and described for the purpose of illustrating the embodiments of the present invention Separate from such principles. Therefore, the scope of the patent of the present invention Equal encompass all variations within the scope of the following patent application scope of the spirit
【圖式簡單說明】 圖為本發明之-較佳具體實施例之半導體晶圓的 上祝》圖。 第一圖為本發明之上述較佳且辦眘a ^:丨> . 連接類晶片之半導體晶圓V視體圖實'例之-端子塾電BRIEF DESCRIPTION OF THE DRAWINGS The Figure is a diagram of a semiconductor wafer of the preferred embodiment of the present invention. The first figure is the above-mentioned preferred and prudent care of the present invention. A semiconductor wafer V-view diagram of a connected wafer is as follows - the terminal is electrically
=圖為依據本發明之上述較佳具體實施例之該 體曰曰囫上-端子塾電連接的類比Ic晶片㈣面透視圖。 圖示符號說明 11切割道 21内部電路 23保險絲 10晶圓主體 2〇類比1C晶片 221端子齒 22端子墊 13 1250565 30導電配置 31導電元件 32辅助導電元件= is a perspective view of an analog Ic wafer (four) wafer in accordance with the above-described preferred embodiment of the present invention. Description of the symbols 11 scribe line 21 internal circuit 23 fuse 10 wafer body 2 〇 analog 1C wafer 221 terminal teeth 22 terminal pads 13 1250565 30 conductive configuration 31 conductive components 32 auxiliary conductive components
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