TWI250454B - Method of using scan chains and boundary scan for power saving - Google Patents

Abstract

The invention provides a method and circuitry to save power in a synchronous logic ASIC with low overhead. The scan chain(s) and boundary scan mechanism of the synchronous logic ASIC are used and modified for shifting out current states of internal memory devices of the synchronous logic ASIC to an external memory and for retaining the power-off blocks' primary output values to the memory devices of the boundary scan circuit, so the proposed gated power method is efficient and low overhead in the synchronous, flop-based, logic circuit design.

Description

1250454 V. Description of the invention (1) [Technical field to which the invention belongs] On ^ ^ is related to the synchronous logic ASIC (Appl icati one)

Spe=m, IC, special integrated circuit) The method of reducing leakage current, especially the method of saving power by technology such as ^:Key (Scan Chain) and boundary scan (ΙΕΕΕ 1149·;[). V t [Prior Art] ^ For all portable equipment (such as PD A, portable computers, mobile phones, etc.), the power saving of integrated circuits is becoming more and more important. The power consumption of these equipment can be divided into two categories: self-state power consumption (power consumed during switching, p = cv2f) and static power consumption (ie leakage). For the consumption of kinetic power, two techniques have been applied to reduce power consumption by reducing C, v or f (integral capacitance, supplied voltage or operating frequency) · · 1 · Improved process technology to supply voltage and circuit size / capacitance And so on (ie lower c and v). 2 • Turn off the clock signal to reduce the switching frequency f. For static power consumption (ie leakage), the following methods have been used: 3 • Improvement of components/circuits, in the sub-micron and portable circuit design, 'leakage becomes a major factor in power consumption, and circuit designers use the cut-in voltage VT (cut- In voltage) higher components to reduce leakage and improve static power consumption. 4 • Turn off the power and turn off the power for unused circuits. For the third method described above, the high cut-in voltage VT may increase the short-circuit current and thus consume more dynamic power. And the first method and the third

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V. Description of the invention (2) The method must change the process technology, the cost is high and the progress is slow. Most of the IC design companies in the factory can not afford the cost and development time because: can use the existing technology to save electricity. Therefore, the second method and the first kind of method are the best way to control the budget for the 1C design company without the fab. The fourth method is the best method for dynamic power saving, and the fourth method is to reduce the best leakage. method. The second method is a well-known method, and it has been widely used. The C A D tool can provide design techniques for turning off the clock signal (for example)

Synopsys’ p〇wer Compiler). The t-style clothing set 9 5 / working time is in the S ^ andby mode, so leakage is one of the main factors of power consumption, but leakage is unable to close the clock signal (the second method) ) and terminated. The fourth method to turn off the power supply is the best solution for static power saving of the portable device. However, the power-off of the fourth method has not been widely used for the following two reasons: 1 • Turning off the power requires additional memory, control circuitry, and wiring to store the contents of the shutdown block, which involves too many hardware management designs. 2 · The procedure for turning off the power/turning on the power is very trivial. Due to the above two disadvantages, the power-off is well known, but it is not commonly used, so there is room for improvement. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method and circuit for utilizing existing Scan Chains and Boundary Scan (WEE 1149. 1) techniques to turn off the power supply and reduce power savings in the synchronous logic ASIC.

1250454 V. Hardware design of invention description (3). The power-saving controller is installed in the same logic AS IC, the original co-processing signal of the keystroke and boundary scan circuit, org_s-enable, org-bs-mode, org-bs- Enab1e , power —of f,cl〇ck and reset signals are input to the power-saving controller to generate a new set of control signals s_mode, s_enable bs-enable, pw-switch, scan-cloc eight to control the scan chain and boundary scan circuit, so : The power-saving controller is installed in the synchronous logic ASIC, so that the bs_mode, mem., bs-c1ock and a) are turned on when the synchronous logic as IC is turned off: 1) The clock signal of the synchronous logic AS IC is turned off first; 2) storing a set of main outputs of the synchronous logic ASIC in the memory component of the circuit, and then switching an external electrode 2 from the main output terminal to the boundary scan circuit; < 3) The internal chain state of the synchronous logic ASK is shifted out to the one via the scan chain circuit by a scan chain circuit: 4) the power supply of the synchronous logic AS丨c is turned off; σ. b) When the synchronous logic AS IC is powered on: 1) Turn on the power and initialize the circuit to be turned off; 2) Drag the value stored in the external memory to the internal memory cell of the synchronous logic ASIC. Back to 3) Switch the input of the external circuit from the boundary ^ to the main output; "Memory element 4 of the circuit" starts the clock signal.

1250454 V. INSTRUCTIONS (4) [Embodiment] Refer to Figure 1, Factory I, Synchronous Logic AS I C No. The main circuit contains 'multiple: the chain circuit will be configured along the main circuit, such as the flip-flop, bit logic/road 1 and many memory component examples 4, multiplex cry 3 right: f is). The tracing chain circuit includes multiplexer 3 and multiplex prize j. There are two inputs: "Reading 31 丄 丄 口 4 has two rounds ", eight 31" and "working 32", multiplex 42" 3" clock signal 41" and "main clock signal Y〇d" 3 are low power; day; work, 4 work: signal s - enable 33 and 4 will be input to the synchronization logic (4) often; signal "The control signal s__enable industry, although the evening and the benefits of 3 and more than the day, the circuit enters the scan mode for production measurement I / - m "〇de 43 for the high potential will replace the "main clock outside the section ^ production Wu, scan clock signal 41 "Test 31" information Jiang Ming ~ "and wheeled into the synchronous logic ASIC, shift register", bypassing the combination logic circuit such as the flip-flop, the bit memory component 2 removes the output for a step by step The boundary η refers to FIG. 2, and when the design function is tested, a flat field (IEEE 11 49·1) mechanism (shaded area) reaches the desired output signal 52. Use bs clock 59 illusion:: circumvent, save/observe the master. The test capital is input to the main S^nabl = 54 signal via the multi-master 55. The main output signal 52 of the signal 5 is removed by the memory element 57 and the scanning mechanism of the unit to be tested. The boundary scan mechanism is designed to pass the boundary. Figure 3 of the first embodiment of the present invention shows an embodiment of the present invention. The existing scan chain and boundary dance 1250454 are surrounded by a combination of inventions (5) and (IEEE 1149·1). Block 8 to turn off the power. j:: and the boundary scan circuit is the integrated field of all portable applications. The invention uses only the scan chain circuit and the boundary: Λ Λ Λ Λ 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 扫描 ° ° ° ° ° ° ° ° ° ° ° The inner valley of the piece is stored in an external memory 6, and the s_enable 33 and s-m〇de 43 of the ghoster 4 are pulled into the eve-turn-multiple power supply block 8 to enter the scanning mode. The present invention turns off the boundary state of the block 8 to be turned off, and the following is the closed sequence planned by the present invention. 9”; secondly, the main output 52 is stored in the next day, the signal is turned off (step = 57, then the external power is 9:1 (boundary scan), the slave is turned off, and the main output is switched). 52 (ie =; and will be internal) the boundary of the flip-flop 2 = the flip-flop 57 (step 4 redundant body 6 (step 9 3); 茫 恶 透过 透过 透过 扫描 扫描 扫描 扫描 扫描 透过 透过 透过 透过 透过 透过 透过 。 。 。 。 。 。 。 。 。 。 。 The step is to turn off the power of the block 8 (step (b) shows ^ ^ ^ thunder closed t source circuit to return to normal work, turn on the power of the program. Hang work mode, Figure four (step 95); its = turn on the power And the initialization is turned off (step 96); the second cow, the over-the-know chain will store the positive and negative crying = block 8 back to normal step 97); finally hit the power off the side, the soil <Step 9 8) In the block 8 of the closed power supply, it is necessary to perform the internal tasks of all the memory elements in the following two types: f first to turn off - set to an external memory

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V. INSTRUCTIONS (6) Body 6 (another set of flip-flops, RAM or any other memory element) causes the process to be restored in a later power-on procedure. Secondly, the power off method will float the main output 5 2 of the block 8 to be powered off, because the floating input is not allowed in the IC design, so an extra body is needed to retain the original signal. See Figure 3 again. In order to achieve the two tasks of turning off the power, FIG. 5 shows a controller 9 and a leaf. The controller 9 collects the original signals of the scan chain and the boundary scan to generate a new set of control signals to save power. Applications. ~ The original signals of the scan chain and boundary scan are used for production measurement and design test respectively. However, after the product passes the test, the original signals of the scan chain and the boundary scan are fixed at a high potential or fixed at a low potential. It is no longer used in the life cycle, so a new set of control signals must be generated for power saving based on the original signals of the scan chain and boundary scan. Scan chain and boundary know that the original # of the field contains 〇rg__s_mode, 〇rg_s__enable, rrg_bs — mode, 〇rg —bs —enable, as shown in Figure 5 on the left side of controller 9. The Power — of f, ci〇ck, and reset signals are also arranged on the left side of Figure 5 to control the controller to indicate the controller. The port is controlled to the right of the 9th output pin s_mode 43 is the internal memory component of block 8 to turn off the power to switch between the three modes of operation: normal 'operation mode, low power mode to turn off the clock signal and shift in/out mode. S-mode 43 is a bus type. As long as the number of flip-flops in the scan chain changes, the controller must be adjusted so that its output signal can meet the time. s —enable 33 switches the internal data path so that the memory element 2 can

1250454

Get different from "Test 31" or "Work 32" bs-mode 53 decide when to switch borders. Or the main output power saving mode. Bs_enable 5/ locks the clock signal 〇rg — bs —enable is the same, because this saves and outputs need to switch to memory element 57, so the external y 冤, the value of block 8. 〃路7 can always get the pw_switch 61 control power switch. Scan —clock 41 provides the scan clock. Ks is used by the internal scan chain. bs_cl〇Ck 59 is controlled by bs —mode 53 to provide the clock signal of the flip-flop 5 7 . 〃 is the boundary scan mem—i f 60 is the memory control interface, and the memory interface must be changed for different print states. &lt; fe body 9. It is not necessary to replace the control shown in Figure 5 with an included CPU. The method of the present invention utilizes existing circuits/techniques to achieve power saving purposes by adding too many circuits. The spirit and scope of the present invention are limited only by the scope of the invention described below. /'No

1250454 Simple description of the drawing [Simple description of the drawing] Figure 1 is a schematic diagram of a scanning chain circuit. Figure 2 is a schematic diagram of a boundary scan (IEEE 1 149. 1) circuit. Figure 3 is a schematic diagram of a combined scan chain circuit and boundary scan (IEEE 1149·1) circuit in synchronous logic AS I C. Figure 4 is a flow chart showing the planned power off/on power cycle procedure of the present invention. Figure 5 shows a block diagram of the control circuit of the present invention.

[Main component symbol description]

1 Logic circuit 2 Memory element 20 Output 埠3 multiplexer 31 Test signal 32 Operation signal 33 s_enab1e 4 multiplexer 41 scan clock signal (scan_c 1 ock) 42 main clock signal 43 s_m〇de 5 unit to be tested 51 main input 52 main output signal

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Claims (1)

1250454 VI. Patent Application Range &quot; ''' 1. A power saving method using scan chain and boundary scan, in a synchronous logic person with scan chain circuit and boundary scan circuit, a controller is loaded, 〇rg—, m〇de, ^ org—s—enable, orgbsm〇de, 〇rgbs—enabie, P〇Wer4—, Cl〇Ck &amp; reset signals of the scan chain circuit and the boundary scan circuit are input to the controller Generate new control signals s —mode, s — enable, bs m〇de, 汲bs—enable, pw—switch, scan_cl〇ck, bs—ci〇ck, mem-1f′ to control the scan chain circuit and boundary with the following procedure Scanning circuit. a) Turn off the power in the synchronous logic ASIC: : Heart circuit. First turn off the synchronization logic "丨c clock signal · 2) Step logic ASIC's set of main wheel ^ storage input switch circuit from the main output Memory component; 3) The chain circuit shifts the directory state of the synchronization logic (6) to an external memory port 4) turns off the power of the synchronous logic ASIC; a bean, b) opens in the synchronous logic ASIC When powering up Turn on the power and initialize the circuit to be turned off. 2) Store the number of external memory:: Back to the internal logic of the synchronous logic ASIC: Move from the known chain circuit. The turn-in end of the external circuit is switched from the edge element η. To the main output; ^Tiandian's memory 4) Start the clock signal.