TWI249854B - A thin film transistor array with an auxiliary signal line - Google Patents

Abstract

A TFT array with an auxiliary signal line comprises thin film transistors, a primary signal line and an auxiliary signal line. The TFT is formed on a glass substrate. The primary signal line is electro-connected to the TFT-gate to provide the input signal. The auxiliary signal line is electro-connected to the primary signal line. The auxiliary signal line and the TFT-gate are formed at the same time.

Description

1249854 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention: The present invention relates to a thin film transistor array, and more particularly to a thin film transistor array having a standby signal line. Prior Art: A flat panel display utilizes a thin film transistor (t h i n f i 1 m t r a n s i s t 〇 r, TFT ) array to control the display of each pixel. The operation of the thin film transistor must be controlled by the signal line (s i g n a 1 1 i n e ) and the gate line (g a t e 1 i n e ). Therefore, if the signal line or the gate line is open, it will affect the normal operation of the thin film transistor, and the halogen will not display properly. Referring to the first figure, a top view of an array of thin film transistors 1 is known. The width of the signal line 2 is much smaller than the width of the gate line 3. Therefore, the particle contamination in the process environment and the heat treatment in the process tend to cause the signal line 2 to be broken. In order to solve the problem caused by the above-mentioned disconnection of the signal line 2, a standby signal line is generally provided to provide a signal to transmit a standby line. Thereby, even if the signal line 2 is broken, the thin film transistor 1 can receive the control signal via the standby signal line. This keeps the display up and running, improving product yield and reliability. Please refer to the second figure, which is a schematic diagram of a conventional thin film transistor 1, a main signal line 30 and a standby signal line 40. The thin film transistor includes a gate 12. A first isolation layer 1 4 2 2 with a source 1 6 , a halogen electrode layer 24 a drain 1 8 a gate channel 2 0

Page 5 1249854 V. DESCRIPTION OF THE INVENTION (2) The gate 1 2 is formed on the upper surface of a glass substrate 10, and the first isolation layer % 1 4 is formed over the glass substrate 10 and covers the gate 1 2 . A gate channel 2 〇 is formed over the first isolation layer 14 and directly above the gate 12 to define an active region of the thin film transistor. The source 16 and the gate 1 are fabricated above the isolation layer 14 and are connected to both sides of the gate channel 2〇. At the same time, the main signal line 30 is also formed above the first isolation layer 14 and extends to connect the source 16 to input signals. The second isolation layer 2 2 is formed over the source 16 , the drain 18 , the gate channel 2 , and the main signal line 30 to protect the thin film transistor. The halogen electrode layer 24 is formed above the second isolation layer 22 for inputting an operating voltage to control the display of the pixel.

The spare js *5 tiger line 4 0 is made above the 2nd isolation layer 2 2, and connected to the main signal line 3 〇 through a pair of teeth 2 2 in the isolation layer 2 2, dream, this, The alternate signal line 40 can be used as a control signal to be transmitted to one of the source ports 6 to prevent the main signal line 3 from being broken. Although the problem of the main signal line 30 being disconnected can be solved by the standby signal line 4 设置 disposed above the second isolation layer 22, the following disadvantages remain to be overcome: ”

1. In general, the halogen electrode layer 24 is located on the lower surface of the light-emitting layer (not shown), and the upper surface of the light-emitting layer is formed with an upper electrode layer (not shown) and is supported by upper and lower electrodes. The potential difference of the layers drives the light-emitting layer to display 0: therefore, the standby signal line 40 is also located on the lower surface of the light-emitting layer. Since only a light-emitting layer is sandwiched between the signal line 40 and the upper electrode layer, it is easy to cause the standby signal line 4〇 to contact the upper electrode layer due to the process of manufacturing.

1249854 V. DESCRIPTION OF THE INVENTION (3) The short circuit' causes the upper electrode layer to be connected to the source J 6 via the standby signal 30, whereby the film is electrically crystallized, thus, the dead pixel. 1. The second signal layer 40 is limited to the second isolation layer 22 on the thin second isolation layer 22 to cause the standby signal line 40. In view of this, the same standby signal line 40 is the invention: = the potential of the pole layer 24 is the same (power-on, Sa is the main k-line 30, and the main signal line is the 'Beisu electrode layer 24 is connected to the bungee 18, when the bean = Kai (〇n), the source 16 and the bungee 18 are extremely similar The electrode layer 24 is equipotential), and the structure design of the dark film transistor 1 is generated. Please refer to the second figure, the surface t is not good, so when the spare signal line is formed, it is easy to be due to the second isolation layer 22 The invention is directed to an array of thin film transistors 1 which is not designed to solve the above problems. The present invention provides a thin film transistor array having a standby signal line, comprising at least one thin film transistor a main signal line and a spare signal line, the thin film electro-crystal system is fabricated on the upper surface of a glass substrate, and the main signal line is connected to the source of the thin film transistor, and the standby signal line is electrically charged. Connect to the main letter It is to be noted that the spare signal line and the idle pole of the thin film transistor can be further understood by the following detailed description of the invention and the accompanying drawings.

Page 7 1249854 V. Description of the invention (4) The embodiment shows that a membrane electrode 18 and gate 40 are also predetermined to be connected to the gate of the gate 1 2 contact gate gate. The second embodiment of the present invention is a schematic diagram of a first embodiment of the present invention, in which the thin film transistor 1, the main signal line 3 〇 and the standby signal line 4 〇, the thin body includes a The gate 1 2, a first isolation layer 14 , a germanium source 16 , a gateless channel 2 , a second isolation layer 22 and a pixel electrode layer 24 . The pole 12 is formed on the upper surface of a glass substrate 1 , and the standby signal line is formed on the upper surface of the glass substrate 10 and is kept away from the gate 12 to avoid mutual interference. The first isolation layer 14 is formed on the glass substrate 10 and covers the above-mentioned standby signal line 4 〇. At the same time, the first isolation layer 14 includes a 141 ′ to expose a portion of the spare signal line 4〇. Above the surface. The pole transit 20' is also made above the first isolation layer 14 and is located directly above. The source 16 and the drain 18 are formed on the first isolation layer 1' and connected to both sides of the gate channel 2'. The source 16 includes a zonal layer 161 and a source ohmic contact layer 丨6 2 , the source metal layer 丨6 J . The source ohmic contact layer is 162, and the gate channel 20 is connected via the source ohmic contact layer 162, and the drain electrode 18 also includes a drain metal layer ΐ8ι 接, contact layer 182, the drain The metal layer 181 covers the drain electrode 182, and the gate channel is connected via the drain ohmic contact layer 182. The signal line 30 is formed on the first isolation layer and the metal is input with an input signal. Same as, through the system - page 8 Ϊ 249854 V. Description of the invention (5) The interconnect 32 in the contact window 141 is connected to the standby signal line 40. The first __- isolation layer 2 2 is formed on the source electrode 16;; and the pole 18, above the gate channel 20 and the main ^ line 30, thereby protecting the thin film transistor 1. At the same time, the second isolation 2 includes a pole contact window 212 to expose a portion of the above-described electrodeless metal layer 181. The halogen electrode layer 24 is formed over the second isolation layer 2 2 and filled in the gate contact window 221 to be connected to the gate metal layer 181, thereby inputting an operation control pixel display. It is to be noted that the above-mentioned standby signal line 40 is formed simultaneously with the gate 1 2 . At the same time, in order to make the standby signal line 40 function, please refer to the second β / 丨 , the standby signal line 4 . The main signal line corresponding thereto is two = two = the last two connection structures 313 and 3113. The front connection structure 31 & provides control for transmission from the primary signal line 3〇 to the alternate signal line 40, and then to the 2 1 b system to provide the control number from the alternate signal line 4. Returning to the main signal β fine this, although the main k唬 line 30 is connected to the front and rear connection structures 31a and 3ib ^, the control signal is transmitted from the input terminal of the main signal line 3〇, and is transmitted from the upper two connection structure 3 1 a to The standby signal line 4〇, the description 刖π , u _ 丹 甶 甶 纟 纟 纟 纟 播 播 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 ...and Sichuan can be connected internally or its far = connection structure and 40 structure. For electrically connecting the two signal lines 3, in the first embodiment of the present invention, the process of fabricating the film line 30 and the standby signal line 40, 浐夂: -, the main letter first 'please refer to the fourth A picture, The production of the four brothers is shown.蜀 layer on a glass substrate 1 〇

Page 9 1249854 V. Inventive Description (6) The upper surface, followed by 'micro-shadowing and #etching the metal layer' to form a gate 12 and a spare signal line 40 on the upper surface of the glass substrate 10. Referring to FIG. 4B, a first isolation layer 14 is formed on the glass substrate 110, and covers the gate 12 and the standby signal line 40. Subsequently, the lithography and the remaining first isolation layer 14' form a contact window 141 to expose the upper surface of the portion of the spare signal line 40. Referring to FIG. 4C, an amorphous germanium layer 15 and a heavily doped amorphous germanium layer 19 are sequentially formed over the first isolation layer 14 to define an active region of the thin film transistor 1. Referring to FIG. 4D, a metal layer is formed over the first isolation layer 丨4 and the heavily doped amorphous layer 11, and is filled in the first contact window 41. Subsequently, the lithography and the last name of the metal layer are formed to form a source 丨6, a drain electrode 18 and a main signal line 30, and a gate channel 2〇 is also formed on the source electrode 16 and the above Bungee between 18. In addition, the main signal line 3 is extended to the source 16 while being connected to the standby signal line 4 through an interconnect 32 located in the first contact window 141. : Green Mai, according to Figure 4E, a second isolation layer 22 is formed above the source 16, the drain, and the main signal line 3 . And, lithography and /

^ Separation layer 22: On > into a bungee contact window 221 to expose a portion of the surface of the bungee. A conductive layer 24 is formed over the second isolation layer 22: the gate contact opening 221 is joined to the drain electrode 18. The value of the message is that, for the gentleman, the line 3 〇 and the alternate signal line 2, the line 32 to connect the main letter, the lithography process and a surname of the purple pass ==, the body of a separation layer 14 A private layer is formed to form the first contact window 141.

Page 10 1249854 V. Inventions (7) Medium & Please refer to? FIG. 5 is a schematic view showing a second embodiment of the present invention, a film ί rm crystal 1, a main signal line 3 〇 and a standby signal line 40. The first day, the electric day body 1 includes a gate 12, a first An isolation layer 14, a source 16, 2*7 and =, a gate channel 20, a second isolation layer 22 and a pixel electrode are used: 40 a connection structure 31 is used to connect the main signal The line 30 and the backup gate 1 2 are fabricated on the upper surface of a glass substrate 1 , and the spare scorpion 4 is fabricated on the upper surface of the glass substrate 10 and with the interpole 12; Interference. The first isolation layer 14 is formed on the glass and covers the gate 1 2 and the standby signal line 4 闸 „ gate channel 20, which is also formed above the first isolation layer 14 and located at / The source 16 and the drain 18' are fabricated on the first isolation layer and are connected to the s sub-channel and connected to the two sides of the gate channel 2. The source 16 includes the 1R1^W genus layer 1 a source ohmic contact layer 162, the source metal layer $ rewinds the source ohmic contact layer 丨62, and via the source ohmic contact layer = the gate channel 20', and the drain electrode 18 also includes a immersion gold The samarium layer 181 is connected to a drain ohmic contact layer 182, which is 哕=ohm=contact layer 182, and is connected to the 迢20 via the drain ohmic contact layer 182. At the same time, the main signal line 3 〇 is also fabricated on the first isolation layer " and is connected to the source metal layer 丨6 1 to input signals: the isolation layer 22 is fabricated on the source 16 and the drain 18' gate channel 2 Above the line k 0, to protect the thin film transistor | is separated by = 2. Including a contactless window 221 to expose the part = on page 11 1249854 DESCRIPTION OF THE INVENTION (8) The halogen electrode layer 24 is formed above the second isolation layer 22, and is not transparent. The pole contact _ 2 2 1 is connected to the electrodeless metal layer 1 8 1 ' by inputting an operating voltage to control the element. The connection structure 31 includes a first plug 311, a conductive connection 312 and a first plug 313, wherein the first plug 311 extends perpendicularly through the first isolation layer 14 and the second isolation layer 22, The second plug 313 is perpendicular to the second isolation layer 22. The conductive connection 312 is formed on the upper surface of the second isolation layer 22, and is respectively connected to the standby signal through the first plug 311 and the second plug 313. The line 4〇 and the main signal line 30. It should be noted that the first plug 311 and the second plug 313 can be used for the second isolation of the lithography by using the reticle pattern for the second isolation layer 22. When the layer 22 is 'simultaneously defined its position. The first plug 3 11 and the second plug 3 1 3 are made by the subsequent process. In the first embodiment, please refer to the fourth b diagram, in / After the first isolation layer 14 is formed, the first isolation layer 14 must be subjected to a lithography and etching process to expose the spare. The line is 4〇, and by the subsequent process, the interconnect 32 is made to connect the main signal line 30 with the standby signal line 4. Therefore, in this embodiment, a lithography process and an etching process can be omitted. In the present invention, the standby signal line 4 is formed simultaneously with the gate 12 of the thin film transistor 1, and the advantages are as follows:

In general, the halogen lower electrode layer 241 is located below a light-emitting layer (not shown), and the upper surface of the light-emitting layer is formed with an upper surface), and the upper and lower electrode layers are expensive A &; ^ Cut the potential difference, drive the light layer to display. Since at least one first isolation layer 14 盥 a second isolation layer 22 is protected above the spare signal line 4 〇 μ ^ ^ 丄 <, the 信号 ^ □ mouth can avoid the standby signal line 40

Page 12 1249854 V. INSTRUCTIONS (9) The upper electrode layer contacts cause a short circuit to prevent dark spots. 1. Please refer to the second figure. In the prior art, the flatness of the upper surface of the second isolation layer 2 2 is not good. Therefore, the spare signal line 4 is formed on the second isolation layer 2 2 . The undulation of the isolation layer 22 causes the spare signal line 4 to be uneven in thickness and even creates an open circuit. In contrast, the standby signal line 40 of the present invention is directly formed on the upper surface of the flat glass substrate 1 to help improve the uniformity of the thickness of the standby signal line 40 and prevent the occurrence of an open circuit. In the first embodiment and the second embodiment, the gate electrode 12 is directly formed on the upper surface of the glass substrate 10. However, the present invention is not limited thereto. Please refer to the sixth embodiment, which is a schematic view of a third embodiment of the present invention. A thin film transistor i, a main signal line 30 and a standby signal line 40 are shown. The thin film transistor 1 includes a gate channel 20, a first isolation layer 丨4, a gate 12, a second isolation layer 2, a source 16 and a drain 18. Wherein, the source electrode 16 and the drain electrode 18 are formed on the upper surface of a glass substrate 1 and the gate, the channel 20' is also formed on the upper surface of the glass substrate 1 and connected to the source 1 6 with no poles 1 8. The first isolation layer 14 is formed over the glass substrate 1 and covers the source 16, the drain 18 and the gate channel 20. The gate electrode 12 is formed on the upper surface of the first isolation layer 丨4 and is located directly above the gate channel 20. The standby signal line 4 is also formed above the first isolation layer 14 and is kept at a predetermined distance from the gate 12 to avoid mutual drying. The second isolation layer 22 is formed over the gate 12, the backup signal line 40 and the first isolation layer 14, and the second isolation layer 22 includes a second contact window 222 to expose the standby signal line 40. The main signal line 3 is made above the second isolation layer 2 2 and connected to the above

Page 13 1249854 V. INSTRUCTION DESCRIPTION (10) J is connected to the standby signal line by inputting a display signal and simultaneously through a second L-connected line 32 formed. A schematic diagram of a fourth embodiment of the present invention is shown in the figure, wherein the main signal line 30 and the standby signal line 40 are shown. _忒溥膜电, body 1 includes a gate channel 20, a first isolation layer 14 , an f pole 1 2 , a second isolation layer 2 2 , a source 16 , a drain 1 8 and a The third f-layer 2 6 is further connected to the main signal line 3: the standby signal line 4〇. The source 16 and the immersion 18 are formed on the upper surface of a Bolivia substrate 10, and the gate channel 20 is also formed on the upper surface of the glass substrate 1 'and the source 16 and the drain 1 are connected. 8. The first isolation layer 14 is formed over the glass substrate 10 and covers the source 16, the drain 18 and the gate channel 20.

The interpole 12 is formed on the upper surface of the first isolation layer 丨4 and is located directly above the gate channel 20. The standby signal line 4 is also formed above the first isolation layer 14 and is kept at a predetermined distance from the gate 12 to avoid mutual interference. The second isolation layer 2 2 is formed over the gate 1 2, the standby signal line 40 and the first isolation layer 14 . The main signal line 3 is formed over the second isolation layer 2 2 and is connected to the source 丨 6 to input a display signal. The third isolation layer 26 is formed over the second isolation layer 2 2 and covers the main signal line 3 〇. The connection structure 31 includes a first plug 311, a conductive connection 312 and a second plug 313, wherein the first plug 311 extends perpendicularly through the second isolation layer 22 and the third isolation layer 26, and the second The plug 313 is perpendicularly penetrated through the third isolation layer. The conductive connection 312 is formed on the upper surface of the third isolation layer 26, and is connected to the first plug 3 11 and the second plug 3 1 3 through the first plug 3 11 and the second plug 3 1 3 respectively. Signal line 4 0

Page 14 1249854 V. Description of invention (11) and main signal line 30. The scope of the present invention is described in detail by the preferred embodiments of the invention, and the scope of the invention is to be understood by those skilled in the art. Not limiting, not doing it properly

Page 15 1249854 Brief Description of the Drawings Brief description of the drawings: 'The first figure is a schematic diagram of a conventional thin film transistor array. The second figure is a schematic cross-sectional view of a conventional thin film transistor, a main signal line and an alternate signal line. Fig. 3A is a schematic view showing a first embodiment of the present invention, showing a thin film transistor, a main signal line and an alternate signal line. The third B diagram is a schematic diagram of the standby signal line of the present invention connected to the main signal line, and the standby signal line is connected to the main signal line through the front and rear connection structures. ❿ FIGS. 4A to 4E are schematic cross-sectional views showing the manufacturing process of the thin film transistor, the main signal line and the standby signal line in the first embodiment of the present invention. Figure 5 is a schematic view of a second embodiment of the present invention showing a film, a transistor, a main signal line and an alternate signal line. Fig. 6 is a schematic view showing a third embodiment of the present invention, showing a thin film transistor, a main signal line and an alternate signal line. Figure 7 is a schematic view showing a fourth embodiment of the present invention, showing a thin film transistor, a main signal line and an alternate signal line. φ Figure No. Description: Thin Film Transistor 1 Signal Line 2 Gate Line 3 Glass Substrate 1 0

Page 16 1249854

The figure briefly illustrates the gate 1 2 the first isolation layer 1 4 the amorphous germanium layer 1 5 the heavily doped amorphous germanium layer 1 9 source 1 6 the drain 1 8 the source metal layer 1 6 1 the source ohmic contact layer 1 6 2 汲 metal layer 1 8 1 ohmic contact layer 1 8 2 gate channel 20 second isolation layer 2 2 昼 电极 electrode layer 2 4 third isolation layer 2 6 main signal line 30 spare signal line 40 connection structure 31 First plug 311 conductive wire 312 second plug 313 front connection structure 3 la rear connection structure 3 lb inner wire 3 2 first contact window 1 4 1 second contact window 2 2 2 bungee contact window 2 2 1 Page 17

Claims (1)

1249854 VI. Patent application scope Patent application scope: 1. A thin film transistor array with a standby signal line, comprising at least: a thin film transistor formed on an upper surface of a glass substrate; a main signal line electrically connected to a source of the thin film transistor; and a standby signal line electrically connected to the main signal line, and the standby signal line is formed simultaneously with the gate of the thin film transistor. 2. The thin film transistor array of claim 1, wherein the thin film transistor comprises at least: a gate formed over a glass substrate; a first isolation layer covering the gate; a source And a drain electrode is formed on the first isolation layer and on both sides of the gate; and a second isolation layer is formed on the gate, the source, the drain and the first isolation Above the layer. 3. The thin film transistor array of claim 2, wherein the main signal line is formed between the first isolation layer and the second isolation layer, and the standby signal line is formed on the glass substrate and the Between the first isolation layers. 4. The thin film transistor array of claim 3, wherein the standby signal line is connected to the main signal line through a connection structure. 5. The thin film transistor array of claim 4, wherein the connection structure comprises an interconnect extending through the first isolation layer. 6. The thin film transistor array of claim 4, wherein the connection structure comprises a first plug, a conductive wire and a second plug, the first plug Page 18 1249854 6. The scope of the patent application is perpendicular to the first isolation layer 盥哕 _ flat on the second isolation layer "- isolation layer, the conductive connection is a water isolation layer, wherein the second :: 'The second plug is connected to the second 7-wire'. The second plug is connected to: the J::: ΐ line and the conductive connection. The film of the sixth item of the patent scope is as follows. Electric carcass, array ^ electric connection. The wire is made of indium tin oxide.曰曰 车 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 • • • • • • • • Includes a gate bungee. ""6 above and connecting the source with the 10th, as in the second paragraph of the patent application, including a source metal layer, a cowpea 1 in which the source metal layer is f is a ^ ^ ^ non-daily 矽 ohmic contact layer, and the source Λ / V heavily doped amorphous 矽 ohmic contact layer upper surface. The thin film transistor = genus layer and a heavily doped amorphous (four) ohmic contact layer of the second aspect of the invention are fabricated on the upper surface of the heavily doped amorphous ohmic contact layer. The thin film transistor array of the first aspect of the invention, wherein the thin film transistor comprises at least: a pole and a drain are formed on a glass substrate; Above the substrate, covering the source and the electrode; a polarity is formed over the first isolation layer; and a second isolation layer is formed on the gate and the first isolation layer 1249854 6. The scope of application for patents. 1. The thin film transistor array of claim 12, wherein the main signal line is formed over the second isolation layer, and the alternate signal line is formed in the first isolation layer and the second isolation Between the layers. Wherein the standby film is a thin film transistor array according to claim 13 of the patent application, wherein the connecting signal line is connected to the main signal line through a connection structure. The crystal array has a structure including an inner wiring extending through the second isolation layer. 1 6 · If the thin film transistor array of claim 14th is applied, the other is a three-layer isolation layer, which is formed above the second isolation and covers the two (four) 'line', and the material connection structure includes - a first plug, a conductive plug, the first plug extends vertically through the second isolation layer, and the conductive connection is horizontally formed on the third isolation layer. The third isolation layer, wherein the second surface, the first signal line is connected to the conductive line, and the second plug system is connected to the conductive connection. ^ Main signal reel where the conduction is the first _ a as applied for w: 2 indium tin oxide as material. The pole channel layer is formed in the array of the thin film and the membrane transistor, and further includes a closed bungee. Above _ and connected to the source and the 20" type of thin film transistor array with a "Tiger line, each of which is electrically ~ The inter-electrode is formed on the upper surface of a glass substrate; ~, is formed on the upper surface of the glass substrate by a signal line; the inter-core and the ί: isolation layer are formed on the glass substrate while covering the ~W 1 a signal line; a read gate channel is formed above the first isolation layer and above an isolation layer, and is connected above an isolation layer, extending to the connection structure, extending the connection to the vibration tow And a drain electrode, the two sides of the first gate channel are formed; the interface, the main signal line is formed at the first source to the input signal, and at the same time, via the standby signal line; a second isolation layer is fabricated The source electrode and the main signal line are above; and the δ 闸 gate electrode and the 昼 电极 electrode layer are formed above the second isolation layer. 2 1 . The thin film transistor array of claim 20, wherein the structure comprises a contact window extending through the first isolation layer. 〃 Τ ~ connection 22 · The thin film transistor array of claim 20, the pot structure comprises a first plug, a conductive wire and a first-second, middle / connecting plug system vertically through the first The isolation layer and the second isolation #, the social, ., ^, Angstrom level is formed on the upper surface of the second isolation layer, the first: cup two conductive connection system / coin - plug transmission two isolation layer, wherein The first plug is connected to the device for use as a ',,>: brother connection, the second plug is connected to the main signal line and the conductive and the conductive 23 · the film of claim 22 The transistor Chen "connects. Dry 5^, where the conductive Page 21 1249854 VI. Scope of Application The connection is made of indium tin oxide. 2 4. The application of the patent range 2 3 # plug and the second plug # > a tie film transistor array, wherein the first system comprises - source metal 曹 曹 Cao / membrane transistor array, The source metal layer is produced. Heavy; Ϊ: Ϊ amorphous contact layer, and the source 26. As claimed in the patent scope ^ /, "Xi Qing, ^,, brother 2 浔 浔 电 电 电 电 、 、 、 、 、 、 、 、 The ohmic contact between the maser® and the epitaxial layer and a heavily doped amorphous yttrium, ϋ:» The epitaxial metal layer is fabricated on the heavily doped amorphous ohmic contact layer 汲27. a thin film electro-crystal surface of the wire. The manufacturing method comprises the following steps: a coating method for providing a glass substrate; preparing a first metal layer on the upper surface of the glass substrate; lithography and etching the first metal layer to form a gate a pole is formed on the glass substrate; a first isolation layer is formed on the W^ line to cover the gate and the standby signal line; and an amorphous germanium layer and a heavily doped amorphous germanium layer are sequentially formed; X is isolated a lithography and a residual amorphous layer and the active region of the heavily doped amorphous germanium, 6 thin film transistor; 曰 该 该; a metal layer is formed on the first isolation layer and the heavily doped amorphous Lithography on the enamel layer and etching the metal layer to form a source, a drain, and a 戚 line /, 土要1吕第22页1249854 VI. Applying for the patent scope to make a first isolation layer covering the source and the line; and 4> and the pole to make a connection structure with the main signal, respectively extending the connection signal line. a Hai main 2 8 · The manufacturer's signal line of the 27th item of the patent application and the preparation method' wherein the steps of fabricating the connection structure include: lithography and etching the first isolation layer, step _ spare signal line; Forming a first contact window to expose the fabrication of an interconnect to the first contact window, the line, and the alternate signal line. 'To connect the main signal 2 9 as in the fabrication of claim 27 The method includes: '' wherein the connection junction is made to make a first plug through the first connection to the standby signal line; and the second isolation layer is formed to start making a second plug through the second isolation layer, And a day of connecting the main signal to form a conductive connection to the first plug and the second plug of the second isolation layer. The upper surface is connected to the conductive connection system 30. The manufacturer according to claim 29 of the patent application uses indium tin oxide as a material, and 3^, as in the production method of the third aspect of the patent application, ... the second plug Indium tin oxide is used as the material.第一 the first plug and 32. According to the manufacturing method of claim 27, in the step of the metal layer, the amorphous germanium layer and the germanium layer are in the lithography and etching isolation layer for the insect insect 1249854 Page 24