12492Q§5twf.doc/m 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構及其製程，且特別 是有關於一種晶圓級封裝製程與晶圓級晶粒尺寸封裝結 構。 【先前技術】 一近年來，隨著半導體製程技術的不斷成熟與發展，各 種尚效能的電子產品不斷推陳出新，而積體電路 (integrated circuit，1C)元件的積集度（integrad〇n)也不 斷提高。在積體電路元件之封裝製程中，積體電路封裝〇c packaging)扮演著相當重要的角色’而積體電路封裝型離 可大致區分為打_合封裝（wke bQnding paekaging， packaging) > (tape aut〇matic packaging，TAB packaging)與覆晶接合封裝（flip cWp packaging，FCpackaging)等型式，且每種封裝形式均具有 其特殊性與應肖躺。值雜冑暇，無論何麵裝方式 均需要-承載HUarrieO，且承載器上之接腳係與晶片 上之接墊（bondingpad)電性連接，其中承載器例如是導 線架（lead frame)或基板（substrate) 〇 圖1繪示習知的光學元件封裝結構的剖面示意圖。請 參照m ’習知的光學元件封I结構刚適於發射或接收 -光束臟，而習知的光學元件封裝結構i⑼包括一承載 基板110、-晶片120、-透明玻璃基板13〇、多條鲜線 (bonding wire) 140與多個銲球15〇，其中承載基板11〇 I2492ft§5twf,oc/m 具有-凹槽112、-第-表面11C)a與相對於第一表面· 之一第二表面110b’而凹槽112係位於第一表面上110b。 ，外，晶片120係配置於承載基板110之凹槽112内而 晶片120係藉由多條銲線14〇與承載基板11〇電性連接。 f =，透明玻璃基板13〇係配置於承載基板11〇上並覆 蓋晶片I20。再者，銲球150係配置於承載基板11〇之第 二表面ii〇b上，且銲球150係依序經由承载基板11〇與銲 線140電性連接至晶片12〇。 、 承上所述’光線l〇〇a能夠經由透明玻璃基板而出 射至外界，或者經由透明玻璃基板13〇而入射至晶片 上。值得一提的是，由於晶片120係配置於承載基板ιι〇 之凹槽内’因此承餘板11G的厚度也就無法進一步縮 小，進而造成承載基板110所佔的成本比重偏高。此外， 晶片120係藉由銲線14〇與承載基板no電性連接，也造 成習知的光學元件封裝結構100的厚度無法進一步縮小, 【發明内容】 ' 有鑒於此，本發明的目的就是在提供一種晶 製程，以製造出成本較低的晶粒尺寸封裝結構。、子裝 此外，本發明的再一目的是提供一種晶圓級晶粒尺 封裝結構，其具有較薄的厚度。 基於上述目的或其他目的，本發明提出一種晶圓級封 裝（wafer level packaging)製程，其包括下列步驟。首先， 提供一晶圓，而晶圓具有一第一表面、相對於第一表面之 一第二表面及至少一切割道。在晶圓之第一表面上形成多 I2492Q!域。c/m 個盲孔（blindhole) ’其中晶圓具有多個第一接塾，且這 些盲孔的位置齡騎應至這m減巾之-的位 置。然後，在這些盲孔内形成多個導電柱（conductive plug)，其中母一導電柱的一端係分別與這些接墊其中之 一電性連接。在晶圓之第一表面上配 i多個膠框'glue f職）’接著在這轉框上配置—基板，其巾基板與晶圓 之間係藉由這些膠框維持一間隙（gap)。之後，研磨晶圓， 以暴露出每一導電柱的另一端。 依照本發明較佳實施例，上述之在研磨晶圓之前，更 包括在基板上配置一保護膜。 依照本發明較佳實施例，上述之在晶圓上配置膠 框之步驟中，膠框係配置於晶圓之切割道上。 依照本發明較佳實施例，上述之在晶圓上配置這些膠 框之後’更包括將多個導電塊，分別 配置於這些第一接墊上，而每一導電塊係分別接觸基板與 這些第一接墊。 依照本發明較佳實施例，上述之在研磨晶圓之後，更 包括進行一切割製程。 依照本發明較佳實施例，上述之在研磨晶圓之後，更 包括晶圓之第二表面上形成多個第二接墊，且每一第二接 墊係分別連接這些導電柱其中之一。此外，在形成這些第 二接墊之後，更包括在這些第二接墊上形成多個銲球。 依照本發明較佳實施例，上述之在研磨晶圓之後，更 包括在晶圓之第二表面上形成一重配線路層（redistribution I2492Q&_m layer，RDL)，且重配線路層係與這些導電柱電性連接。 此外，在形成重配線路層之後，更包括在重配線路層上形 成夕個I于球，且這些銲球係經由重配線路層電性連接至這 些導電柱。 依照本發明較佳實施例，上述之在盲孔内形成導電柱 之方法例如是一填孔電鍍（viaflllingplating)製程。 依照本發明較佳實施例，在盲孔内形成導電柱之方法 包括先在盲孔之内壁上形成一金屬層，然後在盲孔内形成 一核心導體層。 依照本發明較佳實施例，在晶圓上形成盲孔之方法例 如是一雷射鑽孔製程（laser drilling process )。 “基於上述目的或其他目的，本發明提出一種晶圓級晶 粒尺寸封裝（wafer level chip scaie package，wj^csp)結 構，其包括一晶片、一膠框與一基板。晶片具有一第一表 面、相對於第一表面之一第二表面、多個第一接墊與多個 導電柱，其中這些第一接墊係位於第一表面上。此外，這 些導電柱貫穿晶片，且這些導電柱係分別與這些第一接墊 其中之一連接。另外，膠框係配置於晶片之第一表面上， 而基板係配置於晶片之第一表面上，其中基板 係藉由這些膠框維持一間隙。 依照本發明較佳實施例，上述之晶片與基板及膠框之 外側邊緣例如是切齊。 依照本發明較佳實施例，晶圓級晶粒尺寸封裝結構更 包括多個導電塊，其係分別配置於這些第一接塾上，其中 I2492Q§5twf.doc/m 每一導電塊係分別接觸基板與這些第一接墊其中之一。 依照本發明較佳實制，上述之晶4更包括多個第二 接塾’其伽置於第二表面上，其巾每-接㈣分別與這 些導電柱其巾之—紐連接。此外，上述之晶®級晶粒尺 寸封裝結構更包括多個銲球，其係分別配置於這些第二接 塾上。 依照本發明較佳實施爿，上述之晶片t包括一重配線 路層’其係gi置於第二表面上，且重配線路層係與這些導 電柱電性連接。此外，上述之晶®級晶粒尺寸封裝結構更 包括多個銲球，其係分別配置於重配線路層上，且這些銲 球係經由重配線路層電性連接置這些導電柱。 依照本發明較佳實施例，上述之每一導電柱分為一核 心導體層以及在核心導體層外圍之一金屬層。此外，核心 導體層之材質例如是金屬或銲料（solderpaste)。 依照本發明較佳實施例，上述之基板之材質例如是透 明玻璃。 基於上述，本發明之晶圓級封装製程在晶圓内形成導 因此晶圓便可直接基板（透明基板）進行組裝，以 製造出成本較低的晶圓級晶粒尺寸封襞結構。此外，本發 明之晶圓級晶粒尺寸封裝結構具有較薄的厚度以及較佳的 電性品質。 ★為讓本發明之上述和其他目的、特徵和優點能更明顯 易丨董，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 I2492Qg 5twf.doc/m 【實施方式】 【第一實施例] 圖2A至圖2F繪示依照本發明第一較佳實施例之晶圓 級封裝製程的剖面示意圖。請先參考圖2A，本實施例之晶 圓級封裝製程包括下列步驟。首先，提供一晶圓21〇，而 晶圓210具有一第一表面212a、相對於第一表面212&之 一第二表面212b、至少一切割道21〇a與多個第一接墊 214，其中第一接墊214係位於第一表面212&上。此外， 晶圓210之材質例如是石夕或是三五族元素。 然後，在晶圓210之第一表面212a上形成多個盲孔 212c’且這些盲孔212c的位置係分別對應於這些第一接墊 214的位置上。換言之，盲孔212c的位置係與第一接墊214 的位置重豐。此外，形成盲孔2i2c的方法例如是雷射鑽孔 製程或是其他鑽孔製程。值得注意的是，盲孔212c必須避 開晶圓210上之線路，以避免在形成盲孔212e損傷線路。 請參照圖2B ’在這些盲孔212(；内形成多個導電柱 220 ’且母一導電柱220的一端係分別與這些第一接墊214 其中之一連接，其中形成多個導電柱22〇之方法例如是填 孔電鍍製程。接著，在晶圓21〇之第一表面212a上配置多 個膠框230。 在另一較佳實施例中，形成導電柱220之方法例如是 先在盲孔212c之内壁上形成一金屬層222，然後於盲孔 212c内形成一核心導體層224 (如圖2B之虛線區域所 不），其中形成金屬層222的方式例如是電鍍製程，而形 I2492Q§ 5twf.doc/m 成核心導體層224的方式例如是將金屬、焊料或是其他導 體材料填入盲孔212c内。 請參照圖2C，在膠框230上配置一基板24〇，其中基 板240與晶圓210係藉由這些膠框23〇維持一間距D。換 言之，基板240與膠框230係堆疊於晶圓21〇上，其中膠 框230例如是配置於晶圓21〇之切割道21加的兩側上。此 外’膠框230之設計能夠避免外界水汽對於在晶圓21〇之 第一表面212a上的線路造成損傷。然後，在基板上配 置保邊膜25〇 ’以便於在隨後的製程中保護基板24〇的 表面，而保護膜250例如是研磨膠帶（grindi 他膠層。 請參照圖2D，研磨晶圓210’以暴露出這些導電柱22〇 之另一端。換言之，晶圓210之第二表面212b係暴露出這 些導電柱220。此外’上述研磨晶圓21㈣方法例如是化 (chemical mechanical polishing, CMP) 提的是，在研磨晶圓2l〇的過程中，保護膜25〇能夠避 免，板240的表面受到損傷，然而在研磨晶圓21〇的過程 中部不需要配置保護膜祝才能避免基板的表面 受到損傷’亦可採用其他方式。 凊參照圖2E’然後在第二表面212b之這些導電柱220 上形成多個第二接墊216 ’其中每一第二接整216係分別 與這些導電柱220其中之-連接。此外，形成第二接墊216 的方式例如是先於第二表面212b上形成一導體材料層（未 繪不）’再對於此導體材料層進行-圖案化製程（patterning I2492Q§5twf,oc/m process) ° 在形成第二接墊216之後，於這些第二接墊216形 f多個銲球260 ’因此第一表面212a上之第一接墊214 ^ 能夠依序經由導電柱22〇與第二接墊216電性 %〇。最後，對於上述製程所形成之結構體進行切割製 後’再移除保護層25〇，以形成多個晶圓級晶粒尺寸 結構200 (如® 2F所示）。有關於晶圓級 二 構200將詳述如後。 〜了對裝結 請繼續參照圖2F，晶圓級晶粒尺寸封裝結構2〇〇包括 晶片212、膠框230、基板240與多個銲球26〇，其中晶片 212例如是光學元件、影像感測元件或是其他元件種=的 晶片。此外，晶片212具有多個第一接墊214、多個第二 接墊216與多個導電柱230。另外，第一接墊214與第: 接墊216係分別位於晶片212之第一表面212&與第^表: 212b上，且每一個導電柱23〇係分別電性連接對應之第一 接墊214與第二接墊216之間。 " 另外，膠框230與基板240係堆疊於晶片212之第一 表面212a上，其中基板240與晶片212之間係藉由膠框 230維持間隙D。再者，銲球260係配置於第二接墊216 上，其中母一銲球260係分別電性連接至這些第二接墊216 其中之一。上述之基板240之材質例如是透明玻璃、石英 或是其他透明材質。 、 更詳細而言’當晶片212為光學元件時，第一表面B2a 為主動表面，因此第一表面212a上的線路能夠經由導電柱 12 I2492Q§5twfd〇c/m 230電性連接至鲜球260 ’以便於電性連接至一外界電路 (未繪示）。相較於習知技術，本發明之晶圓級晶粒尺寸 封裝結構200係採用導電柱230傳輸訊號，因此本發明之 晶圓級晶粒尺寸封裝結構200具有較佳的電性品質。此 外’相較於習知技術，本發明之晶圓級晶粒尺寸封裝結構 200的厚度較薄，且本發明之晶圓級晶粒尺寸封裝結構2〇〇 的成本也較低。 【第二實施例】 圖3繪示依照本發明第二較佳實施例之晶圓級晶粒尺 寸封裝結構的剖面示意圖。請參照圖3，第二實施例與第 =實施例相似，其不同之處在於：第二實施例之晶圓級晶 粒尺寸封裝結構3〇〇更包括多個導電塊370，其係分別配 置於第一接墊214上，其中每一導電塊37〇係分別接觸基 才f 240與第一接墊214其中之一。此外，導電塊37〇例如 是導電膠塊或是其他導電的彈性體。另外，形成導電塊37〇 的T式例如是將基板240配置於晶圓21〇之前（類似圖2B 所不），將導電塊370配置於各個第一接墊214上，再將 基板240配置於晶圓210上。 承上所述，由於基板24〇上會累積靜電，因此導電塊 370能，將靜電導引至銲球26〇，以便於傳導至外界電路 ^換a之，導電塊370的設計不僅能夠避免基板24〇與 晶片212之間產生靜電放電，則呆護晶片212内的電子元 件，=降低靜電對於晶片212的電磁干擾。 讀繼續參照圖3，晶圓級晶粒尺寸封裝結構更包 13 I2492Qg5twf,oc/m 括一重配線路層380,其係配置於第二表面212b上。此外， 銲球260係經由重配線路層380係與這些導電柱220電性 連接。換言之，藉由重配線路層380的設計，銲球260的 間距（pitch)與佈局（iayout)將不受限於導電柱220的 間距與佈局。另外，形成重配線路層380的方式例如是在 暴露出導電柱220之後（類似圖2D所示），在第二表面 212b上形成重配線路層38〇。 承上所述，基板240、晶片212及膠框330之邊緣例 如疋切齊。舉例而言，膠框330係配置於切割道21〇3上（類 似圖2B所繪示），因此切割製程不僅切割基板24〇與晶 圓210，更是將膠框33〇 一分為二，以使基板24〇、晶片 212及膠框330的邊緣切齊。值得注意的是，第二實施例 與第二實施例之各種變化組合，亦為本發明所揭露之範圍。 細上所述，本發明之晶圓級封裝製程與晶圓級晶粒尺 寸封裝結構具有下列優點·· 、相較於習知技術，本發明之晶圓級封裝製程能夠 直接將晶®與基板（透板）進行組裝，以製造出成本 較低的晶圓級晶粒尺寸封裝結構。 二、 相較於習知技術使用承載基板以承載晶片，本發 明之晶圓級晶粒尺寸封裝結構具有較薄的厚度。 三、 相較於習知技術使用銲線電性連接基板與晶片， =明之晶圓級晶粒尺寸封裝結構使用導電柱電^連接晶 佳本發明之晶圓級晶粒尺寸封裝結構具有較 I2492Qg5twf.doc/m 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 t範圍内’當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示習知的光學元件封裝結構的剖面示意圖。 圖2A至圖2F繪示依照本發明第一較佳實施例之晶圓 級封裝製程的剖面示意圖。 圖3繪示依照本發明第二較佳實施例之晶圓級晶粒尺 寸封裝結構的剖面示意圖。 【主要元件符號說明】 100:習知的光學元件封裝結構 100a :光束 110 :承載基板 110a、212a :第一表面 ll〇b、212b :第二表面 112 :凹槽 120、212:晶片 130 :透明玻璃基板 140 :銲線 150、260 :在旱球 200、300··晶圓級晶粒尺寸封裝結 210 :晶圓 210a :切割道 12492(1 5twf.doc/m 212c :盲孔 214 :第一接墊 216 :第二接墊 220 :導電柱 222 :金屬層 224 :核心導體層 230、330 :膠框 240 :基板 250 :保護膜 370 :導電塊 380 :重配線路層12492Q§5twf.doc/m IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure and a process thereof, and more particularly to a wafer level package process and wafer level grain size Package structure. [Prior Art] In recent years, with the continuous maturity and development of semiconductor process technology, various effective electronic products are constantly being introduced, and the integration of integrated circuit (1C) components is constantly increasing. improve. In the packaging process of integrated circuit components, the integrated circuit package 扮演c packaging) plays a very important role' and the integrated circuit package type can be roughly divided into w_bQnding paekaging (packaging) > ( Tape aut〇matic packaging, TAB packaging) and flip-chip packaging (flip cWp packaging, FC packaging) and other types, and each package has its own special features and should be lying. The hodgepodge is required to carry the HUarrieO regardless of the surface mounting method, and the pins on the carrier are electrically connected to the bonding pads on the wafer, wherein the carrier is, for example, a lead frame or a substrate. (Substrate) FIG. 1 is a schematic cross-sectional view showing a conventional optical component package structure. Please refer to the m 'known optical component package I structure just adapted to emit or receive - the beam is dirty, and the conventional optical component package structure i (9) includes a carrier substrate 110, a wafer 120, a transparent glass substrate 13, and a plurality of a bonding wire 140 and a plurality of solder balls 15 〇, wherein the carrier substrate 11 〇I2492 ft § 5 twf, oc / m has a groove 112, a - surface 11 C) a and a first surface relative to the first The two surfaces 110b' and the grooves 112 are located on the first surface 110b. The wafer 120 is disposed in the recess 112 of the carrier substrate 110, and the wafer 120 is electrically connected to the carrier substrate 11 by a plurality of bonding wires 14A. f =, the transparent glass substrate 13 is disposed on the carrier substrate 11 and covers the wafer I20. Furthermore, the solder balls 150 are disposed on the second surface ii 〇b of the carrier substrate 11 , and the solder balls 150 are electrically connected to the wafer 12 依 via the carrier substrate 11 〇 and the bonding wires 140 . The light ray can be emitted to the outside via the transparent glass substrate or incident on the wafer via the transparent glass substrate 13 . It is worth mentioning that since the wafer 120 is disposed in the recess of the carrier substrate ι, the thickness of the bearing plate 11G cannot be further reduced, and the cost of the carrier substrate 110 is relatively high. In addition, the wafer 120 is electrically connected to the carrier substrate no by the bonding wire 14 , and the thickness of the conventional optical component package structure 100 cannot be further reduced. [In view of the above], the object of the present invention is A crystal process is provided to produce a lower cost grain size package. Sub-assembly Further, it is still another object of the present invention to provide a wafer level die-scale package structure having a relatively thin thickness. Based on the above objects or other objects, the present invention proposes a wafer level packaging process including the following steps. First, a wafer is provided, and the wafer has a first surface, a second surface relative to the first surface, and at least one scribe line. A plurality of I2492Q! domains are formed on the first surface of the wafer. c/m blind holes ‘where the wafer has a plurality of first ports, and the positions of the blind holes are set to the position of the m-negative. Then, a plurality of conductive plugs are formed in the blind holes, wherein one end of the mother-conductive pillars is electrically connected to one of the pads, respectively. The first surface of the wafer is provided with a plurality of plastic frames, and then the substrate is disposed on the frame, and a gap is maintained between the substrate and the wafer by the plastic frame. . Thereafter, the wafer is ground to expose the other end of each of the conductive posts. According to a preferred embodiment of the present invention, before the wafer is polished, the method further includes disposing a protective film on the substrate. According to a preferred embodiment of the present invention, in the step of arranging the plastic frame on the wafer, the plastic frame is disposed on the cutting track of the wafer. According to a preferred embodiment of the present invention, after the plastic frames are disposed on the wafer, the method further includes: arranging a plurality of conductive blocks on the first pads, and each of the conductive blocks respectively contacting the substrate and the first Pads. According to a preferred embodiment of the present invention, after the wafer is polished, the method further includes performing a cutting process. According to a preferred embodiment of the present invention, after the wafer is polished, a plurality of second pads are formed on the second surface of the wafer, and each of the second pads is connected to one of the conductive pillars. In addition, after forming the second pads, a plurality of solder balls are formed on the second pads. According to a preferred embodiment of the present invention, after the wafer is polished, a re-distribution layer (redistribution I2492Q&_m layer, RDL) is formed on the second surface of the wafer, and the wiring layer is reconfigured with the conductive layer. The column is electrically connected. In addition, after the formation of the rewiring circuit layer, the formation of the ball is formed on the re-wiring circuit layer, and the solder balls are electrically connected to the conductive posts via the re-wiring circuit layer. In accordance with a preferred embodiment of the present invention, the method of forming a conductive post in a blind via is, for example, a viaflling plating process. In accordance with a preferred embodiment of the present invention, a method of forming a conductive post in a blind via includes first forming a metal layer on the inner wall of the blind via and then forming a core conductor layer in the blind via. In accordance with a preferred embodiment of the present invention, a method of forming a blind via on a wafer is, for example, a laser drilling process. The present invention provides a wafer level chip scaie package (WJ) structure including a wafer, a plastic frame and a substrate. The wafer has a first surface. a first surface of the first surface, a plurality of first pads and a plurality of conductive pillars, wherein the first pads are on the first surface. Further, the conductive pillars penetrate the wafer, and the conductive pillars Each of the first pads is connected to the first pads. Further, the frame is disposed on the first surface of the wafer, and the substrate is disposed on the first surface of the wafer, wherein the substrate maintains a gap by the frames. According to a preferred embodiment of the present invention, the wafer is aligned with the outer edge of the substrate and the plastic frame. According to a preferred embodiment of the present invention, the wafer-level grain size package further includes a plurality of conductive blocks. Disposed on the first interfaces, wherein each of the conductive blocks of the I2492Q§5twf.doc/m contacts the substrate and one of the first pads respectively. According to the preferred embodiment of the present invention, the above-mentioned crystal 4 The utility model comprises a plurality of second interfaces 其 which are placed on the second surface, and the towels are connected to the conductive pillars of each of the conductive pillars respectively. Further, the above-mentioned crystal-level grain size package structure further comprises Solder balls are respectively disposed on the second interfaces. According to a preferred embodiment of the present invention, the wafer t includes a re-wiring circuit layer s which is placed on the second surface and reconfigured with a line layer And electrically connected to the conductive pillars. Further, the above-mentioned crystalline grade-level grain size package structure further comprises a plurality of solder balls, which are respectively disposed on the re-routing layer, and the solder balls are electrically connected via the re-routing layer The conductive pillars are connected. According to a preferred embodiment of the present invention, each of the conductive pillars is divided into a core conductor layer and a metal layer on the periphery of the core conductor layer. Further, the core conductor layer is made of metal or solder (for example). According to a preferred embodiment of the present invention, the material of the substrate is, for example, transparent glass. Based on the above, the wafer level packaging process of the present invention forms a guide in the wafer so that the wafer can be directly substrate (transparent) The substrate is assembled to produce a lower cost wafer level grain size sealing structure. In addition, the wafer level grain size package structure of the present invention has a thin thickness and better electrical quality. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the preferred embodiments of the invention. 1A to 2F are schematic cross-sectional views showing a wafer level packaging process in accordance with a first preferred embodiment of the present invention. Referring first to FIG. 2A, the wafer level packaging process of the present embodiment includes the following steps. First, a wafer 21 is provided, and the wafer 210 has a first surface 212a, a second surface 212b opposite to the first surface 212, and at least one scribe line 21a and a plurality of first pads 214. The first pad 214 is located on the first surface 212& In addition, the material of the wafer 210 is, for example, a stone or a three-five element. Then, a plurality of blind vias 212c' are formed on the first surface 212a of the wafer 210 and the locations of the blind vias 212c correspond to the locations of the first pads 214, respectively. In other words, the position of the blind hole 212c is heavy with the position of the first pad 214. Further, the method of forming the blind holes 2i2c is, for example, a laser drilling process or other drilling process. It is worth noting that the blind via 212c must avoid the circuitry on the wafer 210 to avoid damaging the circuitry in forming the blind via 212e. Referring to FIG. 2B, a plurality of conductive pillars 220' are formed in the blind vias 212, and one end of the mother-conductive pillars 220 is respectively connected to one of the first pads 214, and a plurality of conductive pillars 22 are formed. The method is, for example, a hole-fill plating process. Next, a plurality of plastic frames 230 are disposed on the first surface 212a of the wafer 21A. In another preferred embodiment, the method of forming the conductive pillars 220 is, for example, first in a blind hole. A metal layer 222 is formed on the inner wall of the 212c, and then a core conductor layer 224 is formed in the blind hole 212c (as shown by the dotted line in FIG. 2B). The manner of forming the metal layer 222 is, for example, an electroplating process, and the shape is I2492Q§ 5twf. The method of forming the core conductor layer 224 is, for example, filling a metal, solder or other conductive material into the blind hole 212c. Referring to FIG. 2C, a substrate 24 is disposed on the plastic frame 230, wherein the substrate 240 and the crystal are The circle 210 is maintained at a pitch D by the plastic frame 23. In other words, the substrate 240 and the frame 230 are stacked on the wafer 21, wherein the frame 230 is, for example, disposed on the scribe line 21 of the wafer 21 On both sides. In addition, the design of the plastic frame 230 can The external moisture is prevented from causing damage to the line on the first surface 212a of the wafer 21. Then, the edge maintaining film 25' is disposed on the substrate to protect the surface of the substrate 24A in the subsequent process, and the protective film 250 For example, a grinding tape (grindi glue layer. Referring to FIG. 2D, the wafer 210' is ground to expose the other end of the conductive pillars 22. In other words, the second surface 212b of the wafer 210 exposes the conductive pillars 220. In addition, the above-mentioned method for polishing the wafer 21 (four) is, for example, chemical mechanical polishing (CMP), in which the protective film 25 is prevented from being damaged during the process of polishing the wafer, and the surface of the plate 240 is damaged. In the middle of the process of rounding 21 turns, it is not necessary to provide a protective film to avoid damage to the surface of the substrate. Other methods may be used. Referring to FIG. 2E', a plurality of second pads are formed on the conductive pillars 220 of the second surface 212b. Each of the second alignments 216 is respectively connected to the conductive pillars 220. Further, the second pads 216 are formed by, for example, forming a second surface 212b. The body material layer (not shown) is further patterned for the conductor material layer (patterning I2492Q § 5 twf, oc / m process) ° after forming the second pad 216, the second pad 216 shape f The plurality of solder balls 260 ′′ are thus electrically connected to the second pads 216 via the conductive posts 22 依 in the first pad 214 ′ of the first surface 212 a. Finally, the structure formed by the above process is cut. The protective layer 25 is then removed to form a plurality of wafer level grain size structures 200 (as indicated by ® 2F). The wafer level structure 200 will be detailed later. Continuing to refer to FIG. 2F, the wafer level die-size package structure 2 includes a wafer 212, a bezel 230, a substrate 240, and a plurality of solder balls 26A, wherein the wafer 212 is, for example, an optical component and a sense of image. Test the component or other component type = wafer. In addition, the wafer 212 has a plurality of first pads 214, a plurality of second pads 216, and a plurality of conductive pillars 230. In addition, the first pads 214 and the first pads 216 are respectively located on the first surface 212 & and the second: 212b of the wafer 212, and each of the conductive pillars 23 is electrically connected to the corresponding first pads. 214 is between the second pad 216. < In addition, the bezel 230 and the substrate 240 are stacked on the first surface 212a of the wafer 212, wherein the gap D is maintained by the bezel 230 between the substrate 240 and the wafer 212. In addition, the solder balls 260 are disposed on the second pads 216, wherein the mother solder balls 260 are electrically connected to one of the second pads 216, respectively. The material of the substrate 240 described above is, for example, transparent glass, quartz or other transparent material. In more detail, when the wafer 212 is an optical component, the first surface B2a is an active surface, and thus the line on the first surface 212a can be electrically connected to the fresh ball 260 via the conductive pillar 12 I2492Q§5twfd〇c/m 230. 'In order to electrically connect to an external circuit (not shown). Compared with the prior art, the wafer level grain size package structure 200 of the present invention uses the conductive pillars 230 to transmit signals. Therefore, the wafer level grain size package structure 200 of the present invention has better electrical quality. In addition, the wafer-level grain size package structure 200 of the present invention is thinner than conventional techniques, and the wafer-level grain size package structure of the present invention is also low in cost. [Second Embodiment] Fig. 3 is a cross-sectional view showing a wafer level die size package structure in accordance with a second preferred embodiment of the present invention. Referring to FIG. 3, the second embodiment is similar to the third embodiment, except that the wafer level grain size package structure of the second embodiment further includes a plurality of conductive blocks 370, which are respectively configured. On the first pad 214, each of the conductive blocks 37 is in contact with one of the base f 240 and the first pad 214, respectively. Further, the conductive block 37 is, for example, a conductive paste or other conductive elastomer. In addition, the T-form forming the conductive block 37A is, for example, before the substrate 240 is disposed on the wafer 21 (similar to FIG. 2B), the conductive block 370 is disposed on each of the first pads 214, and the substrate 240 is disposed on the substrate 240. On the wafer 210. As described above, since the static electricity is accumulated on the substrate 24, the conductive block 370 can guide the static electricity to the solder ball 26〇 so as to be transmitted to the external circuit, and the conductive block 370 can not only avoid the substrate. An electrostatic discharge is generated between the 24 〇 and the wafer 212 to protect the electronic components in the wafer 212, and to reduce the electromagnetic interference of the static electricity on the wafer 212. Continuing to refer to FIG. 3, the wafer level grain size package structure further includes 13 I2492Qg5twf, and the oc/m includes a re-wiring circuit layer 380 disposed on the second surface 212b. Further, the solder balls 260 are electrically connected to the conductive posts 220 via the re-wiring circuit layer 380. In other words, by redesigning the layout of the wiring layer 380, the pitch and layout of the solder balls 260 will not be limited by the pitch and layout of the conductive pillars 220. Additionally, the manner in which the rewiring circuit layer 380 is formed is, for example, after the conductive pillars 220 are exposed (similar to that shown in Figure 2D), and a re-wiring circuit layer 38 is formed on the second surface 212b. As described above, the edges of the substrate 240, the wafer 212, and the bezel 330 are, for example, chopped. For example, the plastic frame 330 is disposed on the dicing street 21〇3 (similar to that illustrated in FIG. 2B ), so that the cutting process not only cuts the substrate 24 〇 and the wafer 210 , but also divides the plastic frame 33 into two. The edges of the substrate 24, the wafer 212, and the bezel 330 are aligned. It is to be noted that the combination of the second embodiment and the various changes of the second embodiment is also within the scope of the invention. As described in detail, the wafer level packaging process and the wafer level grain size package structure of the present invention have the following advantages: Compared with the prior art, the wafer level packaging process of the present invention can directly directly crystallize the substrate and the substrate. (Transparent) is assembled to produce a lower cost wafer level grain size package. Second, the wafer level grain size package structure of the present invention has a relatively thin thickness compared to the prior art using a carrier substrate to carry the wafer. Third, compared with the conventional technology, the bonding wire is electrically connected to the substrate and the wafer, and the wafer-level grain size package structure of the wafer is electrically connected to the wafer. The wafer-level grain size package structure of the invention has a ratio of I2492Qg5twf. The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional optical component package structure. 2A-2F are cross-sectional views showing a wafer level packaging process in accordance with a first preferred embodiment of the present invention. 3 is a cross-sectional view showing a wafer level die size package structure in accordance with a second preferred embodiment of the present invention. [Major component symbol description] 100: A conventional optical component package structure 100a: a light beam 110: a carrier substrate 110a, 212a: a first surface 11b, 212b: a second surface 112: a groove 120, 212: a wafer 130: transparent Glass substrate 140: bonding wires 150, 260: in dry ball 200, 300 · wafer level grain size package 210: wafer 210a: dicing street 12492 (1 5 twf.doc / m 212c: blind hole 214: first Pad 216: second pad 220: conductive post 222: metal layer 224: core conductor layer 230, 330: plastic frame 240: substrate 250: protective film 370: conductive block 380: reconfigurable circuit layer