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TWI249166B - Memory cell, memory device and manufacturing method of memory cell - Google Patents

Memory cell, memory device and manufacturing method of memory cell Download PDF

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Publication number
TWI249166B
TWI249166B TW093109998A TW93109998A TWI249166B TW I249166 B TWI249166 B TW I249166B TW 093109998 A TW093109998 A TW 093109998A TW 93109998 A TW93109998 A TW 93109998A TW I249166 B TWI249166 B TW I249166B
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Taiwan
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film
variable resistive
metal
schottky diode
region
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TW093109998A
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Chinese (zh)
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TW200426827A (en
Inventor
Hidenori Morimoto
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Sharp Kk
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

A memory cell (33) in which a variable resistive element (31) and a Schottky diode (32) are connected in series to each other. In a memory device, bit lines (BL0, BL1 and BL2) are arranged in a column direction, one end of the bit line (BL) is connected to a bit line decoder (34), arid the other end thereof is connected to a reading circuit (37). Word lines (WL0, WL1 and WL2) are arranged in a row direction so as to intersect with the bit lines (BL), and both ends of the word line (WL) are connected to word line decoders (35 and 36). In other words, the bit line (BL) and the word line (WL) are arranged in a matrix and a memory cell (33) is located at a position where the bit line (BL) and the word line (WL) intersect with each other, which constitutes the memory device. An influence of a reading disturbance in the memory cell (33) and the memory device is reduced.

Description

1249166 玖、發明說明： 【發明所屬之技術領域】 本發明係相關於由可變電阻性元件及蕭特基二極體的串 耳即電路組成的1D1R-型態（一單元細胞係由一個二極體及一 個可變電阻性元件所組成）之記憶體單元，一記憶體裝置其 中的這種δ己丨思體單元配置成矩陣，以及這種記憶體單元的 生產方法。 【先前技術】 許多最近發展的MRAMs(磁性隨機存取記憶體）採用了一 種方法’其中組成藉由巨大磁電阻性材料的鐵磁材料殘留 磁性來儲存資料的鐵磁記憶體單元，而此儲存資料係藉由 轉換磁化方向間的差異所產生電阻值的變化成為電壓而加 以讀取。在此鐵磁記憶體單元中提供寫入動作要用的金屬 接線，而此鐵磁記憶體單元的磁化方向在毫安培等級之電 流流到此寫入用的金屬接線時所產生的磁場中改變，由之 寫入資訊或重新寫入到此鐵磁記憶體單元中。 在此MRAM(也就是，鐵磁記憶體單元）中，因為必須在寫 入的時間上流過大量電流（毫安培等級），而寫入用的接線是 以金屬形成的。做為這種MRAM的範例，已知的有1 τ 1R型 悲（一單元細胞由一電晶體及一磁電阻性元件組成）的 MRAM，其組合一對彼此相交的接線來同時做為寫入及讀 取線’以及一用來選擇單元及包含巨大磁電阻性薄膜之磁 電阻性元件的場效電晶體（參閱例如，日本專利申請案 Laid-Open編號第6-84347 (1994))。這種包含巨大磁電阻性 92467.doc 1249166 薄膜的記憶體單元呈現出磁電阻性效應，其中之電阻值隨 著磁化方向而變化。 再者，IBM公司中的w· LGallagher等人所揭示的記憶體 陣列（記憶體裝置），其中丨D丨R型態（一單元細胞由一個二極 體及一個磁電阻性元件組成）的MRAM包含一個磁性電阻 元件及一個由PN接合面形成的二極體，其彼此的串聯連接 是由矩陣中提供之χ _ γ接線所連接（請參閱美國專利編號第 5’640,343號）。根據這個技術，在一磁電阻性元件中被此簡 單矩陣接線夾層之結構所產生之一不可靠電流可以此二極 體加以避免，並因此結構較丨丁以型態為簡單，因而有可能 此記憶體單元的面積可以縮小。在一記憶體陣列中，其中 一單元的記憶體單元包含由矩陣中提供χ_γ接線連接的彼 此串聯連接之一通道磁電阻性元件（TMR元件）及一個由ΡΝ 接a面开）成的二極體，因為需要很大的磁電阻性比率以便 防止TMR元件電阻值變動，二極體順向電阻的變動，接線 的壓降及類似的影響，所以是很難組成記憶體晶片。 根據在美國專利編號第5,640,343號中揭示的生產方法， 因為形成二極體的處理是在形成一 X-Y接線的金屬接線之 後執行的，包含P-型態雜質的複晶矽及包含η-型態雜質的複 曰曰矽被接合而形成此二極體。由形成二極體之熱處理所影 “屬接線的融化及惡化觀點上，有問題的是形成二極體 日守不％採用尚溫的熱處理。結果，因為二極體惡化以及逆 向偏壓蚪的洩漏電流增加的特性，所以很難組成大規模記 憶體陣列。換句話說，雖然因為在配置成矩陣之mram中 92467.doc 1249166 的單元面積小而有整合程度上的優點，卻很難實做為對應 的高度整合元件組成及驅動方法。 當一電阻值變化率高於上述MRAM中磁電阻性元件的可 變電阻性元件，一有著鈣鈦-型態結晶結構的材料，一雙重 對齊鈣鈦-型悲結晶結構或類似的會呈現出巨大磁電阻性 或是高溫超導電性例，例如已知的Pr(i_x)CaxMnC)3 (〇<x<l) ^ La(1.x)CaxMnO3(0<x<l) ^ Nd(1.x)SrxMnO3(0<x<i), Sr2FeMo06 ’ Sr2FeW06，或類似的（參閱美國專利編號第 6,204，139)。當使用這種可變電阻性元件時’上述的問題是 可以解決的。 在美國專利編號第6,204，139號中，有建議一種方法，其 中有一或多個短電氣脈衝施加於一薄膜上或是大量形成有 著鈣鈦結構的薄膜材料，特別是巨大磁電阻性材料及高溫 超導電性材料，而改變其電氣特性。在此時由此電氣脈衝 造成的電場強度及電流密度可以低到足以改變材料的物理 特性但不會破壞材料，而此電氣脈衝可以是正或負的極 性。此材料特性可由施加複數個電氣脈衝到上述可變電阻 性元件而進一步加以改變。圖丨到圖4顯示的是在美國專利 編號第6,204,1 39號中揭示的可變電阻性元件特性。 圖1及圖2為概要顯示在上述可變電阻性元件中所施加脈 衝數目與電阻值間關連的圖表。圖鳴示施加於在金屬基板 上長出之CMR薄膜上的脈衝數目與一電阻值間的關連。在 圖1顯示的範例中，施加最多到47個每個的振幅為+32 v而 脈衝寬度為7.1即的脈衝。在這個情形下，可以從圖丨顯示的 92467.doc -7- 1249166 特性看出’在施加脈衝數 *的一加 増加時電阻值所改變的範圍在 燦，的關中，施加脈衝的條件改 交也就疋’施加的脈衝最多至丨| 1 Μ加— Η, 到168個每個的振幅+27 V而 脈衝覓度為65 ns。在這種情形下 7下，可以從圖2顯示的特性中 看出，在施加脈衝數目增加時電㈤ 了包I且值改變的範圍最多到五 個位數。 ^立 :圖4為概要顯示在上述可變電阻性元件中所施加脈 錄與電阻值間關連的圖表。圖3顯示當施加+i2v(正極 性)與-12 V(負極性)時在施加脈衝數目與電阻值間的關 連。另外，圖4顯示在施加脈衝數目與連續施加+5iv(正極 I·生)及5 1 V (負極性)之後所測量電阻值之間的關連。可從圖 3及圖4看出的，此電阻值在藉由施加正極性脈衝幾次降低 之後可藉由連續施加負極性脈衝而增加（最後成為飽和狀 態）。因此，可理解到此元件可以應用在記憶體裝.置上，藉 由在施加正極性脈衝時設定為重置狀態以及在對之施加負 極性脈衝時而設定為 寫入狀態。 根據傳統的可變電阻性元件，其.特性顯示在圖1到圖4 中’寫入時間大約是幾十到200奈秒，而拭除動作可由在寫 入動作中施加正極性電壓執行，時間大約為幾十到2〇〇奈 秒。另外，當使用這種可變電阻性元件（CMR材料）時，因 為寫入動作中不需很大電流流過金屬接線，在高溫熱處理 中很強壯之鶴線，複晶石夕，石夕基板的一擴散層（雜質區域） 或類似的就可以用在較低的接線。 當此1D1R.型.態的記憶體單元是由可變電阻性材料例如 92467.doc 1249166 CMR形成的可變電阻性元件，以及由pN接合面形成之二極 體所組成時’二極體順向臨限值與施加到可變電阻性元件 電壓的總和在讀取動作的時間内施加於記憶體單元。當讀 取動作日守所W加電壓為南電位時，會產生讀取干擾，在其 中項取動作時的電阻值改變，而因此可變電阻性元件的電 阻值從低電阻狀態改變為高電阻狀態，因此必須要儘可能 地降低讀取電壓。然而，因為由PN接合面形成之二極體的 順向臨限值相當高（大約〇·5 v)，所以會產生讀取干擾。 當生產此由可變電阻材料例如CMR材料及類似的所形成 可炎電阻7C件及由請接合面形成之二極體所組成的 «的記憶體單㈣，首先要形成組成用來選擇記憶 體單7G字線解碼裔以及位兀線解碼器之電晶體（卿WET) 及組成周邊電路例如讀取電路之電晶體，接著形成由複晶 矽PN接合面組成的二極體，而再接著形成可變電阻性元 件。在這個生產方法中，必須 肩要分開地執行用在以接合包 含P-型態雜質之複晶石夕與包含 t 一 - 匕型悲雜質之複晶矽來形成 一極體的熱處理，以及用扁 • 、鍍方法或CVD方法沈積（形 成）以便改善可變阻性材料薄 #胲的釔日日特性之熱處理。因 此’因為形成此記憶體裝置 ^ t 展置周邊電路之電晶體（MOSFET) 之源極區域與汲極區域的 大及；㈣擴放層因為減理數目增加而擴 大及有效閘極長度的縮短， 化。 电日日體特性因短通道效應而惡 發明内容】 本發明觀點就是針對上述 π間缚，而本發明的目的在提 92467.doc 1249166 供由可變電阻性元件及蕭特基 憶體單元，藉之降低讀取干擾 的記憶體裝置。 二極體之串聯電路組成的記 ，以及包含這種記憶體單元 的在提供記憶體單元的生產方 另外，本發明的另一目 法’其中組成記憶體單元周邊電ma^_sFET)特性 上的不良影響可藉由降低在記《單元形成時的熱處理數 目來防止。 在根據本發明之記憶體單 元包含一可變電阻性元件及 流動的電流之電·流控制元件 為蕭特基二極體。 元的第一觀點中，此記憶體單 一控制在此可變電阻性元件中 ’而其特徵為此電流控制元件 在根據本發明之記憶體單元的第二觀點，第―觀點中之 =憶體單元的特徵為此可變電阻性元件係由有著約欽·型 悲結晶結構的阻性材料所形成。 在根據本發明之記憶體單元的第三觀點，第一與第二觀 點中的記憶體單元特徵為此蕭特基二極體的第—電極為形 成在第j專導型怨之半導體基板上的第二傳導型態雜質區 域，而相同之第二電極為沈積在此雜f區域上的金屬薄膜。 在根據本發明之記憶體單元的第四觀點中，帛三觀點中 的記憶體單元特徵為此半導體基板為一矽基板，而此蕭特 基二極體有-蕭特基位能障在此雜質區域與形成在此雜質 區域與金屬薄膜間的金屬矽化物薄臈之間。 在根據本發明之記憶體單元的第五觀點中，第三或第四 觀點中的記憶體單元特徵為此雜質區域係選擇性的形成在 92467.doc -10- 1249166 半導體基板中所形成元件的絕緣區域中。 在根據本發明之記憶體單元的第六觀點中，在第三到第 五觀點中任一的記憶體單元的特徵為組成此可變電阻性元 件之可變電阻性薄膜係以自行對齊方式沈積在蕭特基二極 體的第二電極上。 在根據本發明之記㈣單元的第七觀財，在第一或第 二觀點中的記憶體單元特徵為蕭特基二極體的第-電極係 為選擇性的形成在此絕緣薄膜中的複晶石夕區域，而此相同 的第二電極則為沈積在此複晶♦區域上的金屬薄膜。 在根據本發明.之記憶體單元的第人觀財，第七觀點中 的記憶體單元特徵為此蕭特基二極體有一蕭特基位能障在 此複晶石夕區域與形成在複晶石夕區域及此金屬薄膜間的金屬 矽化物薄膜之間。 在根據本發明之記憶體裝置的第—觀點中，此記憶體裝 置之I的記憶體單元係位在配置成矩陣之字線與位元線彼 此相交的位置’而其特徵為記憶體單元是由包含一可變電 阻性元件及一控制在此可變電阻性元件中流動電流的蕭特 基二極體之串聯電路組成’分別地，此串聯電路之—端點 連接到字線，而相同的另一端點則連接到位元線。 在根據本發明之記憶體裝置的第二觀點令，第一觀點中 的記憶體裝置的特徵為可變電阻性元件是由有著鈣鈦-型 悲結晶結構的阻性材料所形成。 在根據本發明之記憶體裝置的第三觀點中，第一或第_ 觀點中的記憶體裝置特徵為此蕭特基二極體的第一電 92467.doc -11 - 1249166 接到字線，此蕭特基二極體的第二電極連接到此可變電阻 性元件之一端點，而此可變電阻性元株 、 1干的另一端點連接到 此位元線。 在根據本發明之記憶體裝置的第四觀點中，在第一到第 三的任一觀點中的記憶體裝置特徵為字線是由選擇性形成 在半導體基板中所形成之元件絕緣區域中的雜質區域組 成。 在根據本發明之記憶體裝置的第五觀點中，第四觀點中 的記憶體裝置特徵為蕭特基二極體的第一電極為雜質區域 而相同之第二電·極為沈積在此雜質區域上的金屬薄膜。 在根據本發明之記憶體裝置的第六觀點中，第五觀點中 的記憶體裝置特徵為此半導體基板為一矽基板，而此蕭特 基二極體有一蕭特基位能障在此雜質區域及形成在雜質區 域與金屬薄膜間的金屬矽化物薄膜之間。 在根據本發明之記憶體裝置的第七觀點中，第五或第六 觀點中的記憶體裝置特徵為組成可變電阻性元件之可變電 阻性薄膜藉由自行對齊方式沈積在蕭特基二極體第二電極 上。 在根據本發明之記憶體裝置的第八觀點中，第一到第三 觀點中的記憶體裝置特徵為字線是由選擇性形成在絕緣薄 膜中的複晶矽區域所組成。 在根據本發明之記憶體裝置的第九觀點中，第八觀點中 的記憶體裝置特徵為蕭特基二極體的第一電極為複晶矽區 域而相同的弟二電極為沈積在此複晶石夕區域上的金屬薄 92467.doc -12- 1249166 膜。 在根據本發明之記憶體裝置的第十觀點巾，第九觀點中 的記憶體裝置特徵為蕭特基二極體有一蕭特基位能障在此 稷晶石夕區域與形成在此複晶石夕區域與金屬薄膜間的金屬石夕 化物薄膜之間。 在根據本發明之記憶體單元生產方法的第一觀點中，彤 成由可變電阻性元件及蕭特基二極體的串聯電路組成之記 憶體單元在半導體基板上的生產方法的 在此半導體基板一表面上形成有一雜質區域形成二^ 開口的絕緣薄膜的步驟；沈積組成可變電阻性元件電極的 金屬薄膜在絕緣薄膜的開口t;沈積包含可變電阻性元件 電阻的可變電阻性薄膜在此金屬薄膜上；以及藉由熱處理 形成金屬矽化物薄膜在雜質區域與金屬薄膜之間以形成 特基二極體。 在根據本發明之記憶體單元生產方法的第二觀 -觀點中的生產方法特徵為此可變電阻性薄膜係藉由自行 對齊方式沈積在開口中的金屬薄膜上。 在根據本發明之記憶體單元生產方法的第三觀財，第 -或第二觀點中的生產方法特徵為熱處理的溫度是可改盖 可變電阻性薄膜結晶特質的溫度。 ° 在根據本發明之記憶體單元生產方法的第四觀點中，第 -=弟二觀點中任-者的生產方法特徵為半導體基板為— 石夕基板’而此肅特基二極體有一蕭特基位能障1249166 发明, the invention description: [Technical Field] The present invention relates to a 1D1R-type state composed of a variable resistive element and a Schottky diode of a Schottky diode (a unit cell line consists of one A memory unit composed of a polar body and a variable resistive element, wherein the δ 丨 丨 体 unit of a memory device is configured in a matrix, and a method of producing the memory unit. [Prior Art] Many recently developed MRAMs (Magnetic Random Access Memory) employ a method in which a ferromagnetic memory unit that stores data by a residual magnetism of a ferromagnetic material of a giant magnetoresistive material, and this storage The data is read by changing the resistance value generated by the difference in the direction of magnetization to a voltage. The metal wiring for the write operation is provided in the ferromagnetic memory unit, and the magnetization direction of the ferromagnetic memory unit is changed in the magnetic field generated when the current of the milliamperometer level flows to the metal wiring for writing. , by which information is written or rewritten into this ferromagnetic memory unit. In this MRAM (i.e., ferromagnetic memory cell), since a large amount of current (milliampere level) must be flowed during the writing time, the wiring for writing is formed of metal. As an example of such an MRAM, there is known an MRAM having a 1 τ 1R type sorrow (a unit cell consisting of a transistor and a magnetoresistive element), which combines a pair of mutually intersecting wires to simultaneously perform writing. And a read line' and a field effect transistor for selecting a unit and a magnetoresistive element including a giant magnetoresistive film (see, for example, Japanese Patent Application Laid-Open No. 6-84347 (1994)). This memory cell containing a giant magnetoresistive 92467.doc 1249166 film exhibits a magnetoresistance effect in which the resistance value varies with the direction of magnetization. Furthermore, a memory array (memory device) disclosed by W. LGallagher et al. in IBM, in which the MRAM of the 丨D丨R type (a unit cell consists of a diode and a magnetoresistive element) A magnetic resistance element and a diode formed by a PN junction are provided, and their series connection to each other is connected by a χ γ γ wiring provided in a matrix (see U.S. Patent No. 5'640,343). According to this technique, an unreliable current generated by the structure of the simple matrix wiring interlayer in a magnetoresistive element can be avoided by the diode, and thus the structure is simpler than that of the type, so it is possible The area of the memory unit can be reduced. In a memory array, a memory cell of one of the cells includes a channel magnetoresistive element (TMR element) connected in series with a χ_γ wiring provided in the matrix, and a diode formed by the surface of the a a Body, because a large magnetoresistance ratio is required in order to prevent variations in the resistance value of the TMR element, variations in the forward resistance of the diode, voltage drop of the wiring, and the like, it is difficult to form a memory chip. According to the production method disclosed in U.S. Patent No. 5,640,343, since the formation of the diode is performed after forming a metal wiring of an XY wiring, the polycrystalline germanium containing the P-type impurity and the η-type state are included. The retanning of the impurities is joined to form the diode. From the viewpoint of the heat treatment of the formation of the diode, "the melting and deterioration of the wiring is problematic. The problem is that the formation of the diode is not subject to the heat treatment of the temperature. As a result, the diode is deteriorated and the reverse bias is applied. The characteristic of increased leakage current makes it difficult to form a large-scale memory array. In other words, although it is advantageous because of the small unit area of 92467.doc 1249166 in the mram configured as a matrix, it is difficult to implement. For the corresponding highly integrated component composition and driving method. When a resistance value change rate is higher than the variable resistive component of the magnetoresistive element in the above MRAM, a material having a calcium-titanium-type crystal structure, a double alignment of calcium and titanium - Type sorrow crystal structure or the like which exhibits large magnetoresistance or high temperature superconductivity, such as known Pr(i_x)CaxMnC)3 (〇<x<l) ^ La(1.x)CaxMnO3 (0<x<l) ^ Nd(1.x)SrxMnO3(0<x<i), Sr2FeMo06 'Sr2FeW06, or the like (see U.S. Patent No. 6,204,139). When using such a variable resistive element When the above problem can be solved. In Japanese Patent No. 6,204,139, there is proposed a method in which one or more short electric pulses are applied to a film or a large amount of a film material having a calcium-titanium structure, particularly a giant magnetoresistive material and a high temperature super The conductive material changes its electrical properties. At this time, the electric field strength and current density caused by the electrical pulse can be low enough to change the physical properties of the material without damaging the material, and the electrical pulse can be positive or negative. This material property can be further varied by applying a plurality of electrical pulses to the variable resistive element described above. Figure 4 shows the variable resistive element characteristics disclosed in U.S. Patent No. 6,204,1. 1 and FIG. 2 are diagrams schematically showing the relationship between the number of pulses applied and the resistance value in the variable resistive element. The graph shows the number of pulses applied to the CMR film grown on the metal substrate and a resistance value. In the example shown in Figure 1, a maximum of 47 pulses each having an amplitude of +32 v and a pulse width of 7.1 are applied. In the shape, it can be seen from the characteristics of 92467.doc -7- 1249166 shown in the figure ' 'When the number of applied pulses* is increased, the range of resistance changes is in the range of Can, and the conditions for applying the pulse are changed.疋 'Apply pulses up to 丨 | 1 Μ — Η, to 168 each amplitude +27 V and pulse 觅 65 ns. In this case, 7 can be seen from the characteristics shown in Figure 2. Out, when the number of applied pulses increases, the voltage (5) is package I and the value changes up to a maximum of five digits. ^立: Figure 4 is a schematic diagram showing the relationship between the pulse and the resistance value applied in the above variable resistive element. Chart. Figure 3 shows the relationship between the number of applied pulses and the resistance value when +i2v (positive polarity) and -12 V (negative polarity) are applied. In addition, FIG. 4 shows the relationship between the number of applied pulses and the resistance value measured after continuous application of +5 iv (positive I·sheng) and 5 1 V (negative polarity). As can be seen from Fig. 3 and Fig. 4, this resistance value can be increased by continuously applying a negative polarity pulse after the application of the positive polarity pulse is lowered several times (finally becomes a saturated state). Therefore, it can be understood that the component can be applied to the memory device by setting it to the reset state when the positive polarity pulse is applied and the writing state when the negative polarity pulse is applied thereto. According to the conventional variable resistive element, its characteristics are shown in FIG. 1 to FIG. 4, the writing time is approximately several tens to 200 nanoseconds, and the erasing action can be performed by applying a positive polarity voltage in the writing operation, time It is about tens to 2 nanoseconds. In addition, when such a variable resistive element (CMR material) is used, since a large current does not flow through the metal wiring in the writing operation, the crane wire is strong in the high temperature heat treatment, the polycrystalline stone eve, the Shixi substrate A diffusion layer (impurity region) or the like can be used for lower wiring. When the memory cell of the 1D1R. type is a variable resistive element formed of a variable resistive material such as 92467.doc 1249166 CMR, and a diode formed of a pN joint surface, the diode is compliant. The sum of the threshold value and the voltage applied to the variable resistive element is applied to the memory unit during the reading operation. When the reading operation time W is applied to the south potential, read disturbance occurs, and the resistance value changes when the item is taken, and thus the resistance value of the variable resistive element changes from the low resistance state to the high resistance. State, so the read voltage must be reduced as much as possible. However, since the forward threshold of the diode formed by the PN junction is relatively high (about 〇·5 v), read disturb occurs. When producing a memory single (four) consisting of a variable resistance material such as a CMR material and the like formed of a flammable resistor 7C and a diode formed by a joint surface, a composition is first formed to select a memory. A single 7G word line decoding and a transistor of the bit line decoder (Qing WET) and a transistor constituting a peripheral circuit such as a read circuit, and then forming a diode composed of a polysilicon PN junction surface, and then forming Variable resistive element. In this production method, it is necessary to separately perform heat treatment for forming a polar body by bonding a double crystal containing a P-type impurity and a polycrystalline silicon containing a t-type sin-type impurity, and Flattening, plating, or CVD methods are deposited (formed) to improve the heat treatment of the daytime characteristics of the variable resistive material. Therefore, 'because the memory device is formed to extend the source region and the drain region of the transistor (MOSFET) of the peripheral circuit; (4) the expansion layer is enlarged due to the increase in the number of reductions and the effective gate length is shortened. And. The characteristics of the electric solar cell are due to the short channel effect. The present invention is directed to the above-mentioned π-binding, and the object of the present invention is to provide 92467.doc 1249166 for the variable resistive element and the Schottky element. By means of memory devices that reduce read disturb. The composition of the series circuit of the diode, and the production of the memory unit including the memory unit. In addition, another method of the present invention, in which the memory unit is surrounded by the electrical ma^_sFET, has poor characteristics. The effect can be prevented by reducing the number of heat treatments at the time of cell formation. The memory unit according to the present invention comprises a variable resistive element and an electric current control element of a flowing current as a Schottky diode. In the first aspect of the element, the memory is controlled solely in the variable resistive element' and is characterized by the second point of view of the current control element in the memory unit according to the present invention. Characteristics of the unit For this reason, the variable resistive element is formed of a resistive material having a Jochen-type sad crystal structure. In a third aspect of the memory cell according to the present invention, the memory cell features of the first and second aspects are characterized in that the first electrode of the Schottky diode is formed on the semiconductor substrate of the jth-specific type of complaint The second conductive type impurity region, and the same second electrode is a metal thin film deposited on the impurity f region. In the fourth aspect of the memory cell according to the present invention, the memory cell feature in the third aspect is that the semiconductor substrate is a germanium substrate, and the Schottky diode has a Schottky energy barrier. The impurity region is formed between the metal halide thin film formed between the impurity region and the metal thin film. In a fifth aspect of the memory cell according to the present invention, the memory cell feature in the third or fourth aspect is selectively formed in this impurity region by the element formed in the semiconductor substrate of 92467.doc-10-1249166 In the insulation area. In a sixth aspect of the memory cell according to the present invention, the memory cell of any of the third to fifth aspects is characterized in that the variable resistive film constituting the variable resistive element is deposited in a self-aligned manner. On the second electrode of the Schottky diode. In the seventh aspect of the unit according to the invention, the memory unit in the first or second aspect is characterized in that the first electrode of the Schottky diode is selectively formed in the insulating film. The cristobalite region, and the same second electrode is a metal film deposited on the polycrystalline region. In the first aspect of the memory unit according to the present invention, the memory cell feature in the seventh aspect is that the Schottky diode has a Schottky energy barrier in the area of the polycrystalline stone and formed in the complex Between the spar zone and the metal halide film between the metal films. In the first aspect of the memory device according to the present invention, the memory cell of the memory device I is located at a position where the word line and the bit line of the matrix intersect each other' and the memory cell is Composed of a series circuit comprising a variable resistive element and a Schottky diode that controls the flow of current in the variable resistive element 'respectively, the end of the series circuit is connected to the word line, and the same The other endpoint is connected to the bit line. In a second aspect of the memory device according to the present invention, the memory device of the first aspect is characterized in that the variable resistive element is formed of a resistive material having a calcium-titanium-type sad crystal structure. In a third aspect of the memory device according to the present invention, the memory device feature of the first or the first aspect is connected to the word line for the first electric 92467.doc -11 - 1249166 of the Schottky diode. The second electrode of the Schottky diode is connected to one end of the variable resistive element, and the other end of the variable resistive element strain, 1 stem, is connected to the bit line. In a fourth aspect of the memory device according to the present invention, the memory device in any one of the first to third aspects is characterized in that the word line is selectively formed in the element insulating region formed in the semiconductor substrate. Impurity area composition. In a fifth aspect of the memory device according to the present invention, the memory device of the fourth aspect is characterized in that the first electrode of the Schottky diode is an impurity region and the same second electrode is extremely deposited in the impurity region. Metal film on it. In a sixth aspect of the memory device according to the present invention, the memory device of the fifth aspect is characterized in that the semiconductor substrate is a germanium substrate, and the Schottky diode has a Schottky energy barrier in the impurity. The region is formed between the impurity film region and the metal halide film between the metal films. In a seventh aspect of the memory device according to the present invention, the memory device of the fifth or sixth aspect is characterized in that the variable resistive film constituting the variable resistive element is deposited by self-alignment in Schottky II The second electrode of the polar body. In an eighth aspect of the memory device according to the present invention, the memory device of the first to third aspects is characterized in that the word line is composed of a polysilicon region selectively formed in the insulating film. In a ninth aspect of the memory device according to the present invention, the memory device of the eighth aspect is characterized in that the first electrode of the Schottky diode is a polysilicon region and the same two electrodes are deposited in the complex The thin metal on the spar area is 92467.doc -12- 1249166 membrane. In a tenth aspect of the memory device according to the present invention, the memory device of the ninth aspect is characterized in that the Schottky diode has a Schottky energy barrier in which the twin crystal region is formed and formed therein. Between the Shixi area and the metallurgical film between the metal films. In the first aspect of the method for producing a memory cell according to the present invention, a method for producing a memory cell composed of a series circuit of a variable resistive element and a Schottky diode on a semiconductor substrate is used herein. Forming an impurity film on the surface of the substrate to form an insulating film having an opening; depositing a metal film constituting the electrode of the variable resistive element at the opening t of the insulating film; and depositing a variable resistive film including the resistance of the variable resistive element On the metal thin film; and forming a metal telluride film by heat treatment between the impurity region and the metal thin film to form a special base diode. The production method in the second aspect of the memory cell production method according to the present invention is characterized in that the variable resistive film is deposited on the metal thin film in the opening by self-alignment. In the third aspect of the memory cell production method according to the present invention, the production method of the first or second aspect is characterized in that the temperature of the heat treatment is a temperature at which the crystal characteristics of the variable resistive film can be changed. In the fourth aspect of the method for producing a memory cell according to the present invention, the production method of any of the first to second views is characterized in that the semiconductor substrate is a slate substrate and the stellate diode has a spleen Special base energy barrier

物薄膜與雜質區域之間。 G 92467.doc -13- 1249166 在根據本發明之生產方法的第五觀點中，在半導體基板 上形成由可變電阻性元件及蕭特基二極體之串聯電路所組 成的兄憶體單元的生產方法，其特徵包含步驟：形成有在 半導體基板形成的表面上雜質區域在其上被暴露的開口之 絕緣薄膜；在此絕緣薄膜的開口中沈積金屬薄膜以組成可 變電阻性元件電極；沈積有第一薄膜厚度的可變電阻性薄 膜並組成可變電阻性元件的電阻在此金屬薄膜上；藉由以 熱處理在雜質區域與金屬薄膜之間形成金屬矽化物薄膜而 形成蕭特基二極體，並沈積有第二薄膜厚度之可變電阻性 薄膜並在有著第一薄膜厚度之可變電阻性薄膜上組成電 阻。 在根據本發明之生產方法的第六觀點中，在第五觀點中 的生產方法特徵為熱處理的溫度為可以改善有第一薄膜厚 度之可變電阻性薄膜結晶特性的溫度。 在根據本發明之生產方法的第七觀點中，在第五或第六 觀點中的生產方法特徵為此半導體基板為梦基板，而此蕭 特基一極體有一蕭特基位能障在金屬石夕化物薄膜及雜質區 域之間。 在根據本發明之生產方、、土 & # 玍座万法的弟八觀點中，在第五到第七 之任觀點中的生產方法特徵為進一步包含步驟在有第二 薄膜厚度之可變電阻性薄臈的沈積之後再進一步執行執處 理’其中熱處理的溫度為可改善有第二薄膜厚度之可變電 阻性薄膜結晶特性並可以降低金屬石夕化物薄膜電阻值的溫 92467.doc _ 14- 1249166 在根據本發明之生產方法的第九觀點中，形成由可變電 阻性元件及蕭特基二極體串聯電路組成之記憶體單元在半 導體基板上的生產方法，其特徵為包含步驟：選擇性地形 成複晶矽區域在一形成於此半導體基板表面上之絕緣薄膜 中；沈積一金屬薄膜組成可變電阻性元件電極在此複晶矽 區域上；沈積一組成可變電阻性元件之電阻的可變電阻性 薄膜在此金屬薄膜上；以及藉由熱處理在此複晶矽區域與 金屬薄膜之間形成金屬砍化物薄膜而形成蕭特基二極體。 在根據本發明之生產方法的第十觀點中，第九觀點中的 生產方法特徵為此熱處理的溫度是可以改善可變電阻性薄 膜結晶特性的溫度。 在根據本發明之生產方法的第十一觀點中，第九或第十 觀點中的生產方法特徵為蕭特基二極體有一蕭特基位能障 在此金屬矽化物薄膜與此複晶矽區域&間。 在根據本發明之生產方法的第十二觀點中，形成由可變 電阻性元件及蕭特基二極體串聯電路組成之記憶體單元在 半導體基板上的生產方法，其特徵為包含步驟：選擇性形 成複晶矽區域在形成在此半導體基板之一表面上的絕緣薄 膜中；沈積一組成可變電阻性元件電極之金屬薄膜在此複 晶矽區域上，沈積一有第一薄膜厚度並組成可變電阻性元 件電阻之可變電阻性薄膜在此金屬薄膜上；藉由熱處理在 此複晶矽區域與金屬薄膜之間形成金屬矽化物薄臈而形成 蕭特基二極體；以及沈積有第二薄膜厚度之可變電阻性薄 膜並組成電阻在有第一薄膜厚度之可變電阻性薄膜上。 92467.doc -15- 1249166 在根據本發明之生產方法的第十三觀點中，第十二觀點 中的生產方法的特徵為此熱處理的溫度為可以改善有第一 薄膜厚度之可變電阻性薄膜結晶特性的溫度。 在根據本發明之生產方法的第十四觀點中，第十二或十 二觀點中的生產方法的特徵為蕭特基二極體有一蕭特基位 能障在此金屬矽化物薄膜與此複晶矽區域之間。 在根據本發明之生產方法的第十五觀點中，第十二到十 四觀點中任一者的生產方法的特徵為其進一步包含步驟在 有第二薄膜厚度之可變電阻性薄膜的沈積之後執行進一步 的熱處理，其中·熱處理的溫度為可以改善有第二薄膜厚度 之可變電阻性薄膜的結晶特性以及可以降低金屬矽化物薄 膜電阻值的溫度。 在根據本發明之生產方法的第十六觀點中，第一到十四 觀點中任一者的生產方法的特徵為此金屬薄膜係以耐熔化 金屬材料形成。 在根據本發明之生產方法的第十七觀點中，第十六觀點 中的生產方法特徵為此耐熔化金屬材料係從Pt，Ti，Co及Ni 中的至少一個選出。 根據本發明因為此記憶體單元是由可變電阻性元件及蕭 特基二極體的串聯電路組成，故可以降低順向方向中二極 體的臨限電壓。因此，非揮發性記憶體單元其中的讀取干 擾不太可能產生，而此包含這種記憶體單元的記憶體裝置 是可以實現的。 另外’根據本發明，因為有著詞鈦-型態結晶結構的電阻 92467.doc -16- 1249166 材料被用在可變電阻性元件中，可變電阻性元件的電阻變 動率可以增加。因&，記憶體單元及記憶體裝置其中的容 量可以大量地增加而電氣控制則可輕易實現的。 再者，根據本發明，因為此蕭特基二極體的第一電極係 由半導體基板的雜質區域組成，此半導體積體電路可輕易 貫現。另夕卜，因為第二電極係以沈積形成在垂直方向中， 故可實現高度整合的記憶體單元。再者，因為蕭特基二極 體的第-電極也可以當作字線，&高度整合的記憶體裝置 是可以實現。 再者，根據本發明，因為金屬矽化物薄膜係形成在變成 蕭特基二極體之第-電極的石夕基板的雜質區域與變成直第 二電㈣金屬薄膜之間，而此蕭特基位能障係形成在金屬 矽化物薄膜及石夕基板（雜質區域）之間，在順向方向中的二極 體臨限電壓相較於PN-接合面二極體在順向方向中的臨限 電麈可以大大地降低。另外’因為此蕭特基位能障係形成: 在金屬石夕化物薄膜與矽基板(雜質區域)之間，進而 穩定的二極體特性。 再者，根據本發明，因為雜質區域係形成在此元 區域中’雜質區域變成了字線而蕭特基二極體的第—兩搞 dα的形成。因此，記憶體單元及年愔 體裝置的整合程度可獲得改善。 心 再者，根據本發明，因為可變電阻性㈣係藉由 齊方式形成在蕭特基二極體的第二電極上， 體在垂直方向上準確的對齊可變電阻性卜土-極 Ύ 囚此，可變 92467.doc -17- 1249166 電阻性元件的電阻值可準確的加以控制而記憶體單元及記 憶體裝置的整合程度可獲得改善。 再者，根據本發明因為蕭特基二極體的第_電極係由選 擇性地形成在絕緣薄膜上的複晶矽組成，可以實做記憶體 單元堆疊在其中的記憶體單元以外的元件結構。因此，記 憶體單元及記憶體裝置的整合程度可獲得改善。 *再者，根據本發明，因為金屬矽化物薄臈係形成在變成 蕭特基二極體之第一電極的矽基板的雜質區域與變成其第 二電極的金屬薄膜之間，而此蕭特基位能障係形成在此金 屬矽化物薄膜— 與此複晶矽區域之間，順向方向中二極體的 臨限電壓相較於PN-接合面二極體在順向方向中的臨限電 壓可以大大地降低。另外，因為蕭特基位能障係形成在此 金屬矽化物薄膜與此晶基板（雜質區域）之間，故可獲得穩定 的二極體特性。 〜 再者，根據本發明，沈積金屬薄膜以形成蕭特基二極體 的熱處理及用來改善以沈積形成可變電阻性元件之電阻的 可變電阻性薄膜結晶特性的熱處理係在同一時間執行。因 此，因為熱處理的數目可以減少，記憶體單元的生產方法 中可以做到不會產生對周邊電路的不良影響。 再者，根據本發明，此可變電阻性薄膜沈積兩次而蕭特 基二極體的形成及有第一薄膜厚度之可變電阻性薄膜結晶 特性的改善可以在同一時間執行，藉由在第一薄膜厚度之 可變電阻性薄膜的沈積之後的熱處理。因此，因為熱處理 數目可以減少，記憶體單元的生產方法中可以做到不會產 92467.doc -18- 1249166 生對周邊電路的不良影響。另外，因為有〜 可變電阻性薄臈是在有第—薄臈厚度可變=膜厚度: 晶特性改善之後沈積，此有 / 補的結 膜可以根據此有第-薄膜厚度之可變2 =變電阻性薄 性而沈積，藉之記憶體單元的生產方二：：結晶特 電阻性薄膜整個的進-步改善可以實現。—特性及可變 再者，根據本發明，f特基二極體（特別是金屬梦化物薄 、的電阻值可以進一步的降低’藉由在形成有第二薄膜厚 f之μ電阻性薄膜之後再次執行熱處理。另夕卜，有第二 =导度之可㈣阻性薄臈的結晶特性可根 厚度之可變電阻性薄膜進一步改善，此結晶特性與整^的 可變電阻性薄膜可獲得很大的改善。 本發明的上述及進-步目的與特點將由於下面伴隨圖示 的詳細說明而變得更為完整地明顯。 【實施方式】 在之後本㉙明將參考顯示其較佳具體實例的圖示加以說 明。. 圖5Α及圖5Β為解釋根據本發明之記憶體裝置概要組成 的圖不。圖5Α為顯示其中記憶體單元配置成矩陣之記憶體 單元陣列的電路圖，位元線及字線連接到此記憶體單元， 而周邊電路連接到此位元線及n㈣為顯示在圖从中 所顯示之電路在讀取時所施加電虔情形的表格。 麥考圖5 A，參考號碼3丨標記一可變電阻性元件，其電阻 值隨著施加電壓變化而參考號碼32標記-蕭特基二極體， 92467.doc -19- 1249166 其控制在可變電阻性元件31中流動的電流。一個可變電阻 性元件31及一個蕭特基二極體32彼此串聯地連接而這個串 %電路組成每-個根據本發明之記憶體單元33。在此，為 了簡化說明，所說明的是3x3的記憶體單元陣列。因為可變 電阻性元件31的電阻值不會變動，也就是，其電阻值在未 施加電壓時維持不變，可變電阻性元件31可以組成非揮發 性記憶體單元。這表示包含複數個這種根據本發明之記憶 體單元的記憶體裝置也是非揮發性記憶體裝置。 在記憶體裝置中，位元線BL〇, BL1及BL2(當其間的區別 為不必要時將簡單的參考為位元線BL)係配置在行的方向 上。位元線BL的一端點連接到位元線解碼器34，而相同的 另一端點則連接到讀取電路37。字線WL〇, wu及wl2(之 後當其間的區別為不必要時將簡單的參考為字線wl)係配 置在與位元線BL相交的列的方向。字線贾]^的兩端點分別連 接到子線解碼器3 5及3 6。更特定的，此位元線BL及字線Wl 配置成矩陣，記憶體單元係位在位元線BL與字線wl彼此相 又的位置上，其組成整個的記憶體單元陣列（記憶體裝置）。 另外，因為字線解碼器35及36配置在字線WL的兩端點， 例如，偶數字線WL與奇數字線|^可交錯的連接到字線解 碼器35及36。因此，字線WL的間距可以減少而同樣的電路 配置的邊距（電路尺寸）字線解碼器35及36則可以增加。由可 變電阻性元件3 1及蕭特基二極體32所組成的串聯電路（也 就是，根據本發明的記憶體單元33)之一端點連接到字線 WL而相同的另一端點則分開地連接到位元線bl。位元線解 92467.doc -20 - 1249166 石馬器34，及丰綠& ^ 予線解碼裔35及36與讀取電路37組成此周邊電 路在周邊电路中所使用的是，例如，MOSFET(CMOSFET)。 社仏為i阻的可、變電阻性元件31包含有著舞欽-型態結晶 構雙重對齊的甸欽型態結晶結構或類似的電阻性 材料’其顯示出有巨大磁電阻性或高溫超導電性。特定 的包阻性材料所使用的是Pr^yCaxMiiOKOcxcl)，Between the film and the impurity region. G 92467.doc -13- 1249166 In a fifth aspect of the production method according to the present invention, a brother cell unit composed of a series circuit of a variable resistive element and a Schottky diode is formed on a semiconductor substrate a production method comprising the steps of: forming an insulating film having an opening on which an impurity region is exposed on a surface of the semiconductor substrate; depositing a metal film in the opening of the insulating film to constitute a variable resistive element electrode; depositing a variable resistive film having a first film thickness and constituting a resistor of the variable resistive element on the metal film; forming a Schottky diode by forming a metal telluride film between the impurity region and the metal film by heat treatment And depositing a variable resistive film of a second film thickness and forming a resistance on the variable resistive film having the first film thickness. In the sixth aspect of the production method according to the present invention, the production method in the fifth aspect is characterized in that the temperature of the heat treatment is a temperature at which the crystal characteristic of the variable resistive film having the first film thickness can be improved. In a seventh aspect of the production method according to the present invention, the production method in the fifth or sixth aspect is characterized in that the semiconductor substrate is a dream substrate, and the Schottky-pole has a Schottky barrier in the metal Between the film and the impurity region. In the viewpoint of the production side, the earth &# 玍 万 万 , , , , , , , , , , 观点 观点 观点 观点 观点 观点 观点 观点 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产 生产After the deposition of the resistive thin crucible, the processing is further performed. The temperature of the heat treatment is a temperature which can improve the crystal characteristics of the variable resistive film having the thickness of the second film and can lower the resistance value of the metallized film. 92467.doc _ 14 - 1249166 In a ninth aspect of the production method according to the present invention, a method of producing a memory cell composed of a variable resistive element and a Schottky diode series circuit on a semiconductor substrate is characterized in that the method comprises the steps of: Selectively forming a germanium region in an insulating film formed on a surface of the semiconductor substrate; depositing a metal film to form a variable resistive element electrode on the polysilicon region; depositing a component constituting the variable resistive element a variable resistance film of the resistor is on the metal film; and a metal chopping thin film is formed between the polysilicon region and the metal film by heat treatment To form a Schottky diode. In the tenth aspect of the production method according to the present invention, the production method in the ninth aspect is characterized in that the temperature of the heat treatment is a temperature at which the crystal characteristics of the variable resistive film can be improved. In an eleventh aspect of the production method according to the present invention, the production method of the ninth or tenth aspect is characterized in that the Schottky diode has a Schottky barrier and the metal halide film and the polycrystalline germanium Area & In a twelfth aspect of the production method according to the present invention, a method of producing a memory cell composed of a variable resistive element and a Schottky diode series circuit on a semiconductor substrate is characterized in that the method comprises the steps of: selecting Forming a polysilicon region in an insulating film formed on one surface of the semiconductor substrate; depositing a metal film constituting the electrode of the variable resistive element on the polysilicon region, depositing a first film thickness and composing a variable resistive film of a variable resistive element resistance is formed on the metal thin film; a Schottky diode is formed by forming a metal telluride thin layer between the polysilicon region and the metal thin film by heat treatment; and depositing The second film thickness of the variable resistive film and the electrical resistance is formed on the variable resistive film having the first film thickness. 92467.doc -15- 1249166 In the thirteenth aspect of the production method according to the present invention, the production method of the twelfth aspect is characterized in that the temperature of the heat treatment is a variable resistance film which can improve the thickness of the first film The temperature of the crystallization characteristics. In a fourteenth aspect of the production method according to the present invention, the production method of the twelfth or twelfth aspect is characterized in that the Schottky diode has a Schottky energy barrier in the metal halide film and the complex Between the wafer areas. In a fifteenth aspect of the production method according to the present invention, the production method of any one of the twelfth to fourteenth aspects, characterized in that the method further comprises the step of depositing the variable resistive film having the second film thickness Further heat treatment is performed, wherein the temperature of the heat treatment is a temperature which can improve the crystallization characteristics of the variable resistive film having the thickness of the second film and the resistance value of the metal halide film. In a sixteenth aspect of the production method according to the present invention, the production method of any one of the first to fourteenth aspects is characterized in that the metal thin film is formed of a molten metal resistant material. In a seventeenth aspect of the production method according to the present invention, the production method according to the sixteenth aspect is characterized in that the molten metal resistant material is selected from at least one of Pt, Ti, Co and Ni. According to the present invention, since the memory cell is composed of a series circuit of a variable resistive element and a Schottky diode, the threshold voltage of the diode in the forward direction can be reduced. Therefore, reading interference in a non-volatile memory cell is less likely to occur, and a memory device including such a memory cell is achievable. Further, according to the present invention, since the material having the word titanium-type crystal structure 92467.doc -16-1249166 is used in the variable resistive element, the resistance change rate of the variable resistive element can be increased. Because &, the capacity of the memory unit and the memory device can be greatly increased and electrical control can be easily realized. Further, according to the present invention, since the first electrode of the Schottky diode is composed of an impurity region of the semiconductor substrate, the semiconductor integrated circuit can be easily realized. In addition, since the second electrode is formed in the vertical direction by deposition, a highly integrated memory cell can be realized. Furthermore, since the first electrode of the Schottky diode can also be used as a word line, & a highly integrated memory device is achievable. Further, according to the present invention, since the metal telluride film is formed between the impurity region of the shi-ray substrate which becomes the first electrode of the Schottky diode and becomes the straight second electric (tetra) metal thin film, this Schottky The potential barrier is formed between the metal telluride film and the stone substrate (impurity region), and the diode threshold voltage in the forward direction is compared with the PN-junction diode in the forward direction. The power limit can be greatly reduced. In addition, the Schottky barrier structure is formed: a stable diode property between the metallization film and the germanium substrate (impurity region). Further, according to the present invention, since the impurity region is formed in the element region, the impurity region becomes the word line and the first two of the Schottky diodes form the dα. Therefore, the degree of integration of the memory unit and the scorpion device can be improved. Further, according to the present invention, since the variable resistivity (4) is formed on the second electrode of the Schottky diode by the flush mode, the body is accurately aligned in the vertical direction with the variable resistive soil-pole. In this case, variable 92467.doc -17- 1249166 The resistance value of the resistive component can be accurately controlled and the degree of integration of the memory unit and the memory device can be improved. Furthermore, according to the present invention, since the first electrode of the Schottky diode is composed of a polysilicon selectively formed on the insulating film, an element structure other than the memory cell in which the memory cells are stacked can be realized. . Therefore, the degree of integration of the memory unit and the memory device can be improved. Further, according to the present invention, since the metal telluride thin tantalum is formed between the impurity region of the tantalum substrate which becomes the first electrode of the Schottky diode and the metal thin film which becomes the second electrode thereof, this Schott The base energy barrier is formed between the metal halide film and the polysilicon region, and the threshold voltage of the diode in the forward direction is compared with the PN-junction diode in the forward direction. The voltage limit can be greatly reduced. Further, since the Schottky barrier is formed between the metal halide film and the crystal substrate (impurity region), stable diode characteristics can be obtained. Further, according to the present invention, the heat treatment for depositing the metal thin film to form the Schottky diode and the heat treatment for improving the crystallization characteristics of the variable resistive film by depositing the resistance of the variable resistive element are performed at the same time. . Therefore, since the number of heat treatments can be reduced, it is possible to produce a memory cell without adversely affecting peripheral circuits. Furthermore, according to the present invention, the variable resistive film is deposited twice and the formation of the Schottky diode and the improvement of the crystallization characteristics of the variable resistive film having the first film thickness can be performed at the same time by Heat treatment after deposition of the first film thickness of the variable resistive film. Therefore, since the number of heat treatments can be reduced, the memory cell production method can not produce adverse effects on the peripheral circuits. In addition, since there is a variable resistive thinness which is deposited after the thickness of the first thin layer is changed = the thickness of the film: the crystal characteristic is improved, the concavity/compensated conjunctiva may have a variable thickness of the first film according to this 2 = The variable resistance is thin and deposited, and the entire step-by-step improvement of the crystalline specific resistive film can be realized by the production of the memory unit. - Characteristics and Variables, according to the present invention, the f-based diode (especially the metal compound is thin, the resistance value can be further reduced) by the formation of the second film thickness f of the resistive film The heat treatment is performed again. In addition, there is a second = conductivity (4) resistive thin film crystallization characteristic of the root thickness of the variable resistive film is further improved, and the crystal characteristic and the variable resistive film are obtained. The above and further objects and features of the present invention will become more fully apparent from the following detailed description of the accompanying drawings. FIG. 5A and FIG. 5B are diagrams for explaining the outline of a memory device according to the present invention. FIG. 5A is a circuit diagram showing a memory cell array in which memory cells are arranged in a matrix, bit lines. And the word line is connected to the memory unit, and the peripheral circuit is connected to the bit line and n(4) is a table showing the power applied when the circuit shown in the figure is read. Reference numeral 3 丨 marks a variable resistive element whose resistance value is changed by the applied voltage with reference numeral 32 - Schottky diode, 92467.doc -19 - 1249166 which is controlled in the variable resistive element 31 The current flowing in. A variable resistive element 31 and a Schottky diode 32 are connected in series to each other and the string % circuit constitutes each memory unit 33 according to the present invention. Here, for simplicity of explanation, The memory cell array of 3x3 is illustrated. Since the resistance value of the variable resistive element 31 does not fluctuate, that is, the resistance value remains unchanged when no voltage is applied, the variable resistive element 31 can be made non-volatile. Memory unit. This means that the memory device comprising a plurality of such memory cells according to the invention is also a non-volatile memory device. In the memory device, the bit lines BL〇, BL1 and BL2 (when the difference therebetween) A simple reference is made to the bit line BL) in the direction of the row when unnecessary. One end of the bit line BL is connected to the bit line decoder 34, and the other end is connected to the read circuit 37. . The lines WL〇, wu and wl2 (when the difference between them is unnecessary, the simple reference is the word line w1) is arranged in the direction of the column intersecting the bit line BL. Connected to the sub-line decoders 3 5 and 36. More specifically, the bit line BL and the word line W1 are arranged in a matrix, and the memory cell is located at a position where the bit line BL and the word line w1 are adjacent to each other. It constitutes the entire memory cell array (memory device). In addition, since the word line decoders 35 and 36 are disposed at both ends of the word line WL, for example, the even-numbered lines WL and the odd-numbered lines can be interleaved. To the word line decoders 35 and 36. Therefore, the pitch of the word lines WL can be reduced and the margin (circuit size) word line decoders 35 and 36 of the same circuit configuration can be increased. One end of the series circuit composed of the variable resistive element 31 and the Schottky diode 32 (that is, the memory unit 33 according to the present invention) is connected to the word line WL and the other end is separated. Ground is connected to the bit line bl. Bit line solution 92467.doc -20 - 1249166 Stone horse 34, and Feng Green & ^ Pre-decoded 35 and 36 and read circuit 37 constitute this peripheral circuit used in the peripheral circuit, for example, MOSFET (CMOSFET). The variable resistive element 31 of the 阻 i 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 Sex. The specific barrier material used is Pr^yCaxMiiOKOcxcl).

La(1.x)CaxMnO3(0<x<1) , Nd(1.x)SrxMnO3(0<x<l) , Sr2FeMo06 .La(1.x)CaxMnO3(0<x<1), Nd(1.x)SrxMnO3(0<x<l), Sr2FeMo06.

Sr2FeW064類似的。根據由上述電阻性材料組成的電阻， 因^電阻值會隨著所施加的電遂而改變，其可以用作記憶 體4置+ #由讓匕隨著在信號改變之前或之後而更換電阻 值。此蕭特基二極體32係由藉由接合半導體及金屬而形成 :特基位能障而組成。當金屬矽化物(耐熔化的金屬矽化物） 疋由刀別把石夕萄半導體及把耐熱金屬當金屬地執行熱處理 幵y成蕭特基位旎卩羊可以形成在耐熱金屬矽化物及矽之 間（在71面上）。例如，在有鈦矽化物及&型態矽間的介面之 蕭特基二極體中，可以獲得〇.2V的順向臨限電壓。因為這 個值相較於PN-接合面二極體中的順向臨限電壓〇·5 v為一 半或更少，例如，記憶體|置中的讀取干擾的影響，可以 大大的減少。 蕭特基二極體32的第-電極（也就是陰極/負冑極）連接到 字線WL，蕭特基二極體32的第二電極（也就是，陽極/正電 極）連接到可變電阻性元件31之一端點而可變電阻性元件 31的另一端點則連接到位元線bl。 將說明記憶體裝置的基本動作例如，寫入，拭除及讀取 92467.doc -21 - 1249166 動作：首先，將要說明寫入方法的情形是位在位元線BLO 及字線WL0彼此相交位置上的記憶體單元33被選擇為選定 單元而資料被寫入到這個選定單元。分別地，寫入電壓 Vw(V)(之後，電壓的單位（V)將省略）施加到選定單元的位 元線BL0而電壓0則施加至相同的字線WL0。因此，因為當 作選定單元的記憶體單元33的蕭特基二極體32為順向偏 壓，寫入電壓Vw施加到此可變電阻性元件3 1並據之可變電 阻性元件3 1的電阻值變動。 因為在共用位元線BL0卻沒有共用字線WL0之行方向中 的其他記憶體單元（位在位元線BL0與字線WL1及WL2相交 的位置上並與之連接的記憶體單元），此位元線BL只是在位 元線BL及字線WL之間被選定，這樣的單元稱為半選定單元 (BL選擇）。雖然寫入電壓Vw施加到類似於選定單元之半選 定單元（BL選擇）的位元線BL0，電壓Vw/2施加至字線WL (字線WL1及WL2)所以半選定單元（BL選擇）兩端點間的電 位差異成為Vw/2。另外，因為在共用字線WL0但不共用位 元線BL0之列方向中的其他記憶體單元（位在字線WL0與位 元線BL1及BL2相交的位置上並與之連接的記憶體單元記 憶體單元），此字線WL只在位元BL及字線WL間選定，這樣 的單元稱為半選定單元（WL選擇）。雖然電壓0施加到此類似 於此選定單元的半選定單元（WL選擇）的字線WL0，電壓 Vw/2施加到位元線BL(位元線BL1及BL2)使得半選定單元 (WL選擇）兩個端點間的電位差異變成Vw/2。換句話說，藉 由設定寫入電壓Vw使得在半選定單元兩端點間的電位差 92467.doc -22- 1249166 異為Vw/2時對此可變電阻性元件3 1的寫入不會執行，而防 止寫入到半選定單元。 再者，因為相同電壓Vw/2施加在非選定單元（記憶體單元 位在位元線BL1及BL2與字線WL1及WL2相交的位置並與 之連接）的兩個端點，在記憶體單元的兩端點沒有發生電位 差異而因此寫入到可變電阻性元件31不會執行。因此，寫 入只針對選定單元執行，而對半選定單元及未選定單元的 寫不^執行。上述關連摘要在圖5B的表格中。施加在位 元，BL的電壓（BL)及施加在字線WL的電麼（WL)顯示在垂 直部分而以選定狀態分類的記憶體單元類別則顯示在表格 中：：：部分。另夕卜，記憶體單元的選定狀態分類為四種 、讫疋單元半選疋單元（BL選擇），半選定單元（WL選擇） 以及未選疋早几。雖然半選定單元與未選定單元被區分開 :做為表達說明的考量，此半選定單元可以包含在非選定 單凡中另外，蕭特基二極體32的連接方向（整流方向）可以 伙適田的反轉亚在這種情形下，冑由適當的改變施加電壓 的方向（極性)·，在與蕭特基二極體32連接方向（整流方向） 未反轉情形下的相同動作可以執行。 稽田k長句八电魘苑加的時間來執行。 外1取動作可藉由分別地施加讀取電屋Vr到選定單元 位凡線BL以及電壓〇到相 J子a Μ的予線WL。再者，類似於寫 動作的情形，加在未選 k疋早7L兩為點的電位差異要設定，Sr2FeW064 is similar. According to the resistance composed of the above-mentioned resistive material, since the resistance value changes with the applied electric power, it can be used as the memory 4 to set the value of the resistor to be replaced before or after the signal is changed. . The Schottky diode 32 is formed by bonding a semiconductor and a metal: a metastatic barrier. When the metal telluride (melt-resistant metal telluride) 疋 把 把 把 石 石 半导体 半导体 及 及 及 及 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 成 成 成 成 成 成 成 成Between (on the 71). For example, in a Schottky diode having an interface between a titanium telluride and a & type, the forward threshold voltage of 〇.2V can be obtained. Since this value is half or less compared to the forward threshold voltage 〇·5 v in the PN-junction diode, for example, the influence of read disturb in the memory | can be greatly reduced. The first electrode (i.e., the cathode/negative drain) of the Schottky diode 32 is connected to the word line WL, and the second electrode (i.e., the anode/positive electrode) of the Schottky diode 32 is connected to the variable One end of the resistive element 31 and the other end of the variable resistive element 31 are connected to the bit line bl. The basic operations of the memory device will be described, for example, writing, erasing, and reading. 92467.doc -21 - 1249166 Action: First, the case where the writing method is to be described is where the bit line BLO and the word line WL0 intersect each other. The upper memory unit 33 is selected as the selected unit and the data is written to this selected unit. Separately, the write voltage Vw(V) (hereinafter, the unit of voltage (V) will be omitted) is applied to the bit line BL0 of the selected cell and the voltage 0 is applied to the same word line WL0. Therefore, since the Schottky diode 32 of the memory cell 33 as the selected cell is forward biased, the write voltage Vw is applied to the variable resistive element 31 and the variable resistive element 3 1 is used. The resistance value changes. Because the shared bit line BL0 does not share other memory cells in the row direction of the word line WL0 (a memory cell that is located at a position where the bit line BL0 intersects the word lines WL1 and WL2 and is connected thereto), this The bit line BL is selected only between the bit line BL and the word line WL, and such a cell is referred to as a semi-selected cell (BL selection). Although the write voltage Vw is applied to the bit line BL0 similar to the half selected cell (BL select) of the selected cell, the voltage Vw/2 is applied to the word line WL (word lines WL1 and WL2) so the half selected cells (BL select) two The potential difference between the endpoints becomes Vw/2. In addition, because other memory cells in the column direction of the common word line WL0 but not the bit line BL0 are shared (memory cell memory in which the bit line WL0 intersects with the bit lines BL1 and BL2 and is connected thereto) The body cell WL is selected only between the bit BL and the word line WL. Such a cell is called a semi-selected cell (WL selection). Although voltage 0 is applied to word line WL0 which is similar to the half selected cell (WL select) of this selected cell, voltage Vw/2 is applied to bit line BL (bit lines BL1 and BL2) such that half selected cells (WL select) two The potential difference between the endpoints becomes Vw/2. In other words, by setting the write voltage Vw such that the potential difference 92467.doc -22-1249166 between the points of the half-selected cells is different as Vw/2, the writing of the variable resistive element 3 1 is not performed. While preventing writes to semi-selected cells. Furthermore, since the same voltage Vw/2 is applied to the two end points of the unselected cells (the memory cell bits are at the position where the bit lines BL1 and BL2 intersect with the word lines WL1 and WL2 and are connected thereto), in the memory cell The potential difference does not occur at the both end points, so writing to the variable resistive element 31 is not performed. Therefore, writes are only performed for selected cells, while writes to semi-selected cells and unselected cells are not executed. The above related summary is in the table of Figure 5B. The memory cell type that is applied to the bit, the voltage of BL (BL) and the voltage applied to word line WL (WL) are displayed in the vertical portion and sorted in the selected state are displayed in the table::: portion. In addition, the selected states of the memory cells are classified into four types, a cell half-selection cell (BL selection), a semi-selected cell (WL selection), and an unselected cell. Although the semi-selected unit is distinguished from the unselected unit: as a description of the expression, the semi-selected unit may be included in the unselected unit. In addition, the connection direction (rectifying direction) of the Schottky diode 32 may be appropriate. In this case, the direction in which the voltage is applied (polarity) is appropriately changed, and the same action in the case where the connection direction (rectification direction) with the Schottky diode 32 is not reversed can be performed. . Ji Tian k long sentence eight electric 魇 Yuan plus time to implement. The outer 1 take action can be performed by separately applying the read electric house Vr to the selected unit bit line BL and the voltage 〇 to the pre-line WL of the phase J a 。. Furthermore, similar to the case of a write action, the potential difference added to the unselected k疋 early 7L is set.

Vr/2。也就是，圖5B中 W馬入电壓Vw可替換為讀取電壓Vr (具體實例1). 、 92467.doc -23- 1249166 圖6到圖12為解釋具體實例1中根據本發明之記憶體單元 的生產方法步驟的概要圖。在每一圖示中，形成在其中的 5己憶體卓元區域（之後’參考為記憶體區域）的記憶體單元及 形成在其中的周邊電路區域（之後，參考為周邊區域）的周邊 電路分別顯示在左邊及右邊。每一圖示顯示生產步驟中記 憶體單元（蕭特基二極體及可變電阻性元件的串聯電路）及 周邊電路（用在周邊電路中的N-通道MOSFET顯示為代表範 例）的切面結構。另外，在每一圖示中，顯示切面的斜線做 適當的省略。雖然MOSFET—般是由組合P-通道m〇sfet& N-通道MOSF马T.而組成，在此的N-通道MOSFET只是為了簡 化而顯示。 及類似的。例如， 形成的。一雜質d 體區域中，藉由南 圖6為顯示元件絕緣區域狀態的概要圖，蕭特基二極體的 第一電極與N-通道MOSFET係形成在半導體基板上。元件 絶緣區域2係形成來適當的式樣化在半導體基板y之後參 考為基板）上。例如，基板1為第一傳導型態（P-型態）的矽單 曰曰另外，基板1可以是形成在一絕緣基板上的半導體薄膜 ，元件絕緣區域2是以矽氧化物薄膜（Si〇2)Vr/2. That is, the W-input voltage Vw in FIG. 5B can be replaced with the read voltage Vr (Specific Example 1). , 92467.doc -23 - 1249166 FIG. 6 to FIG. 12 are diagrams for explaining the memory unit according to the present invention in Concrete Example 1. A summary of the production method steps. In each of the illustrations, a memory cell in which five memory cells are formed (hereinafter referred to as a memory region) and a peripheral circuit region (hereinafter, referred to as a peripheral region) formed therein Displayed on the left and right respectively. Each of the figures shows a slice structure of a memory cell (a series circuit of Schottky diodes and variable resistive elements) and peripheral circuits (N-channel MOSFETs used in peripheral circuits are representative examples) in the production steps. . Further, in each of the drawings, the oblique line showing the cut surface is appropriately omitted. Although the MOSFET is generally composed of a combined P-channel m〇sfet & N-channel MOSF horse T., the N-channel MOSFET here is shown for simplicity. And similar. For example, formed. In the impurity d body region, a schematic diagram showing the state of the element insulating region is shown in Fig. 6, and the first electrode of the Schottky diode and the N-channel MOSFET are formed on the semiconductor substrate. The element insulating region 2 is formed to be appropriately patterned and referred to as a substrate after the semiconductor substrate y. For example, the substrate 1 is a first conductive type (P-type). Alternatively, the substrate 1 may be a semiconductor thin film formed on an insulating substrate, and the element insulating region 2 is a tantalum oxide film (Si〇). 2)

度整合的記憶體單元。在此， 5艰成，而結果是可以形成高 說明三個雜質區域10(對應到 92467.doc -24 - 1249166 —個予線WL)。另外，因為此雜質區域ίο是由自行對齊方 式形成在元件絕緣區域2，結果是可以準確地樣式化而形 成，蕭特基二極體的特性可以有確定的一致化。 在纪憶體區域中，-絕緣薄膜11例如矽氧化物薄膜，例 如的，在雜質區域10外的形成。藉由形成絕緣薄膜11，因 為°己隐體區域中的元件絕緣區域2及雜質區域10可加以塗 層，記憶體區域可不受周邊區域處理的影響。 /在周邊區域中，^通道]^031^1 (之後參考為M0SFET) 係，據普通CMOS處理步驟的形成。藉由執行利用第二傳導 型態其與基板1-不同的離子生物之離子植入到_附區 域被το件絕緣區域2ϋ繞的通道，此通道的密度受到控制。 接著閘道絶緣薄膜3是藉由熱氧化或類似的形成，並接著 複晶矽以LP-CVD方法及類似的沈積。接著，複晶矽以微影 式樣化形成以複晶矽形成之閘極電極4。此整合程度可由一 般的在通道長度的方向上將閘極電極14的尺寸最小化而改 善。接著，第二傳導型態的離子生物植入到在通道長度方 向上對應到閘極電極4的端點部分之基板丨部分以形成低密 度之LDD(輕度換雜的沒極）區域5。接著，一矽氧化物薄膜 沈積在MOSFET區域中而一側壁6是由回蝕刻形成。接著， 此第二傳導型態離子生物被以高密度植入以形成源極區域 7以及沒極區域8。為了在源極區域…及極區域8中藉由自 行對齊方式地形成秒化物（也就是，形成矽化物：自行對齊 的矽化物）’閘極電極4,源極區域7及汲極區域8的矽表面 被暴露出來，並接著一鈷（Co)薄膜，例如，形成在整個的 92467.doc -25- 1249166 基板1並由上升的悶火及類似的加熱。鈷與矽藉由這個加熱 起化學反應而形成一鈷矽化物薄膜9。另外，因為沈積在絕 緣薄膜11表面上的鈷沒有因加熱與矽氧化物薄膜起化學反 應’銘石夕化物沒有形成在記憶體區域中。加熱之後，未起 化學反應的始薄膜適當的被移除。 圖7為顯示蕭特基二極體電極的開口形成在層間絕緣薄 膜中以形成記憶體單元的狀態的概要圖。例如，以矽氧化 物薄膜形成的絕緣薄膜12形成為層間絕緣薄膜12並以cMp (化學機械拋光）方法平坦化而開口 12w則形成在記憶體區 域中的絕緣薄膜12中。另外，適當的形成此開口 12w以便對 齊雜質區域10。 圖8為顯示蕭特基二極體第二電極形成處之狀態的概要 圖。同時做為蕭特基二極體的第二電極與可變電阻性元件 的下方電極的一金屬薄膜14藉由以CMP方法或回蝕刻方法 埋在開口 12W中形成（沈積）。在這個時間點，對埋下深度加 以凋整使得金屬薄膜14的上方端點可以位在相對開口 12〜 上端點的基板1這邊。換句話說，形成此金屬薄膜14使之低 於開口 12w的高度以便開口 12W的上方端可以暴露出來。結 果，因為開口 12w的上方端點仍維持不變，要在下一步驟（參 閱圖9)形成的一可變電阻性薄膜15L(電阻15)可以在此開口 12w (金屬薄膜14)中藉由自行對齊的方式形成。金屬薄膜μ 的材料最好是耐熔化金屬材料，例如，且特別是pt，Ti， Co及Νι中的任一個或是其適當的組合，就稍後要形成之可 k電阻性薄膜15L材料黏性，安全性及類似的觀點來看。 92467.doc -26 - 1249166 圖9為顯示可變電阻性薄膜沈積處狀態的概要圖。沈積此 變電阻性薄膜15L使之填充開口 12w的上方端點部分。適當 的決定可變電阻性薄膜15L的薄膜厚度，使要在稍後說明之 電阻15的電阻值可以是預定的值。例如，使用 ΡΓ(1-χ；^χΜη〇3(0<χ<1)(之後參考為pCM〇)做為此可變電阻 性薄膜15L。此可變電阻性薄膜1 5l包含一堆疊結構的第一 可變電阻性薄膜15a及一第二可變電阻性薄膜15b。首先， /尤積PCMO以便其第一薄膜厚度薄於要形成此第一可變電 阻性薄膜l5a之可變電阻性薄膜15L的薄膜厚度並以第一溫 度對此薄膜執行·熱處理。快速的執行第一溫度的熱處理一 知:時間，利用RTA(快速熱悶火）方法以減少對M〇SFET，雜 質區域10及類似的影響。另外，此第一溫度必須要滿足的 條件是金屬薄膜14(蕭特基二極體的第二電極以及可變電 阻性元件的下方電極）要可與此雜質區域1〇(矽）起化學反應 並變成金屬矽化物（耐熔化的金屬矽化物）以便可形成金屬 矽化物薄膜16(大約800〇C，在以的情形），以及此第一可變 電阻性薄膜15a的結晶特性可以改善（大約6〇〇。〇，在pcM〇 的情形）。 也就是，當熱處理在滿足上述條件的第一溫度執行時， 此金屬矽化物薄膜16形成並且此第一可變電阻性薄膜 的結晶特性也可以改善。當此金屬矽化物薄膜16形成時， 結果是一蕭特基位能障形成在此金屬矽化物薄膜16及雜質 區域10之間。結果，形成此蕭特基二極體，其第一電極為 此雜質區域丨〇而其第二電極為此金屬薄膜14(金屬矽化物 92467.doc -27- 1249166 薄膜16)。另外，因為蕭特基二極體的雜質區域忉之第一電 極為η-型態的，變成了陰極，而做為蕭特基二極體第二電 極的金屬薄膜14則變成陽極。 在第一温度的熱處理之後，沈積pCM〇以 膜厚度之第二可變電阻性薄膜15b以便與第一可 溥膜15a的第一薄膜厚度一起有等於可變電阻性薄膜说的 薄膜厚度’而其熱處理係在第二溫度上執行。由在第一溫 度上的熱處理形成之金屬矽化物薄膜16藉由在第二溫度上 的熱處理降低其電阻而沈積的第二可變電阻性薄膜^匕的 結晶特性係根據第一可變電阻性薄膜15a的結晶特性而可 獲得進-步改善。另外，此第二溫度必須滿足的條件是要 能降低金屬矽化物薄膜16的電阻值並改善第二可變電阻性 薄膜15b的結晶特性。應注意，此第二溫度可以與第一溫度 相同或不高於第一溫度。為了形成此有著較佳結晶特性之 可變電阻性薄膜15L，第一可變電阻性薄膜15a的第一薄膜 厚度最好要薄於第二可變電阻性薄膜15fc的第二薄膜厚 度。在此，可變電阻性薄膜15；L沈積由兩個分別動作（形成） 的原因疋因為此第二可變電阻性薄膜1 5 b的形成反應了較 低之第一可變電阻性薄膜15a的結晶特性，第二可變電阻性 薄膜15b的結晶特性相較於其由一沈積處理形成的情形則 獲得進一步改善。另外，雖然可變電阻性薄膜1 5L是由上 述兩個分別沈積處理形成，其也可以由單一個沈積處理來 形成的。 在該例子中，，在形成可變電阻性薄膜15L以便藉由一個沈 92467.doc -28- 1249166 積而有預定的薄膜厚度之後，可變電阻性薄膜15L的結晶特 性獲得改善而此金屬矽化物薄膜丨6是由一個熱處理形成， 藉之形成此蕭特基二極體。 圖10為顯示可變電阻性元件形成處狀態的概要圖。在第 二溫度的熱處理之後，包含Pt薄膜l7a&TiN薄膜i7b的金屬 薄膜17形成在可變電阻性薄膜15L的整個表面上。接著，此 TiN薄膜17b及此pt薄膜17a藉由微影及非等方性蝕刻依序 的處理’而可變電阻性薄膜15L則利用處理過的pt/TiN(此 Pt薄膜17a及此TiN薄膜17b)做為遮罩蝕刻來形成電阻15。 因為此可變t阻性薄膜15L係利用處理過的pt/TiN做為遮 罩的處理，此電阻15及金屬薄膜17是以自行對齊方式形成。 接著，有著金屬薄膜14連接到此電阻15一端點做為下方 電極以及有金屬薄膜17連接到電阻15另一端點做為上方電 極的可紜電阻性元件形成。因為此金屬薄膜丨4也做為此蕭 特基二極體的第二電極，此蕭特基二極體的第二電極的狀 恶疋其藉由自行對齊的方式連接到可變電阻性元件的一個 端點·。因此，此蕭特基二極體及此可變電阻性元件可以確 定的彼此對齊形成使其整合程度可以進一步改善。因為此 金屬薄膜14及此電阻15係藉由自行對齊的方式彼此對齊， 可以準確的控制可變電阻性元件下方電極的面積而可以準 確的控制其電阻值。再者，因為此金屬薄膜17及此電阻。 也是藉由自行對齊的方式彼此對齊，此電阻值可以準確的 控制而整合程度也進一步的改善。 圖11為顯示接線形成前表面被平坦化處狀態的概要圖。 92467.doc -29- 1249166 一絕緣薄膜18由矽氧化物薄膜形成，例如，沈積在絕緣薄 膜12上而金屬薄膜17則做為層間絕緣薄膜，接著藉由CMP 方法或類似的加以平坦化。 圖12為顯示接線形成處狀態的概要圖。例如，其顯示鎢 接線19由利用鎢之波狀花紋技術形成處的狀態。如上述 的，周邊區域中的元件以及在記憶體區域中的元件可以不 彼此衫響的分別形成。此鶴接線棒l)及此雜質區域 1 OjWL)刀別形成為記憶體區域中的位元線及字線评乙。 —在子線WL與位元線bl彼此相交位置上的記憶體單元 被選擇而可對之執行寫入，拭除及讀取動作。另外，因為 鶴接線19(WP)係形成在周邊區域中做為電路接線，故可以 執行記憶體裝置所需要的信號處理。 (具體實例2) 圖13到圖2〇為解釋根據本發明之記憶體單元生產方法之 具體實例2生產步驟的概要圖。在每個圖示中，形成在其中 的Z It體單tl區域（在之後參考為記憶體區域）的記憶體單 元以及形成在其中的周邊電路區域（之後參考為周邊區域） 的周邊私路分別顯不在左邊與右邊。每個圖示顯示生產步 驟中記憶體單元（此蕭特基二極體及此可變電阻性元件的 串恥電路）及周邊電路（顯示一用在周邊電路中的N_通道 MOSFET做為代表性範例）的切面結構。在記憶體區域中， 周邊毛路（邛分的周邊電路及類似的）可以提供在記憶體單 兀下方。卩分並做此周邊電路的範例，顯示M〇sfet形成在 。己隱體單元下方部分的情形。另外，在每個圖示中，用來 92467.doc -30- 1249166 顯示此切面的斜線被適當的省略。雖然此CMOS —般是由結 合P-通道MOSFET及N-通道MOSFET而組成，在此為簡化只 顯示N-通道MOSFET。再者，與具體實例2中相同的或對應 部分配予相同的參考號碼（一部份被省略）而不對之做說 明。另外，類似於具體實例1的情形，基板丨可以是半導體 薄膜並類似的形成在絕緣基板上。Degree of integrated memory unit. Here, 5 is difficult, and as a result, three impurity regions 10 (corresponding to 92467.doc -24 - 1249166 - one WL WL) can be formed. Further, since the impurity region ί is formed in the element insulating region 2 by self-alignment, as a result, it can be accurately patterned, and the characteristics of the Schottky diode can be surely uniformized. In the memory region, an insulating film 11 such as a tantalum oxide film is formed, for example, outside the impurity region 10. By forming the insulating film 11, since the element insulating region 2 and the impurity region 10 in the hidden region can be coated, the memory region can be prevented from being affected by the peripheral region. / In the peripheral area, ^ channel] ^ 031 ^ 1 (hereinafter referred to as M0SFET) system, according to the formation of ordinary CMOS processing steps. The density of the channel is controlled by performing the implantation of ions of the ionic organism different from the substrate 1 by the second conduction pattern to the channel surrounded by the ohmic region 2 of the region. Then, the gate insulating film 3 is formed by thermal oxidation or the like, and then subjected to a polycrystalline germanium by an LP-CVD method and the like. Next, the polysilicon is patterned in a lithographic manner to form a gate electrode 4 formed by a polysilicon. This degree of integration can be improved by generally minimizing the size of the gate electrode 14 in the direction of the length of the channel. Next, the ion of the second conductivity type is bioimplanted into the substrate portion corresponding to the end portion of the gate electrode 4 in the channel length direction to form a low density LDD (mildly replaced peak) region 5. Next, a tantalum oxide film is deposited in the MOSFET region and a sidewall 6 is formed by etch back. Next, this second conductivity type ion organism is implanted at a high density to form the source region 7 and the non-polar region 8. In order to form a secondary compound (ie, a telluride: self-aligned telluride) by self-alignment in the source region... and the polar region 8, the gate electrode 4, the source region 7 and the drain region 8 are formed. The surface of the crucible is exposed, and then a cobalt (Co) film, for example, is formed over the entire substrate of 92467.doc -25-1249166 and is heated by rising smoldering and the like. Cobalt and rhodium are chemically reacted by this heating to form a cobalt halide film 9. Further, since the cobalt deposited on the surface of the insulating film 11 is not chemically reacted with the tantalum oxide film by heating, the quartz crystal is not formed in the memory region. After heating, the initial film that has not undergone a chemical reaction is properly removed. Fig. 7 is a schematic view showing a state in which an opening of a Schottky diode electrode is formed in an interlayer insulating film to form a memory cell. For example, the insulating film 12 formed of the tantalum oxide film is formed as the interlayer insulating film 12 and planarized by the cMp (Chemical Mechanical Polishing) method, and the opening 12w is formed in the insulating film 12 in the memory region. Further, this opening 12w is appropriately formed to align the impurity region 10. Fig. 8 is a schematic view showing a state in which a second electrode of a Schottky diode is formed. A metal film 14 which serves as a second electrode of the Schottky diode and a lower electrode of the variable resistive element is formed (deposited) by being buried in the opening 12W by a CMP method or an etch back method. At this point of time, the buried depth is soaked so that the upper end of the metal film 14 can be positioned on the side of the substrate 1 opposite to the upper end 12~. In other words, the metal film 14 is formed to be lower than the height of the opening 12w so that the upper end of the opening 12W can be exposed. As a result, since the upper end point of the opening 12w remains unchanged, a variable resistance film 15L (resistance 15) to be formed in the next step (refer to FIG. 9) can be self-contained in the opening 12w (metal film 14). The alignment is formed. The material of the metal film μ is preferably a material resistant to molten metal, for example, and particularly any one of pt, Ti, Co and Νι, or a suitable combination thereof, and a k-resistive film 15L material to be formed later is viscous. Sex, security and similar perspectives. 92467.doc -26 - 1249166 FIG. 9 is a schematic view showing a state of deposition of a variable resistive film. This variable resistance film 15L is deposited to fill the upper end portion of the opening 12w. The film thickness of the variable resistive film 15L is appropriately determined so that the resistance value of the resistor 15 to be described later may be a predetermined value. For example, 可变(1-χ; ^χΜη〇3 (0<χ<1) (hereinafter referred to as pCM〇) is used as the variable resistive film 15L. The variable resistive film 155 includes a stacked structure. The first variable resistive film 15a and the second variable resistive film 15b. First, the PCMO is especially so that the first film thickness is thinner than the variable resistive film on which the first variable resistive film 15a is to be formed. 15L film thickness and heat treatment of the film at the first temperature. Rapid implementation of the first temperature heat treatment knows: time, using RTA (rapid hot smoldering) method to reduce the M 〇 SFET, impurity region 10 and the like In addition, the first temperature must be satisfied by the metal film 14 (the second electrode of the Schottky diode and the lower electrode of the variable resistive element) and the impurity region 1 (〇) Chemically reacting and becoming a metal telluride (melting resistant metal halide) so that a metal halide film 16 can be formed (about 800 〇C, in the case of Å), and the crystallization characteristics of the first varistor film 15a can be Improvement (about 6 〇〇. Hey, at In the case of pcM〇), that is, when the heat treatment is performed at the first temperature satisfying the above conditions, the metal halide film 16 is formed and the crystal characteristics of the first variable resistance film can be improved. When the film 16 is formed, as a result, a Schottky barrier is formed between the metal halide film 16 and the impurity region 10. As a result, the Schottky diode is formed, and the first electrode is the impurity region. The second electrode is the metal thin film 14 (metal ruthenium 92467.doc -27-1249166 thin film 16). In addition, since the first electrode of the impurity region of the Schottky diode is η-type, it becomes The cathode is formed, and the metal film 14 as the second electrode of the Schottky diode becomes an anode. After the heat treatment at the first temperature, the second variable resistance film 15b having a film thickness of pCM is deposited to be the first The first film thickness of the film 15a together has a film thickness equal to that of the variable resistance film, and the heat treatment is performed at the second temperature. The metal film film 16 formed by the heat treatment at the first temperature is used. The crystallization characteristic of the second variable resistive film deposited by the heat treatment at the second temperature lowering the electric resistance thereof is based on the crystallization characteristics of the first variable resistive film 15a. Further, this second The temperature must satisfy the condition that the resistance value of the metal halide film 16 can be lowered and the crystallization characteristics of the second variable resistance film 15b can be improved. It should be noted that the second temperature may be the same as or not higher than the first temperature. In order to form the variable resistive film 15L having preferable crystal characteristics, the first film thickness of the first variable resistive film 15a is preferably thinner than the second film thickness of the second variable resistive film 15fc. Here, the variable resistive film 15; L deposition is caused by two separate actions (formation), because the formation of the second variable resistive film 15b reflects the lower first variable resistive film 15a. The crystallization characteristics of the second variable resistive film 15b are further improved as compared with the case where it is formed by a deposition process. Further, although the variable resistive film 15L is formed by the above two separate deposition processes, it may be formed by a single deposition process. In this example, after the variable resistive film 15L is formed so as to have a predetermined film thickness by a sinking of 92467.doc -28-1249166, the crystallization characteristic of the variable resistive film 15L is improved and the metal is deuterated. The film 丨6 is formed by a heat treatment to form the Schottky diode. Fig. 10 is a schematic view showing a state in which a variable resistive element is formed. After the heat treatment at the second temperature, the metal thin film 17 containing the Pt film 17a & TiN film i7b is formed on the entire surface of the variable resistive film 15L. Then, the TiN film 17b and the pt film 17a are sequentially processed by lithography and unequal etching, and the variable resistive film 15L utilizes the treated pt/TiN (the Pt film 17a and the TiN film). 17b) Forming the resistor 15 as a mask etch. Since the variable t-resistive film 15L is treated as a mask by using the treated pt/TiN, the resistor 15 and the metal film 17 are formed in a self-aligned manner. Next, a metal thin film 14 is connected to the end of the resistor 15 as a lower electrode and a metal thin film 17 is connected to the other end of the resistor 15 as a top resistive element. Since the metal thin film 丨4 also serves as the second electrode of the Schottky diode, the second electrode of the Schottky diode is connected to the variable resistive element by self-alignment. One of the endpoints. Therefore, the Schottky diode and the variable resistive element can be determined to be aligned with each other so that the degree of integration can be further improved. Since the metal thin film 14 and the resistor 15 are aligned with each other by self-alignment, the area of the electrode under the variable resistive element can be accurately controlled to accurately control the resistance value. Furthermore, this metal film 17 and this resistor are used. It is also aligned with each other by self-alignment. This resistance value can be accurately controlled and the degree of integration is further improved. Fig. 11 is a schematic view showing a state in which the front surface of the wiring is flattened. 92467.doc -29- 1249166 An insulating film 18 is formed of a tantalum oxide film, for example, deposited on the insulating film 12 and the metal film 17 is used as an interlayer insulating film, which is then planarized by a CMP method or the like. Fig. 12 is a schematic view showing a state in which a wiring is formed. For example, it shows a state in which the tungsten wiring 19 is formed by a wavy technique using tungsten. As described above, the elements in the peripheral area and the elements in the memory area can be formed separately from each other. The crane terminal rod l) and the impurity region 1 OjWL) are formed as bit lines and word lines in the memory region. - The memory cell at the position where the sub-line WL and the bit line b1 intersect each other is selected and the writing, erasing and reading operations can be performed thereon. In addition, since the crane wire 19 (WP) is formed in the peripheral area as a circuit wiring, the signal processing required for the memory device can be performed. (Specific example 2) Figs. 13 to 2B are schematic views for explaining the production steps of Concrete Example 2 of the memory cell production method according to the present invention. In each of the illustrations, a memory cell in which a Z It body single-t1 region (referred to as a memory region later) and a peripheral circuit region (hereinafter referred to as a peripheral region) formed therein are respectively respectively Not shown on the left and right. Each figure shows the memory cell in the production step (the Schottky diode and the string circuit of the variable resistive element) and the peripheral circuit (showing a N_channel MOSFET used in the peripheral circuit as a representative) Sexual paradigm). In the memory area, the peripheral hair path (the peripheral circuit of the minute and the like) can be provided below the memory unit. Divide and do an example of this peripheral circuit, showing that M〇sfet is formed in . The situation in the lower part of the hidden unit. In addition, in each of the illustrations, the oblique lines for 92467.doc -30-1249166 showing this section are appropriately omitted. Although this CMOS is generally composed of a combination of a P-channel MOSFET and an N-channel MOSFET, only the N-channel MOSFET is shown here for simplicity. Further, the same or corresponding parts as in the specific example 2 are assigned the same reference numerals (some of which are omitted) and will not be described. Further, similarly to the case of Concrete Example 1, the substrate 丨 may be a semiconductor film and similarly formed on the insulating substrate.

圖13為顯示形成N-通道MOSFET接著表面被平坦化處狀 態的概要圖。也就是，形成义通道訄⑽奸了（之後參考為 MOSFET)並接著堆疊一絕緣薄膜12，一阻隔薄膜2〇及一絕 緣薄膜21。例如，由矽氧化物薄膜形成的絕緣薄膜12形成 為層間絕緣薄膜並由CMP(化學機械拋光）方法平坦化並接 著形成一氮化物薄膜（S i N)做為阻隔薄膜2 〇以做為蝕刻的 阻隔物。另外，在記憶體區域與周邊區域中直到絕緣薄膜 12形成前的步驟與圖6及圖7中所顯示周邊區域的形成步驟 相同（具體實例1)。在阻隔薄膜2〇形成之後，例如，由矽氧 化物薄膜形成的絕緣薄膜21則形成為層間絕緣薄膜。 圖14為顯示在此層間絕緣薄財形成記憶體單元的開口 及形成與MOSFET接觸之開口之形成狀態的概要圖。藉由 利用阻隔薄膜2G做為阻隔物，絕緣薄膜21藉由微影及非等 方性姓刻加以㈣以便其可以有職的樣式。也就是，在 記憶體區域中，用來形成要在稍後步驟中形成複晶石夕區域 …的開口 21W(參閱圖1養，而在周邊區域中，用來开, 成要在之後㈣形成之源極電極山與汲極電極咖（來閱 謂的開口 21W形成。接著，在周邊區域中，為了與源極 92467.doc -31 - 1249166 區域7與汲極區域8接觸，源極區域7與汲極區域8的開口（接 觸的自格）藉由部分移除暴露在開口 21w的阻隔薄膜而進 一步的形成。 圖15為顯示沈積（填充）複晶矽在開口 12w中狀態的概要 圖。此複晶矽區域（22e，22s及22d)係藉由埋在有著預定樣 式且形成在絕緣薄膜21上的開口 21w中而形成（沈積）。例 如，包含鬲密度磷的複晶矽沈積在整個表面上並由cMp* 法或回蝕刻方法平坦化。因此，記憶體區域中由複晶矽形 成在周邊區域中的複晶矽區域22e及源極電極22s與汲極電 極22d被選擇悻的形成在開口 21w中。複晶矽要使用含有高 密度磷做為雜質的原因是因為複晶矽區域22e變成了蕭特 基二極體（及字線WL)的第一電極，最好能與源極電極22s 與汲極電極22d—起有著低電阻。因為複晶矽區域22e含有 磷做為雜質，因而變成了 型態。 圖16為顯示沈積可變電阻性薄膜狀態的要圖。同時做為 蕭特基二極體第二電極與可變電阻性元件下方電極的金屬 薄膜23L係沈積在絕緣薄膜21，複晶矽區域22e，元件電極 22s與汲極電極22d的平坦化表面上。另外，因為金屬薄膜 23L原則上並不需要在源極電極22s與汲極電極22d的表面 上，是可以不沈積的。金屬薄膜23L的材料最好是耐熔化的 金屬材料，例如並特別是，Pt，Ti，〇〇及犯或其適當組合 的任一個’就在之後要形成之可變電阻性薄膜24L(24a及 24b)材料黏性，安全性及類似的觀點來看。另外，類似於 具體實例1的精形，複晶矽薄膜22e與金屬薄膜231係藉由埋 92467.doc -32- 1249166 在絶緣薄膜21的開口中，而可變電阻性薄膜24L(24b在24a 及24b間的金屬薄膜23L這邊）可以藉由自行對齊方式地進 一步形成在此開口中。 形成金屬薄膜23L並接著沈積可變電阻性薄膜24[。適當 的决疋可變電阻性薄膜24L的薄膜厚度使得電阻24的電阻 值可變成預定值。在可變電阻性薄膜24L，使用的是例如Fig. 13 is a schematic view showing a state in which an N-channel MOSFET is formed and the surface is planarized. That is, a channel (10) is formed (hereinafter referred to as a MOSFET) and then an insulating film 12, a barrier film 2, and an insulating film 21 are stacked. For example, the insulating film 12 formed of a tantalum oxide film is formed as an interlayer insulating film and planarized by a CMP (Chemical Mechanical Polishing) method and then a nitride film (S i N) is formed as a barrier film 2 as an etching film. Barrier. Further, the steps before the formation of the insulating film 12 in the memory region and the peripheral region are the same as those in the peripheral regions shown in Figs. 6 and 7 (Specific Example 1). After the barrier film 2 is formed, for example, the insulating film 21 formed of a tantalum oxide film is formed as an interlayer insulating film. Fig. 14 is a schematic view showing a state in which an opening of the interlayer insulating memory cell is formed and an opening in contact with the MOSFET is formed. By using the barrier film 2G as a barrier, the insulating film 21 is engraved by lithography and non-equality (4) so that it can be used in a professional manner. That is, in the memory region, an opening 21W for forming a polylithic area to be formed in a later step (refer to Fig. 1 and in the peripheral region, for opening, forming after (four)) The source electrode mountain and the drain electrode coffee are formed by the opening 21W. Next, in the peripheral region, in order to contact the source region 92467.doc -31 - 1249166 region 7 and the drain region 8, the source region 7 The opening (contact self-lattice) of the drain region 8 is further formed by partially removing the barrier film exposed to the opening 21w. Fig. 15 is a schematic view showing a state in which the deposited (filled) germanium is in the opening 12w. The polysilicon regions (22e, 22s and 22d) are formed (deposited) by being buried in an opening 21w having a predetermined pattern and formed on the insulating film 21. For example, a germanium containing germanium density phosphorus is deposited throughout The surface is planarized by the cMp* method or the etch back method. Therefore, the germanium region 22e and the source electrode 22s and the drain electrode 22d which are formed in the peripheral region by the germanium in the memory region are selectively formed. In the opening 21w. The reason for using high-density phosphorus as an impurity is because the germanium germanium region 22e becomes the first electrode of the Schottky diode (and word line WL), preferably with the source electrode 22s and the drain electrode 22d. Since the polysilicon region 22e contains phosphorus as an impurity, it becomes a pattern. Fig. 16 is a diagram showing the state of depositing a variable-resistance film, and is also used as a second electrode of the Schottky diode. The metal thin film 23L with the lower electrode of the variable resistive element is deposited on the planarized surface of the insulating film 21, the germanium region 22e, the element electrode 22s and the drain electrode 22d. In addition, since the metal thin film 23L is not required in principle On the surface of the source electrode 22s and the gate electrode 22d, it may not be deposited. The material of the metal film 23L is preferably a metal material resistant to melting, such as, in particular, Pt, Ti, 〇〇 and its appropriate Any of the combinations 'is just after the viscosity of the variable resistive film 24L (24a and 24b) to be formed, safety and the like. In addition, similar to the fine form of the specific example 1, the polycrystalline germanium film 22e and metal film 231 By embedding 92467.doc -32-1249166 in the opening of the insulating film 21, the variable resistive film 24L (24b on the side of the metal film 23L between 24a and 24b) can be further formed by self-alignment. In the opening, a metal thin film 23L is formed and then a variable resistive film 24 is deposited. [The appropriate thickness of the film of the variable resistive film 24L allows the resistance value of the resistor 24 to become a predetermined value. In the variable resistive film 24L , using, for example

Pr(1-x)CaxMn03 (0<χ<ΐ)(之後，參考為pCM〇)。此可變電阻 性薄膜24L為包含第一可變電阻性薄膜24a及第二可變電阻 性薄膜24b之一堆疊結構。首先，沈積pCM〇使之有比可變 電阻性薄膜24L薄膜厚度薄的第一薄膜厚度而形成第一可 k電阻性薄膜24a並在第一溫度上對此薄膜執行熱處理。第 一溫度上的熱處理係利用快速的執行RTA(快速熱悶火）及 類似的方法一短時間以便減少對M〇SFET，複晶矽區域2k 及類似的影響。另外，類似具體實例丨的，此第一溫度必須 滿足的條件是金屬薄膜23L (蕭特基二極體的第二電極與可 k電阻性元件的下方電極）與複晶矽22e可起化學反應變成 金屬矽化物（耐熔化的金屬矽化物）以使金屬矽化物薄膜25 可以形成（在Pt的例子大約為8〇〇〇c)，以及第一可變電阻性 薄膜24a的結晶特性可獲得改善（在PCMO的例子大約為 600°C)。 也就是，當在滿足上述條件的第一溫度上執行熱處理， 形成此金屬矽化物薄膜25而此第一可變電阻性薄臈2物的 …曰曰特性可以獲得改善。當金屬矽化物薄膜25形成時，結 果，蕭特基位能障形成在此金屬矽化物薄膜乃及複晶矽22〇 92467.doc -33- 1249166 之間。結果，形成其第一電極為此複晶矽區域22e而其第二 電極為此金屬薄膜23L(金屬矽化物薄膜25)的蕭特基二極 體。另外，因為做為蕭特基二極體第一電極的複晶矽22e為 η-型悲，其變成陰極，而做為蕭特基二極體第二電極的金 屬薄膜23L則變成陽極。因為形成複晶矽區域22e及金屬矽 化物薄膜25使之與自行對齊的開口一致，可以準確的樣式 化來形成，而其結果是蕭特基二極體的特性可確保一致化。 在第一溫度上的熱處理之後，沈積pCM〇以形成有第二薄 膜厚度的第二可變電阻性薄膜24b以使之與第一可變電阻 性薄膜24a的箄一薄膜厚度一起等於可變電阻性薄膜24l的 薄膜厚度，其所執行的熱處理是在第二溫纟。由在第—溫 度上執行熱處理形成的金屬矽化物薄膜25藉由在第二溫度 上的熱處理以降低其電阻，而根據可變電阻性薄膜24&結晶 寺沈積之苐一可變電阻性薄膜2扑的結晶特性可獲得進 一步改善。另外，此第二溫度必須滿足的條件是要降低金 屬石夕化物薄膜25的電阻而第二可變電阻性薄膜⑽的結晶 特性獲付改善。應注意的是，第二溫度可以與第一溫度相 同或疋不同於第一溫度。為了形成有最佳結晶特性的可變 ，阻性薄膜24L，第一可變電阻性薄膜24a的第一薄膜厚度 最好比第二可變電阻性薄膜24b的第二薄膜厚度為薄。在 此，可變電阻性薄膜24L是由兩個分開的沈積處理來沈積的 原因是因為第二可變電阻性薄膜2仆的形成反應了較低之 第一可變電阻性薄膜24a的結晶特性，其結晶特性相較於以 一個沈積處理形成的情形獲得進_步改善。另夕卜雖然在 92467.doc -34- 1249166 上面可變電阻性薄膜24L是由兩分別的沈積處理形成，其是 可以一個沈積處理形成的。在該例子中，在可變電阻性薄 膜24L藉由一個沈積處理形成以有預定薄膜厚度之後，此可 變電阻性薄膜24L的結晶特性獲得改善，而此金屬耗物薄 膜25是由一個熱處理形成，藉之形成蕭特基二極體。 圖17為顯示變成可轡雷p且,降& # 艾取j交私I且注兀件上方電極之金屬薄膜沈 積處狀態的概要圖。做為可變電阻性元件上方電極之金屬 薄膜26L係沈積在可變電阻性薄膜24L的整個表面上。金屬 薄膜26L的材料最好是耐熔化金屬材料，例如且最好是pt，Pr(1-x)CaxMn03 (0<χ<ΐ) (hereinafter, referred to as pCM〇). The variable resistive film 24L is a stacked structure including one of the first variable resistive film 24a and the second variable resistive film 24b. First, the pCM is deposited to have a first film thickness thinner than the thickness of the variable resistive film 24L to form the first k-resistive film 24a and heat treatment is performed on the film at the first temperature. The heat treatment at the first temperature utilizes a fast execution of RTA (rapid hot smoldering) and a similar method for a short period of time in order to reduce the effects on the M 〇 SFET, the polysilicon region 2k and the like. In addition, similar to the specific example, the first temperature must satisfy the condition that the metal thin film 23L (the second electrode of the Schottky diode and the lower electrode of the k-resistive element) and the polysilicon 22e can react chemically. It becomes a metal halide (melting resistant metal halide) so that the metal halide film 25 can be formed (about 8 〇〇〇 c in the example of Pt), and the crystallization characteristics of the first variable resistance film 24a can be improved. (The example in PCMO is about 600 ° C). That is, when the heat treatment is performed at the first temperature satisfying the above conditions, the metal halide film 25 is formed and the ?? characteristics of the first variable resistive thin film can be improved. When the metal telluride film 25 is formed, as a result, a Schottky barrier is formed between the metal halide film and the polycrystalline germanium 22〇 92467.doc -33-1249166. As a result, a Schottky diode whose first electrode is the germanium germanium region 22e and whose second electrode is the metal thin film 23L (metal germanide film 25) is formed. Further, since the polysilicon 22e which is the first electrode of the Schottky diode is η-type sorrow, it becomes a cathode, and the metal thin film 23L which is the second electrode of the Schottky diode becomes an anode. Since the germanium germanium region 22e and the metallization film 25 are formed to conform to the self-aligned opening, they can be formed accurately, and as a result, the characteristics of the Schottky diode can be ensured. After the heat treatment at the first temperature, the pCM is deposited to form the second variable resistive film 24b having the second film thickness to be equal to the variable resistance together with the film thickness of the first variable resistive film 24a. The film thickness of the film 24l, which is performed at the second temperature. The metal telluride film 25 formed by performing the heat treatment at the first temperature is reduced in electrical resistance by heat treatment at the second temperature, and the variable resistive film 2 is deposited according to the variable resistive film 24 & The crystallization characteristics of the puff can be further improved. Further, the second temperature must satisfy the condition that the electric resistance of the metal lithium film 25 is lowered and the crystallization characteristics of the second varistor film (10) are improved. It should be noted that the second temperature may be the same as or different from the first temperature. In order to form the variable, resistive film 24L having the optimum crystal characteristics, the first film thickness of the first variable resistive film 24a is preferably thinner than the thickness of the second film of the second variable resistive film 24b. Here, the reason why the variable resistive film 24L is deposited by two separate deposition processes is because the formation of the second variable resistive film 2 reflects the crystallization characteristics of the lower first variable resistive film 24a. The crystallization characteristics are improved as compared with the case of forming in a deposition process. Further, although the variable resistive film 24L is formed by two separate deposition processes at 92467.doc - 34 - 1249166, it can be formed by a deposition process. In this example, after the variable resistive film 24L is formed by a deposition process to have a predetermined film thickness, the crystal characteristics of the variable resistive film 24L are improved, and the metal consumable film 25 is formed by a heat treatment. By means of the formation of the Schottky diode. Fig. 17 is a schematic view showing a state in which the metal thin film of the electrode above the injection element is deposited in a state in which it can become a smashing p and a drop. A metal film 26L as an electrode above the variable resistive element is deposited on the entire surface of the variable resistive film 24L. The material of the metal film 26L is preferably a molten metal resistant material, for example, and preferably pt.

Τι Co及Νι或其·適當組合的任一個，就可變電阻性薄膜24L 的黏性，文全性及類似的觀點而言。在此，使用h薄膜做Any one of Τι Co and Νι or an appropriate combination thereof is viscous, versatile, and the like of the variable resistive film 24L. Here, using h film

為金屬薄膜26L。接著，一由TiN薄膜形成之硬遮罩薄膜27L 沈積在此金屬薄膜26L的整個表面上，當金屬薄膜26L被蝕 刻時做為硬遮罩蝕刻的遮罩，而此金屬薄膜26L及此硬遮罩 薄膜27L係堆疊的形成。 圖18為顯示可變電阻性元件形成處狀態的概要圖。在圖 17中顯示的步驟之後，此硬遮罩薄膜27L以微影及非等方性 蝕刻加以處理而形成有一預定樣式（更特定的，可變電阻性 元件上方電極的樣式）之硬遮罩27。接著，藉由使用此硬遮 罩27做為遮罩的蝕刻掉金屬薄膜26L，可變電阻性薄膜24乙 及金屬薄膜23L，形成金屬薄膜26(及此硬遮罩27)做為可變 電阻性元件，電阻24的上方電極以及金屬薄膜23做為可變 電阻性元件下方電極。 因為此金屬薄膜23同樣也做為蕭特基二極體的第二電 92467.doc -35- 1249166 極，此蕭特基二極體的第二電極的狀態是以自行對齊方式 連接到可變電阻性元件的一個端點。因此，此蕭特基二極 體及此可變電阻性元件可確保彼此對齊的形成而可以進一 步的改善整合程度。因為金屬薄膜26，電阻24及金屬薄膜 23係藉由利用此硬遮罩27做為遮罩地自行對齊方式彼此對 齊，可ft：電阻性元件的上方電極，電阻及下方電極的區域 可以在電流方向上精確的在相同位置。結果，電阻值可以 準確的控制且也可以進一步改善整合程度。另外，沈積在 周邊區域中的金屬薄膜23L，可變電阻性薄膜24L，金屬薄 膜26L及硬遮罩薄膜27L被以蝕刻移除。 圖19為顯不接線形成前表面被平坦化處狀態的概要圖。 例如，沈積由矽氧化物薄膜形成的絕緣薄膜28做為層間絕 緣薄膜並以CMP方法或類似的加以平坦化。 圖20為顯示接線形成處狀態的概要圖。開口（介層孔）形 成在如圖19所示形成的絕緣薄膜28中，對應到金屬薄膜 26(此硬遮罩27)做為可變電阻性元件的上方電極，m〇sfet 的源極電極22s與汲極電極22d。鎢插頭29係藉由沈積鎢在 此開口中而形成。接著，由例如，TiN薄膜30a，AlCii薄膜 、及ΤιΝ薄膜3〇c二層薄膜組成之金屬接線薄膜形成並樣 、寸應的預疋接線樣式來形成金屬接線30以便適當的連 接到此鎢插頭29。 ^1上述的，周邊區域中的元件及記憶體區域中的元件可 1的形成，並不會彼此影響。金屬接線3〇(bl)及複晶 品或2e(WL)分別在此記憶體區域中形成為位元線6乙及 92467.doc -36- 1249166 字線WL。接著，位在字線界1與位元線31彼此相交位置上 的記憶體單元被選定而可對之形成寫入，拭除及讀取動 作。另外，因為金屬接線30(WP)形成在周邊區域甲做為電 路接線，可以執行記憶體裝置所需要的信號處理。 如上述的，因為本發明的記憶體單元是由藉由利用其電 阻值隨施加電壓而變化之可變電阻性材料形成的可變電2 性元件以及蕭特基二極體的串聯電路組成，可以減少讀取It is a metal film 26L. Next, a hard mask film 27L formed of a TiN film is deposited on the entire surface of the metal film 26L, and is used as a mask for hard mask etching when the metal film 26L is etched, and the metal film 26L and the hard mask are The cover film 27L is formed by stacking. Fig. 18 is a schematic view showing a state in which a variable resistive element is formed. After the step shown in FIG. 17, the hard mask film 27L is processed by lithography and unequal etching to form a hard mask having a predetermined pattern (more specifically, the pattern of the electrodes above the variable resistive element). 27. Then, by using the hard mask 27 as a mask, the metal film 26L, the variable resistive film 24B and the metal film 23L are etched, and the metal film 26 (and the hard mask 27) is formed as a variable resistor. The element, the upper electrode of the resistor 24, and the metal thin film 23 serve as the lower electrode of the variable resistive element. Since the metal film 23 is also used as the second electric 92467.doc -35-1249166 pole of the Schottky diode, the state of the second electrode of the Schottky diode is connected to the variable by self-alignment. An end point of a resistive element. Therefore, the Schottky diode and the variable resistive element ensure the formation of alignment with each other, and the degree of integration can be further improved. Since the metal film 26, the resistor 24 and the metal film 23 are aligned with each other by using the hard mask 27 as a mask, the upper electrode of the resistive element, the area of the resistor and the lower electrode can be in the current. The direction is exactly at the same position. As a result, the resistance value can be accurately controlled and the degree of integration can be further improved. Further, the metal thin film 23L, the variable resistive film 24L, the metal thin film 26L, and the hard mask film 27L deposited in the peripheral region are removed by etching. Fig. 19 is a schematic view showing a state in which the front surface is flattened by the visible wiring. For example, an insulating film 28 formed of a tantalum oxide film is deposited as an interlayer insulating film and planarized by a CMP method or the like. Fig. 20 is a schematic view showing a state in which a wiring is formed. An opening (a via hole) is formed in the insulating film 28 formed as shown in FIG. 19, corresponding to the metal thin film 26 (this hard mask 27) as an upper electrode of the variable resistive element, and a source electrode of the m〇sfet 22s and the bungee electrode 22d. The tungsten plug 29 is formed by depositing tungsten in this opening. Next, a metal wiring film composed of, for example, a TiN film 30a, an AlCii film, and a Τι film 3〇c two-layer film is formed into a combined and pre-wired wiring pattern to form a metal wiring 30 for proper connection to the tungsten plug. 29. ^1 As described above, the elements in the peripheral area and the elements in the memory area can be formed without affecting each other. Metal wiring 3 〇 (bl) and polycrystalline or 2e (WL) are formed in this memory region as bit lines 6 and 92467.doc - 36 - 1249166 word lines WL, respectively. Next, a memory cell positioned at a position where the word line boundary 1 and the bit line 31 intersect each other is selected to form a write, erase and read operation. In addition, since the metal wiring 30 (WP) is formed in the peripheral area A as a wiring, signal processing required for the memory device can be performed. As described above, since the memory cell of the present invention is composed of a variable electric two-component element formed by a variable resistive material whose resistance value varies with an applied voltage, and a series circuit of a Schottky diode, Can reduce reading

干擾的影響。同樣的’纟包含這種本發明之記憶體單元的 記憶體裝置中可以減少讀取干擾的影響。 、，再者’根據—本發明，因為蕭特基二極體的第—電極是由 半導體基板的雜質區域或是選擇性形成在此絕緣薄膜上之 複晶石夕區域組成，記憶體單元的整合程度可獲得改善。另 外’因為可變電阻性薄膜係藉由自行對齊方式形成在蕭特 基二極體的第二電極上，可準確的控制可變電阻性元件的 電阻值而可以實現其中包含這種整合程度改善之記憶體單 元及類似的記憶體裝置。The impact of interference. The same effect can be reduced in the memory device including the memory unit of the present invention. Further, according to the present invention, since the first electrode of the Schottky diode is composed of an impurity region of the semiconductor substrate or a polycrystalline quartz region selectively formed on the insulating film, the memory cell unit The degree of integration can be improved. In addition, since the variable resistive film is formed on the second electrode of the Schottky diode by self-alignment, the resistance value of the variable resistive element can be accurately controlled, and the integration degree can be improved. Memory unit and similar memory device.

再者’根據本發明，因為蕾胜苴_ 局肅特基一極體是由在金屬矽介 物薄膜及矽間的蕭特基位能障 ^ f 此丨早、、且成的，可輕易地降低二極 體之順向臨限值並可得到穩定的二極體特性。 再者，根據本發明，因為藉 Μ ^ 1 啊取早熟處理，肅特基二極Furthermore, according to the present invention, because the singer 苴 苴 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃 肃The ground reduces the forward threshold of the diode and provides stable diode characteristics. Furthermore, according to the present invention, since the premature treatment is taken by Μ ^ 1 , the Sutji dipole

體形成及可變電阻性薄膜的姓S 胰的、、，口日日特性可同時獲得改善，埶 處理的數目可以減少。因此 …、 _對周邊電路影響較少的 3己fe體早兀生產方法而日R、息 周邊电路的整合程度獲得改善。 另外，因為可·變電阻性薄 寻膘疋由兩此分別的沈積處理形 92467.doc -37- 1249166 成，因此可做到可以進一步改善蕭特基二極體的特性（電阻 值）以及可變電阻性薄膜的結晶特性的記憶體單元生產方 法。 因為本發明可以幾種形式具體實例說明而不背離其基本 精神，因此本具體實例是說明性而非限制性的，因為本發 明的範疇由後附申請專利範圍定義而不是之前的說明，而 所有落在申請專利範圍之分野與界限或其此種分野與界限 相等内的改變，均為此申請專利範圍所企圖包含的。 【圖式簡單說明】 圖1為概要I員示所施加脈衝數目與傳統可變電阻性元件 電阻值間關連的圖表； 圖2為概要顯示所施加脈衝數目與傳統可變電阻性元件 電阻值間關連的圖表； 圖3為概要顯示所施加脈衝極性與傳統可變電阻性元件 電阻值間關連的圖表； 圖4為概要顯示所施加脈衝極性與傳統可變電阻性元件 電阻值間關連的圖表； 圖5A為顯示根據本發明之記憶體裝置概要組成的方塊 圖； ® 5B為顯示在讀取時施加於根據本發明之記憶體裝置的 電壓條件的圖； ® 6為解釋根據本發明記憶體單元生產方法之具體實例1 中的生產步驟的概要圖； 圖7為解釋.根據本發明記憶體單元生產方法之具體實例1 92467.doc 1249166 中的生產步驟的概要圖； 圖8為解釋根據本發明記憶體單元生產方法之具體實例】 中的生產步驟的概要圖； 圖9為解釋根據本發明記憶體單元生產方法之具體實例工 中的生產步驟的概要圖； 圖10為解釋根據本發明記憶體單元生產方法之具體實例 1中的生產步驟的概要圖； 圖11為解釋根據本發明記憶體單元生產方法之具體實例 1中的生產步驟的概要圖； 圖12為解釋根據本發明記憶體單元生產方法之具體實例 1中的生產步驟的概要圖； 圖13為解釋根據本發明記憶體單元生產方法之具體實例 2中的生產步驟的概要圖； 圖14為解釋根據本發明記憶體單元生產方法之具體實例 2中的生產步驟的概要圖； 、 圖15為解釋根據本發明記憶體單元生產方法之具體實例 2中的生產步驟的概要圖； 單元生產方法之具體實例 圖16為解釋根據本發明記憶體 2中的生產步驟的概要圖； 圖17為解釋根據本發明 ― 知d °己1餸早兀生產方法之具體實例 中的生產步驟的概要圖； 圖18為解釋根據本發 χ β 〇己^體早兀生產方法之具體實例 2中的生產步驟的概要圖； 圖19為解釋根據本發 ― 奴a。匕愿菔早兀生產方法之具體實例 92467.doc -39- 1249166 2中的生產步驟的概要圖，以及 圖20為解釋根據本發明記憶體單元生產方法之具體實例 2中的生產步驟的概要圖。 【圖式代表符號說明】 1 半導體基板 2 元件絕緣區域 3 閘道絕緣薄膜 4 閘極電極 5 LDD(輕度摻雜沒極）區域 6 -側壁 7 源極區域 8 汲極區域 9 始石夕化物薄膜 10 雜質區域 11 絕緣薄膜 12 _層間絕緣薄膜 12w 開口 14 金屬薄膜 15 電阻 15a 第一可變電阻性薄膜 15b 第二可變電阻性薄膜 16 金屬矽化物薄膜 17 金屬薄膜 92467.doc -40- 1249166 17a 17b 18 19 20 21 21 w 22d 22e 22s 23L 24a 24b 24L 25 26L 27 27L 28 29 30 30a 30bThe body formation and the variable resistive film have the surname S of the pancreas, and the day-to-day characteristics of the mouth can be simultaneously improved, and the number of 埶 treatments can be reduced. Therefore, ..., _ has little influence on the peripheral circuits, and the degree of integration of the R and the peripheral circuits is improved. In addition, since the variable resistance thin search is formed by two separate deposition processing shapes 92467.doc -37-1249166, it is possible to further improve the characteristics (resistance value) of the Schottky diode and A method of producing a memory cell of a crystalline property of a variable resistive film. The present invention is intended to be illustrative, and not restrictive, and the scope of the invention is defined by the scope of the appended claims rather Changes that fall within the boundaries of the scope of application for patents and boundaries or their divisions and boundaries are intended to be included in the scope of this patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a graph showing the relationship between the number of applied pulses and the resistance value of a conventional variable resistive element; FIG. 2 is a schematic view showing the number of applied pulses and the resistance value of a conventional variable resistive element. Figure 3 is a diagram showing the relationship between the applied pulse polarity and the resistance of the conventional variable resistive element; Figure 4 is a graph showing the relationship between the applied pulse polarity and the resistance of the conventional variable resistive element; Figure 5A is a block diagram showing an outline of a memory device according to the present invention; ® 5B is a diagram showing voltage conditions applied to a memory device according to the present invention at the time of reading; ® 6 is for explaining a memory cell according to the present invention A schematic diagram of a production step in a specific example 1 of a production method; FIG. 7 is a schematic view showing a production step in a specific example 1 92467.doc 1249166 of a method for producing a memory cell according to the present invention; FIG. 8 is an explanation according to the present invention. A schematic diagram of a production step in a specific example of a method of producing a memory cell; and FIG. 9 is a view explaining a method of producing a memory cell according to the present invention FIG. 10 is a schematic view for explaining a production step in Concrete Example 1 of a memory cell production method according to the present invention; FIG. 11 is a view for explaining a specific example of a memory cell production method according to the present invention; 1 is a schematic view of a production step in a specific example 1 of a memory cell production method according to the present invention; and FIG. 13 is a view showing a specific example 2 of a memory cell production method according to the present invention. FIG. 14 is a schematic diagram for explaining a production step in Concrete Example 2 of a memory cell production method according to the present invention; and FIG. 15 is a view explaining a specific example 2 of the memory cell production method according to the present invention. FIG. 16 is a schematic view for explaining a production step in the memory 2 according to the present invention; and FIG. 17 is a view for explaining a specific method of producing a method according to the present invention. A schematic diagram of a production step in the example; FIG. 18 is a specific example 2 explaining a production method according to the present invention Summary of production steps of FIG.; FIG. 19 is explained according to the invention - slaves a. A schematic diagram of a production step in a concrete example of the production method 92467.doc -39 - 1249166 2, and FIG. 20 is a schematic diagram explaining a production step in Concrete Example 2 of the memory cell production method according to the present invention. . [Description of Symbols] 1 Semiconductor Substrate 2 Insulation Area 3 Gate Insulation Film 4 Gate Electrode 5 LDD (Lightly Doped Nothing) Region 6 - Sidewall 7 Source Region 8 Deuterium Region 9 Primer Thin film 10 impurity region 11 insulating film 12 _ interlayer insulating film 12w opening 14 metal film 15 resistor 15a first variable resistive film 15b second variable resistive film 16 metal germanide film 17 metal film 92467.doc -40- 1249166 17a 17b 18 19 20 21 21 w 22d 22e 22s 23L 24a 24b 24L 25 26L 27 27L 28 29 30 30a 30b

Pt薄膜 TiN薄膜 絕緣薄膜 鎢接線 阻隔薄膜 絕緣薄膜 開口 沒極電極 複晶梦區域 -珠極電極 金屬薄膜 第一可變電阻性薄膜 第二可變電阻性薄膜 可變電阻性薄膜 金屬矽化物薄膜 金屬薄膜 硬遮罩 硬遮罩薄膜 絕緣薄膜 鎢插頭 金屬接線 TiN薄膜 AlCu 薄膜 30b 92467.doc -41 - 1249166 30c TiN薄膜 31 可變電阻性元件 32 蕭特基二極體 33 記憶體單元 34 位元線解碼器 35 字線解碼器 36 字線解碼器 37 讀取電路 92467.doc -42-Pt film TiN film insulating film tungsten wiring barrier film insulating film opening electrodeless electrode complex crystal dream area - bead electrode metal film first variable resistive film second variable resistive film variable resistance film metal germanide film metal Film hard mask hard mask film insulating film tungsten plug metal wiring TiN film AlCu film 30b 92467.doc -41 - 1249166 30c TiN film 31 variable resistive element 32 Schottky diode 33 memory unit 34 bit line Decoder 35 Word Line Decoder 36 Word Line Decoder 37 Read Circuit 92467.doc -42-

Claims (1)

1249的4〇9998號專利申請案 〜年7月V日修(更)正替換頁 中文申請專利範圍替換本(94年9月）-------—一_一 拾、申請專利範圍： 1 · 一種纪憶體單元，其包含一可變電阻性元件及一控制在 δ亥可變電阻性元件中流動之電流的電流控制元件，其特 徵為該電流控制元件為一蕭特基二極體（32)。 2·如申請專利範圍第丨項的記憶體單元，其中該蕭特基二極 體（32)的第一電極為一選擇性形成在該絕緣薄膜（21)中 的複晶矽區域（22e)，而該蕭特基二極體的第二電極為一 /尤積在该複晶矽區域（22e)上的金屬薄膜（23L)。 3·如申請專利範圍第2項的記憶體單元，其中該蕭特基二極 體（32)有一蕭特基位能障在該複晶矽區域（22e)及形成在 該複晶矽區域（22e)與該金屬薄膜（23L)間的一金屬矽化 物薄膜（25)之間。 4·如申請專利範圍第丨項的記憶體單元，其中該可變電阻性 疋件（31)係由有著鈣鈦_型態結晶結構的電阻性材料形 成。 5·如申請專利範圍第4項的記憶體單元，其中該蕭特基二極 體（32)的第一電極為一選擇性形成在該絕緣薄膜（21)中 的複晶矽區域（22e)，而該蕭特基二極體的第二電極為一 沈積在該複晶矽區域（22e)上的金屬薄膜（23L)。 6·如申請專利範圍第5項的記憶體單元，其中該蕭特基二極 體（32)有一蕭特基位能障在該複晶矽區域（22e)及一形成 在該複晶矽區域（22e)與該金屬薄膜（23L)間的金屬矽化 物薄膜（25)之間。 7·如申睛專利範圍第4項的記憶體單元，其中該蕭特基二極 , 神*2 / EJ 胃 ....... —II, I J 體（32)的第一電極為一形成在一第一傳導型態半導體基 板（1)上的第二傳導型態的雜質區域（10)，而該蕭特基二 極體的第二電極為沈積在該雜質區域（10)上的金屬薄膜 (14) 〇 8·如申睛專利範圍第7項的記憶體單元，其中 該半導體基板（1)為一矽基板，且 該蕭特基二極體（32)有一蕭特基位能障在該雜質區域 (10)和一形成在該雜質區域（1〇)與該金屬薄膜（1句間的金 屬矽化物薄膜（16)之間。 如申咕專利範圍第8項的記憶體單元其中該雜質區域（丨〇) 係選擇性的形成在言亥+ $體基板⑴中形成的元件絕緣區 域（2)中。 1〇·如申請專利範圍第9項的記憶體單元，其中組成該可變電 阻性元件（31)的可變電阻性薄膜（15L)藉由自行對齊方式 沈積在該蕭特基二極體（32)的該第二電極上。 11· 一種記憶體裝置，其中記憶體單元係位在配置成矩陣之 字線與位元線彼此相交的位置上，其特徵為 該圯憶體單元（33)是由包含可變電阻性元件（31)及控 制在違可變電阻性元件（3丨）中流動電流的蕭特基二極體 (3 2)之串聯電路組成，以及 孩串％電路之一端點連接到該字線（WL)，而該串聯電 路的另一端點則連接到該位元線（BL)。 12.如申睛專㈣圍第叫的記憶體裝置，其中該字線（购 疋由選擇性形成在一絕緣薄膜（21)上的複晶矽區域（22匀 92467-940923.doc -2 - 12辨构6/日修(更)正替換頁 組成。 13.如申請專利範圍第12項的記憶體裝置，其中該蕭特基二 極體（32)的該第一電極為該複晶矽區域（22e)，蕭特基二極 體的該第二電極為一沈積在該複晶矽區域（22e)上的金屬 薄膜（23L)。 14·如申請專利範圍第13項的記憶體裝置，其中該蕭特基二 極體（32)有一蕭特基位能障在該複晶矽區域（22e)與一形 成在該複晶矽區域（22e)與該金屬薄膜（23L)間的金屬矽 化物薄膜（25)之間。 15 ·如申請專利範圍第丨丨項的記憶體裝置，其中該可變電阻 性元件（3 1)是由有著鈣鈦_型態結晶結構之電阻性材料形 成。 16·如申凊專利範圍第〖5項的記憶體裝置，其中該字線（ 是由一選擇性的形成在一絕緣薄膜（21)中的複晶矽區域 (2 2 e)組成。 17·如申請專利範圍第16項的記憶體裝置，其中該蕭特基二 極體（32)的該第一電極為該複晶矽區域（22e)，而該蕭特基 一極體的該第二電極是一沈積在該複晶矽區域（22^)上的 金屬薄膜（23L)。 18·如申請專利範圍第17項的記憶體裝置，其中該蕭特基二 極體（32)有-蕭特基位能障在該複晶碎區域（22〇與一形 成在該複晶石夕區域（22e)與該金屬薄膜（23L)間的金屬石夕 化物薄膜（25)之間。 19.如申請專利範圍第15項的記憶體裝置，其中 92467-940923.doc 保辦/日修⑵正替換頁 該蕭特基二極體（32)之一第一電極連接到該字線 (WL)， 該蕭特基二極體（32)之一第二電極連接到該可變電阻 性元件（3 1)之一端點，以及 該可變電阻性元件（31)之該其他端點連接到該位元線 (BL) 〇 20·如申請專利範圍第19項的記憶體裝置，其中該字線（WL) 是由選擇性的形成在該半導體基板中（1)形成之元件絕緣 區域（2)中的雜質區域（1〇)組成。 21·如申請專利範圍第20項的記憶體裝置，其中該蕭特基二 極體（32)的該第一電極為該雜質區域（1〇)，而該蕭特基二 極體的第二電極為一沈積在該雜質區域（1〇)上的金屬薄 膜（14)。 22·如申請專利範圍第21項的記憶體裝置，其中 該半導體基板（1)為一矽基板，以及 該蕭特基二極體（32)有一蕭特基位能障在該雜質區域 (1〇)及_形成在該雜質區域⑽及該金屬薄膜（14)間的金 屬矽化物薄膜（16)之間。 23. 24· 如申請專利範圍第22項的記憶體震置，其中組成該可變 電阻性元件⑼之-可變電阻性薄膜（15L)藉由自行對齊 方式沈積在該蕭特基二極體（32)之該第二電極上。 一種在一半導體基板上形成由可變電阻性元件及蕭特基 二極體之串聯電路組成之記憶體單元的生產方法， 徵為包含步驟： 92467-940923.doc -4-Patent application No. 4,9998 of 1249~ July, V, repair (more), replacement page, Chinese patent application, replacement of this (94 September)------- A recording memory unit comprising a variable resistive element and a current control element for controlling a current flowing in the delta variable resistive element, characterized in that the current control element is a Schottky II Polar body (32). 2. The memory unit of claim 3, wherein the first electrode of the Schottky diode (32) is a polysilicon region (22e) selectively formed in the insulating film (21) And the second electrode of the Schottky diode is a metal film (23L) which is particularly concentrated on the polysilicon region (22e). 3. The memory unit of claim 2, wherein the Schottky diode (32) has a Schottky energy barrier in the polysilicon region (22e) and is formed in the polysilicon region ( 22e) between a metal halide film (25) and the metal thin film (23L). 4. The memory unit of claim 3, wherein the variable resistive element (31) is formed of a resistive material having a calcium-titanium-type crystal structure. 5. The memory unit of claim 4, wherein the first electrode of the Schottky diode (32) is a polysilicon region (22e) selectively formed in the insulating film (21) And the second electrode of the Schottky diode is a metal thin film (23L) deposited on the polysilicon region (22e). 6. The memory unit of claim 5, wherein the Schottky diode (32) has a Schottky energy barrier in the polysilicon region (22e) and a region formed in the polysilicon region (22e) between the metal halide film (25) and the metal thin film (23L). 7. The memory unit of claim 4, wherein the first electrode of the Schottky diode, the god*2/EJ stomach.......-II, the IJ body (32) is one Forming an impurity region (10) of a second conductivity type on a first conductive type semiconductor substrate (1), and a second electrode of the Schottky diode is deposited on the impurity region (10) Metal film (14) 〇8. The memory unit of claim 7, wherein the semiconductor substrate (1) is a germanium substrate, and the Schottky diode (32) has a Schottky potential energy a barrier is formed between the impurity region (10) and a portion of the impurity region (1) between the metal film and the metal halide film (16). The memory unit of claim 8 is claimed. Wherein the impurity region (丨〇) is selectively formed in the element insulating region (2) formed in the body substrate (1). 1) The memory cell according to claim 9 of the patent application, wherein the composition A variable resistive film (15L) of the variable resistive element (31) is deposited on the Schottky diode (32) by self-alignment The second electrode is 11. A memory device, wherein the memory cell is located at a position where the word line and the bit line arranged in a matrix intersect each other, characterized in that the memory unit (33) is included The variable resistive element (31) and the series circuit of the Schottky diode (32) that controls the current flowing in the variable resistive element (3丨), and the end of one of the children's circuits are connected to The word line (WL), and the other end of the series circuit is connected to the bit line (BL). 12. For example, the memory device of the first (four) circumference, the word line (purchased by the choice) Forming a polycrystalline germanium region on an insulating film (21) (22 uniform 92467-940923.doc -2 - 12 constitutive 6 / day repair (more) positive replacement page composition. 13. If the patent application scope 12 The memory device, wherein the first electrode of the Schottky diode (32) is the polysilicon region (22e), and the second electrode of the Schottky diode is deposited on the germanium a metal film (23L) on the region (22e). 14. A memory device according to claim 13 of the patent application, wherein the Schott The base diode (32) has a Schottky energy barrier in the polysilicon region (22e) and a metal halide film formed between the polysilicon region (22e) and the metal film (23L) (25) The memory device of claim </ RTI> wherein the variable resistive element (31) is formed of a resistive material having a calcium-titanium-type crystalline structure. The memory device of claim 5, wherein the word line is composed of a polycrystalline germanium region (2 2 e) selectively formed in an insulating film (21). 17. The memory device of claim 16, wherein the first electrode of the Schottky diode (32) is the polysilicon region (22e), and the Schottky diode The second electrode is a metal thin film (23L) deposited on the polysilicon region (22^). 18. The memory device of claim 17, wherein the Schottky diode (32) has a Schottky energy barrier in the polycrystalline region (22 〇 and one formed in the polycrystalline stone) Between the evening region (22e) and the metal ruthenium film (25) between the metal thin film (23L). 19. The memory device of claim 15 wherein 92467-940923.doc is maintained/daily repaired (2) a replacement page, the first electrode of one of the Schottky diodes (32) is connected to the word line (WL), and the second electrode of one of the Schottky diodes (32) is connected to the variable resistance An end of one of the elements (31), and the other end of the variable resistive element (31) is connected to the bit line (BL) 〇20. The memory device of claim 19, wherein The word line (WL) is composed of an impurity region (1) selectively formed in the element insulating region (2) formed in the semiconductor substrate (1). 21 A memory device as in claim 20 Wherein the first electrode of the Schottky diode (32) is the impurity region (1〇), and the Schottky diode is The electrode is a metal film (14) deposited on the impurity region (1). The memory device of claim 21, wherein the semiconductor substrate (1) is a germanium substrate, and the Schott The base diode (32) has a Schottky barrier between the impurity region (1) and the metal halide film (16) formed between the impurity region (10) and the metal film (14). 24. The memory of the object of claim 22, wherein the variable resistive film (15L) constituting the variable resistive element (9) is deposited on the Schottky diode by self-alignment ( 32) The second electrode is a method for producing a memory cell formed by a series circuit of a variable resistive element and a Schottky diode on a semiconductor substrate, and the method comprises the following steps: 92467-940923. Doc -4- /曰修(更)正替換頁 形成絕緣薄膜（12)，形成在該半導體基板（1)之一表面 上之雜質區域（10)在該絕緣薄膜（12)上的開口（I2w)暴露 出來； 沈積一組成該可變電阻性元件（3 1)之一電極的金屬薄 膜（14)在該絕緣薄膜（12)的該開口（12w)中； 沈積組成該可變電元件（3 1)之一電阻（15)的可變電阻 性薄膜（15L)在該金屬薄膜（14)上；以及 形成一蕭特基二極體（32)，藉由以熱處理形成一金屬矽 化物薄膜（16)在該雜質區域（10)及該金屬薄膜（14)間。 25·如申請專利範圍第24項的生產方法，其中該可變電阻性 薄膜（15L)係藉由自行對齊方式沈積在該開口（12w)中的 該金屬薄膜（14)上。 26如申凊專利範圍第25項的生產方法，其中該熱處理的溫 度為可以改善該可變電阻性薄膜（15l)結晶特性的溫度。 27·如申請專利範圍第26項的生產方法，其中 該半導體基板（1)為一矽基板，而該蕭特基二極體（32) 有一蕭特基位能障在該金屬矽化物薄膜（丨6)及該雜質區 域（10)之間。 28·如申請專利範圍第27項的生產方法，其中該金屬薄膜 (23L)係由耐熔化金屬材料形成的。 29.如申睛專利範圍第28項的生產方法，其中該耐熔化金屬 材料係從Pt，Ti，Co及Ni中的至少一個選出。 30· —種在一半導體基板上形成由可變電阻性元件及蕭特基 92467-940923.doc 修(更)正替換頁 二極體之串聯電路組成之記憶體單元的生產方法，其特 徵為包含步驟： 形成絕緣薄膜（12)，形成在該半導體基板（1)之一表面 上之雜質區域（10)在該絕緣薄膜（12)上的開口（I2w)暴露 出來； 沈積一組成該可變電阻性元件（31)之一電極的金屬薄 膜（14)在該絕緣薄膜（12)的該開口（12w)中； 沈積有第一薄膜厚度並組成該可變電阻性元件（3 1)之 電阻（15)的可變電阻性薄膜（15a)在該金屬薄膜（14)上； 形成一蕭特基二極體（32)，藉由以熱處理形成一金屬矽 化物薄膜（16)在該雜質區域（1〇)及該金屬薄膜（14)間，以及 沈積一具有第二薄膜厚度的之可變電阻性薄膜（15b) 並組成該電阻（15)在具有該第一薄膜厚度之該可變電阻 性薄膜（15a)上。 3 1 ·如申請專利範圍第30項的生產方法，其中該熱處理的溫 度為可以改善具有該第一薄膜厚度之該可變電阻性薄膜 (15 a)結晶特性的溫度。 32·如申請專利範圍第31項的生產方法，其中 該半導體基板（1)為一石夕基板，以及 該蕭特基二極體（32)有一蕭特基位能障在該金屬矽化 物薄膜（16)及該雜質區域（1〇)之間。 33·如申請專利範圍第32項的生產方法，其中還包含在有該 第二薄膜厚度之該可變電阻性薄膜（I5b)的沈積之後進一 步執行熱處理的步驟， 92467-940923.doc -6- 12 辦^/曰修(更)正替換頁 其中該熱處理的溫度為可以改善有該第二薄膜厚产之 該可變電阻性薄，之結晶特性並可以降低該金二夕 化物薄膜（16)電阻值的溫度。 34.如申請專利範圍第33項的生產方法，其中該金屬薄膜 (23L)是由财炼化金屬材料形成。 35·如中請專利範圍第34項的生產方法’其中該耐熔化金屬 材料是從Pt，Ti，Co及Ni中的至少一個選出。 36· —種在一半導體基板上形成由可變電阻性元件及蕭特基 二極體之串聯電路組成之記憶體單元的生產方法，其特 徵為包含下列步驟： 選擇性形成複晶矽區域（22e)在一形成在該半導體基板 (1)之一表面上的絕緣薄膜（21)中； 沈積一組成該可變電阻性元件（3 i)之一電極的一金屬 薄膜（23L)在该複晶碎區域（22e)上； 沈積一組成該可變電阻性元件（3 1)之一電阻（24)的一 可變電阻性薄膜（24L)在該金屬薄膜（23L)上；以及 藉由以熱處理形成一金屬矽化物薄膜（25)在該複晶矽 區域（22e)及該金屬薄膜（23L)間而形成一蕭特基二極體 (32)。 37.如申請專利範圍第36項的生產方法，其中該熱處理的溫 度為可以改善該可變電阻性薄膜（24L)之結晶特性之溫 度。 38·如申請專利範圍第37項的生產方法，其中該蕭特基二極 體（32)有一蕭特基位能障在該金屬矽化物薄膜（25)與該 92467-940923.doc -7- 1|4辦的日敝χΐ ϋιΐ 複晶矽區域（22e)之間。 3 9 ·如申請專利範圍第3 &amp;項的生產方法，其中該金屬薄膜 (23L)是由耐熔化金屬材料形成的。 4 0 ·如申清專利範圍第3 9項的生產方法，其中該耐溶化金屬 材料是從Pt，Ti，Co及Ni中的至少一個選出。 41· 一種在一半導體基板上形成由可變電阻性元件及蕭特基 二極體之串聯電路組成之記憶體單元的生產方法，其特 徵為包含步驟： 選擇性的形成複晶;ε夕區域（22e)在一形成在該半導體基 板（1)之一表面上的絕緣薄膜（21)中； 沈積一組成該可變電阻性元件（3丨）之一電極的一金屬 薄膜（23L)在該複晶矽區域（22e)上； 沈積一具有第一薄膜厚度並組成該可變電阻性元件 (31) 之一電阻（24)的一可變電阻性薄膜（24a)在該金屬薄 膜（23L)上； 藉由以熱處理形成一金屬矽化物薄膜（25)在該複晶矽 區域（22e)A 亥金屬薄膜（23L)間而形成一蕭特基二極體 (32) ;以及 沈積具有第二薄膜厚度並組成該電阻（24)的可變電 阻1±溥膜(24b)在具有該第一薄膜厚度之該可變電阻性薄 膜（24a)上。 42.如申請專利範圍第41項的生產方法，其中該熱處理的溫 度為可以改善具有第_薄膜厚度之該可變電阻性薄膜 (24a)結晶特性的溫度。 92467-940923.doc 12 12/ 修修 (more) replacing the page to form an insulating film (12), the opening (I2w) of the impurity region (10) formed on one surface of the semiconductor substrate (1) on the insulating film (12) is exposed; Depositing a metal film (14) constituting one of the electrodes of the variable resistive element (31) in the opening (12w) of the insulating film (12); depositing one of the variable electrical elements (31) a variable resistive film (15L) of the resistor (15) on the metal film (14); and a Schottky diode (32) formed by heat treatment to form a metal halide film (16) Between the impurity region (10) and the metal thin film (14). The production method of claim 24, wherein the variable resistive film (15L) is deposited on the metal film (14) in the opening (12w) by self-alignment. The production method of claim 25, wherein the temperature of the heat treatment is a temperature at which the crystallization characteristic of the variable resistive film (15l) can be improved. The production method of claim 26, wherein the semiconductor substrate (1) is a germanium substrate, and the Schottky diode (32) has a Schottky barrier in the metal halide film (丨6) and between the impurity regions (10). 28. The production method of claim 27, wherein the metal film (23L) is formed of a molten metal resistant material. 29. The production method according to claim 28, wherein the molten metal resistant material is selected from at least one of Pt, Ti, Co and Ni. 30. A method for producing a memory cell comprising a variable resistive element and a series circuit in which a page diode is replaced by a Schottky 92467-940923.doc on a semiconductor substrate, characterized in that The method comprises the steps of: forming an insulating film (12), exposing an opening (I2w) of the impurity region (10) formed on one surface of the semiconductor substrate (1) on the insulating film (12); depositing a composition of the variable a metal film (14) of one of the electrodes of the resistive element (31) is in the opening (12w) of the insulating film (12); a first film thickness is deposited and constitutes a resistor of the variable resistive element (31) a variable resistive film (15a) of (15) on the metal thin film (14); a Schottky diode (32) formed by heat treatment to form a metal halide film (16) in the impurity region Between the metal film (14) and a variable resistive film (15b) having a second film thickness and constituting the resistor (15) in the variable resistor having the first film thickness On the film (15a). The production method according to claim 30, wherein the temperature of the heat treatment is a temperature at which the crystal characteristic of the variable resistive film (15a) having the thickness of the first film can be improved. 32. The production method of claim 31, wherein the semiconductor substrate (1) is a slab substrate, and the Schottky diode (32) has a Schottky barrier in the metal ruthenium film ( 16) and between the impurity regions (1〇). 33. The production method of claim 32, further comprising the step of further performing heat treatment after deposition of the variable resistive film (I5b) having the second film thickness, 92467-940923.doc -6- 12 ^ / / repair (more) positive replacement page wherein the temperature of the heat treatment is to improve the variability of the second film, the variability of the crystallization characteristics, and can reduce the gold bismuth film (16) The temperature of the resistance value. 34. The production method according to claim 33, wherein the metal thin film (23L) is formed of a chemically-refined metal material. 35. The production method of claim 34, wherein the molten metal resistant material is selected from at least one of Pt, Ti, Co and Ni. 36. A method for producing a memory cell comprising a series circuit of a variable resistive element and a Schottky diode on a semiconductor substrate, comprising the steps of: selectively forming a polysilicon region ( 22e) in an insulating film (21) formed on a surface of one of the semiconductor substrates (1); depositing a metal film (23L) constituting one of the electrodes of the variable resistive element (3 i) in the On the crystal crushing region (22e); depositing a variable resistive film (24L) constituting one of the resistors (24) of the variable resistive element (31) on the metal thin film (23L); The heat treatment forms a metal halide film (25) between the polysilicon region (22e) and the metal film (23L) to form a Schottky diode (32). The production method according to claim 36, wherein the temperature of the heat treatment is a temperature at which the crystal characteristics of the variable resistive film (24L) can be improved. 38. The production method of claim 37, wherein the Schottky diode (32) has a Schottky barrier in the metal halide film (25) and the 92467-940923.doc -7- 1|4 The day of the 敝χΐ ΐ ΐ ΐ ΐ ΐ ΐ area (22e) between. 39. The production method of claim 3, wherein the metal film (23L) is formed of a metal material resistant to melting. The production method of claim 39, wherein the melt-resistant metal material is selected from at least one of Pt, Ti, Co and Ni. 41. A method of producing a memory cell comprising a series circuit of a variable resistive element and a Schottky diode on a semiconductor substrate, comprising the steps of: selectively forming a polycrystal; (22e) in an insulating film (21) formed on a surface of one of the semiconductor substrates (1); depositing a metal film (23L) constituting one of the electrodes of the variable resistive element (3) On the polysilicon region (22e); depositing a variable resistive film (24a) having a first film thickness and constituting a resistor (24) of the variable resistive element (31) in the metal film (23L) Forming a Schottky diode (32) between the polysilicon region (22e) and the metal film (23L) by heat treatment to form a metal halide film (25); and depositing has a second A variable resistance 1±溥 film (24b) having a film thickness and constituting the resistor (24) is on the variable resistive film (24a) having the thickness of the first film. The production method according to claim 41, wherein the temperature of the heat treatment is a temperature at which the crystal characteristic of the variable resistive film (24a) having the thickness of the film is improved. 92467-940923.doc 12 12 •V曰修(更)正替換頁 43.如中請專利範圍第42項的生產方法，其中該蕭特基二極 體（32)有一蕭特基位能障在該金屬矽化物薄膜（25)及該 複晶矽區域（22e)之間。 44.如申請專利範圍第43項的生產方法，其中還包含在具有 該第二薄膜厚度之該可變電阻性薄膜（24b)的沈積之後進 一步執行熱處理的步驟， 其中該熱處理的溫度為可以改善具有該第二薄膜厚度 之該可變電阻性薄膜（24b)結晶特性並可以降低該金屬矽 化物薄膜（25)電阻值的溫度。 45·如申研專利範圍第44項的生產方法，其中該金屬薄膜 (23L)係由一耐熔化金屬材料形成的。 46.如申請專利範圍第45項的生產方法，其中該耐熔化金屬 材料是從Pt，Ti，Co及Ni中的至少一個選出。 92467-940923.doc 9-• V曰修 (more) is being replaced by the production method of claim 42, wherein the Schottky diode (32) has a Schottky barrier in the metal halide film (25). And between the polysilicon regions (22e). 44. The production method of claim 43, further comprising the step of further performing heat treatment after deposition of the variable resistive film (24b) having the second film thickness, wherein the temperature of the heat treatment is improved The varistor film (24b) having the second film thickness has a crystal characteristic and can lower the temperature of the metal halide film (25). 45. The production method of claim 44, wherein the metal film (23L) is formed of a molten metal resistant material. The production method of claim 45, wherein the molten metal resistant material is selected from at least one of Pt, Ti, Co and Ni. 92467-940923.doc 9-
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