1248¾^ doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種且古乂 造方法，且丨σ古關Μ ^有/于置閘極記憶胞元件的製 仏方法X特別疋有關於可整合至邏輯電 = 卞極記憶胞陣列之元件的製造方法。 【先月!j技術】 唯項。己fe體巾包括許乡的記丨 — 憶儲存功能的-半導體元件。 2種具有兄 幕式唯讀記憶體、可程式體唯 讀記憶體或是可電除且可程*彳了抹除且可私式唯 係為-種可電除且可程式化 化的陣列結構，可達到高元件密度及低的疋土於^早 的陣列結構意指快閃記憶體寫人的速的度目 =然= /、抹除的方式以逐區方式為基礎，在各種不ς =快閃記憶體部署的情況下，這些缺點尚不能夠： 快閃記憶體記憶胞與其它可電除且可程式 憶體的記憶胞為了儲存電荷，在控㈣ :署 閉極。其中，這些浮置閘極的材質例如是多晶屬予置 使用。基於氮化賴密組成的特性，熱電 ，電晶體穿遂陷入氮化石夕層’形成一不均勾的電荷濃度分 佈，可增加貧料讀取速度及避免電流洩漏。 又 12482^^^ 以氮化矽為基礎的快閃記憶體，其每一個記憶泸勹 括在半導體基底中形成-源極與—汲極。此外，在 基底表面上源極汲極之間依序形成—絲切層、一氮化 石夕層及-頂氧化石夕層，因此可以形成—浮置閉極以儲存電 荷。另外，在氧化石夕_氮化石夕_氧化石夕結構上形成 存取的控制閘極。 貝料 快閃記憶體的狀態是依照浮置閘極的電荷濃度來決 定的，而㈣記憶體的操作是依照浮置閘極中電荷的注^ 及移除的技術來決定的。因此，#程式化資料寫入時，— 高電壓施加於控卿極上’以使麵來的熱電子穿 氧化石夕層姐人洋置祕巾的氮切層，可增加啟始電壓 以讀取資料。當抹除資料時，熱電洞注入浮置閘極中的 化石夕層並達到和電子相同的位置以和這些電子相互 由此可抹除此物件。 在早期的可電除且可程式化唯讀記憶體元件，包括 早期的快閃記憶體’其每一個記憶胞僅能儲存一位元的資 料。很，地，發展出二位元的的記憶胞，其中一個記憶胞 可以儲存二位兀的資料’儲存的位置在通道的兩末端。豆 用來程式化其中一個位元，汲極的擴散用 來私式化3個位7〇。二位元的記憶胞在設計上所使用的 2電荷陷入層的材料例如是氮化石夕。但是這個方法並不 是完吳的，不論II切的介電特性如何，電荷容易從同一 氮=層的-電荷儲存區顧漏至另一電荷儲存區域而產 生 另夕因為電子和電洞在氮化石夕層中不同的擴散 fdoc/006 特性，使得電洞注入進行抹除時並非完全覆蓋於氮化石夕層 中的電拷區域’而造成抹除不完全的現象。 為了解決這些問題’許多快閃記憶體結構在氮化石夕 層的橫向兩電荷儲存區域之間具有一隔離區域。在一此元 件中，隔離區域係在橫向上兩電荷儲存區域之間值入 的-些離子所形成，以增加此區域中氮切層的絕缘恭 容。在其它元件中，隔離區域係由對氧化石夕-氮、 矽結構中央區域進行一蝕刻製程所形成。 近來，發展出許多具有分_電荷儲 記憶體元件的製造方法，但仍存在一些缺點。例如:= 習知的製造方法所形成的電荷陷入層為彎曲的形狀，^ :直rtm同的厚度。對電子或電洞注入區3 吕，此一結構可以減少弱的或是不受控制的電場。 其它習知技術可以製造出具有正 電荷陷入區域，但是在將製程 的平坦 域的製造流財，並無法有效敕人。2，凡件邏輯區 憶體的製造方法整合至邏輯元二製了快閃記 _乳化石夕氧切結構令的 厚在减石夕 閘氧化石夕層的厚度之間度與邏輯電晶體的 另-個例子錢，當：―取麵厚度關係。又舉 石夕-氮化^氧切結構化層表面進行清洗且氧化 時的頂氧化矽層:受到破T化矽層又暴露出來 進行-勤]餘，對氧切·氮切氧化石夕層 位兀的隔離區域，但是此—方 oc/006 i248UL· ΐ層程後餘留下來氧切-氮切-氧化 步驟在 幕步驟用來定義相對 r將會在氧㈣氮一氧二產 列之要憶胞陣 【發明内容】 以解决上述習知技術的問題。 本發明之保護範圍當視後附之申請 者為準，以下僅概略描述本發明本發明乾 明並f影響本發明之申請專利範圍所保護的範圍下述5兄 憶體元件製造方法中^ 極記 先提供—基底，且在基底上形成—氧化 材料層。接著，移除邏輯電路區中的氧切_氮切 石夕材料層’並形成—氧切取代之。射，此 為閉氧化層使用。然後，在 上1 么:=，其材質例如是多晶石夕。此外’在記憶胞區中， 在埋入式擴散區上形成埋入式擴散氧化元件，再於晶圓上 形成一附加材料層，較佳的是多晶矽層。其中，此一 材料層沉積並形成多㈣隙壁元件，且這些間隙壁元^ I248m ^f.doc/006 倚靠著埋入式擴散氧化元 化石夕材料層妨綱以 ^ ’賴切·氮化石夕-氧 離溝渠。其中，完成對氧=^^立"元之間形形成—隔 刻’並穿魏切_氮切切材料層的韻 裡層的製程，係以倚靠 ；斗曰上方的多晶矽襯 多晶石夕間隙壁作為自我^ f擴散氧化元件之側壁上的 間隙壁同樣可在蝕刻製程中伴t，二另外，此多晶矽 且在絕緣體上形成_=體在隔離溝渠中形成—絕緣體， 邏輯二 對邏輯電路區中的問氧化層上表面進行清洗時，並不卜會= 壞乳化石夕4化石夕-氧化石夕結構中易受破壞的頂氧化層，原 因在於進行清洗時，係於頂氧化層上覆蓋另一材料層。再 者，此一製程將使用高解析度光罩的步驟降到最少。 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 下文中所描述的内容，可使習知此技術領域者製造 及使用本發明，並詳述其特殊應用及操作上所需的必要條 件。任何熟習此技藝者，可輕易對本發明所揭露的實施例 1248213 12235twf-d〇c/〇〇6 不脫離本發明之精神和範圍内，當可作些許 實施例，其範_本文中_ 於本文中所提及的 -致。 所揭路之原則及特徵最廣的範圍 面圖圖首先圖身不本發明—較佳實施例的製造流程剖 立它音+ 的基底11〇。在本發明 存結構=沒有的表面上或是表面下形成電荷儲 上或2表面=限疋此電何儲存結構一定要在基底的表面 所提出ί型態。’且電何儲存結構的型態也不限於本實施例 件。如ίι二ί81二气底材上形成邏輯元件及記憶體元 上，吃情师―左邊的區域為邏輯電路區118。基本 浮置開邏輯差別在於，在記憶胞區具有 體。如圖！所，路區具有習知的場效電晶 η型井區120、曰不的基底U〇包括在邏輯電路區⑽中有 130，另°一方面Ρ，井區124、Ρ井摻雜區126及場氧化層 摻雜區m。雖妙H憶=%114中有η型井區122、Ρ井 離的區域，作d輯電路區與記憶胞區為兩分 區分佈在多數g=r’單—晶圓中會有記憶胞 在輯電路區中，且反之亦然。 以健存電荷的材料層。典型的電以 1248¾¾ twf.doc/006 材料層所組成，即—底氧、 一頂氧化層136。心p &电仃储存層134及 材質例如是氧切與頂氧化層136的 例如是介電材料二屬==二陷广材料: 之三層結構。其並不-定為 電荷儲存位置分散且=二=的，，例如是 的材料層。其中，此材地區或是全部 案化製程。然而，視其操作條件的需要進行圖 請夫昭圖1 士ΐ 例並不用以限定本發明。 112為三γ材料圭實施例中’電荷儲存結構 136的材質例“石^:底氧化層132與頂氧化層 是氮化石夕。因此荷儲存層134的材質例如 石夕-氧化石夕結構。而電構⑴係為一氧化石夕氮化 化矽結構的技術為習知此;氧化矽·氮化矽·氧 在一些習知的製=者所熟知，在此不再費述。 氧化矽·氮切_氧切^構’巾^輯電路餘整合之後， 習知場效電晶體的開氧化化層與邏輯電路區中 特別是，在許多製裎中，二間曰有一互相依存的關係。 積-材料層所形成，c係為在晶圓上各區域沉 丁頁氧化層與邏輯電路區中氮化石夕-氧化石夕結構中的 白σπ效電晶體的閘氧化層會具 12 12仰1 twf.doc/006 有相同的厚度。為了避免這個問題 =r:r層(未叫並移除 ί:ϊ: :圖2 ’對氧化，氮化，氧化石夕複合 製程’以移除邏輯電路區118上的氧化 切複合材料層，_的方式例如是進行一 小於50埃時停止此=程： f路出來的矽基底110上形成一閘氧化層21 $ =埃門形成的方法例如是進行-熱製程。採用本: 2法，閘氧化層21〇的厚度可以獨立出來 胞區m内電荷儲存結構112的頂氧化層的相同。就、 ^後，@ 2崎示，移除記憶胞區ιΐ4上的光阻 曰，、、’在兀件表面上形成一多晶矽層212。在豆它 可用石夕化鍺(SiGe)取代多晶石夕。其巾’多晶石夕層」 /儿積的厚度例如是50埃〜1000埃，形成的 二3、 石夕甲院(SiH4)為反應氣體源進行_爐 ^對= =r侧製程時，多一在邏 幕層使用。另-方面，在進行一姓刻製程以形成隔 =區域時，以及對邏輯電路區118内閘氧化層的^ 製程中’多晶石夕層犯可用以保護電荷儲存結構m 軋化層136易受破壞的上表面。 τ Μ ⑽接下來，請參照圖3，沉積_犧牲材料層31〇，其材 貝例如是氮化石夕，厚度例如是_埃〜3_埃之間^形 13 1248213 12235twf.doc/006 ^ί ^(SiH2Cl2)/|, ^(Ν2)^ 元絲面上形成-光阻層（未 式擴散區域延伸於Λ 出埋人式擴散區域。此埋入 個以上的記憶胞下方，形成一條導體 四個步驟的程接^先在此埋入式擴散區域進行-個 為反應氣體源對氮化秒燒(CH4)與漠化氫(HBr) 步驟，以演化氫/氧電^夕材曰^310進賴刻。第二個 頂氧化層m作為_//;日= 層212進行㈣，並以 料層134上转頂氧化層 對二 在埋入式擴散區上成：m 開_進行層作為罩幕，穿過 豆中，離+始&子植1以形成埋入式擴散線414。 管回火2㈣植入製程’例如是進行爐 料41=盧吕乳化製程及快速熱氧化製程。埋入式擴 :伸區蛣己憶胞區114中，定義出記憶胞電晶體的樺‘ 此’在每—個記憶财，m式擴散緩 極，而另-個埋人式擴散線414作為沒極。= 丄，:底11。橫向延伸於兩埋入式擴散線4〗4之間 糸、、且成電晶體的通道區，且電荷儲存結構n2橫向延伸^ 14 rf.doc/006 一對埋入式擴散線414之間的部份係包含一浮置閘極。 如上所述，一特殊材料層在一特殊製程步驟中作為 罩幕層使用，在此特殊製程進行的過程巾出現上面的材料 層’不論是上層材料層或是中間的材料層，都會被圖案化 而具有和特殊材料層相同的圖案。換句話說’如果此二結 構包括兩相同圖案的材料層，其中—材料層或是兩相同圖 案的材料層’皆可在一特殊製程中作為罩幕層使用。在此 特殊製程巾出現之放在特殊材料層下面的材料層，都呈 有和特殊材料層相__，在特殊製程步驟中，無法阻 ☆，特殊巧料，，作為罩幕層使用。其中，材料層在其它材料 二上方或疋下方意指在各種不同的實施例中，此材料 :之間係藉由-層或是多層中間層所分隔。如果沒有中間 曰％之為直接上方”或是”直接下方”。同樣的證釋方式， 以解釋這裡所提及的把其它材料層放在上面、把其它 材料層放在下φ或是放在其储料層上方。 的太？L來：請參照圖5 ’形成另-氧化層51°’其形成12483⁄4^ doc/006 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method for manufacturing an ancient structure, and a method for preparing a memory cell element In particular, there are manufacturing methods for components that can be integrated into a logic electrical = 记忆 记忆 memory cell array. [First month! j technology] Only item. The body towel includes the record of Xuxiang - the memory component - the semiconductor component. 2 types of read-only memory with cousin type, programmable read-only memory or can be erased and can be erased and can be privately typed as an electrically erasable and programmable array. Structure, can achieve high component density and low bauxite in the early array structure means that the flash memory writes the speed of the person's speed = / =, the way of erasing is based on the region-by-region method, in all kinds of = In the case of flash memory deployment, these shortcomings are not yet possible: Flash memory cells and other memory cells that can be electrically removed and can be programmed to store charge are controlled (4): closed. Among them, the material of these floating gates is, for example, polycrystalline. Based on the characteristics of the composition of the Nitriding, the thermoelectric and the transistor are trapped in the nitride layer to form a non-uniform charge concentration distribution, which can increase the reading speed of the lean material and avoid current leakage. Also 12482^^^ is a flash memory based on tantalum nitride, each of which is formed in a semiconductor substrate to form a source and a drain. In addition, a wire cut layer, a nitride layer and a top oxide layer are sequentially formed between the source and the drain on the surface of the substrate, so that a floating closed pole can be formed to store the charge. In addition, an access control gate is formed on the oxidized stone _-nitridite eve_oxidized oxide structure. The state of the flash memory is determined according to the charge concentration of the floating gate, and (4) the operation of the memory is determined according to the technique of charging and removing the charge in the floating gate. Therefore, when the #stylized data is written, the high voltage is applied to the control layer to make the hot electrons from the surface pass through the nitrogen cut layer of the oxidized stone layer, which can increase the starting voltage to read. data. When the data is erased, the thermal holes are injected into the fossil layer in the floating gate and reach the same position as the electrons to interact with the electrons to thereby erase the object. In the early erasable and programmable read-only memory components, including the early flash memory, each memory cell could store only one bit of data. Very, the two-dimensional memory cells are developed, and one of the memory cells can store the data of the two ticks. The storage location is at both ends of the channel. Beans are used to program one of the bits, and the diffusion of the bungee is used to privately digitize 3 bits. The material of the two-character memory cell used in the design of the charge trapping layer is, for example, nitride nitride. However, this method is not complete. Regardless of the dielectric properties of the II cut, the charge is easily leaked from the same nitrogen=layer-charge storage area to another charge storage area. Another reason is because electrons and holes are in the nitride. Different diffusion fdoc/006 characteristics in the layer make the hole injection not completely cover the electro-copying area in the layer of the nitride layer, resulting in incomplete erasure. To address these issues, many flash memory structures have an isolated region between the lateral charge storage regions of the nitride layer. In one such element, the isolation region is formed by a number of ions that are added between the two charge storage regions in the lateral direction to increase the insulation of the nitrogen cut layer in this region. In other components, the isolation region is formed by an etching process on the central region of the oxidized oxide-nitrogen and ytterbium structures. Recently, many manufacturing methods have been developed which have fractional-charge memory elements, but there are still some disadvantages. For example: = The charge trapping layer formed by the conventional manufacturing method has a curved shape, and the thickness of the straight rtm is the same. For an electron or hole injection zone, this structure can reduce weak or uncontrolled electric fields. Other conventional techniques can produce a positive charge trapping region, but the manufacturing of the flat domain of the process is not effective. 2, the manufacturing method of the logic area of the piece of logic is integrated into the logic element two system of flash flash _ emulsified stone oxime structure is thicker in the thickness of the oxidized stone layer of the stone sluice gate and the logic transistor - An example of money, when: - take the thickness relationship. In addition, the surface of the shixi-nitride-oxygen-cut structure layer is cleaned and the top yttrium oxide layer is oxidized: the ruthenium-deposited layer is exposed and exposed to the surface, and the oxygen-cutting-nitrogen-cut oxide layer Located in the isolated region, but this - square oc / 006 i248UL · ΐ layer after leaving the oxygen cut - nitrogen cut - oxidation step in the curtain step to define the relative r will be in the oxygen (tetra) nitrogen - oxygen production Cellular [Explanation] To solve the above problems of the prior art. The scope of the present invention is defined by the appended claims. The following is a brief description of the invention and the scope of the invention as claimed in the appended claims. The substrate is first provided and a layer of oxidized material is formed on the substrate. Next, the oxygen cut-nitrogen material layer in the logic circuit region is removed and formed by oxygen-cutting. Shot, this is used for the closed oxide layer. Then, on the top: =, its material is for example polycrystalline stone. Further, in the memory cell region, a buried diffusion oxide element is formed on the buried diffusion region, and an additional material layer is formed on the wafer, preferably a polysilicon layer. Wherein, the material layer is deposited and formed into a plurality of (four) gap elements, and the spacers ^ I248m ^f.doc/006 rely on the buried diffusion oxidized fossil material layer to singularly Xi-Oxygen ditches. Among them, the process of forming the rhyme layer of the formation of the oxygen-^^立立-quote between the elements and the "cutting of the material" is carried out by relying on the polycrystalline lining of the polycrystalline lining above the bucket. The spacers on the sidewalls of the self-diffusion oxidization element can also be accompanied by t in the etching process. In addition, the polysilicon is formed on the insulator and the insulator is formed in the isolation trench. The logic two pairs of logic circuits When cleaning the upper surface of the oxide layer in the zone, it is not necessary to = the top oxide layer in the emulsified stone eve 4 fossil-oxidized stone structure, because it is attached to the top oxide layer during cleaning. Cover another layer of material. Furthermore, this process minimizes the use of high resolution masks. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] The present invention will be made by those skilled in the art, and the necessary conditions for its particular application and operation will be described in detail. The embodiment 1248213 12235 twf-d〇c/〇〇6 disclosed in the present invention may be easily practiced by those skilled in the art without departing from the spirit and scope of the invention, and may be embodied in some embodiments. As mentioned in the -. The broadest scope of the principles and features of the disclosed roads is first illustrated in the present invention. The manufacturing process of the preferred embodiment cuts the base 11 of the sound +. In the storage structure of the present invention = no surface or under the surface to form a charge storage or 2 surface = limit this electrical storage structure must be presented on the surface of the substrate. The type of the electrical storage structure is not limited to this embodiment. For example, on the ίι二ί81 second gas substrate to form logic elements and memory elements, the lover-left area is the logic circuit area 118. The basic floating logic difference is that there is a body in the memory cell. As shown! The road area has a conventional field effect electric crystal n-type well region 120, and the substrate U〇 includes 130 in the logic circuit region (10), and on the other hand, the well region 124 and the well doping region 126 And field oxide doped region m. Although M H = %114 has n-type well area 122, the area away from the well, the circuit area and the memory cell area are distributed in two partitions. In most g=r' single-wafer, there will be memory cells in In the circuit area, and vice versa. A layer of material that holds a charge. Typical electricity consists of a layer of material 12483⁄43⁄4 twf.doc/006, namely, bottom oxygen, a top oxide layer 136. The core p & erbium storage layer 134 and the material are, for example, oxygen-cut and top oxide layers 136, for example, a three-layer structure of a dielectric material. It is not defined as a layer of material in which the charge storage location is dispersed and = two =, for example. Among them, this material area or all the cases of the process. However, it is not intended to limit the invention, as required by the operating conditions. 112 is a three-gamma material. In the example of the charge storage structure 136, the bottom oxide layer 132 and the top oxide layer are nitrided. Therefore, the material of the storage layer 134 is, for example, a stone-oxidized stone structure. The technique of the structure (1) which is a structure of a nitric oxide yttrium nitride is conventionally known; yttrium oxide, tantalum nitride, and oxygen are well known in some conventional processes, and will not be described here. After the integration of the nitrogen-cutting-oxygen-cutting structure, the open-oxidation layer and the logic circuit area of the conventional field-effect transistor, in particular, in many systems, the two have an interdependent relationship. Formed by the product-material layer, c is the gate oxide layer of the white σπ effect transistor in the smectite oxide layer and the logic circuit region in each region on the wafer. The elevation of 1 twf.doc/006 has the same thickness. To avoid this problem =r:r layer (not called and removed ί:ϊ: :Fig. 2 'Oxidation, nitridation, oxidized oxide compound process' to remove The oxidized-cut composite layer on the logic circuit region 118, for example, is such that when a less than 50 angstroms is performed, the process is stopped: f Forming a gate oxide layer on the germanium substrate 110. The method of forming the gate oxide is, for example, performing a heat process. By using the method of 2: the thickness of the gate oxide layer 21〇 can be independently derived from the charge storage structure 112 in the cell region m. The top oxide layer is the same. After ^, @2, the photoresist layer on the memory cell layer ι4 is removed, and 'a polycrystalline germanium layer 212 is formed on the surface of the element.锗(SiGe) replaces polycrystalline shi shi. Its towel 'polycrystalline shi shi layer' / thickness of the product is, for example, 50 angstroms to 1000 angstroms, the formation of the second 3, Shi Xijiayuan (SiH4) for the reaction gas source _ When the furnace is in the ==r side process, one more is used in the logic layer. On the other hand, when a process is performed to form the isolation region, and in the process of the gate oxide layer in the logic circuit region 118, The polycrystalline layer can be used to protect the top surface of the charge storage structure m which is susceptible to damage. τ Μ (10) Next, referring to FIG. 3, a layer of sacrificial material 31 is deposited, such as a nitride. In the evening, the thickness is, for example, _ angstroms ~ 3 angstroms ^ shape 13 1248213 12235 twf.doc / 006 ^ ί ^ (SiH2Cl2) / |, ^ (Ν 2) ^ yuan silk A photoresist layer is formed on the surface (the non-diffusion region extends over the buried human diffusion region. This is buried under more than one memory cell, forming a conductor in four steps, first in this buried diffusion region Conducting a reaction gas source for the nitriding second (CH4) and desert hydrogen (HBr) steps to evolve hydrogen/oxygen electricity 曰 ^ 310 into the etch. The second top oxide layer m as _ / /; Day = layer 212 is carried out (4), and the top layer oxide layer is turned on the material layer 134 to form a layer on the buried diffusion region: m open _ layer is used as a mask, passing through the beans, leaving the + start & The implant 1 is formed to form a buried diffusion line 414. Tube tempering 2 (four) implantation process 'for example, the furnace 41 = Lulu emulsification process and rapid thermal oxidation process. Buried expansion: in the area of the cell area 114, the definition of the memory cell of the birch 'this' in every memory, m-type diffusion slow, and another buried diffusion line 414 as Nothing. = 丄,: bottom 11. The lateral extension extends between the two buried diffusion lines 4 and 4, and forms a channel region of the transistor, and the charge storage structure n2 extends laterally between 14 af rf.doc/006 and a pair of buried diffusion lines 414. Some parts contain a floating gate. As described above, a special material layer is used as a mask layer in a special process step, in which the process layer of the special process is formed with the material layer 'whether the upper material layer or the middle material layer is patterned. It has the same pattern as the special material layer. In other words, if the two structures comprise two layers of the same pattern of material, the material layer or the two material layers of the same pattern can be used as a mask layer in a special process. In this special process towel, the material layer placed under the special material layer is formed with a special material layer __, which can not be blocked in special process steps, and is used as a mask layer. Wherein the layer of material above or below the other material means that in various embodiments, the material is separated by a layer or a plurality of intermediate layers. If there is no intermediate 曰% is directly above “or “directly below”. The same way of proof, to explain the layer of other materials mentioned above, put the other material layer under the φ or put it Above the storage layer. To? L: Please refer to Figure 5 to form another oxide layer 51°.
‘式和讀行—高密度電聚化學汽相沉積法 如在1000埃〜30〇〇祕+ ,日 #丄 J 〇埃之間。其中，氧化層510係形成在 缺$，、二会上，填滿開口 412並覆蓋埋入式擴散線414。 光六，除了邏輯電路區118外，在結構上形 510 後進行材料層310作為#刻終止層。隨 孔體進仃—乾式_製程，此-主製程具有終止 15 f.doc/006 ^主，以人氟化奴仰8)、氮氣及—氧化碳(CQ)進行一且 控制的過蝕刻製程。繼之，移除晶片上之光阻層？ 邊化浸潤製程’使氮化石夕犧牲材料層310 暴路出來。騎餘留在埋人式擴散線414 成氧化層610,且氧化層61_於 後績自對準的製程步驟中。在此可以看到，氧化声 =ί，)且高於電荷儲存結構…嫩 除二釋7氟犧== 進行一剝除製程。此時，閘氧^21〇 及夕曰曰石夕層212餘留在元件的邏輯電路區中，另 晶矽層212餘留在記憶胞區114中 ^ 積-層视®多晶料(未標*)，其厚 ^ ϊ程其=:=:r貌為反應氣趙源進行-爐管 存結構;L;層、 « "曰的y子度。此外，概相 形成於記憶胞區氧化層610的上表面上， =層 化層610的側壁形成多晶矽間_81〇。在:， 圖8中的襯裡多晶⑪層其材質並不—定要和圖2 ^ : 石夕層212相同。在本實施例中，襯裡多晶销與多日 212係為同一材質’多晶矽間隙壁81〇在垂直 ^ 度大於電荷儲存結構112上方用以保護電荷儲存結構= 16 的襯裡多晶矽層，所以在進行蝕刻製程時，在穿透多晶 間隙壁81G之前會先穿透電荷料結構112上的概裡^曰曰 石夕層。這裡所提及的，，垂直，，指的是垂直於基底的表面^ 何特膜層的，，垂直，，方向可能會也可能不會一致，原因在於 膜層的表面呈現傾斜或是不平坦，侧為在朗上所進行 =各種製程步驟及各種非重共平面特性所導致。這裡， 橫向”大體上是和基底面平行的方向。 因此在進㈣8中的製程步驟後，此晶圓包括一 土 & 110，此基底110包括一記憶 =18。其中’在記憶胞區114中，晶圓二 ;:ΠΓ此電，存結構112具有-氧切-氮切-氧 =結構，以及在電荷儲存結構112上具有用以保= 儲存結構112的襯裡多晶石夕声 ’二 了 Α^μ ^ 層212另外，埋入式擴散氧 士直延伸穿i電荷 ;;儲 ⑽，更進-步在電荷儲===於2式擴散氧化層 氧化層61G的侧壁形成—， 上A著的埋入式擴散 在邏輯電路請中多：：石夕間隙壁81〇。另-方面， 上，並保護閘氧化層21〇，日f閘氧化層210 上方。 且邊閘乳化層210位於基底ι10 然後，請參照圖9,险τ曰π 在晶圓上形成-光阻層（未了二圓上的記憶胞區114之外， 1禾、、、日不）。接著，對記憶胞區114 1248益?一。6 f仃-非等向性侧製程，在每—記憶胞中形成一自我對 ::隔離溝渠910。此一製程步驟係用以隔離氧化矽-氮 了-氧切結構中的雜可以控制tj#，料㈣ 疋電洞陷入於氧化石夕-氮化石夕.氧化石夕結構中。 卜 =刻製程例如是以溴化氫(HBr)/氧電漿進行一蝕 =多晶梦層212，並以頂氧化層136輕刻終H缺 以四祕奴為反應氣體源進行—_製程並穿過頂氧 化層136，並以電荷儲存層134 終止層。接下來， =臭化氫、六氟化硫及三氟化碳為反應氣體料行一姓刻 ^程並㈣㈣财層m，並以絲化層出為 止層。在其它實施例中，若有需要的話更可以進行敍刻製 私以穿過底氧化層132。在圖9的製程步驟中，使用多曰 石夕間隙壁81G作為罩幕，以進行自我對準的㈣製程，因曰 此可保護易受破壞的頂氧化層136。如同所看到的，在進 行圖9中的製程步驟後，在每一個記憶胞中形成兩個狹窄 的電荷儲存區域912 ’且位於兩相鄰的氧化層61〇之相對 的側壁上，並藉由隔離溝渠91〇進行電性隔離。 再則，請參照圖10〜圖12，係繪示填滿隔離溝準 的三步驟製程。首先，請參照圖1〇，移除晶圓上的光阻 層並在基底110上形成一氧化層1010，其係由絕緣材料 所形成的，其厚度例如是500埃〜2000埃。較佳的是，此 氧化層1010例如是以四乙基鄰矽酸鹽為反應氣體源所形 成的氧化層。其中此氧化層1010填滿隔離溝渠91〇，並 18 1248¾^ f.doc/006 形成於晶圓橫向表面上。請參昭圖 輯電路區m與記憶胞區^ ==二分別對邏 刻製程。更詳盡的說，首先=層1010進行回飯 路區118之外，在晶圓上形成」光二1 二除了邏輯電 層所暴露出來的氧化層_ 4:;;，；被光阻 :=讓止層，因此可二 層並^二：二，=L12 ’首先，移除光阻 甲的虱化層1〇1〇， 1010 =進仃，直到晶片上隔離溝渠91G中的氧化層咖 度約和電荷1存結構112的上表面一樣高為止。 - m ί其貫施例中’此—姓刻製程會停止於隔離溝渠 0 .的氧化層1010仍具有較高之高度的時候，或是在 ，行㈣製程之後，氧化層_的高度會低於電荷儲存 ^構112的上表面。不論如何，形成在隔離溝渠91〇中的 氧化層1010’至少要南於電荷儲存結構II2巾電荷儲存 材=的上表面’以轉電荷儲存材料與閘極導體層（將於 後，製程步驟形成）間的電性絕緣。請參照圖10，在圖⑺ 的Ι&例中’電荷儲存材料例如是三明治結構中，夾在頂氧 化層136與底氧化層132間的電荷儲存層134，而在圖12 中，在隔離溝渠910中的氧化層1〇1〇經蝕刻後的高度， 至少要高於電荷儲存層134的上表面。然而，較佳的是， 此一钱刻製程停在隔離溝渠91〇中氧化層1〇1〇的上表面 和電荷儲存結構112的上表面在同一平面的時候，可提供 19 I248m.d_ 形成)在通道區的延伸區中有一共 控制閘極(於後續製程中 同的底面。 中的氡:屏在！t成拴制閘極多晶矽之前，先對隔離溝渠910 氟酽ϋ 一、、10上表面進行一清洗製程，例如是利用氫 在：、、先：二。其中’多晶矽層212可以保護閘氧化層210 在π洗過轾中不會受到破壞。 / f所不，進行一氧化浸潤製程後留下一結構， 構：每一記憶胞由橫向相鄰的兩埋入_ 414 =線)所界定，且此結構在橫向兩埋入式擴散線414 —電荷儲存結構112。此外，被氧化材料填滿的 网/木910 ’係用以隔離電荷儲存結構η〕巾兩相對的 電荷儲存區域121〇及1212,且電荷儲存區域·及1212 係配置於相對的多晶石夕間隙壁810下方。雖然多晶石夕間隙 壁810是導體，但是藉由電荷儲存結構112中的頂氧化層 136與電荷儲存區域1210及1212進行隔離。在邏輯電ς 區118中，閘氧化層210係配置於多晶矽層212下方。 在另一較佳實施例中，間隙壁是絕緣體而非導體， 則在此實施例中的間隙壁會被移除。較佳的是，間隙壁是 導體，且其材質為多晶石夕，如此一來，就能夠不必再多一 道步驟以移除間隙壁。 接著，請參照圖13,在晶圓上沉積另一多晶石夕層 1310，再於多晶矽層1310上形成一矽化金屬層，係為石夕 化鶴層1312。其中，多晶石夕層1310填滿多晶石夕間隙壁 間的缺口，因此在每一個記憶胞的通道區上形成一均均的 20 12482益 5twf.doc/006 導，材料。而且，多晶矽層Πιο與矽化鎢層1312的複合 層高度高於基底110上的氧化層61〇，因此，此複合層可 被圖案化而形成記憶胞陣列的控制閘極。缺後，進行一微 ^刻製程關案化多晶㈣咖與魏鎢層1312的複 :層’並形成邏輯電路區118中場效電晶體的控制間極(未 才示不），以及記憶胞區114中的控制閘極1314。 於’ 11 1〜圖13的實_製造出二位S記憶 和電洞在/的厚度’且因此更容易控制電子 單一步的1 在製程的容忍範圍内。舉例來說，經由 =⑽t成—材料層’其中在整個表面上沉積-相對平 定會有，，大體上-致的致的厚度”’但是不一 材料層上形成此在一凸起或是升高的底 是起因於在製程早/ b°)其中，此平坦的電荷儲存結構 底)上形成，再進中，於一平坦的下層材料層(基 形成隔離的電荷錯存結^籌。性钱刻，而非在之後的步驟才 矽_虱化矽_氧化矽纟 丁正口更砰进的吮，例如氧化 閘氧化層的厚声八頂氧化層的厚度與邏輯電晶體中 在對邏輯電路：中二：行控制。舉例另-個例子來說， 破壞氧切德切化層上表面進行清洗時，並不會 化石夕結構中易受破壞的頂氧化層， 21 ^482^ c/006 =在，行清洗時，係於頂氧化層上覆蓋另一材料層。 4外’在料切％切_氧切結構崎— 形成二位元隔離區域時，务 衣私以 受3壞 方覆蓋多晶石夕間隙壁，所以不會 此外在圖1〜圖η的實施例中，需要兩道 是在圖4中定義出埋人式擴散線，t 从回巾圖案絲成3個多晶⑪控制間極。至於 ，儲存結構中的隔離溝渠係利用自我對準祕刻 成，毋須在此步驟中多加一道高解析度的光罩步驟。 圖14係緣式圖13中元件之記憶胞區ιΐ4經 後部份區域的上視圖。％ _ 14 。” 的陣列，1中备一圖所不，5己憶胞形成-規則 ^ 彡、里入式擴散線414(位元線)在γ方向 L伸並穿過至>、-個記憶胞，並橫穿過下方至少—個 二:極1314。上述所謂記憶胞陣列，簡單的說就是多ς 二：:的、^型的陣列具有一規則的結構，如圖 中所、、、日不，但疋此一規則的結構並不是必要的。 声J本it ’ *提絲描述材料 件時’這些文字係用以提供結構上的區別，以及 t後續提及這些元件時能夠明確的指出此-元件。其中， k些文字並不意指具有時_序的關係。 、雖然本發明已以較佳實施例揭露如上，然其並非用 =艮定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾。例如;= 22 1248213 12235twf.doc/006 特殊步驟時，作為說明的特定化學物 此技藝者將能夠以許多替代的化跟谁習知 -特殊步驟。另外，〔城、_來進行此 所福㈣〜〜丨卜有任何的_’可藉由參考本發明 所&出的貝_ ’在這個技術 月 述、聯想或是合併的絲^ + 料利應用進行描 ==的原則及實際的應用，因此熟知此-技: :=丄 發明所提出的各實施例加以修飾丄 後附用的功能。因此本發明之保護範圍當： 後附之申μ專利關所界定者為準。 【圖式簡單說明】 面圖圖圖13係綠不本發明一較佳實施例的製造流程剖 r-^係，不圖13之結構中相關元件的上視圖。 【主要兀件符號說明】 no :基底 112 114 116 118 120 124 126 130 132 電荷儲存結構 記憶胞區 分隔線 邏輯電路區 122 : η型井區 Ρ型井區 128 : Ρ井摻雜區 場氧化層 底介電層 23 1248¾^ f.doc/006 134 :電荷儲存層 136 :頂介電層 210 :閘氧化層 212、1310 :多晶矽層 310 :犧牲材料層 412 :開口 414 :埋入式擴散線 510、610、1010 :氧化層 810 :多晶矽間隙壁 910 :隔離溝渠 912 :電荷儲存區域 1210、1212 :電荷儲存區域 1312 :矽化鎢層 1314 :控制閘極 24‘Formation and reading line—high-density electropolymerization chemical vapor deposition method, such as between 1000 angstroms ~ 30 〇〇 secret +, day #丄 J 〇. The oxide layer 510 is formed on the missing space, at the second meeting, filling the opening 412 and covering the buried diffusion line 414. Light six, except for the logic circuit region 118, is formed 510 after the structure, and the material layer 310 is used as the #刻 termination layer. With the hole body into the dry-dry process, this - the main process has a 15 f.doc / 006 ^ main, human fluorinated 8), nitrogen and carbon oxide (CQ) and controlled over-etching process . Then, remove the photoresist layer on the wafer? The edge infiltration process "bursts out the nitride rock sacrificial material layer 310. The ride remains in the buried diffusion line 414 to form the oxide layer 610, and the oxide layer 61_ is in the post-alignment process step. It can be seen here that the oxidized sound = ί,) and higher than the charge storage structure... tender except for the second release 7 fluoride sacrifice == a stripping process. At this time, the thyristor ^ 21 〇 and the 曰曰 曰曰 夕 layer 212 remain in the logic circuit region of the device, and the other wafer layer 212 remains in the memory cell region 114 - the layer-view layer ® polycrystalline material (not Standard *), its thickness ^ ϊ程 its =:=: r appearance for the reaction gas Zhao source - furnace tube storage structure; L; layer, « " 曰 y sub-degree. Further, a general phase is formed on the upper surface of the memory cell oxide layer 610, and the sidewall of the stratified layer 610 forms a polycrystalline inter-turn _81 〇. In:, the lining polycrystalline 11 layer in Figure 8 is not made of the same material as Figure 2^: Shixi layer 212. In this embodiment, the lining polycrystalline pin and the multi-day 212 are the same material 'polysilicon spacers 81', and the vertical polysilicon layer is larger than the charge storage structure 112 to protect the lining polysilicon layer of the charge storage structure = 16, so During the etching process, the interlayer of the charge material structure 112 is penetrated before penetrating the polycrystalline spacer 81G. As used herein, vertical, refers to the surface perpendicular to the surface of the substrate, vertical, direction may or may not be consistent, because the surface of the film is tilted or uneven The side is caused by the various steps of the process and various non-heavy coplanar features. Here, the lateral direction is substantially a direction parallel to the base surface. Therefore, after the process step in the (four) 8, the wafer includes a soil & 110, and the substrate 110 includes a memory = 18. wherein 'in the memory cell region 114 Medium, wafer 2;: 电, the memory structure 112 has an oxygen-cut-azine-oxygen structure, and a lining polycrystalline stone on the charge storage structure 112 to protect the storage structure 112 In addition, the Α^μ^ layer 212 is additionally, the buried diffusion oxygen extends straight through the i-charge; the storage (10), the further step is formed in the charge storage === on the sidewall of the 2-type diffusion oxide layer oxide layer 61G, The buried diffusion on the upper A is more in the logic circuit:: the stone eve spacer 81 〇. On the other side, the upper and the protection gate oxide layer 21 〇, the upper dam gate oxide layer 210. 210 is located on the substrate ι10. Then, referring to FIG. 9, the τ 曰 π forms a photoresist layer on the wafer (not the memory cell region 114 on the two circles, 1 禾, 、, 日日). Then, The memory cell 114 1248 benefits a .6 f仃-non-isotropic side process, forming a self-pair in each memory cell:: isolation trench 910. A process step is used to isolate the yttrium oxide-nitrogen-oxygen-cut structure to control tj#, and the material (4) 疋 hole is trapped in the oxidized stone --nitridite eve. oxidized stone 夕 structure. The hydrogen peroxide (HBr)/oxygen plasma is used to perform an eclipse=polycrystalline dream layer 212, and the top oxide layer 136 is used to smear the final H deficiency and the fourth secret slave is used as the reaction gas source—the process and the top oxidation Layer 136, and terminates the layer with a charge storage layer 134. Next, = stinky hydrogen, sulfur hexafluoride, and carbon trifluoride are the reaction gas materials, and the (4) (four) financial layer m, and the silk layer In other embodiments, if necessary, the engraving can be performed to pass through the bottom oxide layer 132. In the process step of FIG. 9, the multi-stone spacer 81G is used as a mask to The self-aligned (four) process is performed, as this protects the susceptible top oxide layer 136. As can be seen, after performing the process steps of Figure 9, two narrow charges are formed in each memory cell. The storage region 912' is located on the opposite side wall of the two adjacent oxide layers 61, and is separated by the trench 91〇Electrical isolation. Further, please refer to FIG. 10 to FIG. 12, which is a three-step process for filling the isolation trench. First, please refer to FIG. 1 to remove the photoresist layer on the wafer and An oxide layer 1010 is formed on the substrate 110, and is formed of an insulating material, and has a thickness of, for example, 500 Å to 2000 Å. Preferably, the oxide layer 1010 is made of, for example, tetraethyl phthalate. The oxide layer formed by the source, wherein the oxide layer 1010 fills the isolation trench 91〇, and 18 12483⁄4^ f.doc/006 is formed on the lateral surface of the wafer. Please refer to the circuit area m and the memory cell area ^ = = two separate logic processing. More specifically, first, the layer 1010 is returned to the wafer area 118 to form an oxide layer exposed on the wafer except for the logic layer _ 4:;;; Stop layer, so it can be two layers and ^ two: two, = L12 ' First, remove the photoresist layer 1〇1〇, 1010 = enter the 仃, until the oxide layer in the isolation trench 91G on the wafer It is as high as the upper surface of the charge storage structure 112. - m ί In the case of the example, the process of the last name will stop at the isolation trench 0. When the oxide layer 1010 still has a higher height, or after the row (four) process, the height of the oxide layer _ will be low. On the upper surface of the charge storage structure 112. In any case, the oxide layer 1010' formed in the isolation trench 91 is at least south of the upper surface of the charge storage structure II2 to charge the charge storage material and the gate conductor layer (will be formed later, the process steps are formed) Electrical insulation between). Referring to FIG. 10, in the example of FIG. (7), 'the charge storage material is, for example, a sandwich structure, the charge storage layer 134 sandwiched between the top oxide layer 136 and the bottom oxide layer 132, and in FIG. 12, in the isolation trench. The etched layer of 910 has a height after etching which is at least higher than the upper surface of the charge storage layer 134. However, it is preferable that the etching process is performed when the upper surface of the oxide layer 1〇1〇 in the isolation trench 91 is in the same plane as the upper surface of the charge storage structure 112, and 19 I248m.d_ is formed. There is a total control gate in the extension of the channel region (the same bottom surface in the subsequent process. The 氡 in the screen: before the screen becomes a 多 gate polysilicon ,, first on the isolation trench 910 酽ϋ1, 10 The surface is subjected to a cleaning process, for example, using hydrogen in:, first: two. The 'polycrystalline germanium layer 212 can protect the gate oxide layer 210 from being damaged in the π-washed crucible. / f, not performing an oxidation infiltration process Thereafter, a structure is constructed, each memory cell is defined by two laterally adjacent buried _ 414 = lines, and the structure is in the lateral two buried diffusion lines 414 - the charge storage structure 112. In addition, the mesh/wood 910' filled with the oxidized material is used to isolate the charge storage structures η from the opposite charge storage regions 121 and 1212, and the charge storage region and the 1212 are disposed on the opposite polycrystalline slabs. Below the spacer 810. Although the polycrystalline silicon spacer 810 is a conductor, it is isolated from the charge storage regions 1210 and 1212 by a top oxide layer 136 in the charge storage structure 112. In the logic region 118, the gate oxide layer 210 is disposed under the polysilicon layer 212. In another preferred embodiment, the spacers are insulators rather than conductors, and the spacers in this embodiment are removed. Preferably, the spacer is a conductor and the material is polycrystalline, so that no further steps are required to remove the spacer. Next, referring to FIG. 13, another polycrystalline layer 1310 is deposited on the wafer, and a deuterated metal layer is formed on the polycrystalline germanium layer 1310, which is a rock layer 1312. Among them, the polycrystalline lithi layer 1310 fills the gap between the polycrystalline litter spacers, so an average of 20 12482 benefits is formed on the channel region of each memory cell. Moreover, the composite layer height of the polysilicon layer Πιο and the tungsten germanium layer 1312 is higher than that of the oxide layer 61 基底 on the substrate 110. Therefore, the composite layer can be patterned to form a control gate of the memory cell array. After the defect, a micro-etching process is performed to close the polycrystalline (four) coffee and the Wei tungsten layer 1312 of the complex layer: and form the control electrode of the field effect transistor in the logic circuit region 118 (not shown), and the memory Control gate 1314 in cell region 114. The real _ 11 1 to Fig. 13 produces a two-position S memory and a hole thickness in / and thus it is easier to control the electrons in a single step 1 within the tolerance of the process. For example, via =(10)t into a material layer 'where the deposition on the entire surface - relatively flat there will be, substantially the resulting thickness" 'but not one layer of material formed on this bump or liter The high bottom is caused by the early / b°) process, which is formed on the bottom of the flat charge storage structure, and then into the flat underlying material layer (the base forms an isolated charge stack). Money is engraved, not in the later steps. 虱 矽 矽 矽纟 矽纟 矽纟 矽纟 正 正 正 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮 吮Circuit: Medium 2: Line control. For another example, when destroying the upper surface of the oxygen chelate layer for cleaning, it will not degrade the top oxide layer in the stone structure, 21 ^ 482 ^ c / 006 = When cleaning, the top oxide layer is covered with another material layer. 4 Outside 'cutting % cut_oxygen cut structure-- when forming a two-dimensional isolation area, the clothes are privately affected by 3 bad squares. Covering the polycrystalline litter gap, so it will not be furthermore in the embodiment of Figures 1 to η, two In Fig. 4, a buried diffusion line is defined, and t is a three-crystal 11 control interpole from the back towel pattern. As a result, the isolation trench in the storage structure is self-aligned and is not required to be used in this step. Add a high-resolution mask step in the middle. Figure 14 is a top view of the area of the memory cell ιΐ4 of the component in Figure 13. The array of % _ 14 ”, 1 is not a picture. 5 Recalling cell formation - rule ^ 里, immersive diffusion line 414 (bit line) extends in the γ direction L and passes through to >, a memory cell, and traverses at least two below: pole 1314 The above-mentioned so-called memory cell array is simply a multi-two::, ^-type array has a regular structure, as shown in the figure, , and day, but the structure of this rule is not necessary. J Ben it '*When the wire is described as a piece of material' these texts are used to provide structural differences, and t can be clearly pointed out when referring to these elements. Among them, k text does not mean that there is time _ The relationship of the order is the same as the preferred embodiment of the present invention, but it is not It is to be understood that the present invention may be modified and modified without departing from the spirit and scope of the invention. For example; = 22 1248213 12235 twf.doc/006 Specific procedures, specific chemistry as an illustration This artist will be able to use many alternatives to know who--special steps. In addition, [City, _ to carry out this blessing (four) ~ ~ 丨 有 any _' can be referred to by the present invention & The shell _ 'in this technology monthly, Lenovo or the combined wire ^ + material application to describe the principle and practical application of the description ==, so it is well known that this technology - :: 丄 the invention proposed by the various modifications The function of the invention is as follows. Therefore, the scope of protection of the present invention is as defined in the attached patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 13 is a top view of a manufacturing process of a preferred embodiment of the present invention, not a top view of the related elements in the structure of FIG. [Main component symbol description] no : substrate 112 114 116 118 120 124 126 130 132 charge storage structure memory cell division line logic circuit region 122 : n-type well region Ρ type well region 128 : Ρ well doped region field oxide layer Bottom dielectric layer 23 12483⁄4^ f.doc/006 134: charge storage layer 136: top dielectric layer 210: gate oxide layer 212, 1310: polysilicon layer 310: sacrificial material layer 412: opening 414: buried diffusion line 510 610, 1010: oxide layer 810: polysilicon spacer 910: isolation trench 912: charge storage region 1210, 1212: charge storage region 1312: tungsten germanium layer 1314: control gate 24