1248178 九、發明說明： 【發明所屬之技術領域】 本發明係有關於電子封裝技術，其特別有關於晶片尺寸 級封裝構造。 【先前技術】 隨著更輕更複雜電子裝置需求的日趨強烈，晶片的速度 及複雜性相對越來越高，因此需要更高之封裝效率 (packaging efficiency)。微型化(miniaturization)是使用先進 封裝技術（例如晶片尺寸級封裝(chip scale package)以及覆 晶(flip chip))的主要驅動力。相較於球格陣列封裝或薄小 輪廓封裝(thin small outline package，TSOP)而言，晶片尺寸 級封裝以及覆晶這兩種技術均大幅增加封裝效率，藉此減 少所需之基板空間。一般而言，晶片尺寸級封裝之大小與 晶片本身大小相當或稍大於晶片本身（最多約百分之二 十）。此外’晶片尺寸級封裝可直接促成良好晶片（kn〇wn good die，KGD)測試及老化(bum-in)測試。再者，晶片尺寸 級封裝亦可結合表面黏著技術(surface mount SMT)之標準化及可在加工性等優點，與覆晶技術之低阻 抗，咼I/O接腳數及直接散熱路徑等優點，而提升晶片尺 寸級封裝之效能。 然而，與球格陣列(ball grid array)封裝或薄小輪廓封裝 (thin small outline package，TSOP)相比較，晶片尺寸級封裝 具有較高製造成本之缺點。若能將晶片尺寸級封裝以大量 1248178 生產方式製造，前述高製造成本之缺點將可被克服。因此， 封裝業者嘗試開發晶圓層次(wafer level)封裝技術，以能大 量生產晶片尺寸半導體封裝構造。習知晶圓層次封裝技術 的製造步驟，大體上皆需要將一基板直接貼合至一晶圓 (wafer)上’其中該半導體晶圓係尚未切割成個別晶片。該 基板係與整片晶圓之尺寸大致相同，並且包含複數個單元 對應於晶圓上的複數個晶片。 由於該晶圓與基板熱膨脹係數差異相當大（晶圓之熱膨 服係數（coefficient of thermal expansion，CTE)約為 3_5ppm/°C，基板之熱膨脹係數(CTE)約為2〇-3〇ppm/cc )， 因此晶圓與基板會隨溫度變化而產生不同的膨脹或收縮 置。這會該晶圓與基板之介面產生切變(shear)應力或彎曲 (bend)應力。而由於基板係與整片晶圓之尺寸大致相同，因 此該破壞性應力會累積而更擴大其所導致的可靠性問題。 口此有必要哥求一種在晶圓層次(wafer level)製造複數個 晶片尺寸級封裝構造的方法，其可解決前述先前技術的問 題。 【發明内容】 因此，本發明之主要目的係提供一種在晶圓層次製造的 晶片尺寸級封裝構造，其可解決前述先前技術的問題。 、本發明之另一目的係提供—種在晶圓層次㈣沉^㈣ 製造複數個晶片尺寸級封裝構造的方法。 根據本發明之晶μ尺侦封裝構造，其主要包含彼此接 1248178 合在-起的上賴下層铸體晶4，複 電引線分別形成在該上層與下層半導體晶片之 ==;ΓΓ分別將該些上層導電引線電性』 該二下層W·。該下層半導體晶片 於其些下層導電引線之上。每-前述 有一第一编部以及一第二端部，該第一卡 7 兮此s Η妒航今 ^弟鳊邛係電性連接於 =二4:塾之…且該第二端部係延伸至該正面之 緣。母-中間導電引線係連接相對應之上層與下 線之第二端部。 9 當該上層與下層半物⑸倾此接合在-起使得1 背面係彼此面料，每—巾㈣電引線至少有部分形& 該上層與下層半導體晶片之側面。 當該上層與下層半導體晶片係彼此接合在-起使得該 上層半導體晶狀背面正觸下層半導體晶Μ之正面時， 每-中間導電引線至少有部分形成在該上層半導體晶片之 側面。 在本發明之晶片尺寸級封裝構造，由於該上層與下層半 導體晶片係直接接合在一起且該些上層與下層導電引線係 分別利用複數個形成在晶片侧面的中間導電引線彼此電性 連接，因此在晶圓層次封裝製程中不需要基板而免除前述 因熱膨脹係數不一致(CTE mismatch)所導致的問題。 本發明另提供一種晶片尺寸級封裝構造製造方法，其包 含下列步驟：（a)提供一上層晶圓以及一下層晶圓，其各包 含複數個上層半導體晶片以及下層半導體晶片，其中每一 1248178 半導體晶片具有—正面以及— 有複數個晶片銲墊設於其上，該上層:下芦；、t:正面具 ^ ... 电線路以及複數個下層導雷始 路，该母-導電線路係用以電性連接二W線 晶片銲塾係分別位於兩相鄰半導體 曰曰、干墊’母對 :於該些下層半導體晶片之正面二些下 上，（C)在该絕緣層形成之後 τ 、， ，槽’該些溝槽分別對二該^ 域’其中每-該些上層導電線路係被相對應之溝= =層導電引線，並且每—導電引線具有—第— 、於該些晶片銲墊之一以及一第二端部裸露於該相對應 之溝槽；㈤形成複數個中間導電引線，其分別將該些上層 導電引線之第二端部電性連接至該些下層導電線路；以及 ②在該些中間導電引線形成後，沿著該些溝槽切割該晶圓、 堆疊，而製得該些晶片尺寸級封裝構造。此外，在步驟⑷ 中’每-該些下層冑電線路係分別被相對應之溝槽分隔成 兩下層導電引線’並且在步驟(e)中，該些中間導電引線係 分別將該些上層導電引線之第二端部電性連接至該下層導 電引線之第二端部。 【實施方式】 雖然本發明可表現為不同形式之實施例，但附圖所示者 及於下文中說明者係為本發明之較佳實施例，並請了解本 1248178 文所揭示者係考量為本發明之一範例，且並非意圖用以將 本發明限制於圖示及/或所描述之特定實施例中。 第6圖所示為根據本發明一實施例之晶片尺寸級封裝構 造100之剖面圖。該晶片尺寸級封裝構造100主要包含彼 此接合在一起的上層半導體晶片110與下層半導體晶片 120 ’複數個上層導電引線13〇(只有兩個標示於第6圖中） 與下層導電引線140 (只有兩個標示於第6圖中）分別形 成在該上層與下層半導體晶片110以及120之正面ii〇a以 及120a，以及複數個中間導電引線145 (只有兩個標示於 第6圖中）分別將該些上層導電引線13〇電性連接至該些 下層導電引線140。該下層半導體晶片12〇設有一絕緣層 150覆蓋於其正面12〇a與該些下層導電引線14〇之上。該 、、、巴緣層150可利用模塑材料(Molding Compound)或一高分 子材料膠膜形成。 邊上層半導體晶片110與下層半導體晶片120各具有複 數個晶片銲墊(bondingpad)160設於其正面110a以及12〇a 之上，用以連接其内部電路。該些晶片銲墊160係形成在 一基片170上。該基片170可以包含一層半導體材料（例 如矽、砷化鎵、碳化矽、鑽石或是其他業界熟知的基片材 料）。該晶片110以及120各包含一護層180(passivati〇n hyer)覆蓋於該基片17〇上。該護層18〇可以是二氧化矽 層、氮化矽層或是由其他業界熟知的護層材料形成。該護 層180具有複數個開孔位於該些晶片銲墊16〇上使得該護 1248178 層180僅覆蓋到該些晶片銲墊160的頂部邊緣，而留下該 些晶片銲墊160的中間表面部分裸露於該護層18〇。 如第6圖所示，該上層半導體晶片11〇與下層半導體晶 片120係利用一中介層(intermediate-layer) 190例如一黏著 層彼此接合在一起使得其背面ll〇b以及12〇b係彼此面 對。該中介層190可由一接合材料例如銲錫(s〇lder)、聚醯 亞胺(polyimide)或環氧樹脂(ep0Xy)形成。可以理解的是， 該上層半導體晶#與下層轉體晶丨亦可歸熔接(础⑺η fUsion)或陽極鍵結(anodic b〇nding)的方式彼此直接接合， 以此方式所製得的封裝構造將不具有前述之中介層。 如第6圖所示，每一該些導電引線13〇以及14〇之第一 端部130a以及l4〇a係分別經由該護層18〇之開孔連接至 一相對應之晶片銲墊160。每一該些導電引線13〇以及14〇 之第二端部130b以及140b係延伸至該些半導體晶片之正 面11〇a以及120a之邊緣。該些導電引線130或14Ό係為 一層預先設定之線路佈局(trace pattem)的一部分，用以將該 些晶片銲墊160電性連接至為該些半導體晶片之正面n〇a 以及120a之邊緣的適當位置。可以理解的是，雖然在第6 圖中該些導電引線⑽以及140之第-端部13〇a以及馳 係例示為刀別直接接觸相對應之晶片銲墊16〇，然而根據 本發明之封裝構造可設置另外一層線路佈局（未示於圖中） 用以將該些導電引線130以及140之第一端部13〇a以及 14〇a分別電性連接至相對應之晶片銲墊160，藉此該些導 1248178 電引線130以及140無須直接接觸相對應之晶片鮮墊16〇。 值得注意的是’相較於習知晶片尺寸級封震構造利用基 板及/或輝線來電性連接上層半導體晶片110與下層半導體 晶片120相對應之晶片銲塾160，本發明係直接利用該些 形成在晶片側面的中間導電引線145連接相對應之上層與 下層導電引線130以及140之第二端部i3〇b以及i4〇b， 精此電性連接相對應之晶片鲜塾160 (例如兩個分別位於 上層半導體晶片110與下層半導體晶片120上功能相同之 晶片銲藝）。因此在本發明封裝構造之晶圓層次封裝製程中 不需要基板而免除前述先前技術因熱膨脹係數不一致 (CTEmismatch)所導致的問題。在此實施例中，每一中間 導電引線145至少有部分形成在該半導體晶片11()與12〇 之側面。該些中間導電引線之表面較佳具有一抗氧化金屬 層（未示於圖中）用以保護其不受腐银(c〇rr〇si〇n)或污染。 該抗氧化金屬層可包含一層鎳覆蓋於該些中間導電引線上 以及一層金或妃覆蓋於該鎳層。 弟10圖所示為根據本發明另一實施例之晶片尺寸級 封裝構造200之剖面圖。除了該上層半導體晶片11〇與下 層半導體晶片120係彼此接合在一起使得該上層半導體晶 片之背面ii〇b正對該下層半導體晶片之正面12〇a之外， 該晶片尺寸級封裝構造200大致與第6圖所示之封裝構造 1〇〇相同。當該絕緣層152係利用一由高分子材料膠膜形 成日守，戎上層半導體晶片110與下層半導體晶片係直 1248178 接藉由絕緣層152彼此接合在一起。此外，當該絕緣層i52 亦可利用模塑材料(MoldingCompound)形成，此時嗲士 構造200另包含-黏著層（未示於圖中）幾於^層半^ 體晶片110背面與該絕緣層152之間。 曰、 在此實施例中，用以連接上層與下層導電引線13〇以及 140之第二端部i3〇b以及i4〇b的中間導電引線147係並 未延伸至下層半導體晶片120之側面。 ’、亚 現請參考第1圖至第5圖，其侧以說明根據本發明一 實施例之“尺核職構造製造方法，其巾不_ 之相同元件係賦予相同之標號。 晶圓10，各包含複數個上層半導 第1圖所示為一上層 體晶片110。 參見第2圖，將一絕緣層150形成於一下層晶圓20之 上。該下層晶圓20包含複數個下層半導體晶片12〇。 该上層晶® 10與下層晶圓2〇各設有複數個上層 ，12以及複數個下層導電線路22於該上層與下層半^體 ιθ;ϋ〇:12〇之正面_及驗該每一該些導電線路 及2侧叫性連接—對晶片銲塾廳，每對晶片鲜塾 160係分別位於兩相鄰半導體 僅標示-對晶片銲塾16〇)。 〜弟2圖各 蚀緣層形成之後，翻轉第2圖所示之下層晶圓2〇 吏下S半導體晶片12〇之背面遍朝上，之後將其與第！ 12 1248178 圖所示之上層晶圓10利用一中介層(intermedi秦layer)l9〇 接合在一起，而形成一如第3圖所示之晶圓堆疊件。在此 實施例中，該上層與下層半導體晶片11〇及12〇之背面n〇b 及120b係彼此面對。可以理解的是，該上層晶圓1〇與下 層晶圓20亦可以矽熔接(sinconfusi〇n)或陽極鍵結(an〇dic bonding)的方式彼此直接接合，以此方式所製得的封裝構造 將不具有前述之中介層。 參見第4圖，利用一切割刀具(dicingblade)在第3 圖所示之晶圓堆疊件上形成複數個溝槽3G而裸露出該些 半導體晶片11G及12G之侧面，其中該些溝槽3G分別對應 於該些晶片之間的邊界區域。值得注意的是，每一該些上 層導電線路12與每一該些下層導電線路22 (參見第f圖） 係分別被相賴之溝槽30分隔成兩上層導電引線13〇與兩 下層導電引線140。該些導電引線13〇及14〇之第一端部 130a及140a係電性連接於該些晶片銲墊16〇之一，該此導 電引線130及140之第二端部服及i働係裸露於^對 應之溝槽30。 參見第5圖’形成複數個中間導電引線145，其分 將该些上層導電引線13〇之第二端部13%電性連接至該此 下層導電引線140之第二端部灘。在此實施例中，= 中間導電引線145至少有部分形成在該些半導體晶片11〇 及120之側面。在該些中間導電引線145形成後，利用一 切割刀具(dicing bladefe著該些溝槽3〇切割第5 1248178 騎私^尺核封裝構造 另a 第9圖’其伽以酬根據本發明 另^例之晶片尺寸級龍構造製造方法，其中不同圖 不間之相同7〇件係舒相同之標號。 声曰=21圖所示之上層晶圓10與第2圖所示之下 ^ :貝接口在一起形成如第7圖所示之晶圓堆疊件。在 例中，該絕緣層⑼係由—高分子材料膠膜形成， 猎h上層晶圓10與下層晶圓2G係糊該高分子材料膠 膜彼此接合。在此實施例中，該些上層半導體晶片之背面 110b係正職些下層轉體晶片之正面i施。 茶見第8 ®，利用一切割刀具(dicing blade)在第7 固所示之raB]堆f件上|成複數個溝槽而裸露出該些 半導體晶ϋ 110之侧面，其巾該麟槽％分聊應於該些 晶片之間的邊界區域。值得注意的是，每—該些上層導電 線路I2與每-該些下層導電線路π (參見第7圖）係分 別被相對應之溝槽30分隔成兩上層導電引線13〇與兩下層 導電引線140。該些導電引線13〇及14〇各具有一第一端 部130a及140a電性連接於該些晶片銲墊16〇之一以及一 第二端部130b及140b裸露於相對應之溝槽3〇。 參見第9圖，形成複數個中間導電引線147，其分別將 該些上層導電引線130之第二端部13〇b電性連接至該些下 層導電引線140之弟一端部140a。在此實施例中，每一中 間導電引線147至少有部分形成在該些半導體晶片11〇之 14 1248178 在，中間導電引線147形成後，利用—切割刀 二icmg叫沿著該些溝槽3()切割 堆豐件而製得如第1”所狄“尺侦曰〇曰〇圓 可以爾岐，在第4_第8騎示 二：刀4可以不切斷該些下層導電線二: 以一下Η ¥电線路22裸露於形成之溝槽中； ，第9圖所示之中間_丨線形成步驟中，'該‘ 係分!將該些上層導電引細之第二端;130b; 連接至裸路於溝槽巾的該釘層導電線路Μ。最後 ，用切割刀具沿著溝槽將每一該些下層導電線路Μ切斷 成兩下層導電引線14〇而製得個別的晶片尺寸級封裝構造 成品。 根據本發明之封裝構造可以直接利用習知的打線接人 (wirebonding)技術安裝於一外部基板，例如一外部印刷口電 路板。詳細言之，封裝構造係藉由複數條銲線(bonding wires) 電性連接至該外部印刷電路板。此外，亦可先將複數個凸 塊電極形成在本發明之封賴造上，再直接细該些凸塊 電極與外部印刷電路板進行接合。習知凸塊電極製造技術 覆晶植球技術可分為兩個部分，分別為凸塊下金屬層 (UBM ’ Under Bump Metallurgy) ’及金屬凸塊本體。根據 本發明之金屬凸塊可以是利用習知的打線技術(wire bonding technique)形成之柱狀突塊(祕卿)。根據本發明 之金屬凸塊亦可以利用銲錫形成，例如（a)高溫錫鉛合金， 15 1248178 如 5Sn/95Pb 或 3Sn/97Pb，及（b)低溫錫錯球，如 63Sn/37Pb1248178 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to electronic packaging technology, and more particularly to wafer size packaging configurations. [Prior Art] As the demand for lighter and more complex electronic devices becomes stronger, the speed and complexity of wafers are relatively higher, and thus higher packaging efficiency is required. Miniaturization is the primary driving force for using advanced packaging techniques such as chip scale packages and flip chips. Compared to the grid array package or the thin small outline package (TSOP), both the wafer size package and the flip chip technology greatly increase the package efficiency, thereby reducing the required substrate space. In general, the size of the wafer size package is comparable to or slightly larger than the size of the wafer itself (up to about twenty percent). In addition, the wafer size package can directly contribute to good kn〇wn good die (KGD) testing and bum-in testing. Furthermore, the wafer size package can also be combined with the surface mount SMT standardization and processability, the low impedance of the flip chip technology, the number of I/O pins and the direct heat dissipation path. And improve the performance of the wafer size package. However, wafer size packages have the disadvantage of higher manufacturing costs compared to ball grid array packages or thin small outline packages (TSOP). If the wafer size package can be manufactured in a large number of 1248178 production methods, the aforementioned disadvantages of high manufacturing cost can be overcome. As a result, packagers are attempting to develop wafer level packaging techniques to enable mass production of wafer size semiconductor package configurations. Conventional wafer level packaging technology manufacturing steps generally require a substrate to be directly attached to a wafer where the semiconductor wafer has not been diced into individual wafers. The substrate is substantially the same size as the entire wafer and includes a plurality of cells corresponding to a plurality of wafers on the wafer. Since the thermal expansion coefficient of the wafer and the substrate is quite different (the coefficient of thermal expansion (CTE) of the wafer is about 3_5 ppm/° C., the thermal expansion coefficient (CTE) of the substrate is about 2〇-3〇ppm/ Cc), so the wafer and substrate will have different expansion or contraction depending on the temperature. This causes shear stress or bend stress at the interface between the wafer and the substrate. Since the substrate is substantially the same size as the entire wafer, the destructive stress is accumulated and the reliability problem caused by the expansion is further increased. It would be desirable to have a method of fabricating a plurality of wafer-scale package configurations at the wafer level that would solve the aforementioned prior art problems. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a wafer size package structure fabricated at a wafer level that solves the aforementioned prior art problems. Another object of the present invention is to provide a method for fabricating a plurality of wafer size package structures at the wafer level (4). According to the present invention, the crystal micro-detection package structure mainly comprises a lower-layer cast crystal 4 which is connected to each other 1248178, and the re-powered leads are respectively formed on the upper and lower semiconductor wafers ==; Some of the upper conductive leads are electrically 』. The underlying semiconductor wafer is overlying the underlying conductive leads. Each of the foregoing has a first braided portion and a second end portion, and the first card 7 is electrically connected to the 二 ^ ^ ^ 鳊邛 且 且 且 且 且 且 且 且 且 且 且 且 且 且Extend to the edge of the front. The mother-intermediate conductive leads are connected to the second ends of the upper and lower lines. 9 When the upper layer and the lower layer (5) are joined to each other such that the back side is made of a fabric, each of the (four) electrical leads has at least a partial shape & the upper layer and the side of the lower semiconductor wafer. When the upper layer and the lower semiconductor wafer are bonded to each other such that the upper semiconductor crystal back surface directly touches the front side of the semiconductor wafer, at least a portion of each of the intermediate conductive leads is formed on the side of the upper semiconductor wafer. In the wafer-scale package structure of the present invention, since the upper layer and the lower semiconductor wafer are directly bonded together and the upper and lower conductive leads are electrically connected to each other by a plurality of intermediate conductive leads formed on the side of the wafer, The substrate is not required in the wafer level packaging process and the above problems due to CTE mismatch are eliminated. The present invention further provides a wafer size packaging structure manufacturing method comprising the steps of: (a) providing an upper wafer and a lower wafer each comprising a plurality of upper semiconductor wafers and a lower semiconductor wafer, wherein each of the 1248178 semiconductors The wafer has a front surface and a plurality of wafer pads disposed thereon, the upper layer: the lower reed; the t: the positive mask ^ ... the electric circuit and a plurality of lower layer guiding guides, the mother-conductive circuit The two W-ray wafer soldering systems are electrically connected to two adjacent semiconductor germaniums, and the dry pad 'mother pair: on the front side of the lower semiconductor wafers, (C) after the insulating layer is formed, τ, , the trenches 'the trenches respectively correspond to the ^ domain' wherein each of the upper conductive traces is corresponding to the trench == layer conductive leads, and each of the conductive leads has a - -, for the wafer soldering One of the pads and a second end are exposed in the corresponding trenches; (5) forming a plurality of intermediate conductive leads, respectively electrically connecting the second ends of the upper conductive leads to the lower conductive lines; ② After forming the plurality of intermediate conductive leads, the plurality of trenches along dicing the wafer stack, yielding the plurality of wafer-level package structure size. In addition, in step (4), 'each of the lower layer of the electric circuit is separated into two lower conductive leads by the corresponding trenches' and in the step (e), the intermediate conductive leads respectively conduct the upper conductive layers The second end of the lead is electrically connected to the second end of the lower conductive lead. [Embodiment] The present invention may be embodied in various forms, and the embodiments shown in the drawings and the following description are preferred embodiments of the present invention. An example of the invention is not intended to limit the invention to the particular embodiments illustrated and/or described. Figure 6 is a cross-sectional view of a wafer scale package structure 100 in accordance with an embodiment of the present invention. The wafer scale package structure 100 mainly comprises an upper semiconductor wafer 110 and a lower semiconductor wafer 120 bonded to each other. A plurality of upper conductive leads 13 (only two are shown in FIG. 6) and lower conductive leads 140 (only two Illustrated in Fig. 6) formed on the front faces ii 〇 a and 120 a of the upper and lower semiconductor wafers 110 and 120, respectively, and a plurality of intermediate conductive leads 145 (only two are shown in Fig. 6) respectively The upper conductive leads 13 are electrically connected to the lower conductive leads 140. The underlying semiconductor wafer 12 is provided with an insulating layer 150 overlying the front surface 12A and the lower conductive leads 14A. The wrap layer 150 may be formed using a molding compound or a film of a high molecular material. The upper semiconductor wafer 110 and the lower semiconductor wafer 120 each have a plurality of bonding pads 160 disposed on the front surfaces 110a and 12A for connecting their internal circuits. The wafer pads 160 are formed on a substrate 170. The substrate 170 may comprise a layer of semiconductor material (e.g., tantalum, gallium arsenide, tantalum carbide, diamond, or other substrate materials well known in the art). The wafers 110 and 120 each include a cover layer 180 (passivati〇n hyer) overlying the substrate 17A. The sheath 18 can be a hafnium oxide layer, a tantalum nitride layer or a sheath material well known in the art. The cover layer 180 has a plurality of openings on the wafer pads 16A such that the cover 1248178 layer 180 covers only the top edges of the wafer pads 160, leaving the intermediate surface portions of the wafer pads 160 Exposed to the sheath 18 〇. As shown in Fig. 6, the upper semiconductor wafer 11 and the lower semiconductor wafer 120 are bonded to each other by an intermediate layer 190 such as an adhesive layer such that the back surfaces 11b and 12〇b face each other. Correct. The interposer 190 may be formed of a bonding material such as solder, polyimide or epoxy (ep0Xy). It can be understood that the upper semiconductor wafer # and the lower layer wafer can also be directly bonded to each other by means of fusion (7) η fUsion or anodic bonding, and the package structure prepared in this way. Will not have the aforementioned interposer. As shown in Fig. 6, each of the conductive leads 13A and 14's first ends 130a and 14a are connected to a corresponding wafer pad 160 via openings of the cover 18, respectively. Each of the conductive leads 13A and 14b of the second ends 130b and 140b extends to the edges of the front faces 11a and 120a of the semiconductor wafers. The conductive leads 130 or 14 are part of a predetermined trace layout for electrically connecting the die pads 160 to the edges of the front faces n〇a and 120a of the semiconductor wafers. The right place. It can be understood that although in FIG. 6, the conductive leads (10) and the first end portions 13a and 140 of the 140 are exemplified as directly contacting the corresponding wafer pads 16A, the package according to the present invention. The structure may be provided with another layer layout (not shown) for electrically connecting the first ends 13 〇 a and 14 〇 a of the conductive leads 130 and 140 to the corresponding wafer pads 160, respectively. The conductive leads 1248178 and the leads 130 do not need to be in direct contact with the corresponding wafer mat 16 〇. It is noted that the present invention directly utilizes the wafer solder fillet 160 corresponding to the conventional wafer size-level sealed structure using the substrate and/or the bright-line to electrically connect the upper semiconductor wafer 110 to the lower semiconductor wafer 120. The intermediate conductive leads 145 on the sides of the wafer are connected to the second ends i3〇b and i4〇b of the upper and lower conductive leads 130 and 140, and the corresponding electrodes are electrically connected to each other 160 (for example, two separate The wafer soldering function is the same on the upper semiconductor wafer 110 and the lower semiconductor wafer 120). Therefore, the substrate is not required in the wafer level packaging process of the package structure of the present invention, and the problems caused by the above-mentioned prior art due to the thermal expansion coefficient inconsistency (CTEmismatch) are eliminated. In this embodiment, at least a portion of each of the intermediate conductive leads 145 is formed on the side of the semiconductor wafers 11() and 12''. Preferably, the surface of the intermediate conductive leads has an anti-oxidation metal layer (not shown) for protecting it from sulphur (c〇rr〇si〇n) or contamination. The oxidation resistant metal layer may comprise a layer of nickel overlying the intermediate conductive leads and a layer of gold or tantalum overlying the nickel layer. Figure 10 is a cross-sectional view of a wafer scale package structure 200 in accordance with another embodiment of the present invention. The wafer size package structure 200 is substantially identical except that the upper semiconductor wafer 11 and the lower semiconductor wafer 120 are bonded to each other such that the back side ii 〇 b of the upper semiconductor wafer is facing the front side 12 〇 a of the lower semiconductor wafer. The package structure shown in Fig. 6 is the same. When the insulating layer 152 is formed by a polymer material film, the upper semiconductor wafer 110 and the lower semiconductor wafer are directly bonded to each other by the insulating layer 152. In addition, when the insulating layer i52 is also formed by a molding material, the gentleman structure 200 further includes an adhesive layer (not shown) on the back surface of the wafer 110 and the insulating layer. Between 152. In this embodiment, the intermediate conductive leads 147 for connecting the second end portions i3b and i4b of the upper and lower conductive leads 13A and 140 do not extend to the side of the lower semiconductor wafer 120. Please refer to FIGS. 1 to 5 for the purpose of illustrating a method for manufacturing a ruler structure according to an embodiment of the present invention, wherein the same components are given the same reference numerals. Each of the plurality of upper semiconductors is shown in FIG. 1 as an upper wafer 110. Referring to FIG. 2, an insulating layer 150 is formed over the lower wafer 20. The lower wafer 20 includes a plurality of lower semiconductor wafers. 12: The upper layer of the layer 10 and the lower layer of the wafer 2 are each provided with a plurality of upper layers, 12 and a plurality of lower layer conductive lines 22 in the upper layer and the lower layer half of the body ιθ; ϋ〇: 12〇 of the front _ and the test Each of the conductive lines and the two sides of the connection - the wafer welding chamber, each pair of wafers 塾 160 series are located in two adjacent semiconductors only labeled - on the wafer welding 〇 16 〇). After the layer is formed, the underlying wafer 2 is turned over, and the back surface of the S semiconductor wafer 12 is turned upside down, and then the upper wafer 10 is shown as an intermediate layer (Fig. 12 1248178). Intermedi Qin layer) l9〇 joined together to form a wafer stack as shown in Figure 3. In this embodiment, the upper and lower semiconductor wafers 11 and 12 are opposite to each other, n 〇 b and 120 b. It can be understood that the upper wafer 1 〇 and the lower wafer 20 can also The sinconfusi〇 or 〇 bonding bonding is directly bonded to each other, and the package structure produced in this way will not have the aforementioned interposer. See Fig. 4, using a cutting tool ( a plurality of trenches 3G are formed on the wafer stack shown in FIG. 3 to expose sides of the semiconductor wafers 11G and 12G, wherein the trenches 3G respectively correspond to boundary regions between the wafers It should be noted that each of the upper conductive lines 12 and each of the lower conductive lines 22 (see FIG. f) are respectively separated by the adjacent trenches 30 into two upper conductive leads 13 and two lower conductive layers. Lead wires 140. The first ends 130a and 140a of the conductive leads 13 and 14 are electrically connected to one of the die pads 16, and the second ends of the conductive leads 130 and 140 are served. The tether is exposed to the corresponding groove 30 of the ^. See Figure 5 A plurality of intermediate conductive leads 145 are electrically connected to the second end of the upper conductive leads 13 至 to the second end of the lower conductive leads 140. In this embodiment, = intermediate conductive At least a portion of the leads 145 are formed on the sides of the semiconductor wafers 11 and 120. After the intermediate conductive leads 145 are formed, a cutting tool is used to cut the 5th 448178. The core package structure is the same as that of the other embodiment. The top layer wafer 10 shown in Fig. 21 and the bottom layer wafer shown in Fig. 2 are joined together to form a wafer stack as shown in Fig. 7. In the example, the insulating layer (9) is formed of a polymer material film, and the polymer film of the upper layer wafer 10 and the lower layer wafer 2G paste are bonded to each other. In this embodiment, the back side 110b of the upper semiconductor wafers is the front side of the lower layer of the wafer. The tea sees the 8th, using a dicing blade on the 7th solid-formed raB] stacking member | into a plurality of trenches to expose the sides of the semiconductor wafers 110, % talks should be in the boundary area between the wafers. It should be noted that each of the upper conductive lines I2 and each of the lower conductive lines π (see FIG. 7) are respectively divided by the corresponding trenches 30 into two upper conductive leads 13 and two lower conductive leads. 140. The conductive leads 13 and 14 have a first end 130a and 140a electrically connected to one of the die pads 16 and a second end 130b and 140b are exposed to the corresponding trench 3〇. . Referring to FIG. 9, a plurality of intermediate conductive leads 147 are formed to electrically connect the second end portions 13b of the upper conductive leads 130 to the one end portion 140a of the lower conductive leads 140. In this embodiment, each of the intermediate conductive leads 147 is at least partially formed on the semiconductor wafers 11 144848178. After the intermediate conductive leads 147 are formed, the dicing knife 2 is called along the trenches 3 ( The cutting of the pile of parts is made as the first "dimensions", "the Detective 曰〇曰〇 可以 可以 岐 岐 岐 岐 岐 岐 岐 岐 岐 岐 第 第 第 第 第 第 第 第 第 第 第 第 第 : : : : : : : : : Η Η 电 电 电 电 裸 裸 裸 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电The nail layer conductive path to the bare groove on the grooved towel. Finally, each of the lower conductive traces is cut into two lower conductive leads 14 by a cutting tool along the trench to produce individual wafer scale package constructions. The package construction in accordance with the present invention can be mounted directly to an external substrate, such as an external printed circuit board, using conventional wire bonding techniques. In detail, the package structure is electrically connected to the external printed circuit board by a plurality of bonding wires. Alternatively, a plurality of bump electrodes may be formed on the seal of the present invention, and the bump electrodes may be directly bonded to the external printed circuit board. Conventional bump electrode fabrication technology The flip chip bonding technique can be divided into two parts, namely a UBM 'Under Bump Metallurgy' and a metal bump body. The metal bump according to the present invention may be a columnar protrusion (secret) formed by a conventional wire bonding technique. The metal bumps according to the present invention may also be formed using solder, such as (a) high temperature tin-lead alloy, 15 1248178 such as 5Sn/95Pb or 3Sn/97Pb, and (b) low temperature tin bump, such as 63Sn/37Pb.
或40Sn/60Pb。此外，根據本發明之金屬凸塊可以是金凸 塊’其一般包含至少九十重量百分比的金，以電鍍的方式 沉積在該凸塊下金屬層上。該凸塊下金屬層可以利用加成 製程（additiveprocess)形成，其係選擇性的沉積該凸塊下 金屬層之各層金屬於本發明封裝構造之適當位置上。該加 成製程係為習知，其一般包含懸空技術（lifr〇fftechnique) 亚且使用陰影遮蔽（shadowmask)。此外，前述凸塊電極 亦可以利用減成製程（subtractiveprocess)形成，其一般包 含（a)將凸塊下金屬層濺鍍沉積在本發明封裝構造之上層 晶片整個表面；（b)塗佈光阻以及形成圖案結構 (patterning) ; (c)電沉積（dectr〇dep〇siti〇n)銲錫（或金） 於光阻層的開孔區域；⑷以銲錫（或金）為遮蔽侧該 凸塊下金屬層。最後，若以銲錫作為金屬凸塊成分，則必 須進行回焊步驟。Or 40Sn/60Pb. Furthermore, the metal bumps according to the present invention may be gold bumps which typically comprise at least ninety percent by weight of gold deposited on the underlying metal layer of the bumps by electroplating. The sub-bump metal layer can be formed by an additive process that selectively deposits the metal layers of the sub-bump metal layer at appropriate locations in the package construction of the present invention. This addition process is conventional and generally includes a dangling technique and uses a shadow mask. In addition, the aforementioned bump electrodes may also be formed by a subtractive process, which generally comprises (a) sputtering a metal under bump deposit on the entire surface of the wafer above the package structure of the present invention; (b) coating the photoresist And forming a patterning; (c) electrodepositing (or dectr〇dep〇siti〇n) solder (or gold) in the open area of the photoresist layer; (4) using solder (or gold) as the shielding side under the bump Metal layer. Finally, if solder is used as the metal bump component, the reflow step must be performed.
根據本發明之封裝構造，其上層晶片係堆疊於下層晶片 亡以增加封裝效率，並且其堆疊步驟係在晶圓層次進行， 藉此可有效增加產率，並且降低成本。此外，根據本發明 之龍構造雖以堆疊兩晶片（晶圓）作為健實施例，伸 j本發明之·構造射用以形成三他上的晶片堆疊 封衣構造而進一步增加封裝效率。 雖然本發明已以前述麵實關揭示，然其並非用以限 疋本發明，任何抑此郷者，林麟本㈣之精神和 16 1248178 範圍内，當可作各種之更動與修改。因此本發明之保護外 圍當視後附之申請專利範圍所界定者為準。 軏 【圖式簡單說明】 顯明之上述和其他目的、特徵、和優點能更明 α ’下文特舉本_概實酬，並配 細說明如下。 I I 1乍砰According to the package structure of the present invention, the upper wafer is stacked on the lower wafer to increase the packaging efficiency, and the stacking step is performed at the wafer level, whereby the yield can be effectively increased, and the cost can be reduced. Further, although the dragon structure according to the present invention is a stacked embodiment in which two wafers (wafers) are stacked, the structure of the present invention is used to form a wafer stacking and sealing structure on the other side to further increase the packaging efficiency. Although the present invention has been disclosed in the foregoing, it is not intended to limit the present invention, and any such modifications and modifications may be made within the scope of the spirit of Lin Linben (4) and 16 1248178. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims.軏 [Simple description of the diagram] The above and other objects, features, and advantages are apparent. α ‘ The following is a general remuneration and is described below. I I 1乍砰
曰至第5圖：其係用以說明根據本發明—實施例之 曰曰曰片^寸__造製造方法； 湖1::圖根據本發明-實施例之晶片尺寸級封裝構造 第7圖至第9 g甘/ 之晶片尺寸用以說明根據本發明另-實施例 第10 FI · α、纪衣造方法；以及 造2〇〇之^面^據本發明另—實施例之晶片尺寸級封裝榍5 to FIG. 5 is a view showing a manufacturing method according to the present invention - an embodiment of the invention; a lake 1:: a wafer size-level packaging structure according to the present invention - an embodiment FIG. The wafer size to the ninth g/g is used to illustrate the 10th FI·α, the method of fabricating the film according to another embodiment of the present invention; and the wafer size of the other embodiment of the present invention. Package榍
【主要元件符號說 圖號說明： 10 晶圓 20 晶圓 12 導電線路 30 溝槽 22 導電線路 17 1248178 100 110 110b 120a 130 130b 140a 145 150 160 180 200 110a正面 120 半導體晶片 120b 背面 130a端部 140 導電引線 140b 端部 147 導電引線 152 絕緣層 170 基片 190 中介層 晶片尺寸級封裝構造 半導體晶片 背面 正面 導電引線 端部 端部 導電引線 絕緣層 晶片銲墊 護層 晶片尺寸級封裝構造[Main component symbol diagram number description: 10 wafer 20 wafer 12 conductive line 30 trench 22 conductive line 17 1248178 100 110 110b 120a 130 130b 140a 145 150 160 180 200 110a front 120 semiconductor wafer 120b back 130a end 140 conductive Lead 140b End 147 Conductive Lead 152 Insulation Layer 170 Substrate 190 Interposer Wafer Size Package Structure Semiconductor Wafer Back Side Conductive Lead End End Conductive Lead Insulation Wafer Pad Cover Wafer Size Package Structure
1818