TWI246176B - Electrostatic discharge protection apparatus for high voltage device, and the manufacturing method thereof - Google Patents

Abstract

The present invention provides an electrostatic discharge protection apparatus for high voltage device, and the manufacturing method thereof, which is to configure a N-type diffusion protection ring in the N-type well in the semiconductor substrate, a P-type diffusion protection ring in the P-type well, and forming a N-type buried diffusion area between the N-type well and the semiconductor substrate as the protection ring for the semiconductor substrate; thus, the present invention could prevent the latch-up effect on the electrostatic discharge protection apparatus for high voltage device under normal operation voltage, and further solve the problem in prior art of easily occurring latch-up effect under normal operation.

Description

1246176 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a related technology of an electrostatic discharge protection device (ESD P r tectec device), in particular to an electrostatic discharge protection device applied to a high-voltage component. Structure and its manufacturing method. [Prior art]

According to the structure of N-type or P-type transistor (N / P MOS), such as gg (gate-ground) N / PMOS, gc (gate-control) N / PMOS element or other similar structure, it is used as electrostatic The discharge protection device must also be a high-voltage component structure, otherwise it will be destroyed at any time under the operation of a high-voltage environment greater than 20 volts. The N / PM0S of high voltage components is mainly due to the characteristics of its parasitic bipolar transistor (B i ρ ο 1 ar). When a high voltage occurs for a moment, its parasitic bipolar transistor will be triggered to properly guide its high voltage. The high current generated by the voltage reaches the Vss or Vdd terminal.

The ggN / PMOS element used to provide electrostatic discharge protection in the integrated circuit is used as an electrostatic discharge protection device. The circuit structure of the 10 is shown in the first figure. The instantaneous forward ESD high voltage will activate the parasitic bipolar element of NM0S 12, The high current is directed to the Vss terminal; the instantaneous reverse ESD high voltage activates the parasitic bipolar element in PM0S 14 and the high current is directed to the Vdd terminal. This application principle is as shown in the second figure. 'When an electrostatic discharge event occurs at the pad of an input terminal, the ggN / PMOS of this high-voltage component will be triggered and enter the sudden turning area ( snapback region), and in this snap region, the ggN / PMOS will clamp a low potential voltage across itself and maintain a high current, so that the electrostatic discharge current can be effectively guided out.

1246176 V. Description of the invention (2) Since high-voltage components are used in high-voltage environment operation, the electrostatic discharge protection device for high-voltage components is designed to be triggered when high-voltage ESD is generated; however, under high-voltage operation environment This ESD structure is extremely susceptible to latch-up under normal operation. That is to say, the parasitic PNP bipolar and NPN bipolar PNPN structures between the PMOS and NMOS are triggered in the CMOS structure of the high-voltage device to generate a latch. Therefore, the present invention is directed to the above-mentioned problems, and proposes an electrostatic discharge protection device for high voltage components and a manufacturing method thereof to solve the problems of the prior art. [Summary of the Invention] The main purpose of the present invention is to provide an electrostatic discharge protection device for a high-voltage component and a manufacturing method thereof, which can prevent the electrostatic discharge protection device of a high-voltage component from a latch-up effect under a normal operating voltage. Another object of the present invention is to provide an electrostatic discharge protection device for a high-voltage component and a manufacturing method thereof. The structure is capable of preventing a punch through phenomenon and a major carrier generated by a potential latch. Drain to semiconductor substrate. In order to achieve the above-mentioned object, the present invention mainly adds an N-type diffusion protection ring in an N-type well in a semiconductor substrate, adds a P-type diffusion protection ring in a P-type well, and then sets the N-type well and the semiconductor substrate There is an N-type buried diffusion area as a guard ring to use this structural design to avoid latch-up. The present invention proposes an electrostatic discharge protection device with the above structural design and a method for manufacturing the device. Detailed descriptions are given below with specific embodiments and accompanying drawings.

Page 1246176 5 'Description of the invention (4) N-type buried doped region 3 2 is located at the bottom of the N-type well 2 4 and the semiconductor substrate 2 〇 as the N-type well 2 4 and the semiconductor substrate 2 A protective ring of 0 is then deposited as shown in the third (C) figure on the semiconductor substrate 20 and a polycrystalline silicon layer is deposited on the surface of the semiconductor substrate 20 and on the P-well 22 using lithographic etching technology. A polycrystalline silicon gate structure 3 4, 3 6 is formed above the N-type well 2 4 respectively; and then an N-type source / drain region 3 is formed in the p-type well 22 and the N-type well 2 4 by ion implantation. 8 and a P-type source / drain region 40, of which the N-type source △ and the pole region 38 are located on two sides of the polycrystalline silicon gate structure 34 on the p-type well 22 respectively, and the p-type source / drain Region 40 is located on both sides of the polycrystalline silicon gate structure 36 on the n-type well 24. Finally, a p-type diffusion guard ring 42 is formed in the p-type well 22, It is adjacent to the N-type source / inverted region 38, and an N-type diffusion guard ring 44 is formed in the n-type well 24, so that the N-type diffusion guard ring 4 4 series P-type source / drain region 4 adjacent square. Finally, the structure of the electrostatic discharge protection device of the CMOS can be as shown in the third (d) figure. In order to prevent the latching phenomenon of the CMOS element, the present invention provides an N-type diffusion guard ring in the N-type well and a p-type diffusion guard ring in the p-type well. There is an N-type buried diffusion area as a protection against radon. Among them, the N-type diffusion guard ring to the _ well and the P-type diffusion guard ring to the P-well can provide a guide channel to discharge the majority carrier generated by the latch that may occur to Vdd. Or Vss, and the above-mentioned N-type buried diffusion region can prevent

1246176 V. Description of the invention (5) ~-The source / electrode region and the semiconductor substrate break down and start the PNPN structure. 'The majority carriers generated by potential latches can also be arranged in the vertical (vertica 1) direction to the semiconductor. In the substrate to avoid the latch-up phenomenon caused by the activation of the horizontal p N pn structure due to the lateral flow. Therefore, the present invention can effectively prevent the occurrence of a latchip phenomenon during the normal operation of the circuit, thereby solving the prior art in the high voltage element; the parasitic pNp bipolar and NpN bipolar between PM〇 ^ NM〇s are easily generated in the CMOS structure The PNPN structure is triggered to generate the missing one. & The embodiments described above are only for explaining the technical ideas and characteristics of the present invention, and the purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. The scope, that is, any equivalent change or modification made according to the spirit disclosed by the present invention, should still be covered by the patent scope of the present invention. "'[Illustration of drawing number]

1 〇 ESD protection device 12 NM0S

14 PM0S 2 0 Semi-ship base 2 2 P-type well 2 4 N-type well 26 N-type drift region 2 8 P-type drift region 30 Field oxide layer 3 2 N-type buried doped region.

1246176 V. Description of the invention (6) 3 4, 3 6 Polycrystalline silicon gate structure 38 N-type source / drain region 4 0 P-type source / drain region 42 P-type diffusion protection ring 44 N-type diffusion protection ring 1246176 Simple diagram Explanation The first figure is a schematic diagram of the circuit structure of the M 0 S element of the conventional electrostatic discharge protection device applied to the integrated circuit. The second figure is a graph showing the occurrence of electrostatic discharge. The third (a) to third (d) diagrams are cross-sectional views of the structure of each step in manufacturing the electrostatic discharge protection device of the present invention.

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Claims (1)

1246176 VI. Scope of patent application1. An electrostatic discharge protection device for high-voltage components, the structure of which includes: a semiconductor substrate on which a plurality of isolation elements are arranged; an N-type well and a P-type well, respectively formed on the semiconductor Within the substrate and adjacent to it; an N-type drift region and a P-type drift region, which are respectively located in the P-type well and the N-type well; an N-type buried doped region, which is located in the N-type well Where the bottom meets the semiconductor substrate; two polycrystalline silicon gate structures are respectively located on the surface of the semiconductor substrate above the N-type well and the P-type well; an N-type source / drain region and a P-type source / drain region, respectively Located in the P-type well and the N-type well, so that the N-type source / drain region is located on both sides of the polycrystalline silicon gate structure on the P-type well, and the P-type source / drain region is located on the N-type well On both sides of the polysilicon gate structure, an N-type diffusion guard ring is disposed in the N-type well and adjacent to the P-type source / drain region; and a P-type diffusion guard ring is disposed in the P-type well and Adjacent to the N-type source / drain region. 2 · The electrostatic discharge protection device for the high-voltage component as described in item 1 of the patent application scope, wherein the isolation component has a field oxide layer structure. 3. The electrostatic discharge protection device for the high-voltage component according to item 1 of the scope of the patent application, wherein the N-type buried doped region serves as a guard ring for the N-type well and the semiconductor substrate. 1246176 6. Scope of patent application N + ions with a concentration greater than 1 * 1 0 14 / cm 2 are implanted at the bottom of the N-type well. 7. The manufacturing method as described in item 4 of the scope of patent application, wherein the isolation element has a field oxide layer structure.