TWI246003B - Method for dynamic balancing of a clock tree - Google Patents

Abstract

The present invention provides a method to balance a clock tree dynamically. A controllable buffer is inserted in a specific level of a clock tree, and a controller is provided for adjusting two clocks with different skew by controlling the PMOS/NMOS arrangements in the controllable buffer so as to generate more current for compensating the time delay of slow clock to a sink. This method effectively suppressed the clock skew generated by the voltage drop or the temperature variations in the synchronous logic circuit design.

Description

1246003 Description of the five inventions (1) The technical field of the invention The present invention relates to a method of disparity, in particular to a clock circuit phase in a logic circuit design. The clock phase is balanced in a synchronous logic circuit design. Specially designed circuit for synchronous disparity.

AJULM designs a synchronous circuit day car, a, y ^ It is generally assumed that all memory elements use the same, tc 1 ock), the clock signal of each memory element is transformed into evil at the same time (from South potential Han Cheng 彳 κ φ y θGAN ^ ^ π + 锝 烕 low potential, or change from low potential to high potential), and /, ', and combination logic blocks all use the same clock interval, so = setup time (setup Ume) and maintenance of clock change state The time vno 1 d time) can be estimated by using the wrong memory, flip-flop (f 丨 ifi), ^^ (latch), etc. However, Zhongxun is connected to different paths of the component: the length and the different input capacitance of the specific component make the above assumption impossible. The pill diagram Γ shows that the Zhongxun is transmitted from the Zhongxun source 0 to the sink (l) than to the sink. ..h is fast, because the wire to the fall point n has higher resistance and capacitance than the wire to the fall point, which makes the extension line produced by Zhong Xun delayed. . Captain Car currently uses a clock branch circuit synthesizer = _heS1S t00ls) to produce a "balanced clock tree" that groups each group of clock source 0 into a clock source. A branch of 〇, 1 knife, solid group is repeatedly used on the branch, so a bell branch is formed, such as the ^ second-order bell synthesis tool can consider the resistance and capacitance of the wire and '; ^ = electricity

Page 5 12460003 V. Description of the invention (2) = 5 weeks of the entire wire length 'makes the length of each drop point of the clock signal source, so the clock signal of each drop point has zero routes and has been applied to the earliest H- Tree branches stretch. This view. As long as the bell signal branch is generated = method: = near Steiner-branch root) to each point (leaf of the bell branch), the extension = if "balanced bell branch" cannot be used, the buffer contains The two divisions will insert buffers on the appropriate branch (hot branch); 201 will generate a "buffer branch", as shown in Figure 2 with an inverter. The above method assumes that the temperature and voltage of the entire circuit are the same, that is, the above method treats the clock signal branch circuit as static, but it is actually not the case for a working integrated circuit chip. The integrated circuit chip at work, because some circuit blocks have more switching actions, have different surface temperatures in different areas. The difference in temperature will affect the hole / electron's different fluidity in the semiconductor device and also change the resistance of the wire. These phenomena also cause the clocks to distort the clock. In addition, the circuit that generates more action (more heat) will form a larger voltage drop. This larger voltage drop will make the local V dd (power supply) lower than other parts on the chip, so some related circuits ( (Eg, inserted buffers) respond more slowly than other components with normal Vdd. Both the voltage drop and the increase in temperature make the above-mentioned "balanced" clock branch circuit unbalanced. In order to take care of the circuits with different temperatures and voltage drops in various corners, commercial computer-aided design tools insert too many buffers in the clock signal tree circuit, making the clock signal balance worse, because active components (such as buffers) are more passive than passive elements.丄 246003. V. Description of the invention (3) Items (such as wires) are more susceptible to voltage and temperature

Therefore, the method of the present invention provides a group of PM0S / NM0S in a controllable buffer, and controls the two clock signals of the hunting control, so it generates more electricity and adjusts the slow clock signals with different phase differences. time delay. Comparison of claws with μ to compensate for a certain fall point

A controllable buffer and providing a control _ Please refer to FIG. 3, which shows a clock signal branch circuit = 31 is inserted in a special level of the clock signal branch circuit to 50 to control the controllable buffer 31. Figure 4 shows an example of the controllable buffer 31, which has a combination of several lines of hidden and NMOS, each line has two PM0s and two serially connected, as shown in the figure. The clock input signal Clk_ln is input to the gates of the top PM0S 42 and the bottom NMOS 45 of each row via an inverter 41. Control signals c (0), C (l), C (2), ... C (x) are input to the middle of each row and the gates of NMOS 44 respectively. An inverter 46 is inserted between the gates of pM0s 43 and NMOS 44 in the middle of each row. When each control signal C (0), C (l), (: (2), ... (: (χ) is "1" (high potential), a duplicated clock signal input signal Clk_in will appear in The output terminal 47 of each row is used as the clock output signal cik_out. When the control signals C (0), CO), C (2), ... C (x) are "0" (low potential), each

Page 7 1246003 V. Description of the Invention (4) The output terminal 47 of the row will show high impedance. Therefore, the control signals C (0), C (l), C (2), ... C (x) can control which rows are connected in parallel to provide the clock output signal C1 k_out. Provides clock output k number C 1 k-out and the more rows connected in parallel, the more current is output. The clock output signal C1 k_out turns to the next level of the clock branch.

凊 Referring to FIG. 5, a controller 50 0 ′ is designed according to a phase-locked loop (P L L), and two clock signals of two different landing points (s i nk) are input to the controller 50. The controller 50 compares the phase difference between the two input clock signals through a phase detector 51, and then generates a proper voltage with a charging circuit 52, and then uses the voltage detector 5 3 to generate "increase", " The signal of "flat" or "down" instructs the up / down counter 54 to control an output bus C [X: 0]. The output bus C [X: 〇] contains C (0), C (l), C (2), ... C (X), C (0), C (l), C (2),. ..C (x) is input to the gates of the PMOS 43 and NMOS 44 in the middle of each row respectively. Please refer to Figure 6. For any two landing points (S i nk), arrange the controller 5 to receive the relevant clock signals and compare them. The phase difference generates an output bus c [χ: 〇] sent to a specific level of the Zhongxun tree branch, so as to adjust the number of parallel lines to provide the Zhongxun output signal Clk-out ', thus providing the appropriate output current to drive the relevant landing point χ, then compensate for the phase difference between the two clocks. Please refer to Figure 6. The controller 50 can be arranged between any two clocks, so a control loop is formed, as shown in the figure. The spirit and scope of the present invention are limited only by the scope of the following patent applications, and are not limited to the embodiments described above.

1246003 Schematic description '' Figure 1 is a schematic diagram of an unbalanced clock signal circuit. -Figure 2 is a schematic diagram of a balanced clock branch circuit. FIG. 3 is a schematic diagram of a dynamic balanced clock signal branch circuit according to the present invention. FIG. 4 is a schematic diagram of a controllable buffer according to the present invention. FIG. 5 is a block diagram of the controller of the present invention. FIG. 6 is a schematic diagram of a dynamic balanced clock signal branch circuit with a control loop according to the present invention. Brief description of component representative symbols 〇 Clock source 20 Inserted buffer 31 Controllable buffer 41 Inverter

42 PM0S

43 PM0S

44 NM0S

45 NM0S 46 Inverter 4 7 Output 50 Controller 51 Phase detector 52 Charger 53 Voltage detector 54 Up / down counter

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Claims (1)

1246003 ι · A method for dynamically balancing a clock circuit in a clock signal tree, a controllable buffer circuit, a clock signal tree level, and providing a controller to enter a specific signal of the clock tree circuit, and The controller-wheel output takes the arrangement of PM0S / NM0S in Zhong Chongyi with two different phase differences. The g non-C [χ. 0] control can control the slow end to generate more current. Controls the time delay of the slow clocking out of the buffer. Comparison of a falling point of a branch circuit of a bell tree. 2. If the method of the first scope of the patent application is applied, the position detector in A, a charging circuit, and a question ^: The working state includes one and one output. Bus C [x: 〇]. Earth, ', 丨 state,-up / down counter ^ Renru * The method of applying for the scope of patent No. 1, wherein the controllable buffer cry contains a combination of several rows of S and _8, each of which has two counters And two ^ NM0S in series, a clock signal input signal is input to the gate of PM0S and NM0S at the top of each row through an inverter, and outputs the bus signal c [x: 0]-control signal C (0), C (l), C (2), ... C (x) are input to the gates of PM0S and NM0S in each row, and an inverter is inserted between PM0S and NM0S in the middle of each row, and PM0S in the middle. A clock output signal appears where it is connected to the NM0S.