1244743 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝構造及其製造方法，更 特別有關於一種具有雙基板之半導體封裝構造及其製造方 法。 【先前技術】 隨著更輕更複雜電子裝置需求的日趨強烈，晶片的速度 及複雜性相對越來越高。半導體晶片需要提供相對上更多 的接腳’用以輸入及輸出訊號。然而，習用之半導體封裝1244743 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor package structure and a manufacturing method thereof, and more particularly to a semiconductor package structure with a dual substrate and a manufacturing method thereof. [Previous Technology] With the increasing demand for lighter and more complex electronic devices, the speed and complexity of chips are relatively higher and higher. The semiconductor chip needs to provide relatively more pins' for inputting and outputting signals. However, conventional semiconductor packages
構 ie 諸如小外形封裝（Small Outline Package ; SOP)、四 方平坦封裝（Quad Flat Package ; QFP)、球格陣列封裝（BaUStructures such as Small Outline Package (SOP), Quad Flat Package (QFP), Ball Array Package (BaU)
Grid Array; BGA)，皆僅能提供單一方向的連接，因此造 成了連接上的方向性限制。Grid Array (BGA), which can only provide connections in a single direction, thus creating a directional limitation on the connection.
以第1圖及第2圖之兩種不同型式的球格陣列(關 GHd Array ; BGA)封裝構造i ^列，於該球格陣列封裝構 、中帛導體明片11、12係各別藉由打線技術及覆晶 技術而電性連接至一基板1 3 、 饥υ上以猎由禝數個錫球14電 生連接至一外部電路如：一印刷雷 1 W逼路板（未顯示）上。由 於該錫球14係設於該基板1 3 壯μ 之下表面，因而使得該球格 降列封Α構造10本身僅能提供 此從仏早方向的連接，造成了苴 使用上之限制。 女仏风J /、 已能與輕薄則、的需求帶動τ，半導體 翥界已υ Μ種Μ㈣m㈣裝構 Package ; SiP)，用 w 脸工 y 1 ^ (i>y em in 將兩個或兩個以上之晶片組合在單一 1244743 封裝構造中，藉以使整個系統之體積最小化，並進而降低 晶片間訊號延遲以及存取時間。 第3圖係顯示一習知的系統級封裝構造（sip ) 1 〇〇。該 系統級封裝構造100包含一底座基板1 〇2以及一中介基板 104設於該底座基板102之上方。該底座基板1〇2以及該 中介基板1 04上分別設有一第一半導體晶片丨〇6以及一第 二半導體晶片（或一晶片尺寸級封裝構造（Chip Scale Package; CSP)) 108,其中該第一半導體晶片1〇6以及該 第二半導體晶片108分別電性連接於該底座基板丨〇2以及 該中介基板104。該中介基板104具有一開口 i〇4a，用以 容納該第一半導體晶片1 06。另外，該中介基板丨〇4之上 下表面分別具有複數個第一接墊丨丨2以及第二接墊丨丨4，用 以分別電性連接至該第二半導體晶片1〇8以及該底座基板 102上之第一半導體晶片106，使得該第一半導體晶片ι〇6 及a亥第-一半導體晶片108可相互電性連接。 然而，由於δ亥第一半導體晶片i 06係必需藉由焊線 105、該底座基板102上之導電線路（未顯示）、該第二接 墊114上之金屬凸塊、該中介基板以及該第一接墊ιΐ2上 之金屬凸塊而電性連接至該第二半導體晶片1()8，因此該 第:半導體晶片106與該第二半導體晶片1〇8間之導電路 徑係為較長的，因而造成了阻抗（impedance)、電感 (indUCtanee)及雜訊（nGise)之增加，進而影響最終封裝構造 之電性效能。再者，該中介基板1〇4上的開口 1〇乜之設置 係縮小了其本身上下表面可被利用之面積’因而限制了該 第-半導體W 106與該第二半導體晶片1()8間電性連接 1244743 的I/O數目。 有鑑於此，有必要存在—種半導體封裝構造，用以提供 又方向的电I·生連接、肖1/〇接腳數以及短的導電路徑，以 解決上述之問題。 【發明内容】 本發明之一目的在於提供一種半導體封裝構造，其不但 具有又方向的電性連接，更具有冑1/0接腳數以及較短的 導電路徑，用以解決習知的封裝構造所存在之問題。 本毛明之另一目的在於提供一種半導體封裝構造之製 k方法，藉由該方法所製造的半導體封裝構造係具有雙方 向的電性連接、高1/0接腳數以及短導電路徑之特性，以 解決習知的封裝構造所存在之問題。 為達上述之目的，本發明係提供一種半導體封裝構造， 其包含-上基板、一下基板以及一半導體晶片，該上基板 之上表面具有複數個第一接墊，I其下I面具有複數個第 一接墊電性連接至其上表面之該等第一接墊；該下基板之 上表面具有複數個第三接塾m表面具有複數個第四 接墊電性連接至其上表面之該等第三接墊；以及該半導體 晶2係設置於該上基板與該下基板間，並與該上基板之該 等第二接墊及該下基板之該等第三接墊電性連接。 根據本發明之半導體封裝構造，該上基板上表面之第一 接墊與該下基板下表面之第四接墊係可用以電性連接至其 它外部電路。 本發明另提供一種半導體封裝構造之製造方法，該方法 1244743 已3下列步驟·提供一下基板，其上表面具有複數個第一 I執且其下表面具有複數個第二接塾電性連接至該等第 -接塾’·設置一半導體晶片於該下基板之上表面上… Π:體:%片上設有複數個第一晶片接塾及複數個第：晶 墊，精由複數條焊線將該半導體晶片之該等第二晶片 接墊電性連接至該下基板之該等第一接墊；提供一上基 :二其上表面具有複數個第三接塾，且其下表面具有《 個弟四接塾電性連接至該等第三接墊，·以及設置該上 於該，導體晶片上，並藉由複數個第一金屬凸塊將該：基 板之該等第四接塾電性連接至該半導體晶片之該等第一晶 片接墊。 根據本發明之半導體封裝構造及其製造方法，其提供了 一具有高封裝效率之半導體封裝構造，並相當適用於一系 統級封裝構造（SiP)及其製程中。 為了讓本發明之上述和其他目的、特徵、和優點能更明 顯下文將配合所附圖示，作詳細說明如下。 【實施方式】 第4圖係為根據本發明一實施例之半導體封裝構造2〇〇 的示心圖。孩半導體封裝構造2〇〇係包含一下基板、 一上基板204以及一半導體晶片2〇6。該下基板2〇2之上 表面202a係設有複數個接墊2〇3a，其下表面2〇2b係設有 複數個接墊203b，其中該複數個接墊2〇3a係藉由設於該 下基板202内部的複數條導電線路如：鍍通孔（未顯示） 而與該複數個接墊203b電性連接。該上基板2〇4之上表面 1244743 係設有複數個接塾205a，其下表面2〇4b係設有複數 個接墊205b，其中該複數個接墊2〇5a係藉由設於該上基 板204内部的複數條導電線路如：鍍通孔（未顯示）而與 該複數個接墊205b電性連接。該半導體晶片2〇6係夹設於 該下基板202 <上表® 202a以及該上基板2〇4之下表面 204b間且其具有複數個晶片接墊207a、207b設置於其 主動表面206a上。該複數個晶片接墊2〇7b係配置於該複 數個晶片接墊207a之周圍，如第5圖所示。於此實施例中， 該複數個晶片接墊207a係可電性獨立於該複數個晶片接 墊207b，或者可藉由形成於該主動表面2〇6a上之導電線 路（未顯示）而選擇性地電性連接至該複數個晶片接墊 207b 〇 現請參考第4圖及第5圖，該半導體晶片2〇6之主動表 面206a上的複數個晶片接墊207b係藉由複數條焊線21〇 而分別電性連接至該下基板202上之複數個接墊2〇3a。另 外’該晶片206之主動表面206a上的複數個晶片接墊2〇7a 係藉由複數個金屬凸塊2 1 2而分別電性連接至該上基板 204下之複數個接墊205b。較佳地，該半導體晶片2〇6係 包覆於一封膠體（package body ) 2 1 4中，藉此保護該半導 體晶片206以及其與該下基板202以及該上基板204之電 性連接。或者，該半導體晶片206係可包覆於一填膠 (underHll )中，藉以達到相同之保護目的。 於此實施例中，由於該半導體晶片206係分別藉由該焊 線2 1 0與該金屬凸塊2 1 2而電性連接該下基板202上之接 墊203a與該上基板204下之接墊205b，且又由於該接塾 1244743 203a與該接墊205b係各別電性連接於該下基板2〇2下之 接墊203b與該上基板204上之接墊205a，因此該半導體 晶片206係可藉由該下基板2〇2下之接墊2〇3b與該上基板 204上之接墊205a而與其它外部電路電性連接。 於本發明之另一實施例中，該下基板202與該上基板 204上之電路亦可藉由複數個金屬凸塊2丨6而相互電性連 接’如第ό圖之半導體封裝構造25〇所示。 根據本發明之半導體封裝構造2〇G，其係可藉由該下基 板202與該上基板204之接墊203b、205a而各別與其它外 邓電路電性連接，因而具有雙方向性的電性連接特性。再 者，由於讓半導體封裝構造2〇〇具有雙方向性的電性連接 特性，使得其本身係相當適用於一系統級封裝構造（sip)中。 現請參考第7圖，其係為利用第4圖之半導體封裝構造 2〇〇所達成的-系統級封裝構造（Sip)3aG之示意圖。於該系 統級封裝構造300中，一半導體元件2〇8如：一覆晶（fUp AiP)或一晶片尺寸級封裝構造（chip scale)係經 由一迴焊（reflow)製程而設置於該上基板2〇4之上表面 2〇4a，並藉由複數個金屬凸塊218而與該上基板2㈧上之 接塾咖電性連接。應了解到，該半導體元件2G8並不限 於覆晶或晶片尺寸級封裝構造，#亦可為其它任何型態之 半導體封裝構造或裝置。 另外，複數個錫球或金屬凸& 220係設置於該下基板 2〇2之下表面㈣的接墊繼上，用以電性連接至一外 部電路如··一印刷電路板（未顯示）上。 1244743 相較於習知的系統級封裝構造丨00 (如第3圖所示）之 半導體晶片106而言，由於本發明之半導體晶片2〇6另具 有複數個晶片接墊207a電性連接至該上基板2〇4，且該上 基板204上並無任何開口之設計，因此該半導體晶片2〇6 係可提供更多的I/O數（接墊205a、205b)及更短的導電 路徑，用以與其它半導體元件或晶片電性連接。 第8圖至第1 2圖係用以說明根據本發明之該半導體封 裝構造200的製造方法。 # 現請參考第8圖，一下基板2〇2係先被提供，該下基板 202之上表面2〇2a設有複數個接墊2〇3a，而其下表面2〇2b 係設有複數個接墊203b與該複數個接墊203a電性連接。 現請參考第9圖，一半導體晶片2〇6係被設置於該下基 板202之上表面202a上。該半導體晶片2〇6之主動表面 206a上係具有複數個晶片接墊2〇7a及複數個晶片接墊 207b ’其中該複數個晶片接墊2〇7a上另具有複數個錫球或 • 金屬凸塊212植於其上。另外，該複數個晶片接墊207b係 配置於該複數個晶片接墊2〇7a之周圍，如第5圖所示。 現請參考第10圖，複數條焊線210係可藉由打線技術 而各別形成於該複數個晶片接墊2〇7b與該複數個接墊 2〇3a間，使得該半導體晶片2〇6係能夠與該下基板2〇2電 性連接。 現請參考第11圖，一上基板204係被提供並設置於該 半導體晶片206上。該上基板204之上表面2〇4a係設有複 數個接墊205a，且其下表面2〇4b係設有複數個接墊2〇5b 1244743 與該複數個接墊205a電性連接。該半導體晶片2〇6上之複 數個晶片接墊207a係藉由該複數個金屬凸塊2丨2而與該上 基板204之複數個接墊205b電性連接，使得該半導體晶片 2 06係能夠藉此而與該上基板204電性連接。 現請參考第12圖，一封膠模具2丨8係可接合於該上基 板204與該下基板202間。之後，一封膠材料（m〇lding compound)係可經由一封膠模具218之注膠道218a而注入 • 於該上基板204與該下基板202間，以形成一封膠體 (package body) 214，用以保護該半導體晶片2〇6以及其 《亥下基板2 0 2以及5亥上基板2 0 4之電性連接，如第4圖 所不。或者，於另一替代實施例中，一填膠（underfiu )係 可注入於該上基板204與該下基板202間，藉以達到相同 、之保護目的。 ' 第8_1()圖以及第13_14圖係用以說明根據本發明之該 半導體封裝構造250的製造方法。 鲁現凊參考第13圖，一封膠體（package body ) 214係可 藉由一封膠模具而形成於該下基板202上，用以包覆並保 護該半導體晶片206以及其與該下基板202之電性連接。 現請參考第14圖，該封膠體214之頂部214a係藉由一 機械研磨機（未顯示）研磨，藉以使該複數個金屬凸塊212 可裸露於該封膠體214之頂部214a。接著，將複數個錫球 或金屬凸塊216設置於該下基板202之上表面202a，用以 電性連接於該下基板202上之其它電路接點或接墊（未顯 不）°應了解到，第13圖與第14圖之用以形成封膠體214 12 1244743 於該上基板204與該下基板202間的方法亦可應用於該半 導體封裝構造200中。 最後，如第6圖所示，一上基板204係被提供並設置於 該封膠體214上。該上基板204之上表面204a係設有複數 個接墊205a，且其下表面204b係設有複數個接墊2〇5b與 該複數個接墊205a電性連接。該半導體晶片2〇6上之複數 個晶片接墊207a係藉由裸露於該封膠體2 14之頂部21乜 上的複數個金屬凸塊212而與該上基板204之複數個接墊 2〇5b電性連接，使得該半導體晶片2〇6係能夠藉此而與該 上基板204電性連接。同時，該上基板2〇4之下表面汕仆 另。又有其匕電路接點或接墊（未顯示），用以電性連接至該 複數個金屬凸塊216，使得該上基板2〇4與該下基板2〇2 上之電路能夠藉此而相互電性連接。 以便能夠提供一體化的電子模組 綜前所述，根據本發明之半導體封裳構造係具有上下基 板:用以提供雙方向的電性連接。尤其，該半導體封裝構 造係^於系統級封裝構造中（System & paekage ; Μ)， 雖然本發明已以前述實-^ 〇 Μ ^例揭不，然其並非用以限定本 發明，任何熟習此技藝者， ^ ^ _ ., . ^ 在不脫離本發明之精神和範圍 内，*可作各種之更動盘修对 m 視後P# t Φ β ϋί ~ > 。口此本發明之保護範圍當 視後附之申凊專利乾圍所界定者為準。 【圖式簡單說明】 第1圖及第2圖係為先 陣列封裝構造之示意圖。 珂技術t之兩種不同型式 的球格 13 1244743 示意圖 弟3圖係泛 ’、為~習知的系統級封裝構造之示意圖。 第4圖係A 〜、艮據本發明一實施例之半導體封裝構造 之 第5圖係A # 一 為弟4圖中之半導體晶片上 不意圖。 的晶片接墊之配置 之示〃咅圖\系為根據本發明另一實施例之半導體封裝構造Use the two different types of ball grid array (off GHd Array; BGA) package structure i ^ row in Figure 1 and Figure 2. In this ball grid array package structure, the medium and large conductor plate 11, 12 are borrowed separately. It is electrically connected to a substrate 1 3 by wire bonding technology and flip chip technology. It is electrically connected to an external circuit by a plurality of solder balls 14 and is electrically connected to an external circuit such as: a printed thunder 1 W circuit board (not shown) on. Since the solder ball 14 is located on the lower surface of the substrate 13, the ball grid structure A structure 10 itself can only provide this connection from the early direction, resulting in restrictions on the use of 苴. Nv style J /, has been able to drive τ with the demand for thin and light, and the semiconductor industry has υ Μ species Μ㈣m device structure package; SiP), using w face workers y 1 ^ (i > y em in will be two or two More than one chip is combined in a single 1247443 package structure, thereby minimizing the size of the entire system, and further reducing the signal delay and access time between chips. Figure 3 shows a conventional system-level package structure (sip) 1 〇. The system-level package structure 100 includes a base substrate 102 and an interposer substrate 104 provided above the base substrate 102. A first semiconductor wafer is provided on each of the base substrate 102 and the interposer substrate 104. 〇〇6 and a second semiconductor wafer (or a chip scale package (CSP)) 108, wherein the first semiconductor wafer 106 and the second semiconductor wafer 108 are electrically connected to the base, respectively Substrate 〇〇2 and the interposer substrate 104. The interposer substrate 104 has an opening IO4a for receiving the first semiconductor wafer 106. In addition, the upper and lower surfaces of the interposer substrate 04 have a plurality of A pad 丨 2 and a second pad 丨 4 are used to electrically connect to the second semiconductor wafer 108 and the first semiconductor wafer 106 on the base substrate 102, respectively, so that the first semiconductor wafer ι 〇6 and a first semiconductor wafer 108 can be electrically connected to each other. However, since the first semiconductor wafer i 06 of δ Hai must be connected by a bonding wire 105, a conductive line (not shown) on the base substrate 102, the The metal bumps on the second pad 114, the interposer substrate, and the metal bumps on the first pad 2 are electrically connected to the second semiconductor wafer 1 () 8, so the first: semiconductor wafer 106 and the The conductive path between the second semiconductor wafer 108 is longer, which results in an increase in impedance, indUCtanee, and nGise, which in turn affects the electrical performance of the final package structure. The arrangement of the opening 10 乜 on the interposer substrate 104 reduces the area on which the upper and lower surfaces can be used, thereby limiting the electrical properties between the first semiconductor W 106 and the second semiconductor wafer 1 () 8. Number of I / Os connected to 1244743. Given It is necessary to have a semiconductor package structure to provide the electrical connection in the other direction, the number of pins of 1/0, and the short conductive path to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention The purpose is to provide a semiconductor package structure that not only has electrical connections in the other direction, but also has a number of 胄 1/0 pins and a short conductive path to solve the problems existing in the conventional package structure. An object is to provide a method for manufacturing a semiconductor package structure. The semiconductor package structure manufactured by the method has the characteristics of bidirectional electrical connection, high 1/0 pin number, and short conductive path to solve the conventional problem. Problems with the package structure. To achieve the above object, the present invention provides a semiconductor package structure including an upper substrate, a lower substrate, and a semiconductor wafer. The upper surface of the upper substrate has a plurality of first pads, and the lower I surface has a plurality of first pads. The first pads are electrically connected to the first pads on the upper surface thereof; the upper surface of the lower substrate has a plurality of third pads; the surface has a plurality of fourth pads electrically connected to the upper surface thereof; And other third pads; and the semiconductor crystal 2 is disposed between the upper substrate and the lower substrate, and is electrically connected to the second pads of the upper substrate and the third pads of the lower substrate. According to the semiconductor package structure of the present invention, the first pads on the upper surface of the upper substrate and the fourth pads on the lower surface of the lower substrate can be electrically connected to other external circuits. The present invention further provides a method for manufacturing a semiconductor package structure. The method 1244743 has the following steps. A substrate is provided with an upper surface having a plurality of first terminals and a lower surface having a plurality of second terminals electrically connected to the substrate. Waiting-Connections' · A semiconductor wafer is set on the upper surface of the lower substrate ... Π: body:% wafers are provided with a plurality of first wafer connections and a plurality of first: crystal pads, which are composed of a plurality of bonding wires The second wafer pads of the semiconductor wafer are electrically connected to the first pads of the lower substrate; an upper base is provided: two upper surfaces have a plurality of third contacts, and the lower surface has The fourth connection is electrically connected to the third connection pads, and is provided on the conductor wafer, and the fourth connection is electrically connected to the substrate by a plurality of first metal bumps. The first wafer pads connected to the semiconductor wafer. According to the semiconductor package structure and its manufacturing method of the present invention, it provides a semiconductor package structure with high package efficiency, and is quite suitable for a system-level package structure (SiP) and its manufacturing process. In order to make the above and other objects, features, and advantages of the present invention more apparent, the following description will be described in detail with reference to the accompanying drawings. [Embodiment Mode] FIG. 4 is a schematic diagram of a semiconductor package structure 2000 according to an embodiment of the present invention. The semiconductor package structure 200 includes a lower substrate, an upper substrate 204, and a semiconductor wafer 206. The upper surface 202a of the lower substrate 202 is provided with a plurality of pads 203a, and the lower surface 202b is provided with a plurality of pads 203b, wherein the plurality of pads 203a are provided by A plurality of conductive lines inside the lower substrate 202 are electrically connected to the plurality of pads 203b, such as plated through holes (not shown). The upper surface of the upper substrate 2104 is provided with a plurality of contacts 205a, and the lower surface 204b is provided with a plurality of contacts 205b. The plurality of contact pads 205a are provided on the upper surface. The plurality of conductive lines inside the substrate 204 are electrically connected to the plurality of pads 205b, such as plated through holes (not shown). The semiconductor wafer 206 is sandwiched between the lower substrate 202 < Upper Table® 202a and the lower surface 204b of the upper substrate 204 and has a plurality of wafer pads 207a, 207b disposed on its active surface 206a. . The plurality of wafer pads 207b are arranged around the plurality of wafer pads 207a, as shown in FIG. In this embodiment, the plurality of wafer pads 207a can be electrically independent of the plurality of wafer pads 207b, or can be selectively selected by a conductive circuit (not shown) formed on the active surface 206a. The ground is electrically connected to the plurality of wafer pads 207b. Please refer to FIG. 4 and FIG. 5. The plurality of wafer pads 207b on the active surface 206a of the semiconductor wafer 206 are connected by a plurality of bonding wires 21. 〇 and a plurality of pads 203a electrically connected to the lower substrate 202, respectively. In addition, a plurality of wafer pads 207a on the active surface 206a of the wafer 206 are electrically connected to a plurality of pads 205b under the upper substrate 204 through a plurality of metal bumps 2 1 2 respectively. Preferably, the semiconductor wafer 206 is coated in a package body 2 1 4 to protect the semiconductor wafer 206 and its electrical connection with the lower substrate 202 and the upper substrate 204. Alternatively, the semiconductor wafer 206 can be covered in an underfill (Hll) to achieve the same protection purpose. In this embodiment, since the semiconductor wafer 206 is electrically connected to the bonding pad 203a on the lower substrate 202 and the bonding pad under the upper substrate 204 through the bonding wires 2 10 and the metal bumps 2 12 respectively. Pad 205b, and since the contact pad 1247443 203a and the pad 205b are respectively electrically connected to the pad 203b under the lower substrate 202 and the pad 205a on the upper substrate 204, the semiconductor wafer 206 It can be electrically connected to other external circuits through the pads 203b under the lower substrate 200 and the pads 205a on the upper substrate 204. In another embodiment of the present invention, the circuits on the lower substrate 202 and the upper substrate 204 can also be electrically connected to each other by a plurality of metal bumps 2 丨 6, such as the semiconductor package structure 25 in the figure. As shown. According to the semiconductor package structure 20G of the present invention, it can be electrically connected to other external circuit through the lower substrate 202 and the upper substrate 204 by the pads 203b and 205a, respectively. Sexual connection characteristics. Furthermore, because the semiconductor package structure 2000 has bidirectional electrical connection characteristics, it is quite suitable for a system-level package structure (sip). Please refer to FIG. 7, which is a schematic diagram of a system-level package structure (Sip) 3aG achieved using the semiconductor package structure 2000 of FIG. 4. In the system-level package structure 300, a semiconductor device 208 such as: a flip-up chip (fUp AiP) or a chip-scale package structure (chip scale) is disposed on the upper substrate through a reflow process. The upper surface 204 of the 204 is electrically connected to the socket on the upper substrate 2 through a plurality of metal bumps 218. It should be understood that the semiconductor device 2G8 is not limited to a flip-chip or wafer-scale package structure, and # can also be any other type of semiconductor package structure or device. In addition, a plurality of solder balls or metal bumps & 220 are arranged on the pads on the lower surface of the lower substrate 200 for electrical connection to an external circuit such as a printed circuit board (not shown) )on. Compared to the conventional system-level package structure 00 (as shown in FIG. 3) of the semiconductor wafer 106, 1244743, the semiconductor wafer 206 of the present invention has a plurality of wafer pads 207a electrically connected to the semiconductor wafer 106. The upper substrate 204 is designed without any openings on the upper substrate 204, so the semiconductor wafer 206 can provide more I / O numbers (pads 205a, 205b) and shorter conductive paths. Used to electrically connect with other semiconductor components or chips. 8 to 12 are diagrams for explaining a method of manufacturing the semiconductor package structure 200 according to the present invention. # Now refer to FIG. 8, the lower substrate 202 is provided first. The upper substrate 202a of the lower substrate 202 is provided with a plurality of pads 203a, and the lower surface 202b is provided with a plurality of pads. The pads 203b are electrically connected to the plurality of pads 203a. Referring now to FIG. 9, a semiconductor wafer 206 is disposed on the upper surface 202a of the lower substrate 202. The active surface 206a of the semiconductor wafer 206 has a plurality of wafer pads 207a and a plurality of wafer pads 207b. The wafer pads 207a further include a plurality of solder balls or metal bumps. A block 212 is planted thereon. In addition, the plurality of wafer pads 207b are arranged around the plurality of wafer pads 207a, as shown in FIG. Now referring to FIG. 10, a plurality of bonding wires 210 are respectively formed between the plurality of wafer pads 207b and the plurality of pads 203a by wire bonding technology, so that the semiconductor wafer 206 It can be electrically connected to the lower substrate 200. Referring now to FIG. 11, an upper substrate 204 is provided and disposed on the semiconductor wafer 206. The upper surface 204a of the upper substrate 204 is provided with a plurality of pads 205a, and the lower surface 204b is provided with a plurality of pads 205b 1244743 and is electrically connected to the plurality of pads 205a. The plurality of wafer pads 207a on the semiconductor wafer 206 are electrically connected to the plurality of pads 205b of the upper substrate 204 through the plurality of metal bumps 2 丨 2, so that the semiconductor wafer 2 06 series can Thereby, it is electrically connected to the upper substrate 204. Please refer to FIG. 12. A plastic mold 2 丨 8 can be bonded between the upper substrate 204 and the lower substrate 202. After that, a mold compound can be injected through the injection channel 218a of a mold 218 between the upper substrate 204 and the lower substrate 202 to form a package body 214. It is used to protect the electrical connection between the semiconductor wafer 206 and its lower substrate 202 and upper semiconductor substrate 204, as shown in FIG. 4. Alternatively, in another alternative embodiment, an underfill may be injected between the upper substrate 204 and the lower substrate 202 to achieve the same protection purpose. 'FIGS. 8_1 () and 13_14 are used to explain a method of manufacturing the semiconductor package structure 250 according to the present invention. With reference to FIG. 13, Lu Xianzheng, a package body 214 can be formed on the lower substrate 202 by a plastic mold to cover and protect the semiconductor wafer 206 and the semiconductor wafer 206 and the lower substrate 202. Electrical connection. Referring to FIG. 14, the top portion 214 a of the sealing compound 214 is ground by a mechanical grinder (not shown), so that the plurality of metal bumps 212 can be exposed on the top portion 214 a of the sealing compound 214. Next, a plurality of solder balls or metal bumps 216 are disposed on the upper surface 202a of the lower substrate 202 for electrically connecting to other circuit contacts or pads on the lower substrate 202 (not shown). Thus, the method for forming the sealant 214 12 1244743 between the upper substrate 204 and the lower substrate 202 in FIGS. 13 and 14 can also be applied to the semiconductor package structure 200. Finally, as shown in FIG. 6, an upper substrate 204 is provided and disposed on the sealing body 214. The upper surface 204a of the upper substrate 204 is provided with a plurality of pads 205a, and the lower surface 204b is provided with a plurality of pads 205b and is electrically connected to the plurality of pads 205a. The plurality of wafer pads 207a on the semiconductor wafer 206 are connected to the plurality of pads 205b of the upper substrate 204 by a plurality of metal bumps 212 exposed on the top 21 乜 of the sealing compound 214. The electrical connection enables the semiconductor wafer 206 to be electrically connected to the upper substrate 204 by this. At the same time, the lower surface of the upper substrate 204 is different. There are also dagger circuit contacts or pads (not shown) for electrically connecting to the plurality of metal bumps 216, so that the circuits on the upper substrate 204 and the lower substrate 202 can be used to thereby Electrically connected to each other. In order to be able to provide an integrated electronic module In summary, the semiconductor package structure according to the present invention has an upper and lower substrate: it is used to provide a bidirectional electrical connection. In particular, the semiconductor package structure is in a system-level package structure (System &paekage; M). Although the present invention has been disclosed with the foregoing examples-^ 〇 Μ ^, it is not intended to limit the present invention, any familiarity For this artist, ^ ^ _.,. ^ Without departing from the spirit and scope of the present invention, * can make various changes to repair the view of m P # t Φ β ϋί ~ >. The scope of protection of the present invention shall be determined by the scope of the attached patent application. [Brief description of the drawings] Figures 1 and 2 are schematic diagrams of the first array package structure. Ke Technology t two different types of ball grids 13 1244743 Schematic diagram 3 is a general diagram of the conventional system-level package structure. FIG. 4 is A to A. According to a semiconductor package structure according to an embodiment of the present invention, FIG. 5 is A # 1 to the semiconductor wafer in FIG. 4 is not intended. Schematic diagram of the configuration of the wafer pad is a semiconductor package structure according to another embodiment of the present invention
弟7圖传jit λ» . κ 示音圖。乂據本發明一實施例之系統級封裝構造 之 弟8圖牵策1 , ^ 乐12圖係用以說明根據本發明一實施例之半 封裒構造的製造方法。 第13圖至莖^ 乂 圖係用以說明根據本發明另一實施例之 、、體封裝構造的製造方法。 、 【圖號說明】Brother 7 Picture Biography jit λ ». According to an example of the system-level package structure according to an embodiment of the present invention, FIG. 8 and FIG. 12 are used to explain a method for manufacturing a semi-enclosed structure according to an embodiment of the present invention. 13 to ^ ^ are diagrams for explaining a method for manufacturing a body package structure according to another embodiment of the present invention. [Illustration of drawing number]
10球格陣列封裝構造 12 半導體晶片 14 錫球 1〇2底座基板 l〇4a 開口 106第一半導體晶片 112第一接墊 200半導體封叢構造 11半導體晶片 13 基板 1 〇 〇系統級封裝構造 104中介基板 105焊線 108第二半導體晶片 114第二接墊 2〇2下基板 1244743 202a上表面 202b 下表面 203a接墊 203b 接墊 204上基板 204a 上表面 204b下表面 205a 接墊 205b接墊 206 半導體晶片 206a主動表面 207a 晶片接墊 207b晶片接墊 208 半導體元件 2 1 0焊線 212 金屬凸塊 214封膠體 216 金屬凸塊 2 1 8模具 218a 注膠道 1510 ball grid array package structure 12 semiconductor wafer 14 solder ball 102 base substrate 104a opening 106 first semiconductor wafer 112 first pad 200 semiconductor package structure 11 semiconductor wafer 13 substrate 100 system-level package structure 104 intermediary Substrate 105 Welding wire 108 Second semiconductor wafer 114 Second pad 202 Lower substrate 1247443 202a upper surface 202b lower surface 203a pad 203b pad 204 upper substrate 204a upper surface 204b lower surface 205a pad 205b pad 206 semiconductor wafer 206a Active surface 207a Wafer pad 207b Wafer pad 208 Semiconductor component 2 1 0 Welding wire 212 Metal bump 214 Sealant 216 Metal bump 2 1 8 Mold 218a Injection channel 15