TWI244201B - N-P butting connections on SOI substrates - Google Patents

Abstract

An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Description

1244201 发明 Description of the invention: [Technical field to which the invention belongs] This month is related to the field of integrated circuits formed on a substrate of silicon on an insulating layer (Can VII; so). [Previous technology] The parasitic phenomenon related to the thin film silicon layer formed by i and Wangdong device on it has been recognized for many years that silicon provides better performance on the insulating substrate. The silicon substrate circuit can be laid out in the same way as normal silicon substrate circuits. However, as will be explained later in this application, some benefits can be gained by designing such circuits with silicon on an insulating layer. First, reviewing a current circuit connection and its application in a static random access memory (SRAM) cell can help to understand the specific embodiments of the present invention described below. Figure 1 shows 7F-a typical connection, from the drain region 15 of a p-channel transistor to the drain terminal 14 of an n-channel transistor. It should be understood first that the n-channel transistor is formed in a -p-type well, and the p-channel transistor is formed in a n-type well 12. This configuration is suitable for a non-silicon substrate. The self-aligned silicide layer on the regions 14 and 15 includes a via, which allows the regions 14 and 15 to be connected. Generally speaking, a field oxide or an oxygen-filled HZ trench is formed on the oxide insulating structure 13. This oxide separated area is called well 12 and area 15 and well 1. It should be understood that without the insulation provided by thorium oxide, a current path will exist between area 14 and well 12, as shown by arrow 2, and area 15 and Between wells 11, as shown by arrow 22. The graph structure is often used in static random access memory cells (cross-coupled inverters forming a pair of 87535 1244201 stabilization circuits are used here). In Figure 2, the connection of Figure 1 is used twice, as shown by the dashed lines 22 and 24. SUMMARY OF THE INVENTION The present invention discloses a connection formed between a silicon type and a p-type (source / drain region) in a silicon-on-insulator (SOI) substrate. Certain specific details will be provided in the following description. In order to have a complete understanding of the present invention. Those skilled in the art should clearly know that in the absence of these specific details, she can still implement the present invention. In other examples, the well-known processing steps have not been described in detail So as not to cause unnecessary confusion to the present invention, reference is first made to FIG. 3, which illustrates a connection according to a specific embodiment of the present invention. The connection is made of a silicon on an insulating substrate. The substrates have been known in the prior art It is usually formed by a single crystal substrate (such as the substrate 30 in FIG. 3). A relatively high-quality single crystal silicon layer 35 is formed on the substrate, and an intermediate oxide layer 31 is placed on a relatively thick substrate. Between the substrate body 30 and the thin film layer%. Generally, the buried oxide layer 31 of FIG. 3 is a relatively high-quality oxide layer grown from the substrate as described above.

πarm. A further technology is to form a buried oxide layer 31 while implanting oxygen ions into a single crystal silicon substrate while leaving a single crystal silicon layer on the layer 31. For the present invention, a type region 33 is directly adjacent to a P + -type region 32, as shown in FIG. 3 as 87535 1244201. The n + -type region may be a source or drain region of a ^ -channel transistor and the p + -type region 32 may be a source or drain region of a p-channel transistor. Regions 32 and 33, along with the formation of their individual field effect transistors, are formed using a standard self-alignment procedure, which will be described. In a circuit application described below, region 33 is the non-polar region of an n-channel transistor in an inverter, and p + region 32 is the drain region of a p-channel transistor in an inverter. The inverter is part of a SRAM cell and is therefore cross-coupled with another inverter to form a bistable circuit, which will be described with reference to FIGS. 4 and 5. A self-aligned silicide layer 34 extends from the upper surface of the region 33 so as to continuously cover the upper surface of the region 32. This layer provides a conducting path between regions 32 and 33. This layer 34 is a self-aligned silicide layer formed of, for example, silicon and titanium or nickel, or other metals. [Embodiment] Comparing the structures of FIG. 3 and FIG. 1, it can be seen that the source / drain regions are close to each other. This structure reduces the area of the substrate required for connection. In addition, the connection is simpler. No through hole is required, as shown in FIG. 1, which is used to connect the area to the metal 20. In addition, the metal layer 20 is not needed for the connection of FIG. 3 because the self-aligned silicide layer 34 performs this function. The connection of FIG. 3 is used to reduce the layout area required for the SRAM cell of FIG. 2. Figure 4 shows a SRAM cell that includes alternating and coupled inverters to form a bistable circuit and a pair of pass gate transistors (which couple the bistable circuit to the bit line). Each inverter includes a field effect transistor connected in series with a p-type channel and an n-type channel. 1244201 85 was completed before formation). ) Now use another mask + _ jjy ^, w ... to form a photoresist layer 90 to cover the area ⑽ gate; b 83 and 柘 F 桄, ^ ^ 丨 邻接 which are adjacent to the area 88 and the substrate E domain. A P-type dopant such as boron;: A is formed in the silicon layer 81'-source or drain region 91, and the JL electrode and the spacer 86 are aligned. Fig. 7 shows that the region 88 is in contact with the region%, that is, it is adjacent or adjacent, and there is no undoped region in the middle. -Next, as shown in FIG. 8, after removing the photoresist 90, use Ruqin or Lu to form a stone evening chemical layer 95. This layer is self-aligned 'because it is shaped only on the fragment <. As mentioned, this layer is called a salidde because it is a self-aligning silicide. Since this layer 95 is formed only on the stone eve, it is not formed on the spacers adjacent to the gates 83 and 84, and thus the gates and the source / drain regions are not short-circuited. As shown in Figure 8, this layer is interconnected with regions 88 and 91. Thus, 'a connection between two regions of opposite conductivity type has been described' in which the regions are contiguous, and a covering self-aligned silicide layer interconnects the regions. This connection is particularly useful for SRAM cells. [Schematic description] Figure 1 is a cross-sectional front view of a silicon substrate, showing a source / dead region of a transistor having a first conductivity type and a source of another transistor having an opposite conductivity type The connection between the pole / drain regions. FIG. 2 is a prior art layout of a SRAM cell using the connection of FIG. 1. FIG. 3 is a specific embodiment of the present invention, showing the difference between the source / drain of one transistor having a first conductivity type and the source / drain of another transistor having an opposite conductivity type.一 连接。 One connection. 87535 -11-1244201 Figure 4 shows the connection of Figure 3 used in the layout of one of the six transistor SRAM cells. The solid member shows the connection of Figure 3 used in the other / larger version of the acupoint SRAM cell. FIG. 6 is a cross-sectional front view of a silicon substrate on an insulating layer, in which a first impurity replacement region is formed. Figure 7 shows the substrate of TF Figure 6 after an additional masking step and an additional doping step. "Fig. 8 shows the situation after the substrate of Fig. 7 is formed with a self-aligned petrified layer. [Illustration of Representative Symbols of the Drawings] 10 Non-silicon in the insulating substrate 11 P-type well 12 η-type well 13 Oxide insulation structure Terminal / region 15 > and region 20 metal wire 21 arrow 22 arrow 22, 23, 24 dash line 30 substrate / substrate body 31 intermediate oxide layer 32 p + type region 33 η + type region 87535 1244201 34 self-aligned silicide layer 35 Relatively high-quality monocrystalline silicon layer / thin film layer 40 Common source region 41, 42 Polycrystalline gate structure 42 Silicon structure 45 P + type region 46 P + type region 47 region 48, 49 n + type drain region 50 area 50,51 metal member 52 ground line 53, 54 n + type area 55, 56 contact 57, 58 bit line 60 power line 61 gate structure 65 n + type source area 66 gate 71 gate 72 gate ( (Character line) 75 non-polar area 76, 79, 80 area 80 5th substrate 87535 -13- polycrystalline ♦ buried electrode oxide layer single crystal silicon layer gate polycrystalline broken gate sidewall spacer spacer photoresist layer source Source or drain of photoresist layer Region silicide layers -14-

Claims (1)

I244 ^ Qil24472 Patent Application Chinese Application for Patent Scope Replacement (July 1994) and the year of July 7th (Revision) (Original) Original, patent application scope: ~~ 1. An integrated circuit, which contains · · /…, There is Shi Xizao, and the surface of the silicon-on-insulator (SOI) contains active devices; at least two of the #active devices are field effect transistors, and each device is formed in the chip A source and drain region of the opposite conductivity type on the surface of the insulating layer, wherein the first transistor region is adjacent to a region of the second transistor; and a self-aligned silicide is used to provide a dielectric A conductive path between the adjacent regions of the first and second transistors, which extends from the face of the region of the first transistor to an upper surface of the region of the second transistor, and only contacts A metal member adjacent to one of the P-type and n-type regions. 2. If the integrated circuit of item i in the patent application scope, the adjacent regions in # are a P-type drain region and an n-type non-polar region. 3. The integrated circuit of item 丨 in the scope of application for a patent, wherein the insulation system is a sulphur dioxide. 4. The integrated circuit of item 2 in the scope of the patent application, wherein the insulation system is a sulphur dioxide. 5. The integrated circuit of item 1 in the scope of patent application, wherein the self-aligned silicide is formed by using titanium. 6. The integrated circuit of item 4 of the patent application, wherein the self-aligned silicide is formed of nickel. 7. A circuit formed on a silicon-on-insulator layer (SOI) substrate, comprising: a first transistor having a source formed on the silicon-on-insulator layer 1244221 having a source of a first conductivity type And drain regions; a first transistor having a source and drain region having a second conductivity type formed in the silicon in the insulating layer substrate; and 8. 9. 10. 11. Μ * The source and the non-polar region of the 5th Temple of Sun and the Sun ^ _ and one of the source and drain regions of the first Thai body are adjacent to each other through a self-aligned silicide layer for providing A conductive path between the two contact regions of the first and second transistors, which extends from an upper surface of the region of the first transistor to an upper surface of the region of the second transistor; And a metal member that contacts only one of the adjacent P-type and n-type regions. For example, the circuit of the seventh scope of the patent application, wherein these types of drain regions and -n-type drain regions. Up The circuit of item 8 in the patent fc of Shenyang Patent, in which the insulation system is stone dioxide. For the circuit in the patent application No. 9, the self-aligned silicide is nickel or titanium. An integrated circuit includes: a silicon-on-insulator substrate; a first and a second inverter formed on the substrate, which are cross-coupled to form a bistable circuit; and each inverter includes One of the 1) -type channels and -n-channel transistors connected in series, so one in each inverter? A type region and an n-type region are adjacent to each other through: a continuous self-aligning layer, the self-aligned fragmentation layer is used to provide a conductive channel between the adjacent p-type and n-type regions, which The phaser extends from an upper surface of the p-type region to the upper surface of the mouth-shaped region; and a metal 87535 1244201 that contacts only one of the adjacent p-type and n-type regions is called 仵. Wherein the silicide layer includes where the silicon is in an insulating layer and where the bistable circuit is 12. For example, the integrated circuit of the U-item in the patent application, Cin or Ni. 13. For the integrated circuit substrate of the integrated circuit substrate of item u in the patent application, the silicon dioxide of the insulation system. For example, the integrated circuit of item 13 of the scope of the patent application is incorporated into a six-transistor static random access memory unit. 15. A method of manufacturing an integrated circuit, which includes: forming a first and a second spaced apart A gate, which is insulated from and formed on a silicon-on-insulator (SOI) substrate; a first conductivity type, one of which is adjacent to one of the gates, is formed in the silicon A doped region; doped into a first impurity region of a second conductivity type adjacent to another gate, the first and second regions being adjacent to each other; and formed on an upper surface of the doped regions A continuous self-aligned silicide layer interconnecting the doped regions and forming a metal member on only one of the doped regions. / ΐ6. The method of claim 15 in which the dopant ion implantation is formed. / Straw field 17 .: The method of applying for item 15 of the patent scope, wherein the petrified layer is titanium 18. The method of applying for item 15 of the patent scope, wherein the silicidation is formed. Actinic nickel 57535