TWI244175B - Semiconductor package having stacked chip and a method for fabricating - Google Patents

Abstract

A semiconductor package having stacked chip and a method for fabricating the same are proposed. A semiconductor package includes a chip carrier having a carrier surface. At least two stacked chips are mounted on the carrier surface of the chip carrier. A spacer is further interposed between the two chips and formed with a plurality of supporting portions for supporting the peripheral portion of the upper chip. The chip carrier is electrically connected to the chip via a plurality of bonding wire. A resin body is formed to encapsulate the chip carrier, chips and wires. By means of the supporting portions of the spacer, the peripheral portion of upper chip can be prevented from crack during wire bonding process.

Description

1244175 V. Description of the invention α) [Technical field to which the invention belongs] A semiconductor package with a stacked wafer and a manufacturing method thereof, particularly a semiconductor package that can enhance the peripheral strength of the stacked wafer, and a manufacturing method thereof. [Previous technology] With the vigorous development of the electronics industry, electronic products have gradually moved into a multi-functional, high-performance R & D direction to meet the packaging requirements of semiconductor packages with high integration and miniaturization.

And in order to improve the performance and capacity of a single semiconductor package, in order to meet the trend of miniaturization, large capacity and high speed of electronic products, it is known that most semiconductor modules are multi-chip module (Mul ti Chip Module; MCM) In the form of this package, this package can also reduce the overall package size and improve electrical functions, and has become a mainstream package. It is a semiconductor package with at least two semiconductor wafers on a single package (semiconductor). 〇r chip), and each wafer and the chip carrier are directly stacked vertically. For the structure of the conventional stacked wafer, since the periphery of the wafer must be provided with a bonding pad for electrically connecting the wafer carrier, the area of the upper wafer must be smaller than that of the lower wafer. The structure of the structure is as if it is gold-plated, and the disadvantage of this structure is that it cannot stack wafers of the same size, which limits the type of wafers stacked. In order to improve the lack of a pyramid stacking structure, a spacer is sandwiched between two stacked wafers, so that the upper and lower wafers can be separated by the spacers, so that the upper and lower layers are separated. The wafer surface ^ can be designed to be the same size, so that the solder g of the wafer on the lower layer is exposed.

1244175 V. Description of the invention (2) ----- To be used with f electrical connection, and this type of stacked chip package structure has been found in the conventional technology of US Patent No. 6,5 9 3, 6 6 2.

A diagram of FIG. 6A and FIG. 6B is a cross-sectional view of the package disclosed in US Patent No. 6,5 9 3, 6 62, which is a wafer carrier 21 (carrierXh is connected to a first wafer 22) (first die), a spacer 23 (叩 3 ^ 1 ^) having a volume smaller than that of the first wafer 22 is placed on the upper surface 211 of the first wafer 22 opposite to the wafer carrier 21, and the spacer 23 A second wafer 2 4 (second di e) with a volume equivalent to the first wafer 22 is placed on the surface 2 2 1 of the first wafer 22, and the area of the spacer 23 is smaller than that of the first wafer 22. And the second wafer 24, and a plurality of bonding pads 2 2 2, 241 (bonding pads) are provided on the first wafer 22 and the second, and a corresponding bonding pad 212 (finger) is provided on the wafer carrier 21 ), And a plurality of bonding wires 25 are connected to the bonding pads 2 2 2, 2 4 1 and the bonding pads 2 1 2 so that the first chip 2 2 and the second chip 2 4 pass through the I main line 2 5 to the chip The carrier 21 is electrically connected; if the wafer carrier 21 is a substrate, a solder ball 26 is provided on the bottom surface of the wafer carrier 21 for connection with an external circuit.

However, when the second wafer 24 is placed on the spacer 23, since the pad 2 4 1 as an electrical connection point is provided around the second wafer 24, the bonding wire 2 5 When electrical connection is performed, the periphery of the second wafer 2 4 is a cantilever beam (cant i 1 ever beam) force type in material mechanics, and the characteristic of the cantilever fork force is the fixed end support and another When the free end is subjected to a force, the deformation amount δ = WL3 / 3EI when the force is applied, that is, when the subsequent wire bonding operation is performed, the position where the pad 2 2 1 is provided on the second wafer 2 4 will have no support, At this time, if the force of the wire is too large, the flexibility (def 1 ecti 〇n) will be deformed.

17841 Shi Xipin.ptd Page 10 1244175 V. Description of the invention (3) The second crystal caused by the big one caused structural damage. Therefore, the problem that the wafer needs to be urgently solved when the wafer of the existing layer has the maximum line operation. [Summary of the Invention] The semiconductor seal of the main edge strength of the present invention The semiconductor seal of the other edge strength of the present invention To avoid causing duplicates of the present invention, it can be used to increase the wafer. Another effect of the present invention on the underlying wafer is to achieve the above and the semiconductor package carrier of the wafer; at least two spacers of the wafer carrier, and the space between It is electrically connected to the wafer carrier. The purpose of the package is the purpose of the package. The purpose of the wafer is the peripheral purpose of the welding wire. The other parts are stacked. The surface-mounting spacer and the chip are being manufactured. For the purpose of lifting the position, the structure is on the wafer; to the periphery of the wafer carrier and the wafer 24, the peripheral edges of the wafer are cracked, and how to take into account each of the stacked package designs. Circuit function and the number of contacts, and at the same time can avoid the occurrence of cracking, indeed this research and development field is Reinforced Stacked Wafer Periphery Provides a method to enhance stacked wafer peripherals. Provides a simple supporting stacked crystal package structure. Provides a manufacturing method without changing the original packaging process. Provided is a semiconductor package that can support the upper wafer. The invention provides a stacking type comprising: a wafer with a bearing surface, and the stacked wafers are connected to each other and arranged between two adjacent wafers, and a plurality of supporting portions are extended; Wire; and encapsulant gel formed on the spacer and bonding wire.

17841 Shi Xipin.ptd Page 11 1244175 V. Description of the invention (4) The manufacturing method of the semiconductor package with stacked wafers according to the present invention includes the following steps: preparing a wafer carrier with a bearing surface; at least one wafer It is placed on the bearing surface of the wafer carrier; the wafer carrier and the wafer are electrically connected by a bonding wire; at least one spacer is prepared, and a plurality of support portions are extended around the periphery of the spacer to connect the spacer Placed on the surface where the wafer is not in contact with the wafer carrier; preparing at least another wafer, and placed the other wafer on the other surface where the spacer is not placed, and supporting the periphery of the spacer It rests on the periphery of the second wafer; electrically connects the wafer carrier and another wafer with a bonding wire; and forms an encapsulating gel on the wafer carrier to cover the wafer, the spacer and the bonding wire. The present invention is to support the wafers stacked on the upper side by the supporting portions formed on the periphery of the spacer, so that the supporting portions are supported under the peripheral edge of the upper layer wafer to be in a stressed state of a simple beam (simp 1 ebeam). This type of force is supported at both ends and the middle part is stressed. At this time, the amount of deformation will be δ = WL 3/4 8 EI. In this way, compared with the conventional cantilever beam, the deformation is Amount 6 = WL3 / 3EI. The strength of this simply supported beam will be increased to 16 times, and the strength of the peripheral edges of the stacked wafers will be strengthened to prevent the wafers from cracking during wire bonding operations. Moreover, the spacer only has a plurality of supporting portions on its periphery, which does not change the packaging process. Therefore, the strength of the wafer periphery can be improved without changing the packaging process, and the increase in the number of process changes can be eliminated. manufacturing cost. In addition, when the support portions are formed at the corner edges of the spacer, the structure of the support portions can also be prevented from affecting the bonding wire position of the underlying wafer, and

17841 Shi Xipin.ptd Page 12 1244175 V. Description of the invention (5) There is no need to change the design position of the wire pad on the wafer, so as to avoid the increased manufacturing cost caused by the design change. [Embodiment] The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention in any way. The present invention is that a plurality of wafers are sequentially stacked on a chip carrier, and a spacer is sandwiched between two stacked wafers, and a plurality of support portions are formed at the periphery of the spacer. By supporting the supporting portion below the peripheral edge of the upper layer wafer, the strength of the peripheral edge of the upper layer wafer is strengthened, which will be described in detail through the following embodiments. Please refer to FIG. 1A and FIG. 1B. The stacked wafer semiconductor package 1 of the present invention includes a wafer carrier 10 for electrically connecting to an external device. The wafer carrier 10 has a carrier Surface 1 0 1; at least two first wafers 11 and second wafers 1 Γ stacked on each other are connected to the bearing surface 1 0 1 of the wafer carrier 10; at least one is sandwiched between two stacked first A spacer 12 between the second and second wafers 1 1 and 1 1 ', and the corner edge of the spacer 12 is extended to form four radial support portions 1 2 1; a plurality of support portions are used for electrical connection Wafer carrier 10 and the bonding wires of the first and second wafers 1 1 and 1 1 ′

17841 石 夕 品 .ptd Page 13 1244175 V. Description of the invention (6) 1 3; and a packaging colloid 14 which is formed on the wafer carrier 10 and covers the first and second parts The wafers 11, 1 1 ′, the spacers 12 and the bonding wires 13. The manufacturing method of the aforementioned stacked wafer semiconductor package 1 further includes: preparing a wafer carrier 10 having a carrier surface 10, and adhering at least one first wafer on the carrier surface 10 of the wafer carrier 10. 1 1; Next, the above-mentioned wafer carrier 10 and the first wafer 1 1 are electrically connected by bonding wires 1 3 according to the layout design of the circuit; a spacer 12 is then placed above the first wafer 11 and the interval The corner edge of the piece 12 is extended to form four radial supporting portions 1 2 1. Next, at least one second wafer 1 1 ′ is prepared, and the second wafer 1 1 ′ is placed on the spacer 1. 2 on the other surface of the first wafer 1 1 and supporting the corner 12 of the spacer 12 below the corner of the second wafer 1 1 '; A bonding wire 13 is used to electrically connect the wafer carrier 10 and the second wafer 1 1 ′. Finally, an encapsulant 14 is formed on the wafer carrier 10 to cover the first and second wafers 1 1. , 1 Γ, spacers 12 and bonding wires 1 3, the packaging process is completed. The area of the aforementioned spacer 12 is slightly smaller than that of the second wafer 1 Γ, so that the support portions 1 2 1 extending from the four corner edges of the spacer 12 can be located at the four corners of the second wafer 1 1 ′. Below the edge, the corner edge of the second wafer 1 1 ′ can be supported, so that the part of the second wafer 1 1 ′ extending out of the spacer 12 becomes a stressed state of the simply supported beam, and the deformation amount will be 5 = WL3 / 48EI, as shown in Figure 2A, so that its strength can be increased (compared to the conventional cantilever force state, its deformation 5 = WL3 / 3EI, as shown in Figure 2B), avoid When the electrical connection is made with the bonding wire 1 3, the upper second chip 1 1 '

17841 Silicon. Ptd Page 14 1244175 V. Description of the invention (7) When it is stressed, it will crack and damage. The area dimensions of the first and second wafers 11, 11 may be the same or different, that is, the size of the second wafer 11 of the upper layer may be larger than, equal to, or smaller than the area of the first wafer 11 of the lower layer. Dimensions. At the same time, the spacer 12 may be an insulating plate (in su 1 ati on boar d), or made of metal materials such as copper, aluminum or the like. In the other drawings 1A and 1B, a plurality of bonding pads 102 (finger) are provided above the wafer carrier 10, and the functions of the first and second wafers 101 and 101 are: A plurality of corresponding fresh pads 1 1 1 and ill (bonding pad) 'are respectively provided on the surface, so that the wafer carrier and the first and second pieces of film Π, 11 can be electrically connected with each other by a bonding wire 13. The spacer 12 and the supporting portion 1 2 1 only need to avoid the positions where the pads u and 11 Γ of the first and second wafers n and ij are disposed. In addition, the distribution number and position of each of the aforementioned support portions i 2 1 are not limited by the present invention, and its position is not limited to the corner edge of the spacer 12, but is also formed on the edge of the edge spacer 12. As shown in FIG. 3A and FIG. 3β, the embodiment of the j 1 spacer is also capable of achieving the effect of the branch of the present invention t 10 series of stacked chip semiconductor packages, and the chip carrier card is shown in the third design form. And you have to be accustomed—to know the wafer carrier, let the lead frame shown above, 10, (lead fame), the lead frame 1 (1 V, Japanese film holder 10a), the first, The second chip 11, the transfer line, and the interval 12 are stuck on the chip holder i0a, and then electrically connected with the channel T, and then the package is completed with the sealing gel 14. It is electrically connected to the exterior by the lead frame 10 ', which is the present invention.

1244175 V. Description of the invention (8) Specific embodiments. As shown in FIG. 4B, it is revealed that the wafer carrier 10 is a printed circuit board 10 '' (printed circuit board), and the printed circuit board includes a build-up substrate or a stamper. A laminated substrate (Laminated Substrate) on the printed circuit board ι ″ ″ has at least one wafer preset area 10 ′ ″ and a plurality of solder balls 1 Ob are implanted on the bottom surface of the printed circuit board 〇π. , Equivalent to the first and second wafers 丨, ii described in the previous paragraph, and the spacers 12 sandwiched therebetween are glued to the wafer preset area 丨 0a,, and then electrically connected with bonding wires 13 The second embodiment is the second embodiment of the present invention. ~ This invention is referred to the fifth embodiment. Figure _ ,, ... 2 j: Firstly mount the first wafer " on the top of the first wafer, and use the bonding wire 13 to electrically connect the wafer carrier 10 and the first wafer u to the first wafer ii above the first wafer ii. The spacer 1 2 and the first spacer 1 and the second spacer 12 are sequentially stacked on top of the first spacer 丨 2, and then The bonding wire 1 3 is electrically connected to the first and second pieces of wafer W, and then is electrically connected to the wafer carrier 13 on the second spacer 12 and Guanghui line 13: Take the third one, and then seal the gel. 14 completes the packaging, which is the example of the present invention. The wafer carrier 10 is the same as the second tool 10 or the printed circuit board 10 ", which can also be implemented. Dry lead frame The above embodiments are merely illustrative to illustrate the principle of the present invention and are used to limit the present invention. Anyone who is familiar with this :: To…… the spirit and scope of the Ming, to the above embodiment ::::;

17841 Silicon products · ptd page 16 1244175 5. Description of the invention (9). Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

1BB 17841 Silicon Product.ptd Page 17 1244175 Brief Description of Drawings [Simplified Description of Drawings] Figure 1A is a cross-sectional view of a semiconductor package with stacked wafers and a method for manufacturing the same; Figure 1B is a view of the present invention Top view of a semiconductor package with stacked wafers and its manufacturing method; Figure 2A is a schematic diagram of the stress state of a simply supported beam; Figure 2B is a schematic diagram of the stress state of a cantilever beam; Figure 3A is a diagram of the present invention. Top view of another implementation of a stacked semiconductor package and a spacer made therefrom; FIG. 3B is a top view of another implementation of a semiconductor package with a stacked wafer and a spacer made of the same; FIG. 4A FIG. 4B is a cross-sectional view of a semiconductor package with a stacked wafer of the present invention and a method for manufacturing the same using a lead frame; FIG. 4B is a cross-sectional view of a semiconductor package with a stacked wafer of the present invention and a method for manufacturing the same using a printed circuit board; Figure 6 is a cross-sectional view of a semiconductor package with stacked wafers and a method for manufacturing the same in a multi-chip stacked package according to the present invention; Figure 6A is disclosed in US Patent No. 6,5 9 3, 6 6 2 Cross-sectional view of a semiconductor package; FIG based and are 6 B over the semiconductor package is disclosed in the U.S. Patent of 6,5 3,6. 6 9 2 view. (Description of component symbols) 1 Semiconductor package 1 0, 2 1 Wafer carrier

17841 Silicon product.ptd Page 18 1244175 Brief description of the drawing 10, lead frame 10 " printed circuit board 101 bearing surface 102, 212 recording wire 10a, 10 aπ wafer holder 10 b, fresh ball η, 1 r chip m , 111 'pads 12, 12, spacers 121, support parts 13, 25 fresh line 14 package gel 211 upper surface 22 first wafer 221 surface 222, 241 pads 23 spacers 24 second two wafers 26 solder balls

17841 Shi Xipin.ptd Page 19

Claims (1)

1244175 VI. Scope of patent application 1. A semiconductor package with stacked wafers, comprising: a wafer carrier having a bearing surface; at least two wafers stacked on each other are connected to the bearing surface of the wafer carrier At least one spacer provided between the stacked wafers, and the peripheral edge of the spacer is extended with a plurality of supporting portions, so that the supporting portion is positioned just below the peripheral edge of the stacked wafer; A plurality of bonding wires are used to electrically connect the wafer and the wafer carrier; and a packaging gel is formed on the wafer carrier to cover the wafer, the spacer and the bonding wires. 2. The semiconductor package of claim 1, wherein the support portion is formed at a corner edge of the spacer. 3. The semiconductor package of claim 1, wherein the support portion is formed on an edge of the spacer. 4. The semiconductor package of claim 1, wherein each corner edge of the spacer is extended to form the supporting portion. 5. The semiconductor package of claim 1, wherein each edge of the spacer is extended with the supporting portion. 6. The semiconductor package of claim 1, wherein the chip carrier is a lead frame (1 e a d f r a m e). 7. The semiconductor package of claim 1, wherein the wafer carrier is a substrate (S u b s t r a t e). 8. The semiconductor package of item 7 in the scope of patent application, in which the substrate 11 II Ϊ 1 11 II 17841 silicon product. 1 0. If applying for the special stacking crystal 1 1. If applying for the special part is a 12. If applying for the special part is zinc 1 3. If applying for the special bearing part 1 4. If applying for the special role table 1 5. — Seed stacking steps: The preparation will be the top; a plurality of solder balls on the bottom surface are prepared by soldering a plurality of the pieces to be connected. In the semiconductor package according to claim 1, the area dimensions of the mutual wafers are the same. The semiconductor package according to the first item, wherein the area sizes of the mutual wafers are different. The semiconductor package of claim 1, wherein the spacer is an insulating plate. The semiconductor package of claim 1, wherein the spacer is made of one of the spacers, copper, and Ie materials. The semiconductor package of claim 1, wherein the wafer carrying surface is provided with a plurality of bonding wires f (f i n g e r). The semiconductor package of claim 1, wherein a plurality of bonding pads (b ο n d i n g p a d) are provided on the wafer surface. A method for manufacturing a semiconductor package of a stacked wafer includes the following wafer carrier, which has a carrier surface; at least one first wafer is connected to the carrier surface of the wafer carrier to electrically connect the wafer carrier and the first Wafer; at least one spacer, the periphery of which is extended to form a supporting portion; the spacer is placed on the first wafer and is not connected to the wafer bearing surface; at least another second wafer, and the second wafer is connected Put 17841 Shi Xipin.ptd Page 21 Sat 1244175 'The other part of the patent application for the spacer relative to the first wafer is located just below the periphery of the second wafer ", which is electrically connected from the bonding wire The wafer carrier is formed on the wafer carrier to form a sheet, a spacer, and a bonding wire. The body is covered with the Zhongming patent No. 1 $ semiconductor. The method of manufacturing the supporting body adjacent to the wound V = 5 is a method of manufacturing a package. A 17A out of M 糸 is formed at the corner edge of the spacer. Please enclose the semiconductor enveloping part of the patent range item 5 in the edge of the spacer. Each corner edge of the spacer for the semi-conductor of the patent range 15 of the patent application extends the shape m i9. Semiconductors with 15 items: = each edge of the spacer is extended a as in the scope of the patent application · Half of 15 items = support: sheet, carrier is-lead frame (lej = method '21. ^ 7 The semiconductor of the 15th scope of the patent The wafer carrier is a substrate (Substratt 22. For example: the green patent scope 帛 22 of the semiconductor 23: Ϊ: ΪΞ, each is located on the bottom of the tin ^-= = body The manufacturing method of the package, and the area size of the wafer is the same. 2 4 · If you apply for a patent], the above-mentioned _ should be stacked with each other, 25. If you apply for a patent; = not the same. Guodi's 15-item semiconductor package manufacturing method, which requires that: and the crystal therein, among which, among them. Among the middle. Among which the ball) among which 1244175 6. the scope of patent application The spacer is an insulation Board 2 6. As the scope of patent application No. 1 5 The method for manufacturing a semiconductor package, wherein the spacer is made of one of zinc, copper and aluminum materials. 27. The method for manufacturing a semiconductor package according to item 15 of the patent application scope, wherein the wafer carrier A plurality of bonding pads (finger) are provided on the bearing surface. 28. For example, the method for manufacturing a semiconductor package according to item 15 of the patent application scope, wherein a plurality of bonding pads (b ο nding pad) ο 17841 Shi Xipin.ptd Page 23