TWI244031B - Booting switch method for computer system having multiple processors - Google Patents

Abstract

A booting switch method for computer system having multiple processors utilizes a baseboard management controller to manage abnormal issue while booting a computer system having multiple processors. In accordance with the operating status of CPU in the computer system or of the BIOS stored in a ROM, an acceptable CPU or BIOS can be switched to boot up through a CPU switching step or a ROM switching step, so as to effectively improve the system stability.

Description

1244031 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for managing a boot abnormality of a multiprocessor computer system, and particularly to a CPU or ROM switching program through a BMC (Baseboard Management Controller) To manage abnormal boot problems. [Previous technology] In the computer system, based on the design concept of the High Available system, in order to maintain the system's continued operation without any manual operation to troubleshoot, it is necessary to have a backup system. This is a reprocessing. Processor (multiple processor) system. Reprocessing physical computer systems, such as servers (s e v e r), have multiple central processing units το (CPU), so they can improve overall processing performance and be used as a replacement when a designated CPU error occurs. — Generally speaking, the boot process of a multiprocessor computer system means that a single boot CPU (Boot strap Processor) provides the computing function 'responsible for processing the basic input and output system (B〗 0 s) instructions at boot, in order to Carry out computer system initialization and load the operating system (0s); of which, BI 0S is stored in the "Read Only Memory of Basic Input Output System" (BIOS ROM), and other (: 1) 1 ] Is defined as "application CPU" and is set to "wait state". § When the CPU cannot be turned on when using the boot, the existing method is to write a program to switch the CPU when booting in BI0S, and switch from boot (: 1) 11 to other applications. The switching mechanism is shown in Figure 1. Another possible problem is that β 丨 〇S has been switched to all 1244031

ask,. In order to solve the problem of B1 os anomaly, one or more backup read-only memories (backup ROM) are used as an alternative solution; switch the boot BI0s to the backup stored in the backup ROM, and continue to boot. The program's switching mechanism is shown in Figure 2. CPl ^ I tried, but still could not boot; this situation may be out of BI0s R, however, the disadvantage of the previous method is that special BIOS must be used to switch μ, or "read-only memory boot switch" (ROM β 〇〇ΐ Swap) The electronic circuit of BIOS ROM is very complicated, so it is really too cumbersome and not cost-effective. [Summary of the Invention] The technical problems to be solved by the present invention, such as writing BIOS, designing ROM switching, and other methods, are not compatible with cost-effectiveness and work requirements. In the conventional technology, the problem of the above-mentioned conventional technology is to change the abnormality of the booting abnormality. The present invention provides a method for switching on a multiprocessor, and uses a baseboard management controller BMC to manage, Judgment and execution of switching between CPU and BI0S when sweat + abnormality includes the following steps: Confirm a boot (Central Processing Unit) to switch the program through a MC (substrate management controller) and restart; restart: program failed At this time, λ includes the steps of performing a ROM (read-only memory) MC and restarting. Among them, the CPU switching process is performed by changing the program: switching between the machine CPU and at least one application CPU; furthermore, the ROM of the Reach machine ROM Through the BMC, the BI0S that executes the boot process is stored in an open BIOS. Boot BIOS and switch to one of the backup ROMs stored in at least one backup ROM.

Page 6 1244031 V. Description of the invention (3) The effect achieved by the present invention is that the BMC can manage the abnormal startup problem. The system B10S and ROM do not need to make additional designs, which can further improve system stability. [Embodiment] The present invention is a booting switching method for a multiprocessor computer system, which mainly uses a baseboard management controller (BMC) to manage the judgment and execution of CPU and BIOS switching during abnormal booting. BMC was originally applied to the intelligent platform management interface (I PM I), the interface between the management software of the control system and the platform management hardware, providing independent monitoring, event recording and recovery control functions, and can be used as system management software and intelligent platform The network gateway between the management platform IPMB (Intelligent Platform Management Bus) and the intelligent chassis management bus ICMB (Intelligent Chassis Management Bus) interface is used. The reason why the BMC can be used to manage system abnormality is because the system can obtain the system status information from the BMC through the "Low Pin Count (LPC) Interface". The present invention is another brand-new application field of the BMC. The following describes the processing method for managing the abnormal situation of booting through the BMC with reference to FIG. 3. The execution priority order is basically a CPU switch and a reboot. If it is not possible, a ROM switch and a reboot are performed. First, after the system power is turned on, confirm that the BMC has not received a boot message from the boot BIOS (step 11 〇): if it receives a boot message, it means

1244031

^ The system starts up normally (steps 丨 20). The BMC is powered by the system's backup power. Therefore, the BMC is ready before the system power is turned on. In this way, as soon as the system power is turned on, it can receive the operating status of the boot process from BIOs. Then 'disc recognizes that the CPU switching procedure and ROM switching procedure have not been completed (step 130). If the system has completed the cpu and r 0μ switching procedures but cannot boot, it means that all CPUs have errors and the system cannot boot. (Step丨 4〇), /, month b manual troubleshooting, such as replacing C p U. Next, confirm that the CPU switching procedure is not completed (step 50), and then execute the CPU switching procedure (step 160). The CPU switching procedure of step 160 includes two detailed processes; it is to change the state of all CPUs to change the BSPCPU (the so-called BSPCPU refers to the boot strap processor, which means to start the operation at the beginning of the boot.) The CPU, which is preset to boot iCPu; in the second and subsequent CPU switching procedures, it is the previous 2CPU boot) and is isolated from the (^ 1) bus (step 1 61), and then the BMC generates a CPU switch The signal and a restart signal to the BI 0S or backup BI 0S (step 16 2). After restarting, return to step 11 0 to confirm the power-on state. After the judgment in step 150, if the CPU switch has been performed, r 〇m Switch the program (step 170). This program is to switch on the BI 0 S in BI 0 SR 0 Μ from the BI 0 S in which the boot process will be executed, and switch to the backup BIOS in backup r 〇 μ, and The backup BIOS restarts; in detail, the BMC generates a ROM switching signal to a complex programmable logic device CPLD (Complex Programmable Logic Device) to switch to the backup ROM and generates a system restart signal to the backup BI OS. After booting, Back to step

1244031 V. Description of the invention (5) 11 0 Confirm the startup state. Please refer to FIG. 4 to illustrate the execution flow in the BMC when performing CPU switching, which can prove the feasibility of the present invention. SM 11 and SM I 2 are two "System Management Interrupts (SMI)" on the BMC. The SWAP status indicates the switching status. STBY_PGD, R0M_SWAP, STATE_CHANGE, SYS_PGD, CPU_SWAP, etc. are the functional parameters of the control program in the BMC. STBY_PGD is the standby power-on state, R0M_SWAP is the ROM switching state, STATE_CHANGE is the state transition, SYS_PGD is the system restart state, and CPU_SWAP is the CPU switching state. The CPU switching in the figure includes four states, which allows the BMC to know the number of CPUs to switch to. The execution content of each state is described as follows: (1) The execution content of the first state includes ... a. Set SM 11 to LOW (Low); b. Set SMI2 to HIGH; c. Set SWAP status to the second status; d. Set STATE —CHANGE to CHANGE. (2) The execution content of the second state includes ... a. Set SMI 1 to HIGH; b. Set SMI2 to LOW; c. Set SWAP state to the third state; d. Set STATE_CHANGE to CHANGE ° (3) the third state The execution contents include: a. Set SMI1 to LOW; b. Set SMI2 to LOW;

1244031 V. Description of the invention (6) c. Set SWAP state to the fourth state; d. Set STATE_CHANGE to CHANGE. (4) The execution content of the fourth state includes: a. Setting the SWAP state to the fourth state; b. Setting STATE_CHANGE to CHANGE ° Figure 5 illustrates the details of the present invention when using the BMC to perform ROM switching (R0M SWAP) The procedure can also be used to verify the feasibility of the present invention. Among them, B A C K U P R 0 Μ represents a backup ROM state. In the present invention, the backup r μ may be in a normal state or a backup state; ROMs witch represents a function parameter of a ROM switching state. With the CPU and ROM flow in Figures 4 and 5, the BMC can follow the flow in Figure 3 'to switch the CPU in Figure 4 when the boot is abnormal, and then perform the ROM switch in Figure 5 when it fails to boot. c. It is indeed feasible to manage abnormal situations during startup. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. Those skilled in the art will be able to modify and replace the ones based on the disclosure of the present invention based on the technical ideas of the present invention. Derivative creation. Therefore, all equal changes and modifications made without departing from the scope of the technical idea of the present invention should be covered in the patent application park of the present invention.

1244031 Brief description of the drawings. Figures 1 and 2 illustrate the booting switching mechanism of the multiprocessor system in the prior art. Figure 3 illustrates the booting switching mechanism of the multiprocessor system managed by the BMC of the present invention. Figure 4 illustrates the present invention. The CPU switching process for booting a multiprocessor system using a BMC; and FIG. 5 illustrates the ROM switching process for booting a multiprocessor system using a BMC according to the present invention. [Illustration of Symbols]

Step 1 10 The BMC has not received one of the booting BIOS boot messages. Step 1 2 0 The system is booting normally. Step 1 30 The CPU switching and ROM switching procedures are not completed. Step 1 4 0 The system fails to boot. Step 1 50 Confirm that the CPU switching is not complete. Procedure Step 1 60 Perform CPU switching procedure Step 161 Change the SMI status of all CPUs to isolate the BSP CPU from the CPU bus

Step 162 The BMC generates a CPU switching signal and a reboot signal to boot the BIOS or backup the BIOS. Step 1 70 ROM switching program CPU Central processing unit BIOS Basic input output system ROM Read-only memory BMC baseboard management controller

Page 114034031 Brief description of the CPU with BSP CPU default boot SMI 1, SMI 2 System management interrupt SWAP state switching state STBY_PGD Standby power-on state R0M_SWAP ROM switching state STATE_CHANGE State transition SYS_PGD System restart state CPU_SWAP CPU switching state LOW low HIGH High BACKUPR0M backup ROM status ROMswi tch R0M switch status

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Claims (1)

1244031 1. A step-by-step switching method of a multiprocessor computer system: // Contains the following steps to confirm the opening through a BMC (Baseboard Management Controller) = -⑽ (Central Processing Unit M switching program and restart; = = the CPU switching The program is to switch between one application CPU and the other through the BMC; /. To this, when the program cannot be switched on through the CPU, the steps of -_ (read-only memory) tool change procedure and restart are performed s ™ Its; l: f0M switching program is to use the BMC to switch the BIOS that executes the booting procedure from one of the boot ROMs to ^ 〇8, and switch to at least one of the backup ROMs to back up Bios. 2 .; if the scope of patent application The method for switching a multi-processor computer system as described in the above item, wherein the CPU switching procedure further includes: changing the SMI (System Management Interrupt) state of each CPU to switch the CPU and a CPU bus from the mine to the next boot Isolate; and heart, 刖 — generate a CPU switch signal and a reboot boot BIOS or the backup BiOS through the BMC. Thief 3 · The boot switcher of the multiprocessor computer system as described in item 1 of the scope of patent application The ROM switching procedure is to generate a ROM switching signal from the BMC to a complex programmable logic device CPLD (complex, Programmable Logic Device) to switch to the backup ROM and generate a system restart signal. To the backup 3 丨 0s. 4. The method for switching on the multiprocessor computer system as described in item 1 of the scope of patent application, wherein the abnormal startup means that the BMC has not received the boot from the boot. 1244031 VI. Patent application scope BIOS or one of the backup BIOS has booted message. -5. The method for switching on a multiprocessor computer system as described in item 1 of the scope of patent application, which further includes a step of confirming that the CPU switching program and the ROM switching program are not completed after confirming the abnormal startup. 6. The method for switching on the multi-processor computer system as described in item 5 of the scope of patent application. The method for switching on the CPU further includes a step of confirming that the CPU switching procedure has not been completed before the CPU switching procedure is performed. Page 14