1243977 玖、發明說明： t發明戶斤屬之技術領域】 相關申請案之交互參照 本申請案是2003年3月14日申請的美國臨時申請案第 5 10/389, 037號的後續申請案，其教示内容在此被引作參 考，這兩個申請案都要求2002年11月12日申請的美國臨時 申請案第60/425,553號的權益，其教示内容在此亦被引作 參考。 發明領域 10 本發明係關於用於直流/直流（直流對直流）變換器的 控制器，更具體的是有關於用於控制電感電流位準而不需 直接測量該電流位準的控制器。 發明背景 15 直流/直流變換器用來把一個輸入直流電壓轉換為一 個輸出直流電壓。該類變換器可以降低或升高輸入直流電 壓。一種降壓型變換器為同步降壓型變換器。該變換器通 常有一個控制器、驅動器、一對開關和一個與該對開關相 連的電感電容（LC)濾波器。該控制器提供一個控制信號 20 給驅動器，從而驅動該對開關，例如一個高側開關和一個 低側開關。該驅動器交替地閉合和斷開每個開關，從而控 制電感電流和直流/直流變換器的輸出電壓。該控制器通常 利用一個脈寬調變信號來控制高側和低側開關的狀態。 通常，如果PWM(脈寬調變）信號為高位準，則高側開關 1243977 為閉合（ON)且低側開關為斷開（OFF)。此開關狀態在此 稱為“開關閉合” （switch ON)狀態。在該狀態，電感與 輸入電壓源相連。對於降壓型變換器，輸入電壓必定大於 輸出電壓，因此在該開關閉合狀態，電感上有一個淨正電 5 壓。因此，電感電流開始斜線上升。如果PWM(脈寬調變）信 號為低位準，則高側開關為斷開（OFF)且低側開關為閉合 (ON)。此開關狀態在此稱為“開關斷開” （switch OFF) 狀態。對於降壓型變換器，在此開關斷開狀態電感上有一 個淨負電壓。因此，電感電流在該開關斷開狀態開始斜線 1〇 下降。從而，PWM(脈寬調變）信號的脈衝寬度決定開關閉合 狀態的閉合時間和開關斷開狀態的斷開時間。該脈衝寬度 可以通過一個檢測電阻或比較輸出電壓和參考電壓位準方 式直接監控電感電流位準來調變。 因此，在本領域中對於用於直流/直流變換器的控制器 15 就存在一種需要，即根據直流/直流變換器的輸入電壓與表 示輸出電壓的信號的差值，在第一時間間隔内提供一個 PWM(脈寬調變）信號。 【發明内容】 發明概要 20 在一個實施例中，本發明的一種切換電路包括：至少 一個開關和一個產生該週期控制信號的控制器。至少一個 開關響應該週期控制信號，在週期控制信號的每個週期開 始時改變狀態，其中週期控制信號的頻率有一個大於人耳 可聽頻率範圍的預設最小頻率值。 1243977 在另一個實施例中，本發明的一種切換電路包括··至 少一個開關和一個通過週期控制信號來控制至少一個開關 狀態的控制器。該至少一個開關回應該週期控制信號，在 週期控制信號的每個週期開始時改變狀態。控制器還有一 5 個跳過模式（skip mode )，其中控制器至少保持一個開關處 於斷開（OFF)狀態。該控制器回應一個計時器，該計時 器基於週期控制信號的每個週期的起始來對預設時間間隔 計時’其中控制器回應預設時間間隔的終止而啟動週期控 制信號的一個新的週期，該預設時間信號是設置來得到一 10個大於人耳可聽最小聲頻的週期控制信號的預設最小頻率 值〇 在另一個實施例中，提供了一種保持開關狀態切換的 最小頻率大於人耳可聽頻率的方法。本發明的方法包括： 在開關轉變為第一狀態的第一狀態切換的起始，啟動對預 15設時間間隔的計時；監控開關的狀態；如果開關仍處於第 一狀態，則改變開關的狀態來回應預設時間間隔的終止， 從而保持開關的狀態切換的最小頻率大於人耳可聽頻率。 在另一個實施例中，還提供了一個用來把輸入電壓轉 換為輸出電壓的直流/直流變換器。該直流/直流變換器包 20括：一個根據表示輸入電壓的第一信號與表示輸出電壓信 號的第二信號的差值、在第一狀態下的第一時間間隔内提 供一個第一狀態下的PWM(脈寬調變）信號的控制器；一個 接收至少該PWM信號且產生一個開關驅動信號的驅動電 路；一對包括一個高側開關和一個低側開關的開關，該開 1243977 關對響應開關驅動信號從而被驅動至開關閉合狀態，其中 當PWM信號處於第一狀態時高側開關閉合、低側開關斷 開；和一個與該對開關的輸出相連接的電感，其中在開關 閉合狀態下該電感上的電流位準增加；和一個提供一個具 5 有致能狀態和無效狀態的低側致能信號的邏輯電路，其中 當低側致能信號處於致能狀態時，PWM信號控制低側開 關，該邏輯電路接收一個來自過電流比較器的比較信號， 其中該過電流比較器基於流經該電感的電流位準與一個臨 界電流值的比較提供一個比較信號，如果流經電感的電流 10 位準大於該臨界電流值，邏輯電路還提供處於致能狀態的 低側致能信號。 在另一個實施例中，提供了一種使用與直流/直流變換 器的交換節點相連的現有引腳來檢測直流/直流變換器的 輸入電壓位準的方法。該方法包括：判定與輸入電壓源和 15 交換節點相連的高側開關的狀態；判定與地和交換節點相 連的低側開關的狀態；和當高側開關閉合、低側開關斷開 時檢測輸入電壓。 在另一個實施例中，本發明的直流/直流變換器的控制 器包括：一個與直流/直流變換器的交換節點相連的輸入引 20 腳端；當高側開關閉合、低側開關斷開時與輸入電壓相連 的直流/直流變換器的交換節點；與輸入引腳端相連的輸入 電壓檢測電路。該輸入電壓檢測電路包括：一個開關狀態 判定電路，當交換節點基於高側開關和低側開關的狀態與 該輸入電壓相連時，該開關狀態判定電路回應從而進行檢 1243977 測並提供一個判定信號；和一個電壓檢測電路，該電壓檢 測電路回應表示與該輸入電壓相連的交換節點的判定信 號，從而檢測表示所述輸入電壓的電壓位準。 在另一個實施例中，本發明的一個雙相直流/直流控制 5 器包括：一個來提供一個第一PWM信號的第一相位控制 器，該第一PWM信號基於表示直流/直流變換器的輸入電壓 的第一信號與表示直流/直流變換器的輸出電壓的第二信 號的差值；一個提供一個第二PWM信號的第二相位控制 器，該第二PWM信號基於表示直流/直流變換器的輸入電壓 10 的第一信號與表示直流/直流變換器的輸出電壓的第二信 號的差值；和一個用來選擇該第一相位控制器和第二相位 控制器的相位選擇電路。 在另一個實施例中，給出了一種能提供一個控制信號 來控制至少一個開關狀態的控制器。該控制器包括一個在 15 至少一個開關改變狀態至第一狀態後，對預設時間間隔計 時的計時器。如果至少一個開關自該預設時間間隔開始處 於第一狀態，則控制器回應時間間隔的終止而切換至少一 個開關的狀態，其中預設時間間隔設置用來保證狀態切換 的最小頻率大於一個人耳可聽頻率。 20 圖式簡單說明 本發明的優點將可由下文針對本發明幾個例示性實施 例所作的詳細欽述中明顯看出，而此等欽述應配合附圖來 考量；在附圖中： 第1A圖所示為本發明的一種包括一個控制器的直流/ 1243977 直流（直流對直流）變換器的方塊圖； 第1B圖所示為根據輸入PWM(脈寬調變）信號和低側致 能信號，描述第1A圖中的該對開關的開關狀態的示範表格； 第2A圖所示為用於第ία圖的直流/直流變換器的控制 5 器的一個實施例的方塊圖； 第2B圖所示為描述第2A圖中控制器的能量記憶元件 的充電位準的變化和在相同的時間間隔内電感電流位準的 相應變化的比較曲線圖； 第3圖所示為用於第丄八圖的直流/直流變換器的控制器 10 的另一個實施例的方塊圖； 第4圖所示為第3圖中的示範延遲電路的詳細方塊圖； 第5圖所示為用作第1八圖的直流/直流變換器的控制器 的另一個實施例的方塊圖； 第6圖所示為一個示範性的雙相控制器方塊圖； 15 第7圖所示為一個使用控制器LX引腳的輸入電壓檢測 電路的電路圖； 第8圖所示為本發明的帶有一個内部計時器供控制最 小切換頻率的控制器的另一個實施例的方塊圖； 第9圖所示為一個帶有位於控制器外部的計時器供控 2〇制最小切換頻率的直流/直流變換器的方塊圖；和 弟10圖所示為第8圖和第9圖實施例的時序圖。 C實方式]I 較佳實施例之詳細說明 根據本發明，第1A圖所示為一個包括-個控制器搬 1243977 的示範直流/直流變換器100。該控制器102可以用於各種直 流/直流變換器。所示直流/直流變換器100為一個同步降壓 型變換器，該變換器通常包括：控制器102、一個驅動器電 路104、一對包括一個高側開關Q1和一個低側開關Q2的開 5 關106和一個低通濾波器1〇8。該低通濾波器包括一個電感L 和一個電容C。 控制器102通常用於提供一個PWM(脈寬調變）信號和 低側開關致能信號（LDR_EN)給驅動器電路104。基於這 些信號，驅動器電路104便能控制高側開關Q1和低侧開關 10 Q2的狀態。 控制器102具有一個能設定需要的輸出電壓目標的輸 入引腳SLEW。在第1A圖的示範實施例中，壓擺電容（siew capacitor ) Cslew基於電阻分壓器R2/R3中的電阻值和參考 電壓值REF充電。本領域的技術人員將知道給壓擺電容充 15 電且產生目標電壓信號的各種方法。在該實施例中，電壓 從0擺動至根據壓擺電容Cslew設定的一個值。一個任選的 檢測電阻R1可以用來提供一個表示流經電感L的電流位準 的反饋電壓值給控制器102的引腳CSN和CSP。另外控制器 102的VFB引腳可以接收表示輸出電壓位準Vout的反饋信 20 號。 第1B圖所示為第1A圖中的高側開關Q1和低側開關Q2 在各種PWM(脈寬調變）信號和LDR_EN信號狀態下的各個 開關狀態的示範表格。如果LDR__EN信號為表格120中列122 的數位1，則PWM(脈寬調變）信號的狀態控制開關Q1和 11 1243977 信號變為數位〇，因此開關被驅動為開關斷開狀態。從而， 電感電流隨著能量記憶元件202上的電壓的減小而成比例 的減小。 控制器200通常包括不同的電流源II、12和13，這些電 5 流源基於由比較器CMP2、CMP3和CMP4產生的各個比較電 壓，給能量記憶元件202充電和放電。第一電流源II與輸出 電壓或目標電壓成一定比例，例如Vslew，且用於提供一個 第一電流位準。第二電流源12與直流/直流變換器的輸入電 壓成一定比例，且用於提供一個第二電流位準。最後，第 10 三電流源13與輸出電壓成一定比例，且用於提供一個第三 電流位準，該第三電流位準通常大於第一電流位準，但並 不必須大於。第三電流源13並非必須。但是，它能濾除一 個新PWM脈衝的寄生觸發。如果沒有採用第三電流源13， 開關S2能直接給能量記憶元件202放電。控制器200還可以 15 包括一個輸出判定電路240來提供PWM信號給開關驅動電 路。 控制器200還可包括一個第一比較器CMP1，該比較器 用於比較能量記憶元件202 (例如電容C1)上的電壓與第二 參考電壓V2。第二參考電壓V2可以是一個額定電壓，例如 20 在一個實施例中為20毫伏，且與比較器CMP1的正極引腳相 連’從而當能量記憶元件202上的電壓小於額定電壓V2時， CMP1提供一個高信號。1243977 发明 Description of the invention: The technical field of the invention is cross-referenced to related applications. This application is a follow-up application to US Provisional Application No. 5 10/389, 037 filed on March 14, 2003. The teaching content is incorporated herein by reference. Both applications require the benefit of US Provisional Application No. 60 / 425,553, which was filed on November 12, 2002. The teaching content is also incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to a controller for a DC / DC (DC to DC) converter, and more specifically to a controller for controlling an inductor current level without directly measuring the current level. BACKGROUND OF THE INVENTION 15 A DC / DC converter is used to convert an input DC voltage into an output DC voltage. This type of converter can reduce or increase the input DC voltage. One step-down converter is a synchronous step-down converter. The converter usually has a controller, a driver, a pair of switches, and an inductive capacitor (LC) filter connected to the pair of switches. The controller provides a control signal 20 to the driver to drive the pair of switches, such as a high-side switch and a low-side switch. The driver alternately closes and opens each switch to control the inductor current and the output voltage of the DC / DC converter. The controller usually uses a PWM signal to control the state of the high-side and low-side switches. Generally, if the PWM (Pulse Width Modulation) signal is high, the high-side switch 1243977 is closed (ON) and the low-side switch is open (OFF). This switching state is referred to herein as the "switch ON" state. In this state, the inductor is connected to the input voltage source. For a buck converter, the input voltage must be greater than the output voltage, so when the switch is closed, there is a net positive voltage on the inductor. Therefore, the inductor current starts to ramp up. If the PWM (Pulse Width Modulation) signal is low, the high-side switch is OFF and the low-side switch is ON. This switching state is referred to herein as a "switch OFF" state. For a buck converter, there is a net negative voltage across the inductor in this switch-off state. As a result, the inductor current begins to decrease with a diagonal line 10 when the switch is off. Therefore, the pulse width of the PWM (Pulse Width Modulation) signal determines the closing time of the switch-on state and the opening time of the switch-off state. This pulse width can be adjusted by monitoring the inductor current level directly with a sense resistor or comparing the output voltage and reference voltage levels. Therefore, there is a need in the art for the controller 15 for a DC / DC converter, which is provided in the first time interval according to the difference between the input voltage of the DC / DC converter and the signal representing the output voltage. A PWM (Pulse Width Modulation) signal. [Summary of the Invention] Summary of the Invention 20 In one embodiment, a switching circuit of the present invention includes at least one switch and a controller that generates the cycle control signal. At least one switch responds to the cycle control signal and changes state at the beginning of each cycle of the cycle control signal, where the frequency of the cycle control signal has a preset minimum frequency value greater than the audible frequency range of the human ear. 1243977 In another embodiment, a switching circuit of the present invention includes at least one switch and a controller that controls the state of at least one switch by a cycle control signal. The at least one switch responds to a cycle control signal and changes state at the beginning of each cycle of the cycle control signal. The controller also has 5 skip modes, in which the controller keeps at least one switch in the OFF state. The controller responds to a timer that counts a preset time interval based on the start of each cycle of the cycle control signal ', where the controller starts a new cycle of the cycle control signal in response to the end of the preset time interval The preset time signal is set to obtain a preset minimum frequency value of 10 periodic control signals that is greater than the minimum audible audio frequency of the human ear. In another embodiment, a minimum frequency for maintaining switching state switching is provided. Ear audible frequency method. The method of the present invention includes: starting the first state switching at the start of the switch transitioning to the first state, starting a timer for a preset time interval of 15; monitoring the state of the switch; and changing the state of the switch if the switch is still in the first state In response to the expiration of the preset time interval, the minimum frequency of the state switch to keep the switch is greater than the audible frequency of the human ear. In another embodiment, a DC / DC converter is provided for converting an input voltage to an output voltage. The DC / DC converter 20 includes: providing a first state in a first time interval according to a difference between a first signal representing an input voltage and a second signal representing an output voltage signal; A controller for a PWM (pulse width modulation) signal; a drive circuit that receives at least the PWM signal and generates a switch drive signal; a pair of switches including a high-side switch and a low-side switch, the on 1243977 off the response switch The driving signal is thereby driven to the switch-on state, where the high-side switch is closed and the low-side switch is open when the PWM signal is in the first state; and an inductor connected to the output of the pair of switches, wherein the switch is in the closed state The current level on the inductor increases; and a logic circuit that provides a low-side enable signal with 5 enabled and inactive states, where the PWM signal controls the low-side switch when the low-side enabled signal is in the enabled state, The logic circuit receives a comparison signal from an over-current comparator, where the over-current comparator is based on a current level flowing through the inductor and Comparison of a critical current value to provide a comparison signal if the current level flowing through the inductor 10 is greater than the threshold current value, the logic circuit is also provided in the lower side of the disable status enable signal. In another embodiment, a method for detecting an input voltage level of a DC / DC converter using an existing pin connected to a switching node of the DC / DC converter is provided. The method includes: determining a state of a high-side switch connected to an input voltage source and a 15 switching node; determining a state of a low-side switch connected to ground and the switching node; and detecting an input when the high-side switch is closed and the low-side switch is open Voltage. In another embodiment, the controller of the DC / DC converter of the present invention includes: an input terminal 20 connected to the switching node of the DC / DC converter; when the high-side switch is closed and the low-side switch is open A switching node of a DC / DC converter connected to the input voltage; an input voltage detection circuit connected to the input pin terminal. The input voltage detection circuit includes a switching state determination circuit. When the switching node is connected to the input voltage based on the state of the high-side switch and the low-side switch, the switching state determination circuit responds to perform a test 1243977 and provide a determination signal; And a voltage detection circuit, the voltage detection circuit responds to a determination signal indicating a switching node connected to the input voltage, thereby detecting a voltage level indicating the input voltage. In another embodiment, a dual-phase DC / DC controller according to the present invention includes: a first phase controller to provide a first PWM signal based on an input representing a DC / DC converter The difference between the first signal of the voltage and the second signal representing the output voltage of the DC / DC converter; a second phase controller providing a second PWM signal based on the A difference between a first signal of the input voltage 10 and a second signal representing an output voltage of the DC / DC converter; and a phase selection circuit for selecting the first phase controller and the second phase controller. In another embodiment, a controller is provided that is capable of providing a control signal to control the state of at least one switch. The controller includes a timer that counts a preset time interval after at least one switch changes state to the first state. If the at least one switch is in the first state since the preset time interval, the controller switches the state of the at least one switch in response to the end of the time interval, wherein the preset time interval is set to ensure that the minimum frequency of state switching is greater than one human ear Listening frequency. 20 The drawings briefly illustrate the advantages of the present invention will be apparent from the following detailed descriptions of several exemplary embodiments of the present invention, which should be considered in conjunction with the drawings; in the drawings: Section 1A The figure shows a block diagram of a DC / 1243977 DC (DC to DC) converter including a controller according to the present invention. Figure 1B shows the input PWM (pulse width modulation) signal and the low-side enable signal according to the input. An exemplary table describing the switching states of the pair of switches in Fig. 1A; Fig. 2A shows a block diagram of an embodiment of a control device for the DC / DC converter of Fig. Α; Fig. 2B shows Shown is a comparison curve describing the change in the charge level of the energy memory element of the controller in Figure 2A and the corresponding change in the inductor current level in the same time interval; Figure 3 is used for Figure 28 A block diagram of another embodiment of the controller 10 of the DC / DC converter; FIG. 4 shows a detailed block diagram of the exemplary delay circuit in FIG. 3; FIG. DC / DC converter controller Block diagram of another embodiment; FIG. 6 shows a block diagram of an exemplary dual-phase controller; 15 FIG. 7 shows a circuit diagram of an input voltage detection circuit using the LX pin of the controller; FIG. 8 Shown is a block diagram of another embodiment of the controller with an internal timer for controlling the minimum switching frequency according to the present invention; FIG. 9 shows a timer with a timer provided outside the controller for control of the 20 system Block diagram of the DC / DC converter with minimum switching frequency; and Figure 10 shows the timing diagrams of the embodiments of Figures 8 and 9. [Real mode] I Detailed description of the preferred embodiment According to the present invention, FIG. 1A shows an exemplary DC / DC converter 100 including a controller 1243977. The controller 102 can be used for various DC / DC converters. The DC / DC converter 100 shown is a synchronous step-down converter, which typically includes a controller 102, a driver circuit 104, a pair of on and off switches including a high-side switch Q1 and a low-side switch Q2 106 and a low-pass filter 108. The low-pass filter includes an inductor L and a capacitor C. The controller 102 is generally used to provide a PWM (pulse width modulation) signal and a low-side switch enable signal (LDR_EN) to the driver circuit 104. Based on these signals, the driver circuit 104 can control the states of the high-side switch Q1 and the low-side switch 10 Q2. The controller 102 has an input pin SLEW which can set a desired output voltage target. In the exemplary embodiment of FIG. 1A, a siew capacitor Cslew is charged based on the resistance value in the resistor divider R2 / R3 and the reference voltage value REF. Those skilled in the art will know various methods to charge the slew capacitor and generate a target voltage signal. In this embodiment, the voltage swings from 0 to a value set in accordance with the swing capacitance Cslew. An optional sense resistor R1 can be used to provide a feedback voltage value representing the level of the current flowing through the inductor L to the pins CSN and CSP of the controller 102. In addition, the VFB pin of the controller 102 can receive a feedback signal No. 20 indicating the output voltage level Vout. Fig. 1B shows an exemplary table of the switching states of the high-side switch Q1 and the low-side switch Q2 in Fig. 1A under various PWM (pulse width modulation) and LDR_EN signal states. If the LDR__EN signal is digit 1 of column 122 in table 120, the state of the PWM (pulse width modulation) signal controls the switches Q1 and 11 1243977. The signal becomes digit 0, so the switch is driven to the off state. Therefore, the inductor current decreases proportionally as the voltage on the energy storage element 202 decreases. The controller 200 typically includes different current sources II, 12 and 13 which charge and discharge the energy memory element 202 based on the respective comparison voltages generated by the comparators CMP2, CMP3 and CMP4. The first current source II is proportional to the output voltage or the target voltage, such as Vslew, and is used to provide a first current level. The second current source 12 is proportional to the input voltage of the DC / DC converter and is used to provide a second current level. Finally, the third current source 13 is proportional to the output voltage and is used to provide a third current level. The third current level is usually greater than the first current level, but it does not have to be greater. The third current source 13 is not necessary. However, it can filter out the parasitic trigger of a new PWM pulse. If the third current source 13 is not used, the switch S2 can directly discharge the energy storage element 202. The controller 200 may further include an output decision circuit 240 to provide a PWM signal to the switch driving circuit. The controller 200 may further include a first comparator CMP1 for comparing the voltage on the energy storage element 202 (for example, the capacitor C1) with the second reference voltage V2. The second reference voltage V2 may be a rated voltage, for example 20 is 20 millivolts in one embodiment, and is connected to the positive lead of the comparator CMP1 'so that when the voltage on the energy memory element 202 is less than the rated voltage V2, Provide a high signal.
比較器CMP1的輸出還可以和反及閘G1相連。一個 SKIP輸入可以和反及閘G1的另一個輸入端相連。如果SKIP 14 信號為Ο ’不管比較器CMP1的信號是什麼，LDRJEN信號 為數位1，從而PWM信號控制開關Ql、Q2的狀態。但是如 果SKIP信號為數位1且比較器CMP1的輸出也為數位1，則反 及閘G1的輸出為數位0。如此，如果PWM為數位〇，則開關 Ql和Q2都被驅動為斷開狀態。 工作過程中，因為能量記憶元件202上的電壓被放電至 地’能量記憶元件202上的電壓初始設定為0伏，且輸出判 定電路240提供一個數位〇的pwM信號。當控制器獲致能， SLEW電壓將從零開始增加到基於R2和R3的比值。比較器 CMP3接著檢測到SLEW電壓大於表示輸出電壓Vout的反饋 電壓VFB，因此提供一個數位1信號給輸出判定電路240的 及閘G2。 因為電感L沒有電流流過，比較器CMP4不會檢測到任 何過電流狀況，所以提供一個數位1信號給及閘G2。另外， 因為能量記憶元件202上的電壓被放電至〇伏，當比較該電 麈與額定臨界電壓V2時，比較器CMP1的輸出信號也同樣為 數位1。如此’及閘G2所有的輸入信號都為數位1，所以正 反器242被觸發。此時，PWM信號變為數位1且開關S1閉合。 當開關S1閉合，能量記憶元件202由一個等於第二電流 源提供的第二電流位準減去第一電流源提供的第一電流位 準的電流充電。有利的是，第一電流源提供的第一電流位 準巧*以表示輸出電壓’例如，可以正比於例如Vout的輸出 電麈值，或一個例如Vslew或Vtarget的目標電壓位準。如 此，能量記憶元件202由一個成比於i(Vin - Vout)或（Vin - 1243977The output of the comparator CMP1 can also be connected to the inverse gate G1. One SKIP input can be connected to the other input of the inverse gate G1. If the SKIP 14 signal is 0 ', regardless of the signal of the comparator CMP1, the LDRJEN signal is a digital one, so that the PWM signal controls the states of the switches Q1 and Q2. However, if the SKIP signal is a digital one and the output of the comparator CMP1 is also a digital one, the output of the inverse gate G1 is a digital zero. As such, if the PWM is digital zero, both switches Q1 and Q2 are driven to the off state. During operation, the voltage on the energy storage element 202 is discharged to ground. The voltage on the energy storage element 202 is initially set to 0 volts, and the output determination circuit 240 provides a digital pwM signal of zero. When the controller is enabled, the SLEW voltage will increase from zero to a ratio based on R2 and R3. The comparator CMP3 then detects that the SLEW voltage is greater than the feedback voltage VFB indicating the output voltage Vout, and therefore provides a digital 1 signal to the AND gate G2 of the output decision circuit 240. Because there is no current flowing through the inductor L, the comparator CMP4 will not detect any overcurrent condition, so it provides a digital 1 signal to the gate G2. In addition, because the voltage on the energy storage element 202 is discharged to 0 volts, when the voltage is compared with the rated threshold voltage V2, the output signal of the comparator CMP1 is also a digital one. In this way, all the input signals of the gate G2 are digital ones, so the flip-flop 242 is triggered. At this time, the PWM signal becomes digital 1 and the switch S1 is closed. When the switch S1 is closed, the energy storage element 202 is charged by a current equal to the second current level provided by the second current source minus the first current level provided by the first current source. Advantageously, the first current level provided by the first current source is smart * to represent the output voltage ', e.g., may be proportional to the output voltage of, for example, Vout, or a target voltage level such as Vslew or Vtarget. As such, the energy memory element 202 consists of a ratio of i (Vin-Vout) or (Vin-1243977
Vslew)的電流位準充電。 能量記憶元件202被充電直到達到預先設定的臨界電 壓位準，例如VI或一個實施例中的2.5伏。比較器CMP2把 能量記憶元件202上的電壓與預先設定的臨界電壓值進行 5 比較，並基於它們之間的差值產生一個輸出信號給輸出判 定電路。如果能量記憶元件202的電壓達到預先設定的臨界 電壓值VI，則比較器CMP2將輸出一個數位1信號給正反器 242的復位引腳R來復位正反器，從而正反器的輸出q變為 數位0，從而PWM信號也同樣變為數位〇。 10 此時，因為正反器輸出Q為數位0，開關S1被斷開。如 此，能量記憶元件202由電流源12放電。如果及閘G3的輸出 為數位1，則能量記憶元件202將會加速放電。如果PWM信 號為數位0，上述情況就會發生，因此來自正反器242的QB 引腳的及閘G3的一個輸入為數位1。另外，如果反饋電壓 15 VFB信號小於SLEW電壓，則來自比較器CMP3的及閘G3的 另一個輸入為數位1。如此，及閘G3的一個數位1將使得開 關S2閉合。這樣’第三電流源可以與能量記憶元件202相連 接來提供加速放電。在一個實施例中，電流源13的值為1〇 χ I一Vout，該值可以根據特定的能量記憶元件2〇2和其他參數 20調整，從而得到一個想要的加速放電位準。另外，第三電 流源13也可以由短路來代替，從而開關32會把能量記憶元 件202放電至接地。 當PWM信號為數位〇，能量記憶元件202上的電壓位準 會繼續放電。根據比較器CMP3提供的SLEW電壓和反饋電 16 1243977 壓VFB的比較，該放電可以是正常速度或加速。 一旦能量記憶元件202上的電壓位準被放電為小於額 定臨界值V2的一個值（因此比較器CMP1的輸出為數位1)， 且比較器CMP3和CMP4的輸出都為數位1，隨著正反器的輸 5 出Q變為數位1，便產生一個新PWM脈衝。 結合第2A圖，第2B圖所示為隨著時間變化能量記憶元 件202上的電壓位準曲線203。另外，曲線205為在相同的時 間間隔内電感L上的電感電流位準。例如，在控制器200工 作的起始時間（t0)，能量記憶元件上的電壓為〇伏。在第 10 —時間間隔内或時間t0和tl之間的Ton，當PWM輸出信號為 數位1，能量記憶元件202上的電壓位準線性增加直到達到 預先設定的臨界值VI，例如在一個實施例中為2.5伏。 如此，t0和tl之間的Ton取決於代表輸入電壓Vin的信號 和代表輸出電壓Vout或Vtarget的信號之間差值，因為能量 15 記憶元件202在該時間間隔内，由一個與該差值成比例的電 流（電流源12-11)進行充電。Ton的持續時間還取決於臨界 電壓值VI和能量記憶元件202的電壓值。其中能量記憶元件 為一個電容C1，且第二電流源正比於Vout，Ton的持續時間 可以由如下式3得到： 20 (3) Ton = Cl*Vl/I(Vin - Vout) 其中Cl為電容Cl的值，VI為預先設定的充電臨界值 (在一個實施例中為2.5伏），當第二電流源正比於Vout 時，I (Vin - Vout)為第二電流源12和第一電流源II之間的差 值提供的充電電流值。 17 1243977 器的輸入電壓與表示輸出電壓的信號（例如Vout或Vtarget) 的差值、提供一個PWM控制信號給相關的驅動器電路。但 是，不是給能量記憶元件充電和放電，控制器3〇〇實際上對 時間段進行計數，並基於這些計數提供合適的PWM和 5 LDR_EN信號。 例如，控制器300通常包括一個選通時間單觸發電路 (on-time one shot circuit) 302、一個低側驅動單觸發電路 (a low side driver one shot circuit ) 304、一個比較器306、 一個時間延遲電路308和一個反或閘310。時間延遲電路308 10 可以是一個產生選通時間單觸發電路302的再觸發消隱電 路。單觸發電路302和304可以由輸入信號下降緣觸發。 理想情況下，單觸發電路302的選通時間與直流/直流 變換器的輸入電壓Vin與直流/直流變換器的輸出目標電壓 Vtarget之間的差值成一定比例，且tldr與vtarget成比例， 15 如式（5)中所示： T〇n 二 K _ V— (5) T[dr Vtarget 貫際上’ Tldr通常選得比式（5 )所得的短一點。有 幾種方法可以產生Τοπ/Tldr。通常，Vtarget可以是一個不 變值或者一個可變的離散值。單觸發電路3〇2和304的延遲 2〇 可以是基本時延的倍數的實際時延，例如，時延To可以由 式（6)和（7)得到： (6) Ton = Tol * ΜVslew). The energy storage element 202 is charged until a predetermined threshold voltage level is reached, such as 2.5 V in one embodiment or VI. The comparator CMP2 compares the voltage on the energy storage element 202 with a preset threshold voltage value 5 and generates an output signal to the output determination circuit based on the difference between them. If the voltage of the energy storage element 202 reaches the preset threshold voltage value VI, the comparator CMP2 will output a digital 1 signal to the reset pin R of the flip-flop 242 to reset the flip-flop, so that the output q of the flip-flop becomes It is digital zero, so that the PWM signal also becomes digital zero. 10 At this time, because the output Q of the flip-flop is digital 0, the switch S1 is turned off. As such, the energy storage element 202 is discharged by the current source 12. If the output of the AND gate G3 is a digital one, the energy storage element 202 will accelerate the discharge. If the PWM signal is digit 0, the above situation will occur, so one input from the QB pin of the flip-flop 242 and the gate G3 is digit 1. In addition, if the feedback voltage 15 VFB signal is less than the SLEW voltage, the other input from the comparator CMP3 and the gate G3 is a digital one. Thus, a digit 1 of the AND gate G3 will cause the switch S2 to close. In this way, the third current source can be connected to the energy storage element 202 to provide accelerated discharge. In one embodiment, the value of the current source 13 is 10 × I−Vout, and the value can be adjusted according to the specific energy memory element 202 and other parameters 20 to obtain a desired accelerated discharge level. In addition, the third current source 13 may be replaced by a short circuit, so that the switch 32 will discharge the energy storage element 202 to ground. When the PWM signal is a digital zero, the voltage level on the energy storage element 202 will continue to discharge. According to the comparison between the SLEW voltage provided by the comparator CMP3 and the feedback voltage VFB, the discharge can be normal speed or acceleration. Once the voltage level on the energy memory element 202 is discharged to a value less than the rated threshold V2 (the output of the comparator CMP1 is therefore a digital one), and the outputs of the comparators CMP3 and CMP4 are both a digital one. The output Q of the converter becomes digit 1 and a new PWM pulse is generated. In conjunction with FIG. 2A and FIG. 2B, a voltage level curve 203 on the energy storage element 202 is shown as a function of time. In addition, the curve 205 is the level of the inductor current on the inductor L during the same time interval. For example, at the start time (t0) of the operation of the controller 200, the voltage on the energy storage element is 0 volts. In the 10th time interval or Ton between time t0 and time t1, when the PWM output signal is digital 1, the voltage level on the energy storage element 202 increases linearly until reaching a preset threshold VI, for example, in one embodiment Medium is 2.5 volts. In this way, Ton between t0 and tl depends on the difference between the signal representing the input voltage Vin and the signal representing the output voltage Vout or Vtarget, because the energy 15 of the memory element 202 during this time interval is determined by Proportional current (current source 12-11) for charging. The duration of Ton also depends on the threshold voltage value VI and the voltage value of the energy storage element 202. The energy storage element is a capacitor C1, and the second current source is proportional to Vout. The duration of Ton can be obtained by the following formula 3: 20 (3) Ton = Cl * Vl / I (Vin-Vout) where Cl is the capacitor Cl V is the preset charge threshold value (2.5 volts in one embodiment). When the second current source is proportional to Vout, I (Vin-Vout) is the second current source 12 and the first current source II The difference between the values of the charge current provided. 17 1243977 The difference between the input voltage of the device and the signal (such as Vout or Vtarget) that indicates the output voltage, and provides a PWM control signal to the relevant driver circuit. However, instead of charging and discharging the energy memory element, the controller 300 actually counts the time periods and provides the appropriate PWM and 5 LDR_EN signals based on these counts. For example, the controller 300 usually includes an on-time one shot circuit 302, a low side driver one shot circuit 304, a comparator 306, and a time delay Circuit 308 and a reverse OR gate 310. The time delay circuit 308 10 may be a re-trigger blanking circuit that generates a gate time single trigger circuit 302. The one-shot circuits 302 and 304 can be triggered by the falling edge of the input signal. Ideally, the gate time of the one-shot circuit 302 is proportional to the difference between the input voltage Vin of the DC / DC converter and the output target voltage Vtarget of the DC / DC converter, and tldr is proportional to vtarget, 15 As shown in formula (5): T0n two K _ V — (5) T [dr Vtarget In general, 'Tldr is usually chosen to be shorter than that obtained by formula (5). There are several ways to generate Toπ / Tldr. Generally, Vtarget can be an invariant value or a variable discrete value. The delay 2 of the one-shot circuits 3 02 and 304 may be an actual delay that is a multiple of the basic delay. For example, the delay To may be obtained by equations (6) and (7): (6) Ton = Tol * Μ
(7) TLDR = To2 * N 19 1243977 第4圖所示為一個示範延遲電路400，其可產生一個想 要的時延來使為選通時間單觸發電路3〇2保持合適選通時 間。延遲電路400通常包括一個產生時間脈衝的振盪器 402 ' —個計數時間脈衝的計數器4〇4和一個比較計數值和 5倍數（例如Μ或N)的數位比較器406。從而，比較器產生 一個表示計數器404是否達到必需的]^或1^數值的輸出信 號。因此，適當的選通時間是通過計數與倍數Μ或ν相比較 的數目來控制的。 因此就能通過倍數Μ和Ν選擇適當的延時。因為Ton是 10 Vin和Vtarget的函數，且TLDR是Vtarget的函數，就有幾種方 法可以控制它們。在第一個例子中，丁〇1和丁〇2相等且為常 數。如此，倍數N可以由一個設定vtarget的數位信號從詢查 表(LUT)中產生。該例中的LUT是一維的，因為各個N值對 應一個相應的Vtarget值。在相同的例子中，其中τ〇1和To2 15相荨且為常數’倍數Μ可以由一個設定Vtarget的數位信號 和一個數位化Vin信號從詢查表(LUT)中產生。該數位化Vin 信號可以採用一個A/D轉換器來得到。如此，該例中產生Μ 的LUT為二維，因為μ值對應一個相應的vtarget和Vin值。 在另一個例子中，Tol和To2不相等。該例中，如果To2 20為常數’則倍數Ν與第一個例子中產生的方法相同。倍數Μ 可以通過一個具有一個設定Vtarget的數位信號的一維LUT 產生。但是，Tol不是常量，而是Vin或Vin和Vtarget的函數。 第5圖所示為本發明的用作第ία圖的直流/直流變換器 的控制器的另一種控制器500。第5圖所示控制器500的很多 20 1243977 部件都和第2A圖所示的控制器200相似，且標號相同。因為 上文已經對第2A圖的部件詳細描述過，在此為簡潔起見， 省略對相似部件的重複描述，而詳細闡述第2A圖和第5圖之 間的不同之處。通常，控制器500有一個額外的連接511把 5比較器CMP4的輸出和反及閘G1的輸入相連。 該反及閘G1現在有三個輸入：來自比較器CMP1的第 一輸入；來自SKIP端的第二輸入；和來自比較器CMP4的第 三輸入。如果這三個反及閘G1的輸入中的任何一個為數位 〇，則反及閘G1的輸出就為數位1。這在過電流狀況下的跳 10過模式中尤為有用。該例中，比較器CMP4的輸出可以是數 位0，而直流/直流變換器的輸出電壓會下降，從而比較器 CMP3的輸出為數位丄。如此，開關S2將閉合，加速能量記 憶元件202的放電。由於比較器CMP4和反及閘G1之間的連 接511，只要比較器CMP4的輸出為數位〇,反及閘的輸出 15就為數位1，因此LDR-EN為數位1，從而使得低側開關Q2 閉合。當反及閘G1的三個輸入都為高位準時，LDRjgN信 號變為低位準。同時，由及閘〇2的輸出設置的正反器FF1 開始新的PWM週期。 第6圖所示為本發明的一個雙相控制器6〇〇。通常，該 20雙相控制器600包括··一個第一相位控制器602、一個第二 相位控制器604和一個相位選擇電路6〇6。該相位選擇電路 選擇相位控制裔602和604，來使其中一個在任何一個時間 產生PWM控制信號。第一相位控制器6〇2和第二相位控制 器604的很多部件都與第5圖所示的控制器5〇〇的部件相似 21 1243977 (也可參考第2A圖所示的控制器2〇〇)。因此為了簡潔起 見，在此省略對任何相似部件和操作的重複描述。 相位選擇電路606使得在任何一個時間，相位控制器 602、604中只有一個能產生PWM信號。可以採用各種電路 5配置來實現相位選擇電路606期望的功能。在一個實施例 中’相位選擇器606包括一個正反器619和反及閘G7。反及 閘G7接收來自第一相位控制器602的第一PWM信號PWM1 和來自第二相位選擇器604的第二PWM信號PWM2。反及閘 G7的輸出接著反饋至正反器619的時鐘端“ck” 。正反器 10 619的“Q”端與第一相位控制器602的及閘G2的輸入相 連，正反器619的“QB”端與第二相位控制器604的及閘G5 的輸入相連。及閘G2和G5的輸入都必須是數位1，從而提 供一個數位1的輸出來設置相關的正反器FF1或FF2。 “QB”為“Q”的反相，從而保證正反器FF1和FF2的設置 15 發生在不同時間。 工作過程中，第一相位控制器602產生一個PWM脈衝 之後，正反器619 PWM1端的PWM脈衝的下降緣改變狀 態，從而允許第二相位控制器604的PWM2產生一個PWM脈 衝。當反饋電壓VFB下降至SLEW電壓以下時，第二相位控 2〇 制器604的PWM2端產生一個PWM脈衝。PWM脈衝的下降 緣再次改變正反器619的狀態。因此，下一個PWM信號由 第一控制器602的PWM1端產生，隨著正反器619在每個 PWM脈衝的下降緣改變狀態，進程繼續進行。在跳過 (SKIP )模式，由於每個控制器602、604分別有獨立的 22 1243977 LDR一ΕΝ脈衝估計值，即ldrjen^ldR-Enlpwj^^ 能精確的交替產生。 第7圖所示為本發明的一個不需要控制器上單獨的輸 入引腳的輸入電壓檢測電路700。這樣控制器上的總引腳數 5目就減小了。該輸入電壓檢測電路700接收LX引腳703的輸 入h號。LX引腳703與直流/直流變換器的交換節點715 (第 9圖所示）相連。當高側開關Q1閉合、低側開關〇2打開時， 該交換節點715與輸入電壓相連。當高側開關Q1打開、低側 開關Q2閉合時，該交換節點715也可以接地。另外，該交換 10節點可以在Q1和Q2都打開的跳過狀態保持漂移狀態。 通常，輸入電壓檢測電路700有一個開關狀態判定電路 740和一個電壓檢測電路742。當高側開關Q1閉合、低側開 關Q2打開時，該交換節點715與輸入電壓相連，此時該開關 狀態判定電路740進行判定。該開關狀態判定電路740接著 15 提供一個判定信號給電壓檢測電路742,來使電壓檢測電路 742檢測表示LX引腳703處電壓的電壓。 該開關狀態判定電路740還包括一個及閘712。當及閘 712接受到的延遲PWM信號和PWM信號都為數位1時，該及 閘712的輸出也同樣為數位i，從而接著閉合開關7〇6。該輸 2〇入電壓檢測電路還可以包括一對電阻702、704構成的分壓 器來把LX引腳703處的電壓按一定比例縮小至一個低位 準。在一個實施例中，電阻7〇2可以為210千歐姆，電阻704 可以為30千歐姆。 當開關狀態判定電路740判定在交換節點715處的電壓 23 1243977 表示輸入電壓位準時（例如，及閘712接受到的PWM信號 都為高位準），就閉合開關706。電壓檢測電路742包括一個 跨導放大器714和電晶體Q3。該跨導放大器714在其同向輸 入端接收一個表示輸入電壓的輸入信號，並提供一個信號 5 給電晶體Q3的控制電極。電晶體Q3接著提供一個表示輸入 電壓位準的信號，例如I—Vin。因此，提供了 一個輸入電壓 檢測電路700，而無需控制器上單獨的輸入引腳。這樣，控 制器上的總引腳數目就減小了。另外，如果有一個和第6圖 所示的控制器600相似的在一片晶片上的雙相控制器，則每 10 個控制器能檢測各自不同的輸入電壓。例如，第一控制器 可以把電池電壓16伏轉換為2.5伏，第二控制器可以把5伏 輸入電壓轉換為1.5伏。兩個控制器都能正常工作。 第8圖所示的電路圖中，控制器8〇〇内部的pwM端和反 及閘G1的輸入之間加入了一個計時器8〇2。第9圖所示為控 15制器PW]V^SKIP端之間的計時器802的外部實現。計時器 802在一個能控制高側開關Q1和低側開關〇2狀態的週期控 制信號（例如PWM信號）的前緣開始時間計時，本文將參 照第10圖的時序圖進一步詳述。計時器8〇2保證了開關在一 個大於人耳可聽的聲頻範圍（即，大約2〇千赫茲到25千赫 20茲）的頻率切換狀態，本文將通過對控制週期控制信號的 頻率來詳述。 如第10圖所不的時序圖，tl時刻產生一個PWM脈衝。 在tl和t2時刻之間，PWM脈衝為數位i。因此高侧開關以 為閉合而低側開關Q2為斷開。另外，在時間間隔^至^之 24 1243977 間，低側致能信號LDR_EN也為數位1。因此，在“開關閉 合”狀態期間，電感電流增加。 在時刻t2和t3之間，PWM信號為數位〇且LDR_EN信號 為數位1。從而在該時間間隔，高側開關Q1為斷開而低側開 5 關Q2為閉合。因此，在該“開關斷開”狀態期間電感電流 下降，直到在時刻t3下降為0。在時刻t3，LDR_EN信號變 為數位0。因為在該時刻PWM信號也為數位〇,則在時刻t3 進入跳過狀態。如此，在時刻t3至t4之間的跳過狀態，高側 開關Q1和低側開關Q2都為斷開。 10 如果由控制器反饋端VFB所測得的輸出電壓下降至設 定電壓位準VSET之下，就會產生一個新的PWM脈衝。另 外’計時器802的工作也能保證輸入電壓下降至vsET位 準。例如，計時器在PWM脈衝的前緣開始計時，或在時刻 tl開始一個預設時間間隔（x秒）。在第8圖所示的實施例 15中，計時器在時刻t3至t4的時間間隔内提供一個數位i信號 給反及閘G1。 預設時間間隔限制（X秒）在時刻t4終止之後，LDR EN 信號變為數位1。在第8圖所示的實施例中，這是因為反及 閘G1的計時器信號輸入變為了數位〇 ,從而使得反及閘〇1 20的輸出或LDRJEN信號變為數位i。在第9圖所示的實施例 中，汁時器802控制SKIP端的輸入狀態，從而和第8圖的計 時器一樣產生相同的效應。即，當預定時間間隔限制終止 後，LDR—EN信號變為數位1。從而跳過模式為無效且低側 開關Q2在時刻t2閉合。一旦低側開關Q2閉合，輸出電壓就 25 1243977 開始下降，因為輸出電容C經由電感低側開關路徑放電至 地。當輸出電壓下降至設定電壓VSET以下時，例如在15時 刻，則會產生一個新的PWM脈衝並再次開始進程。 有利的是，計時器802可以選擇一個時間限制來保證使 5用跳過模式時PWM脈衝的最小頻率，從而實現開關狀態的 最小切換頻率。更有利的是，該時間限制還可以選擇來使 得PWM脈衝的頻率大於人耳可聽頻率範圍。人耳可聽的平 均頻率範圍是20赫茲到20千赫茲。為使頻率保持在最小值 20千赫茲，該時間限制可以設置為5〇微秒。為使頻率保持 10在稍高一點的25千赫茲，該時間限制可以設置為4〇微秒， 因此，通過恰當的選擇計時器802的時間限制，高側開關Q1 和低側開關Q2的最小切換頻率就可以保持在一個範圍，例 如，大於20千赫茲，即大於人耳可聽的平均頻率範圍。儘 管在此所述的計時器用於直流/直流變換器的控制器，本領 15域的技術人員將知道該計時器還可以用於其他各種切換電 路，該切換電路期望得到一個最小切換頻率來避免人耳可 聽到的切換雜訊。 在此描述的實施例只是採用本發明的其中幾個，且只 供舉例說明之用，而無限制本發明之意。顯而易見，本領 20域的技術人員將可輕易思及許多其他的實施例，而並不會 貫貝脫離後附申請專利範圍所定義的本發明的精神和範 圍0 【圖式簡單說明】 26 1243977 第1A圖所示為本發明的一種包括一個控制器的直流/ 直流（直流對直流）變換器的方塊圖； 第1B圖所示為根據輸入PWM(脈寬調變）信號和低側致 能信號，描述第1A圖中的該對開關的開關狀態的示範表格； 5 第2A圖所示為用於第1A圖的直流/直流變換器的控制 器的一個實施例的方塊圖； 第2B圖所示為描述第2A圖中控制器的能量記憶元件 的充電位準的變化和在相同的時間間隔内電感電流位準的 相應變化的比較曲線圖； 10 第3圖所示為用於第1A圖的直流/直流變換器的控制器 的另一個實施例的方塊圖； 第4圖所示為第3圖中的示範延遲電路的詳細方塊圖； 第5圖所示為用作第1A圖的直流/直流變換器的控制器 的另一個實施例的方塊圖； 15 第6圖所示為一個示範性的雙相控制器方塊圖； 第7圖所示為一個使用控制器LX引腳的輸入電壓檢測 電路的電路圖； 第8圖所示為本發明的帶有一個内部計時器供控制最 小切換頻率的控制器的另一個實施例的方塊圖； 20 第9圖所示為一個帶有位於控制器外部的計時器供控 制最小切換頻率的直流/直流變換器的方塊圖；和 第10圖所示為第8圖和第9圖實施例的時序圖。 【圖式之主要元件代表符號表】 100…直流/直流變換器 102、200、300…控制器 27 1243977 104···驅動器電路 106、S1 〜S4、706···開關 108…低通濾波器 C、C1〜C2、708…電容 Cslew···壓擺電容 L···電感 Q1···高側開關 Q2···低側開關 R1 〜R3、702、704···電阻 Vin…輸入電壓 Vout…輸出電壓 120…表格 122、124…列 202···能量記憶元件 240···輸出判定電路 242、619···正反器 REF···參考電壓值 II〜15···電流源 VI…臨界電壓值 V2···第二參考電壓 CMP1 〜4、COMP1 〜6、306 …比 較器(7) TLDR = To2 * N 19 1243977 Figure 4 shows an exemplary delay circuit 400, which can generate a desired delay to keep the single-trigger circuit 302 for the gate time a proper gate time. The delay circuit 400 generally includes an oscillator 402 'which generates a time pulse, a counter 404 which counts time pulses, and a digital comparator 406 which compares the count value with a multiple of 5 (for example, M or N). Thus, the comparator generates an output signal indicating whether the counter 404 has reached the required value of ^ or 1 ^. Therefore, the appropriate strobe time is controlled by counting the number compared with the multiple M or v. Therefore, the appropriate delay can be selected by the multiples M and N. Because Ton is a function of 10 Vin and Vtarget, and TLDR is a function of Vtarget, there are several ways to control them. In the first example, ding 〇1 and ding 〇2 are equal and constant. In this way, the multiple N can be generated from a lookup table (LUT) by a digital signal that sets vtarget. The LUT in this example is one-dimensional because each N value corresponds to a corresponding Vtarget value. In the same example, where τ〇1 and To2 are 15 phase constants and a multiple of 'M can be generated from a lookup table (LUT) by a digital signal that sets Vtarget and a digitized Vin signal. The digitized Vin signal can be obtained by an A / D converter. As such, the LUT that generates M in this example is two-dimensional, because the μ value corresponds to a corresponding vtarget and Vin value. In another example, Tol and To2 are not equal. In this example, if To2 20 is constant, then the multiple N is the same as that produced in the first example. Multiples M can be generated by a one-dimensional LUT with a digital signal that sets Vtarget. However, Tol is not a constant, but a function of Vin or Vin and Vtarget. Fig. 5 shows another controller 500 of the present invention, which is used as the controller of the DC / DC converter of Fig. Α. Many components of the controller 500 shown in FIG. 5 are similar to those of the controller 200 shown in FIG. 2A and the same reference numerals are used. Since the components of FIG. 2A have been described in detail above, for the sake of brevity, repeated description of similar components is omitted, and the differences between FIG. 2A and FIG. 5 are explained in detail. Generally, the controller 500 has an additional connection 511 to connect the output of the 5 comparator CMP4 to the input of the inverse gate G1. The inverse gate G1 now has three inputs: the first input from the comparator CMP1; the second input from the SKIP terminal; and the third input from the comparator CMP4. If any one of the inputs of the three inverting gates G1 is a digit 0, the output of the inverting gate G1 is a digital one. This is especially useful in the skip 10-over mode under overcurrent conditions. In this example, the output of the comparator CMP4 can be digital 0, and the output voltage of the DC / DC converter will drop, so that the output of the comparator CMP3 is digital 丄. In this way, the switch S2 will be closed and the discharge of the energy memory element 202 will be accelerated. Because of the connection 511 between the comparator CMP4 and the inverting gate G1, as long as the output of the comparator CMP4 is digital 0, the output 15 of the inverting gate is digital 1, so LDR-EN is digital 1, which makes the low-side switch Q2 closure. When all three inputs of the inverse gate G1 are high, the LDRjgN signal becomes low. At the same time, the flip-flop FF1 set by the output of AND gate 02 starts a new PWM cycle. Figure 6 shows a two-phase controller 600 of the present invention. Generally, the 20 bi-phase controller 600 includes a first phase controller 602, a second phase controller 604, and a phase selection circuit 606. The phase selection circuit selects the phase control signals 602 and 604 to cause one of them to generate a PWM control signal at any one time. Many components of the first phase controller 602 and the second phase controller 604 are similar to those of the controller 500 shown in Fig. 5 21 1243977 (see also the controller 2 shown in Fig. 2A). 〇). Therefore, for the sake of brevity, repeated description of any similar components and operations is omitted here. The phase selection circuit 606 enables only one of the phase controllers 602, 604 to generate a PWM signal at any one time. Various circuit 5 configurations can be employed to achieve the desired function of the phase selection circuit 606. In one embodiment, the 'phase selector 606 includes a flip-flop 619 and a flip-flop G7. Reverse gate G7 receives a first PWM signal PWM1 from the first phase controller 602 and a second PWM signal PWM2 from the second phase selector 604. The output of the inverting gate G7 is then fed back to the clock terminal "ck" of the flip-flop 619. The "Q" terminal of the flip-flop 10 619 is connected to the input of the first phase controller 602 and the gate G2, and the "QB" terminal of the flip-flop 619 is connected to the input of the second phase controller 604 and the gate G5. The inputs of the gates G2 and G5 must be digit 1 to provide a digit 1 output to set the associated flip-flop FF1 or FF2. “QB” is the inversion of “Q”, which ensures that the settings 15 of the flip-flops FF1 and FF2 occur at different times. During operation, after the first phase controller 602 generates a PWM pulse, the falling edge of the PWM pulse at the PWM1 terminal of the flip-flop 619 changes state, thereby allowing the PWM2 of the second phase controller 604 to generate a PWM pulse. When the feedback voltage VFB drops below the SLEW voltage, the PWM2 terminal of the second phase controller 604 generates a PWM pulse. The falling edge of the PWM pulse changes the state of the flip-flop 619 again. Therefore, the next PWM signal is generated by the PWM1 terminal of the first controller 602. As the flip-flop 619 changes state at the falling edge of each PWM pulse, the process continues. In Skip (SKIP) mode, since each controller 602, 604 has an independent 22 1243977 LDR-EN pulse estimated value, that is, ldrjen ^ ldR-Enlpwj ^^ can be generated alternately accurately. Figure 7 shows an input voltage detection circuit 700 of the present invention that does not require a separate input pin on the controller. This reduces the total number of pins on the controller to 5 meshes. The input voltage detection circuit 700 receives the input h number of the LX pin 703. The LX pin 703 is connected to the switching node 715 (shown in Fig. 9) of the DC / DC converter. When the high-side switch Q1 is closed and the low-side switch 02 is open, the switching node 715 is connected to the input voltage. When the high-side switch Q1 is opened and the low-side switch Q2 is closed, the switching node 715 can also be grounded. In addition, the switch 10 node can maintain the drift state in the skip state where both Q1 and Q2 are open. Generally, the input voltage detection circuit 700 has a switching state determination circuit 740 and a voltage detection circuit 742. When the high-side switch Q1 is closed and the low-side switch Q2 is open, the switching node 715 is connected to the input voltage, and at this time, the switching state determination circuit 740 makes a determination. The switching state determination circuit 740 then provides a determination signal to the voltage detection circuit 742 to cause the voltage detection circuit 742 to detect a voltage indicating the voltage at the LX pin 703. The switching state determining circuit 740 further includes an AND gate 712. When both the delayed PWM signal and the PWM signal received by the AND gate 712 are digital 1, the output of the AND gate 712 is also the digital i, and then the switch 706 is closed. The input voltage detection circuit may further include a pair of resistors 702 and 704 to divide the voltage at the LX pin 703 to a low level by a certain ratio. In one embodiment, the resistor 702 may be 210 kiloohms, and the resistor 704 may be 30 kiloohms. When the switching state determining circuit 740 determines that the voltage 23 1243977 at the switching node 715 indicates the input voltage level (for example, the PWM signals received by the gate 712 are all high level), the switch 706 is closed. The voltage detection circuit 742 includes a transconductance amplifier 714 and a transistor Q3. The transconductance amplifier 714 receives an input signal representing the input voltage at its non-inverting input terminal, and provides a signal 5 to the control electrode of the transistor Q3. Transistor Q3 then provides a signal indicating the level of the input voltage, such as I-Vin. Therefore, an input voltage detection circuit 700 is provided without a separate input pin on the controller. This reduces the total number of pins on the controller. In addition, if there is a two-phase controller on a chip similar to the controller 600 shown in FIG. 6, every 10 controllers can detect different input voltages. For example, a first controller can convert a battery voltage of 16 volts to 2.5 volts, and a second controller can convert a 5 volt input voltage to 1.5 volts. Both controllers work properly. In the circuit diagram shown in Figure 8, a timer 802 is added between the pwM terminal of the controller 800 and the input of the feedback gate G1. Figure 9 shows the external implementation of the timer 802 between the controllers PW] V ^ SKIP. The timer 802 starts timing at the leading edge of a period control signal (such as a PWM signal) that can control the states of the high-side switch Q1 and the low-side switch 02, and will be further described in detail with reference to the timing diagram in FIG. The timer 802 guarantees the switching state of the switch at a frequency greater than the audible audio range of the human ear (ie, about 20 kHz to 25 kHz 20 Hz). This article will detail the frequency of the control cycle control signal. Described. As shown in the timing diagram in Figure 10, a PWM pulse is generated at time t1. Between t1 and t2, the PWM pulse is digital i. Therefore, the high-side switch is considered to be closed and the low-side switch Q2 is to be opened. In addition, the low-side enable signal LDR_EN is also a digital one during the time interval ^ to 24 1243977. Therefore, during the "on and off" state, the inductor current increases. Between times t2 and t3, the PWM signal is digital 0 and the LDR_EN signal is digital 1. Therefore, at this time interval, the high-side switch Q1 is open and the low-side switch Q2 is closed. Therefore, the inductor current drops during this "switch-off" state until it drops to zero at time t3. At time t3, the LDR_EN signal becomes digital zero. Because the PWM signal is also digital 0 at this time, the skip state is entered at time t3. As such, in the skipped state between times t3 and t4, both the high-side switch Q1 and the low-side switch Q2 are turned off. 10 If the output voltage measured by the feedback terminal VFB of the controller drops below the set voltage level VSET, a new PWM pulse will be generated. In addition, the operation of the 'timer 802 can ensure that the input voltage drops to the vsET level. For example, the timer starts counting at the leading edge of the PWM pulse, or starts a preset time interval (x seconds) at time t1. In the fifteenth embodiment shown in Fig. 8, the timer supplies a digital i signal to the reverse gate G1 in a time interval from time t3 to t4. After the preset time interval limit (X seconds) expires at time t4, the LDR EN signal becomes digital one. In the embodiment shown in FIG. 8, this is because the timer signal input of the anti-gate G1 becomes a digital digit 0, so that the output of the anti-gate 012 or the LDRJEN signal becomes a digital i. In the embodiment shown in FIG. 9, the timer 802 controls the input state of the SKIP terminal, so that it has the same effect as the timer in FIG. 8. That is, the LDR_EN signal becomes a digital one when the predetermined time interval limit is terminated. Thus, the skip mode is inactive and the low-side switch Q2 is closed at time t2. Once the low-side switch Q2 is closed, the output voltage 25 1243977 begins to drop because the output capacitor C is discharged to ground via the inductor's low-side switching path. When the output voltage drops below the set voltage VSET, for example at 15 o'clock, a new PWM pulse is generated and the process starts again. Advantageously, the timer 802 can select a time limit to ensure the minimum frequency of the PWM pulse in the skip mode, thereby realizing the minimum switching frequency of the switching state. More advantageously, this time limit can also be selected so that the frequency of the PWM pulses is greater than the audible frequency range of the human ear. The average audible frequency range of the human ear is 20 Hz to 20 kHz. To keep the frequency at a minimum of 20 kHz, this time limit can be set to 50 microseconds. In order to keep the frequency at a slightly higher 25 kHz, the time limit can be set to 40 microseconds. Therefore, by properly selecting the time limit of timer 802, the minimum switching of the high-side switch Q1 and the low-side switch Q2 The frequency can be kept in a range, for example, greater than 20 kHz, which is greater than the average frequency range audible to the human ear. Although the timer described herein is used in the controller of a DC / DC converter, those skilled in the art will know that the timer can also be used in various other switching circuits that expect a minimum switching frequency to avoid people The ear can hear the switching noise. The embodiments described here are just a few of the inventions, and are for illustrative purposes only, and are not intended to limit the invention. Obviously, those skilled in the art will be able to think about many other embodiments without departing from the spirit and scope of the present invention as defined by the appended patent claims. [Simplified description of the drawing] 26 1243977 Figure 1A shows a block diagram of a DC / DC (DC-to-DC) converter including a controller according to the present invention; Figure 1B shows the input PWM (pulse width modulation) signal and the low-side enable signal according to the input An exemplary table describing the switching states of the pair of switches in Figure 1A; Figure 2A shows a block diagram of an embodiment of a controller for the DC / DC converter of Figure 1A; Figure 2B shows Shown is a comparison curve describing the change in the charge level of the energy memory element of the controller in Figure 2A and the corresponding change in the inductor current level in the same time interval; 10 Figure 3 is used for Figure 1A A block diagram of another embodiment of a controller of a DC / DC converter; FIG. 4 shows a detailed block diagram of an exemplary delay circuit in FIG. 3; FIG. 5 shows a DC used as the DC in FIG. 1A / DC converter control FIG. 6 is a block diagram of an exemplary dual-phase controller; FIG. 7 is a circuit diagram of an input voltage detection circuit using the LX pin of the controller; FIG. 8 The figure shows a block diagram of another embodiment of the controller with an internal timer for controlling the minimum switching frequency of the present invention; FIG. 9 shows a timer with an external timer for controlling the minimum switching frequency. A block diagram of a switching DC / DC converter; and FIG. 10 shows timing diagrams of the embodiments of FIGS. 8 and 9. [Representative symbols for main components of the diagram] 100 ... DC / DC converter 102, 200, 300 ... Controller 27 1243977 104 ... Driver circuit 106, S1 to S4, 706 ... Switch 108 ... Low-pass filter C, C1 ~ C2, 708 ... Capacitor Cslew ... Swing capacitor L ... Inductor Q1 ... High-side switch Q2 ... Low-side switch R1 ~ R3, 702, 704 ... Resistor Vin ... Input voltage Vout ... Output voltage 120 ... Tables 122, 124 ... Column 202 ... Energy storage element 240 ... Output determination circuits 242, 619 ... Flip-flop REF ... Reference voltage value II ~ 15 ... Current source VI ... critical voltage value V2 ... second reference voltage CMP1 to 4, COMP1 to 6, 306 ... comparator
Gl、G4、G7…反及閘 G2〜G3、G5〜G6、712···及閘 203···電壓位準曲線 205…曲線 302···選通時間單觸發電路 304…低側驅動單觸發電路 308···時間延遲電路 310···反或閘Gl, G4, G7 ... Gates G2 ~ G3, G5 ~ G6, 712 ... Gate 203 ... Voltage level curve 205 ... Curve 302 ... Gating time single trigger circuit 304 ... Low-side drive single Trigger circuit 308 ... Time delay circuit 310 ... Reverse OR gate
Vtarget···輸出目標電壓 400…延遲電路 402···振盪器 404…計數器 406···數位比較器 500、800…控制器 511…連接 600…雙相控制器 602···第一相位控制器 604…第二相位控制器 606···相位選擇電路 700…輸入電壓檢測電路 703".LX 引腳 714…跨導放大裔 740···開關狀態判定電路 742···電壓檢測電路 Q3···電晶體 802···計時器 715···交換節點 tl〜t7···時間/時刻 28Vtarget ... Output target voltage 400 ... Delay circuit 402 ... Oscillator 404 ... Counter 406 ... Digital comparator 500, 800 ... Controller 511 ... Connection 600 ... Two-phase controller 602 ... First phase control 604 ... Second phase controller 606 ... Phase selection circuit 700 ... Input voltage detection circuit 703 " LX pin 714 ... Transconductance amplifier 740 ... Switch state determination circuit 742 ... Voltage detection circuit Q3 ... · Transistor 802 · · Timer 715 · · Switching nodes tl ~ t7 · · Time / Time 28