1243453 七、發明說明· 【發明領域】 本發明係有關於晶圓在完成積體電路後之處理技 術，特別係有關於一種在晶粒表面形成結合黏性之晶圓产 理方法。 【先前技術】 在半導體晶圓完成積體電路並切割成晶粒（die)，依封 裝型態之不同黏貼於各式各樣之基板，如黏貼於另一晶粒 以形成多晶片堆疊體、黏貼於一印刷電路板以進行球格陣 列（Ball Grid Array)之封裝或者是黏貼於導線架之晶墊或 内引指以進行薄小外觀封裝（Thin Small 0utline Paekage) 或四方扁平封裝（Quad Flat Package)，習用之晶粒黏著劑 係為液態熱固性銀膠（Silver paste)或是聚亞醯胺 (polyimide)之固態黏性膠帶。 在美國專利第2〇01/0005935號專利中描述一種多 片杈組之組裝方法’其係先將較大晶片以黏晶機貼附於 基板，再將-較小晶片固定於該較大晶片之上，而用以 ^車乂大曰曰片與較小晶片之黏著劑係為一種液態熱固性 ’或疋1%膠V，$而未能揭露黏{劑係先塗施於較小 片^較大晶^及黏晶與打線之順序，實際上，當黏著 ^、用種液恶熱固性黏膠，由於液態熱固性黏膠在黏 —”有机動性’故無法預先塗施於較小晶片(上晶片) 二易污染較大晶片(下晶片)之焊塾，同時在較大晶片上 ’…固性黏膠必須進行在打線之前，因為打線形成 4 1243453 火干線無法再放置網版，使得多晶片封裝之加工限制相當 夕’當黏著劑係選用一種固態膠帶，不但成本較高，在多 曰曰片封装時’固態膠帶係具有雙面黏性，一旦黏貼於較小 曰曰片之下表面，即使得較小晶片具有黏性，如晶片翻轉、 移動或勝帶之成形與定位，不適用於晶圓級之黏性處理， 同守為了在母一顆晶片上黏附一膠帶所需要的設備與花 費時間，均不符成本。 【發明目的及概要】 本卷明之主要目的在於提供一種在晶粒表面形成結 口黏性之晶圓處理方法，利用在晶圓上大面積塗佈一具兩 階段特性之黏膠，並預烤該具兩階段特性之黏膠使其達到 固態不具有流動性及黏性之B階段（B-Stage)膠膜，在切割 後可得到大量複數個具有黏性之晶粒，以降低黏晶成本。 一本發明之次一目的在於提供一種在晶粒表面形成結 T黏性之晶圓處理方法，利用在晶圓上印刷形成一具兩階 奴特性之黏膠，並預烤該具兩階段特性之黏膠使其在室溫 達到固態不具有流動性及黏性之B階段⑺膠膜，在 切割後可得到具有熱結合黏性之晶粒，其具有良好之可加 工性，以供各種型態之半導體封裝製造。 队不贫明之在晶粒表面形成 馬了達到上述之 合黏性之晶圓處理方法，其係提供一完成積體電路之半 體晶圓’該晶圓具有一表面’其係可為主動表面或非主 表面’在肖晶圓之該表面均句塗佈—層具兩階段特性之 體，如網版印刷（screen printing)、鋼版印刷pdnti 5 1243453 或離心塗佈（spin coating)，使該具兩階段特性之膠體局部 或元全塗佈於该晶圓之該表面，在一較佳具體實施例中， 該具兩階段特性之膠體係局部塗佈於該晶圓之該表面，以 不覆蓋晶圓之切割道或焊墊，之後預烤該晶圓，使該具兩 P白#又特性之膠體在室溫達到固態不具流動性及黏性之B階 段（B-stage)膠膜，此時，該具兩階段特性之膠體仍未完全 熱固化反應而具有熱結合之黏性，以供翻轉或黏晶機吸附 之加工，在切割成晶粒後，得到表面形成有熱結合黏性之 晶粒，以黏貼至一基板，該基板可為另一晶粒、印刷電路 板陶瓷電路基板或導線架，以低成本高效率地廣泛運用 於晶片堆疊或各種封裝時基板之黏貼。 【發明詳細說明】 睛參閱所附圖式，本發明將列舉以下之實施例說明： 如第1圖所示，本發明之在晶粒表面形成結合黏性之 晶圓處理方法係包含之主要步驟係有：「提供晶圓」u、「塗 佈具兩階段特性之膠體」12、「預烤晶圓」13、「翻轉晶圓」 14及.「切割晶圓」，其詳述如下：1243453 7. Description of the invention · [Field of the invention] The present invention relates to the processing technology of a wafer after the integrated circuit is completed, and particularly relates to a wafer production method for forming bonding adhesion on the surface of a die. [Previous technology] Complete integrated circuits on semiconductor wafers and cut them into dies, and stick them to various substrates depending on the package type, such as sticking to another die to form a multi-chip stack, Adhering to a printed circuit board for Ball Grid Array packaging, or attaching to a lead pad crystal pad or internal lead for thin small package (Thin Small 0utline Paekage) or Quad Flat Packaging (Quad Flat) Package), the conventional grain adhesive is a liquid thermosetting silver paste (Silver paste) or a polyimide solid adhesive tape. A method for assembling a multi-chip branch set is described in US Patent No. 2001/0005935, which involves attaching a larger wafer to a substrate with a die attacher, and then fixing a smaller wafer to the larger wafer. Above, and the adhesive used for ^ car 乂 big and small tablets and small wafers is a liquid thermosetting 'or 疋 1% glue V, $, but failed to expose the adhesive {The agent is first applied to the smaller tablets ^ Larger crystal ^ and the order of sticky crystals and wire bonding. In fact, when the adhesive ^ is used, the liquid thermosetting adhesive is used. Because the liquid thermosetting adhesive is sticking-"has mobility", it cannot be applied to smaller wafers in advance ( (Upper wafer) Second, the solder joints of the larger wafer (lower wafer) are easy to contaminate, and at the same time on the larger wafer, '... the solid adhesive must be carried out before the wire bonding, because the wire formation 4 1243453 fire trunk line can no longer be placed on the screen, making more The processing limitation of the chip package is quite 'when the adhesive is a solid tape, it is not only costly. In the case of multi-chip packaging, the solid-state tape is double-sided, and once it is adhered to the surface of the smaller chip, , Even making smaller wafers sticky, such as wafer flipping The forming and positioning of moving or winning tapes are not suitable for wafer-level adhesive processing, and the equipment and time required to attach an adhesive tape to a mother wafer are not consistent with the cost. [Objective and Summary of the Invention] The main purpose of this volume is to provide a wafer processing method for forming junction viscosity on the surface of the die. A large area of the wafer is coated with a two-stage adhesive, and the two-stage characteristic is pre-baked. The viscose allows it to reach a solid B-Stage film without fluidity and viscosity, and a large number of viscous crystal grains can be obtained after cutting to reduce the cost of viscous crystals. One purpose is to provide a wafer processing method for forming junction T-adhesion on the surface of a die, by printing on the wafer to form a two-stage slave adhesive, and pre-baking the two-stage adhesive adhesive. Reaching solid B-stage adhesive film without fluidity and viscosity at room temperature, after cutting, crystal grains with thermal bonding can be obtained, which has good processability for various types of semiconductor package manufacturing . team The poor formation of the wafer processing method to achieve the above-mentioned cohesiveness on the surface of the die is to provide a half-body wafer that completes the integrated circuit. 'The wafer has a surface', which can be an active surface or a non- The main surface is uniformly coated on the surface of the Xiao wafer-the layer has two-stage characteristics, such as screen printing, stencil printing pdnti 5 1243453, or spin coating, so that the The two-stage characteristic colloid is partially or fully coated on the surface of the wafer. In a preferred embodiment, the two-stage characteristic gel system is partially coated on the surface of the wafer so as not to cover. The dicing path or pad of the wafer, and then pre-bake the wafer, so that the colloid with two P white # and characteristics reaches a solid B-stage film with no fluidity and viscosity at room temperature. At the same time, the two-stage colloid has not fully thermally cured and has thermally bonded viscosity for processing by inversion or adsorption by a sticky crystal machine. After cutting into grains, a thermally bonded viscosity is formed on the surface. Die to adhere to a substrate, which can be another A die, printed circuit board, ceramic circuit board, or lead frame is widely used at low cost and high efficiency for substrate bonding during chip stacking or various packages. [Detailed description of the invention] With reference to the drawings, the present invention will enumerate the following examples: As shown in FIG. 1, the wafer processing method of the present invention for forming a cohesive bond on the surface of a die includes the main steps There are: "provide wafers" u, "coated with two-stage characteristics of colloids" 12, "pre-baked wafers" 13, "flip wafers" 14 and "cut wafers", which are detailed as follows:
表面lll(inactive surface)及複數個未分離並而呈一體之 晶粒113，其中焊墊115係位於晶粒1 113四周係為筆直之切割道114，依封 圓110欲形成黏性之表面可為主動表面 113之周邊，在晶粒 依封裝製程之需求，晶 表面112或非主動表面 1243453 111，在本實施例中，當預定在晶圓110之非主動表面1U 形成黏性，則該非主動表面111係朝上，之後，進行「塗 佈具兩階段特性之膠體」12之步驟，如第3B圖所示，以 網版印刷（screen printing)、鋼版印刷（stencil prinUn幻或離 心塗佈（spin coating)方法局部或完全塗佈形成一種具兩階 段特性之膠體130，其係先在晶圓n〇之非主動表面 放置一網版121，再以刮刀122將該具流動性並具兩階段 特性之膠體130印刷至該非主動表面m，在本實施例中， 網版121係覆蓋晶圓11〇之切割道114，使得該具兩階段 特性之膠體130局部印刷於該晶圓11〇之該非主動表面 111而不覆蓋切割道Π4,在第一實施例中所形成具局部 結合黏性之晶粒係供晶片堆疊，具兩階段特性之膠體130 在不同狀悲係呈現不同特性，其包含有熱固性聚合物如 聚亞醯胺（polyimide)、聚啥琳（p〇lyquin〇lin)或苯環丁稀 (benzocyclobutene)，由於該兩階段之膠體13〇在塗施時係 具有A階段（A-sUge)之特性，其呈液態以利印刷成形。 然後，進行「預烤晶圓」13之步驟，如第3^圖所示， 將阳圓110放置於一烤箱，加熱至一適當溫度，以局部熟 化=兩P皆段之膠體130至B階段〔B_stage〕，此係針料 有環氧化合物之具兩階段特性之膠體130，不同之熱固性 聚合物應調整其適當之預烤溫度及條件，使在晶圓110之 非主動表面ill上之具兩階段特性之膠體13〇形成一種不 埶桃動性之乾膜，在本實施例中，可另執行一真空乾燥加 “、、此時，在晶圓110之具兩階段特性之膠體i30係具有 1243453 即在室溫下成為不具有流動性與The surface lll (inactive surface) and a plurality of undivided and integrated grains 113, of which the pad 115 is located around the grain 1 113 is a straight cutting path 114, and the surface to be adhered according to the sealing circle 110 may be For the periphery of the active surface 113, the crystal surface 112 or the non-active surface 1243453 111 depends on the needs of the packaging process. In this embodiment, when it is planned to form the adhesive on the non-active surface 1U of the wafer 110, the non-active surface The surface 111 is facing upward, and then the step of "coating the colloid with two-stage characteristics" 12 is performed, as shown in Fig. 3B, by screen printing, stencil prinUn or centrifugal coating. The (spin coating) method is used to partially or completely coat to form a colloid 130 with two-stage characteristics, which is to first place a screen 121 on the non-active surface of the wafer n0, and then use a doctor blade 122 to flow the The colloid 130 with stage characteristics is printed on the non-active surface m. In this embodiment, the screen plate 121 covers the cutting track 114 of the wafer 110, so that the colloid 130 with two-stage characteristics is partially printed on the wafer 110. The non-active table 111 does not cover the cutting path Π4. In the first embodiment, a grain system with local bonding viscosity is formed for wafer stacking. The colloid with two-stage characteristics 130 exhibits different characteristics in different states, including thermosetting polymerization. Such as polyimide, polyquinol or benzocyclobutene, since the two-stage colloid 13 has A-sUge at the time of application It is in a liquid state to facilitate printing and forming. Then, the "pre-bake wafer" 13 step is performed, as shown in Figure 3 ^, the male circle 110 is placed in an oven and heated to an appropriate temperature to partially mature. = Colloids 130 to B in both P stages [B_stage]. This is a colloid 130 with two-stage characteristics of epoxy compounds. Different thermosetting polymers should be adjusted to their proper pre-baking temperature and conditions so that The colloid 13 with two-stage characteristics on the non-active surface ill of the wafer 110 forms a dry film that is not susceptible to peach motion. In this embodiment, a vacuum drying can be performed. The two-stage colloid i30 series of Yuan 110 has 1243453 that it does not have fluidity at room temperature and
B階段（B-stage)之特性， 黏性之B階段膠膜，可名 裝之如工’然而彳乃且古為 114切割晶圓110,以構成複數個具有熱結合黏性之晶粒 113不但可低成本快速提供並可供各種封裝使用。如第 3E圖所示，在本實施例中，可先將另一晶粒16〇黏固於一 基板170,並打線將焊線162電性連接晶粒16〇之焊墊i6i 至基板170,將該具有熱結合黏性之晶粒113以黏晶機 bonder)吸附起來並以該具兩階段特性之膠體13〇黏附至 另一晶粒160 ’可完成一晶片堆疊體（如第3f圖所示），在 黏合後該具兩階段特性之膠體13〇仍i未完全熱固化反 應’然後’打線將焊線180電性連接晶粒113之焊墊115 至基板170 ’本發明之在晶粒表面形成結合黏性之晶圓處 理方法可供晶片堆疊黏結，在不同實施例中亦可供一般封 裝之黏晶結合，在「塗佈具兩階段特性之膠體」12之步驟， 以離心塗佈或全面印刷方法完全塗佈形成一層具兩階段 8 1243453 特（生之膠體於晶圓之非主動表面，並經預烤、翻轉跟切割 步驟後’得到多個在非主動表面具有熱結合黏性之晶粒， ^ptL·襄占空 甘 /…B芏一基板，由於具兩階段特性之膠體在預烤後不 如省用之銀膠般具有高流動性，因此，基板之連接墊與晶 粒之間的間隔可縮短，使得基板之尺寸更進一步縮小，以 適用於晶片尺寸封裝（Chip Scale Package)。 為使了解本發明係不局限晶圓之印刷表面，在第二具 體實施例中’如第4 A圖所示，首先提供-晶BI 21 〇，該 晶圓210具有一形成有焊墊215(或凸塊）之主動表面211、 一對應之非主動表面212及複數個晶粒213,其中焊墊215 係在對應晶粒213之中央位置，該主動表面211係朝上， 之後，如第4B圖所示，以網版印刷或鋼版印刷方法形成 一種具兩階段特性之膠體23〇於主動表面211，其係先在 晶圓210之主動表面211放置一網版221，再以刮刀Μ] 將該具流動性並具兩階段特性之膠體2 3 〇印刷至該主動表 面212，在本實施例中，網版221係覆蓋晶圓21〇之焊墊 215，使得該具兩階段特性之膠體23〇局部印刷於該晶圓 210之該主動表面212。 然後，如第4C圖所示，預烤該晶圓21〇，使在晶圓 210之主動表面211上之具兩階段特性之膠體23〇形成— 種不具流動性之乾膜’即在室溫下成為不具有黏性之膠 膜，可供堆疊搬運或儲放，但仍具有熱結合（thermai bonding)之黏性。接著，如第4D圖所示，將晶圓21〇翻轉， 使得主動表面211朝下並貼合至一定位膠帶24〇,在固定 !243453 曰曰圓210後，利用切割刀具25〇沿切割道切割晶圓 ^邝，以構成複數個在主動表面211具有熱結合黏性之晶 2 213，不但可低成本快速提供並可供各種封裝使用。如 第4E圖所示，在本實施例中可將該具有熱結合黏性之晶 粒213以黏晶機吸附並以該具兩階段特性之膠體23〇黏附 至一如印刷電路才反260 3戈陶究電路基板之基才反，僅需數秒 寺門即陕速黏合至一基板，並經打線焊線262、壓模 封膠體263及結合焊球261 |，建構成—球袼陣列（bga) 之封裝結構（如第4F圖所示）。 匕卜在本發明之第二具體實施例中，其前段步驟係 如同第二具體實施例之第4A至40:圖，之後，如第5圖所 不，在預烤該晶圓210後，直接以晶圓21〇之非主動表面 212黏貼至一定位膠帶24〇，其晶圓21〇之主動表面 係朝上，在切割成個別之晶粒213後，如第6圖所示，吸 寸:曰粒213至一載台Μ，再以一 L〇c(Lead 〇n_chip)導 線架之内引指271往下黏貼該具兩階段特性之膠體23〇， 以結合晶片213與具有引腳270之導線架，在打線形成焊 線274、壓模形成封膠體273與導線架修剪成形之後，而 製備1薄小外觀封裝（Thin Small 〇utHne packag勾或四 方扁平封裝（Quad Flat Package)之封裝結構（如第7圖所 不），因此，本發明之在晶粒表面形成結合黏性之晶圓處理 方法係可大量並低成本地製造具有熱結合黏性之晶粒，以 供後段之封袭製程。 故本發明之保護範圍當視後附之申請專利範圍所界 10 1243453 ’在不脫離本發明之精神 ’均屬於本發明之保護範 定者為準，任何熟知此項技藝者 和範圍内所作之任㈣化與修改 圍。 【圖式說明】 第 1 圖： 第 2 圖·· 第3A至3F圖 •本發明之在晶粒表面形成結合黏性之晶圓 處理方法之流程圖； 依本發明之在晶粒表面形成結合黏性之晶 圓處理方法，所提供晶圓之正視圖； :依本發明之第一具體實施例，在晶粒表面 形成結合黏性之晶圓處理方法中流程之 截面示意圖； 第4A至4F圖：依本發明之第二具體實施例，在晶粒表面 形成結合黏性之晶圓處理方法中流程之 截面示意圖； 第 5 圖：依本發明之第三具體實施例，在晶粒表面 形成結合黏性之晶圓處理方法中晶圓之 非主動表面黏設於定位膠帶以供切割之 截面示意圖； 第 6 圖·依本發明之第三具體實施例，在晶粒表面 形成結合黏性之晶圓處理方法中已切割 之晶粒黏设一導線架之截面示意圖；及 第 7 圖：依本發明之第三具體實施例，在晶粒表面 形成結合黏性之晶圓處理方法中已切割 之晶粒應用於一封裝結構之截面示意圖。 11 1243453 【圖號說明】 _ 11 提供晶圓 13 預烤晶圓 110晶圓 • 111非主動表面 • 114切割道 121網版 130具兩階段特性之 150切割刀具 16 0晶粒 170基板 210晶圓 211主動表面 214切割道 221網版 230具兩階段特性之 250切割刀具 260印刷電路板 263封膠體 270弓丨腳 273封膠體 塗佈具兩 ^皆段特性之膠體 翻轉晶圓 15 切割晶圓 主動表面 113 晶粒 焊墊 刮刀 140 定位膠帶 焊墊 162 焊線 焊線 非主動表面 213晶粒 焊墊 刮刀 240定位膠帶 焊球 262焊線 内引指 272載台 焊線 12The characteristics of B-stage, the adhesive B-stage adhesive film can be installed as it is. However, it is 114 to cut the wafer 110 to form a plurality of crystal grains 113 with thermal bonding. Not only can it be provided quickly and cost-effectively, but also in various packages. As shown in FIG. 3E, in this embodiment, another die 160 may be adhered to a substrate 170, and a wire 162 may be electrically connected to the pad i6i of the die 16 to the substrate 170. The heat-adhesive die 113 is bonded with a die bonder and adhered to another die 160 with the two-stage colloid 13 ′ to complete a wafer stack (as shown in FIG. 3f). (Shown), after the two-stage colloid 130 has not been completely thermally cured after bonding, and then the wire 180 is electrically connected to the bonding pad 115 of the die 113 to the substrate 170 'the on-die of the present invention A wafer processing method for forming a bond on the surface can be used for wafer stacking and bonding. In different embodiments, it can also be used for bonding of ordinary packages. In the step of "coating a colloid with two-stage characteristics," it can be coated by centrifugation. Or the full printing method is applied to form a layer with two stages of 8 1243453 (raw colloid on the non-active surface of the wafer, and after pre-baking, turning and cutting steps), a plurality of non-active surfaces have thermal bonding viscosity. Crystal grains, ^ ptL · Xiang Kongkong / ... B 芏Since the colloid with two-stage characteristics does not have the high fluidity after pre-baking, as compared with the saving silver glue, the interval between the connection pads of the substrate and the crystal grains can be shortened, which further reduces the size of the substrate to apply to Chip Scale Package. In order to understand that the present invention is not limited to the printed surface of a wafer, in the second specific embodiment, 'as shown in Figure 4A, first-the wafer BI 21 〇, the wafer 210 has an active surface 211 formed with a solder pad 215 (or a bump), a corresponding non-active surface 212 and a plurality of grains 213, wherein the solder pad 215 is at the center of the corresponding grain 213, and the active surface 211 The system faces upward, and then, as shown in FIG. 4B, a two-stage colloid 23 is formed on the active surface 211 by screen printing or stencil printing, which is first placed on the active surface 211 of the wafer 210. The screen plate 221 is then printed on the active surface 212 with a fluidity and two-stage characteristics by a doctor blade M]. In this embodiment, the screen plate 221 is a pad 215 covering the wafer 21 To make the glue with two-stage characteristics 23 ° is partially printed on the active surface 212 of the wafer 210. Then, as shown in FIG. 4C, the wafer 21 is pre-baked to make the colloid 23 with two-stage characteristics on the active surface 211 of the wafer 210 〇Formation—A kind of non-fluid dry film, that is, a non-adhesive adhesive film at room temperature, which can be stacked or stored, but still has the adhesiveness of thermal bonding. As shown in the 4D figure, the wafer 21o is turned over, so that the active surface 211 faces downward and is attached to a positioning tape 24o. After fixing! 243453, said circle 210, the wafer is cut along the dicing path with a cutting tool 25o ^ Alas, to form a plurality of crystals 2 213 with thermal bonding adhesiveness on the active surface 211, not only can be quickly provided at low cost and can be used in various packages. As shown in FIG. 4E, in this embodiment, the crystal grains 213 having thermal bonding viscosity can be adsorbed by a crystal stick machine and adhered to the printed circuit circuit with the two-stage colloid 23. 260 3 Ge Tao researched the foundation of the circuit board. It only took a few seconds for the gate to be bonded to a substrate, and then wire bonding wire 262, die-molded gel 263, and combined solder balls 261 | were constructed-ball array (bga) Package structure (as shown in Figure 4F). In the second specific embodiment of the present invention, the steps in the first stage are the same as in the fourth specific embodiment of FIGS. 4A to 40: after, as shown in FIG. 5, after pre-baking the wafer 210, directly The non-active surface 212 of the wafer 21 is adhered to a positioning tape 24o, and the active surface of the wafer 21 is faced up. After cutting into individual grains 213, as shown in FIG. 6, the suction is: The granules 213 to a stage M are then pasted with the lead 271 of a Loc (Lead 〇n_chip) lead frame 271 to adhere the two-stage colloid 23o to combine the wafer 213 and the pin 270 The lead frame is prepared by forming a bonding wire 274, forming a sealant 273 by compression molding, and trimming the lead frame to prepare a thin small package (Thin Small Outlet Packag or Quad Flat Package) package structure ( (As shown in FIG. 7). Therefore, the wafer processing method for forming bonding stickiness on the die surface of the present invention can manufacture a large number of low-temperature bonding sticky grains at a low cost for the subsequent sealing process. Therefore, the scope of protection of the present invention Jie 10 1243453 "Without departing from the spirit of the present invention" belongs to the protection scope of the present invention. Any person skilled in the art and the scope of any changes and modifications within the scope. [Illustration of the diagram] Figure 1 : Fig. 2 · · Figs. 3A to 3F · Flow chart of the wafer processing method for forming bonding adhesion on the surface of the die according to the present invention; wafer processing method for forming bonding adhesion on the surface of the die according to the present invention, Front view of the provided wafer ;: Schematic cross-sectional views of the flow of a wafer processing method for forming a bonding adhesive on the die surface according to the first embodiment of the present invention; Figures 4A to 4F: Figures 2A to 4F according to the second embodiment of the present invention In a specific embodiment, a schematic cross-sectional view of a flow in a wafer processing method for forming a cohesiveness on a die surface; FIG. 5: A wafer processing method for forming a cohesiveness on a die surface according to a third specific embodiment of the present invention A schematic cross-sectional view of a non-active surface of a middle wafer bonded to a positioning tape for cutting; FIG. 6 • According to a third specific embodiment of the present invention, the wafer has been cut in a wafer processing method for forming adhesiveness on the surface of a die. A schematic cross-sectional view of a die bonded with a lead frame; and FIG. 7: According to a third embodiment of the present invention, a die that has been cut in a wafer processing method for forming a bond on a die surface is applied to a package Sectional schematic diagram of the structure. 11 1243453 [Illustration of drawing number] _ 11 Provide wafers 13 Pre-baked wafers 110 wafers • 111 non-active surfaces • 114 cutting lanes 121 stencils 130 two-stage 150 cutting tools 16 0 grains 170 substrate 210 wafer 211 active surface 214 cutting path 221 screen plate 230 250 cutting tool with two-stage characteristics 260 printed circuit board 263 sealing gel 270 arch 丨 foot 273 sealing colloid coating colloid flip wafer with two characteristics 15 Active surface for dicing wafer 113 Die pad scraper 140 Positioning tape pad 162 Welding wire non-active surface 213 Die pad scraper 240 Positioning tape solder ball 262 Inner finger 272 stage welding wire