1242648 A7 -—_____B7___ ___ 五、發明說明（j ) 本發明之背景 本發明一般而言有關於電容之量測，而更特別的是’ 有關於藉由傳送已知數値的電荷封包給予未知數値的電容 器，直到最終電壓被判斷出爲止，並且之後基於已知的總 電荷以及所量測到的電壓來計算電容値，如此進而量測其 電容。 電容量測乃是測量儀器的一種重要的特點，諸如數位 電錶。皆讓與Fluke股份有限公司的美國專利第5073757 號以及美國專利第5136251號揭示測量小與大電容的方法 ，其中容許一個未知的電容器在其RC速率下完全充飽電 荷至一參考電壓，在相同的時間下正比於充電電流的電流 會累加於雙斜率積分的類比至數位轉換器(ADC)之儲存電 容器上。小電容可能僅在ADC的一個積分週期中便會完全 充飽電荷，而大電容需要數個積分週期方能完全充飽電荷 。在兩種情形下，儲存於積分ADC的儲存電容器上之比例 電荷會在所儲存的電荷量所決定的時間週期之“解除積分” 週期期間內移除，而且測量其時間，藉以給定電容値的指 示。 由於等待未知的電容器完全充飽電荷所導致的太過冗 長之量測時間，因而習知技術的電容量測技術乃是不符合 要求的，此導致揭示於1999年3月12日申請之審理中的 美國專利申請案序號第09/267504號中之電容量測系統的 發展，其中一個定電流源被用來產生跨於所要測量的電容 器上之線性斜坡電壓。如此則允許測量差値電壓（△▽)以及 —___— ____3_ 本度適用中國國家標準（CNS)A4規格（210 X 297公釐) '~" (請先閱讀背面之注意事項再B本頁) --------訂---------· 1242648 A7 --- -B7____ 五、發明說明（/ ) 差値時間（ΔΤ)，進而從其比率來計算電容値。儘管就大範 圍的電容器而言，改善了量測速度以及準確度兩者，然而 使用複雜的多斜率類比至數位轉換器來蒐集所需的參數， 其仍是相當緩慢的處理過程。 所有這些習知技術方法的問題乃是由於電容器的數値 未知，因而相當大的努力耗費在尋找能夠量測的適當範圍 上。同樣的是，特別接近所給定範圍的低値末端，由於解 析度的壓縮，其電容値便可能會失真。 本發明之槪要 根據本發明，提供一種測量電容的裝置及方法，其中 將已知數値的電荷封包傳送至未知數値的電容器直到判斷 出最終電壓爲止，而且基於已知的總電荷以及所量測到的 電壓來計算其電容。 對熟知此項技術者而言，經由閱讀以下結合附圖的說 明，本發明其他的目的、特性、以及優點將會是明白的。 附圖之簡略說明 圖1爲電容器相關的基本電流與電壓關係圖示，有助 於了解本發明； 圖2爲根據本發明的容量測系統之方塊圖； 圖3爲適用於圖2系統的可程式的定電流源之槪賽表 示圖；以及 圖4爲顯示圖2系統的操作之程式列表。 _ -_— Δ____ 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公S ) ----^ -------I---------1---二π·--------. (請先閱讀背面之注意事項再^一·本頁) A7 電容器 輸入端 可程式的定電流源 放電開關 比較器 類比至數位轉換器(ADC) 微處理器（μΡ) 記憶體 顯示裝置 定電流產生器 AND邏輯閘 η選1的選擇器 可選擇的脈波寬度產生器 1242648 _ B7 五、發明說明) 附圖之元件符號說明 10 12 14 16 18 20 24 26 28 30η 32η 34 36 本發明之細節說明 圖1乃是提供來輔助了解本發明之原理，其並且顯示 與電容器有關的基本之電流與電壓關係。電容在教科書上 的定義爲電壓-電流關係1 = c de/dt，電容器的電壓可以從 之而定義爲e(t)= ^J^dt此提供一種眾所周知的觀念之理解 ，即如果傳送至電容器的電流爲定値，則其電壓便會隨著 電容器以時間積分該固定電流而呈現線性變化。此能夠於 圖1觀察到，其中定電流1在整個時間區間ΔΤ中傳送， 而導致一斜坡電壓Δν。同樣的是，電流積分於任何的時 _5___ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再本頁) --------訂---------線· A7 1242648 -------- -B7__ _ 五、發明說明（令） 間區間則爲累加於電容器中的電荷Q，或者Q = pdt。因 ‘此’可以說圖1的電流波形所包圍的面積等於所累積的電 荷Q。最後，由於Q = CV，因此能夠得知如果所累加的電 荷Q以及跨於電容器上的電壓Δν是已知的，便能夠計算 其電容値C。 圖2爲根據本發明的電容量測系統槪要圖，用以測量 連接到一輸入端12的電容器10之電容値。同樣連接到輸 入端12的是一可程式的定電流源14、一放電開關16、-比較器18、以及一類比至數位轉換器(ADC)20。在動作上 連接到所有這些裝置的是微處理器（μΡ)24，其包含一個與 之結合的記憶體26以及一個顯示裝置28。 儘管對熟知此項技術者而言，圖2所有的電路元件乃 是眾所周知的，然而可程式的定電流源14的一些細節乃是 爲了滿足其目的所爲的。關於可程式的定電流源14的一種 方式乃是由於其傳送定電流量⑴給予電容器10-段特定的 時間區間（dt)，因此實際上則是一種電荷封包產生器。適用 的可程式的定電流源之細節顯示於圖3。所示的乃是多數 個的定電流產生器30A、30B、30C、…、30η，每一個皆 會產生不同的已知或者預定之定電流數値。這些數値可能 以任何所需的順序增加，例如，以二進制的順序，諸如1 微安培(μΑ)、2μΑ、4μΑ、8μΑ等等，或者以其他的任何順 序，諸如ΙμΑ、2μΑ、5μΑ、ΙΟμΑ等等，視能夠利用的特 定系統以及適用的時間區間之效用而定。連接到每一個定 電流產生器30Α、30Β、30C、…、30η的是個別的AND邏 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再®:本頁) --訂·--------一 A7 1242648 ___B7 _____ 五、發明說明（〈） 輯閘 32A、32B、32C、…、32η。每一個 AND 邏輯閘 32A- 32η的輸入來自n選1的選擇器34，其可能是一種位址計 數器，用以選擇其中一個定電流產生器30Α-30η。每〜個 AND邏輯閘32Α-32η的另一個輸入則是來自可選擇的脈波 寬度產生器36，當其受到促動時，便會提供所選擇或所預 定的寬度之脈波，藉以閘控所選擇的定電流產生器作用一 段正確的已知時間區間。η選1的選擇器34以及脈波寬度 產生器36的輸入是由微處理器24所提供的。因此，能夠 察知的是，爲了傳送電荷封包q〇給予電容器10，微處理器 24·會選擇那一個電流產生器將會閘控而作用，並且選擇那 一段時間區間來提供所需的數値qG = fidt充當可程式的 定電流源14的輸出。 圖2系統用以決定電容器10的電容數値之操作將結合 圖4所示的程式來說明之。 在步驟40，微處理器24會將系統初始化。比較器18 的(+)輸入藉由VREF(0)的施加而被設定爲略高於零，並且 將放電開關16閉合。在電容器10上的任何電壓會經由開 關16放電。 在步驟42，藉由監視比較器18的輸出，微處理器24 便會檢視電容器10是否放電。如果電容器的電壓低於在步 驟40所設定的臨界電壓，比較器18的輸出將會是高態， 此係發訊給微處理器24告知電容器的電壓小於VREF(0)。 之後則將放電開關開路。 所要點出的是，比較器18在此用來充當一種電壓監視 - —-____2____ ____ 本紙張尺度適用中國國家標準（CNtS)a4規格（210 X 297公釐） (請先閱讀背面之注意事項再1®本頁) --------訂---------線· 1242648 A7 --—_______B7 ___ 五、發明說明（& ) 裝置，藉以監視與臨界電壓比較的電容器電壓。如同熟知 此項技術者所認知的，比較器可以一種高速的ADC來替代 ，而且電壓的臨界位準會設定於與微處理器24相結合的朝 體或軟體。 在步驟44，藉由ADC 20來測量跨於電容器10上的 電壓Vc(())，並且將之儲存於記憶體26。能夠調整實際的讀 取時間，以便提供介電性吸收效應，而隨著微量電荷重新 分布於電容器物理之內，導致電容器電壓微量的增加。在 如此的情況下，開關16會再一次閉合一段短的時間區間， 藉以移除殘留的電荷，並且之後會再一次開路以便能夠從 事新的Vc(。)讀値。 再者，如果以高速ADC來替代比較器18，則ADC便 會執行兩者工作，其中兩比較器18以及ADC 20可以由單 一個高速的ADC來替代之。程式能夠指示已經達到臨界， 並且儲存ADC讀値。 在步驟46，藉由選擇可程式的定電流源14的適當的 電流位準以及間隔組合，微處理器24便會選擇最低有效的 電荷封包數値q〇，並且設定比較器18在略低於ADC 20滿 刻度輸入規格一半的電壓VREF下跳動。 在步驟48，隨著監視電壓比較器18的輸出，微處理 器24指示來自可程式的電流源14的電流給予電容器10 — 整段已知的時間區間，藉以將電荷封包q〇置於電容器之上 〇 在步驟50，如果比較器18無法跳動，則意謂著傳送 -------8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------^---------線 (請先閱讀背面之注意事項再0本頁) 1242648 Δ7 Α7 ___Β7___ 五、發明說明（7 ) 至電容器10的電荷封包還不夠產生達到步驟46所設定的 跳動位準之電壓。如果比較器18跳動，則意謂著置於電容 器10上的電荷會產生等於或者大於步驟46所設定的跳動 位準之電壓。 在步驟52，如果電壓比較器18並不會在電荷qQ置於 其上之後跳動，則會重複步驟48致使電容裝置有置於其上 的電荷Q = q〇 +q〇。如果傳送到電容器10的新電荷封包仍 然不夠產生達到跳動位準的電壓，則微處理器24便會選擇 一電流位準/時間區間組合，藉以提供新的電荷封包qi = 2q0，並且導引此電荷傳送至電容器10。重複步驟48、50 、以及52直到電容器10上的總電荷Q產生用以跳動比較 器18，此係指示由電容器10所產生的電壓是在ADC 20特 定的操作視窗一半與滿刻度的某個點上。微處理器24會追 蹤傳送至電容器10的電荷封包，並且將總電荷Q儲存於 記憶體26之中。 如果比較器18在預定的時間區間之後仍然無法跳動， 則測試便會由於其意謂著電容器因某種原因不能取得電荷 而終止；其中該預定的時間區間是允許數種藉以找到電流 位準/時間區間組合之嘗試，而其電流位準/時間區間組合 會則產生足夠跳動比較器18的電壓。 在步驟54，於比較器18跳動之後，微處理器24便會 致能ADC 20，以便測量電容器10上的最終電壓Vc⑺。在 一段短時間後從事第二次讀値，藉以驗證最終電壓VC(F)相 同於第一次的値，因爲如果微低的話，則指示出一種小量 . --------訂---------i (請先閱讀背面之注意事項本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1242648 A71242648 A7 --- _____B7___ ___ V. Description of the invention (j) Background of the invention The invention generally relates to the measurement of capacitance, and more specifically, 'is related to giving an unknown number by transmitting a charge packet of a known number 値' Until the final voltage is determined, and then calculate the capacitance 基于 based on the known total charge and the measured voltage, and then measure its capacitance. Capacitance measurement is an important feature of measuring instruments, such as digital electricity meters. Both US Patent No. 5073757 and US Patent No. 5136251 to Fluke Co., Ltd. disclose methods for measuring small and large capacitances, which allow an unknown capacitor to be fully charged at a RC rate to a reference voltage at the same The current that is proportional to the charging current at this time will be accumulated on the double-slope integral analog-to-digital converter (ADC) storage capacitor. Small capacitors may be fully charged in only one integration cycle of the ADC, while large capacitors require several integration cycles to be fully charged. In both cases, the proportional charge stored on the storage capacitor of the integrating ADC will be removed during the “unintegrate” period of the time period determined by the amount of stored charge, and its time will be measured to give a given capacitance 値Instructions. Because the waiting time for the unknown capacitor to be fully charged is too long, the capacitance measurement technology of the conventional technology is not in compliance with the requirements. This led to the disclosure in the trial of the application on March 12, 1999. The development of the capacitance measurement system in US Patent Application Serial No. 09/267504, where a constant current source was used to generate a linear ramp voltage across the capacitor to be measured. In this way, it is allowed to measure the differential voltage (△ ▽) and —___— ____3_ This standard is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) '~ " (Please read the precautions on the back before B page ) -------- Order --------- · 1242648 A7 --- -B7 ____ V. Description of the invention (/) Rated time (ΔΤ), and then calculate the capacitance 从 from its ratio. Although a wide range of capacitors improves both measurement speed and accuracy, using a complex multi-slope analog-to-digital converter to gather the required parameters is still a relatively slow process. The problem with all these conventional techniques is that because the number of capacitors is unknown, considerable effort is expended in finding the appropriate range that can be measured. Similarly, the capacitors may be distorted due to the compression of the resolution, particularly close to the low chirp end of the given range. According to the present invention, according to the present invention, a device and method for measuring capacitance are provided, in which a known number of charge packets are transferred to a capacitor of an unknown number until a final voltage is determined, and based on the known total charge and amount Measure the voltage to calculate its capacitance. For those skilled in the art, other objects, features, and advantages of the present invention will be apparent by reading the following description in conjunction with the accompanying drawings. Brief Description of the Drawings Figure 1 is a diagram showing the relationship between the basic current and voltage of a capacitor, which is helpful to understand the present invention; Figure 2 is a block diagram of a capacity measurement system according to the present invention; Figure 3 is a A diagram of a constant current source of the program is shown; and FIG. 4 is a list of programs showing the operation of the system of FIG. 2. _ -_— Δ ____ This paper size applies to China National Standard (CNS) A4 (210 X 297 male S) ---- ^ ------- I --------- 1 --- Two π · --------. (Please read the precautions on the back first and then ^ one page) A7 Programmable constant current source discharge switch comparator at the capacitor input Analog to Digital Converter (ADC) Micro Processor (μP) Memory display device Constant current generator AND logic gate n Selector 1 Selectable pulse width generator 1242648 _ B7 V. Description of the invention) Symbol description of the elements in the drawings 10 12 14 16 18 20 24 26 28 30η 32η 34 36 Detailed description of the present invention FIG. 1 is provided to assist in understanding the principle of the present invention, and it also shows the basic current-voltage relationship related to capacitors. The definition of capacitance in a textbook is the voltage-current relationship 1 = c de / dt, from which the voltage of a capacitor can be defined as e (t) = ^ J ^ dt. This provides an understanding of the well-known concept that if transmitted to a capacitor The current is constant, and its voltage will change linearly as the capacitor integrates the fixed current over time. This can be observed in Figure 1, where the constant current 1 is transmitted throughout the time interval ΔT, resulting in a ramp voltage Δν. Similarly, the current is integrated at any time _5___ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before this page) ------- -Order --------- line · A7 1242648 -------- -B7__ _ 5. The description of the invention (order) is the charge Q accumulated in the capacitor, or Q = pdt. Because of this, it can be said that the area enclosed by the current waveform of FIG. 1 is equal to the accumulated charge Q. Finally, since Q = CV, we can know that if the accumulated charge Q and the voltage across the capacitor Δν are known, we can calculate its capacitance 値 C. Fig. 2 is a schematic diagram of a capacitance measuring system according to the present invention for measuring the capacitance of a capacitor 10 connected to an input terminal 12. Also connected to the input 12 is a programmable constant current source 14, a discharge switch 16, a comparator 18, and an analog-to-digital converter (ADC) 20. Connected operatively to all of these devices is a microprocessor (µP) 24, which contains a memory 26 in combination with it and a display device 28. Although all the circuit elements of FIG. 2 are well known to those skilled in the art, some details of the programmable constant current source 14 are provided to meet its purpose. One way to program the constant current source 14 is because it transmits a constant current amount to the capacitor for a specific period of time (dt) 10-, so it is actually a charge packet generator. Details of a suitable programmable constant current source are shown in Figure 3. Shown are a plurality of constant current generators 30A, 30B, 30C, ..., 30η, each of which will generate a different known or predetermined constant current number 値. These numbers may increase in any desired order, for example, in a binary order such as 1 microampere (μΑ), 2μΑ, 4μΑ, 8μΑ, etc., or in any other order such as 1μΑ, 2μΑ, 5μΑ, 10μΑ And so on, depending on the particular system available and the utility of the applicable time interval. Connected to each constant current generator 30A, 30B, 30C,…, 30η is an individual AND logic. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back first) (Re®: this page) --- Order · -------- 一 A7 1242648 ___B7 _____ V. Description of the invention (<) Gates 32A, 32B, 32C, ..., 32η. The input of each AND logic gate 32A-32η comes from an n-selected selector 34, which may be an address counter to select one of the constant current generators 30A-30η. The other input of each of the AND logic gates 32A-32η is from a selectable pulse width generator 36. When actuated, it will provide a pulse wave of the selected or predetermined width for gate control. The selected constant current generator acts for a correct known time interval. The inputs of the selector 34 and the pulse width generator 36 selected by n are provided by the microprocessor 24. Therefore, it can be seen that, in order to transfer the charge packet q0 to the capacitor 10, the microprocessor 24 · will select which current generator will be gated and act, and select that period of time to provide the required number of qG = fidt acts as the output of a programmable constant current source 14. The operation of the system of FIG. 2 to determine the capacitance of the capacitor 10 will be described in conjunction with the program shown in FIG. At step 40, the microprocessor 24 initializes the system. The (+) input of the comparator 18 is set slightly higher than zero by the application of VREF (0), and the discharge switch 16 is closed. Any voltage on the capacitor 10 will be discharged via the switch 16. At step 42, by monitoring the output of the comparator 18, the microprocessor 24 checks whether the capacitor 10 is discharged. If the voltage of the capacitor is lower than the threshold voltage set in step 40, the output of the comparator 18 will be high. This sends a signal to the microprocessor 24 to inform that the voltage of the capacitor is less than VREF (0). Then open the discharge switch. What I want to point out is that the comparator 18 is used as a kind of voltage monitoring here ---____ 2____ ____ This paper size is applicable to the Chinese National Standard (CNtS) a4 specification (210 X 297 mm) (please read the precautions on the back first) 1® this page) -------- Order --------- Line · 1242648 A7 ---_______ B7 ___ V. & Invention Device to monitor capacitors compared with threshold voltage Voltage. As is known to those skilled in the art, the comparator can be replaced by a high-speed ADC, and the threshold level of the voltage will be set in the body or software combined with the microprocessor 24. At step 44, the voltage Vc (()) across the capacitor 10 is measured by the ADC 20 and stored in the memory 26. The actual read time can be adjusted to provide a dielectric absorption effect, and as a small amount of charge is redistributed within the capacitor physics, it results in a slight increase in the capacitor voltage. In such a case, the switch 16 will be closed again for a short period of time to remove the remaining charge, and then it will be opened again to be able to read from the new Vc (.). Furthermore, if the comparator 18 is replaced by a high-speed ADC, the ADC will perform both tasks. The two comparators 18 and the ADC 20 may be replaced by a single high-speed ADC. The program can indicate that the threshold has been reached and store the ADC reads. In step 46, by selecting the appropriate current level and interval combination of the programmable constant current source 14, the microprocessor 24 will select the lowest effective charge packet number 値 q0, and set the comparator 18 to be slightly lower than ADC 20 bounces at a voltage VREF which is half of the full-scale input specification. At step 48, as the output of the voltage comparator 18 is monitored, the microprocessor 24 instructs the current from the programmable current source 14 to be given to the capacitor 10 for a known period of time, thereby placing the charge packet q0 in the capacitor. Above 〇 In step 50, if the comparator 18 cannot jump, it means transmission ------- 8- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---- ---- ^ --------- Line (please read the precautions on the back and then 0 page) 1242648 Δ7 Α7 ___ Β7 ___ V. Description of the invention (7) The charge packet to the capacitor 10 is not enough to reach the step 46 Set the bounce level voltage. If the comparator 18 bounces, it means that the charge placed on the capacitor 10 will generate a voltage equal to or greater than the bounce level set in step 46. In step 52, if the voltage comparator 18 does not jump after the charge qQ is placed on it, step 48 is repeated to cause the capacitor device to have a charge Q = q0 + q0 placed on it. If the new charge packet transmitted to the capacitor 10 is still not enough to generate a voltage that reaches the bounce level, the microprocessor 24 will select a current level / time interval combination to provide a new charge packet qi = 2q0 and guide this The charge is transferred to the capacitor 10. Repeat steps 48, 50, and 52 until the total charge Q on the capacitor 10 is generated to jump the comparator 18, which indicates that the voltage generated by the capacitor 10 is at a certain half of the specific operating window of the ADC 20 and at a point of full scale on. The microprocessor 24 tracks the charge packet transferred to the capacitor 10 and stores the total charge Q in the memory 26. If the comparator 18 is still unable to jump after a predetermined time interval, the test will be terminated because it means that the capacitor cannot obtain the charge for some reason; the predetermined time interval allows several ways to find the current level / The time interval combination is attempted, and its current level / time interval combination will generate enough voltage to beat the comparator 18. In step 54, after the comparator 18 is tripped, the microprocessor 24 enables the ADC 20 to measure the final voltage Vc⑺ on the capacitor 10. After a short period of time, read the second read, to verify that the final voltage VC (F) is the same as the first read, because if it is slightly low, a small amount is indicated. -------- Order --------- i (Please read the note on the back page first) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1242648 A7
C B7 五、發明說明（3 ) 電荷流出的洩漏電容器。 在步驟56，對qn = qQ + qi + q2 ，丨的情況而言 ，根據以下的方程式藉由微處理器24電容來計算：C B7 V. Description of the Invention (3) Leakage capacitor with charge flowing out. In step 56, for the case of qn = qQ + qi + q2, 丨, it is calculated by the microprocessor 24 capacitor according to the following equation:
N △V V咖厂vc_ 再者，就二進位順序而言，能夠顯示如下之說明QT = ，其中qO爲最小的電荷封包，而n爲比較器18電 荷循環週期的數目，藉以指示已經超過步驟46所設定的跳 動位準。 •在下表中能夠察知在電容器10上的總電荷Q以二進 位順序增加： 電荷循環週期 1 2 3 4 5 6 等等 電荷數量 q〇 q〇 2q〇 4q〇 8q〇 16q〇 ... 總電荷Q q〇 2q〇 4q〇 8q〇 16q〇 32q〇 ... 此一電荷順序允許電容裝置有大範圍的電容數値，例 如八十組數値，以便非常快速地決定之，而不用尋找適當 的電容範圍。同樣的是，由於是以一系列的步驟從接近零 至ADC操作視窗上半部內的電壓來對電容器充電，亦即滿 刻度的一半以及滿刻度之間，因此其量測解析度在所有的 量測範圍中爲定値。在量測範圍的兩末端不會呈現解析度 的壓縮。在此所說明的技術之動態範圍僅受限於產生電荷 封包所用的電流位準以及時間區間，並且因而視可程式的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 --------^---------線 (請先閱讀背面之注意事項本頁)N △ VV Coffee Factory vc_ Moreover, in terms of binary order, it can be shown as follows QT =, where qO is the smallest charge packet, and n is the number of charge cycle periods of the comparator 18, indicating that step 46 has been exceeded The set bounce level. • It can be seen in the table below that the total charge Q on the capacitor 10 increases in binary order: the charge cycle period 1 2 3 4 5 6 etc. the number of charges q〇q〇2q〇4q〇8q〇16q〇 ... total charge Q q〇2q〇4q〇8q〇16q〇32q〇 ... This charge sequence allows the capacitor device to have a wide range of capacitance numbers, such as eighty sets of numbers, in order to determine it very quickly without having to find the appropriate Capacitance range. Similarly, because the capacitor is charged in a series of steps from near zero to the voltage in the upper half of the ADC's operating window, that is, between half of the full scale and between the full scale, its measurement resolution is in all quantities. The measurement range is fixed. There is no compression of resolution at both ends of the measurement range. The dynamic range of the technology described here is only limited by the current level and time interval used to generate the charge packet, and therefore the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable depending on the programmable paper size -------- ^ --------- line (please read the note on the back page first)
1242648 A7 ____ B7__ 五、發明說明（f ) 電流產生器14的能力而定。例如，假設藉由ADC 20從初 始以及最終電壓的量測來計算ΔΥ = I·00伏特。對Qmin = q〇 =0.5pAx200psec = 100p庫侖而言，便能夠測量100pF的 電容。另一方面，以1mA的電流源在接近5秒內便能夠測 量到lOOOOgF。此表示八十組的電容數値跨距(從100pF至 ΙΟΟΟΟμΡ)或者如果需要三個位數的解析度，則涵蓋六十組 範圍。 之後則會察知電容量測的自動設定範圍乃是在此所說 明的方法之自動部分，避免尋找範圍的程式以及技術之需 求·。由於電容器從初始電壓數値至最終電壓數値充電，而 且電容數値乃是從電容器上的總電荷所決定的，因此會避 免電容範圍低値末端上所呈現的數値之解析度壓縮，此表 示一種超過習知技術顯著的改善。同樣地，避免在RC時 間常數曲線高値末端上所呈現的數値之壓縮。再者，能夠 檢測出具有介電吸收問題的多缺點電容器或者洩漏電容器 〇 儘管我們已經顯示並且說明了本發明的較佳實施例， 然而對熟知此項技術者而言，仍可以從事許多的改變與修 改是顯而易見的，而不會脫離本發明廣大的觀念。例如， 電壓比較器18能以單一個高速ADC來替代之，藉以從事 起始以及最終電壓之決定。因而預期所附的申請專利範圍 將會涵蓋所有如此的改變以及修改，如同落於本發明的實 際範疇之內。 (請先閱讀背面之注意事項1242648 A7 ____ B7__ 5. Description of the invention (f) Depending on the capabilities of the current generator 14. For example, suppose that ΔΥ = I · 00 volts is calculated by the ADC 20 from the initial and final voltage measurements. For Qmin = q〇 = 0.5pAx200psec = 100p Coulomb, it is possible to measure a capacitance of 100pF. On the other hand, a current source of 1 mA can measure 1000 gF in approximately 5 seconds. This means that there are eighty groups of capacitors and spans (from 100 pF to 100 μp) or if three-digit resolution is required, it covers sixty groups. Later, it will be known that the automatic setting range of the capacitance measurement is the automatic part of the method described here, to avoid the need to find the range of programs and technical requirements. Since the capacitor is charged from the initial voltage number to the final voltage number, and the capacitor number is determined by the total charge on the capacitor, the compression of the resolution of the number presented at the lower end of the capacitor range is avoided. Denotes a significant improvement over conventional techniques. Similarly, avoid compression of the numbers presented at the high end of the RC time constant curve. Furthermore, it is possible to detect multiple fault capacitors or leakage capacitors with dielectric absorption problems. Although we have shown and described the preferred embodiment of the present invention, many changes can be made to those skilled in the art. Modifications and modifications are obvious without departing from the broad concept of the invention. For example, the voltage comparator 18 can be replaced with a single high-speed ADC to make the initial and final voltage decisions. It is therefore expected that the scope of the appended patent application will cover all such changes and modifications as if falling within the true scope of the present invention. (Please read the notes on the back first
本頁) -------訂---------線(This page) ------- Order --------- Line
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)