TWI241769B - Charge pumping circuit for a universal series bus (USB) device - Google Patents

Abstract

A charge pumping circuit for a USB device is disclosed. The device includes a voltage input terminal, a voltage output terminal, and a first P-type MOSFET between the voltage input terminal and the voltage output terminal. The switch of the first P-type MOSFET can conduct the voltage from the voltage input terminal to the voltage output terminal. The charge pumping circuit further includes an N-type MOSFET and the second P-type MOSFET for controlling the voltage at the gate of the first P-type MOSFET and further controlling the switch of the first P-type MOSFET. Moreover, the charge pumping circuit also includes a third P-type MOSFET and a fourth P-type MOSFET which are used to control the voltage at the drain of the second P-type MOSFET and further controlling the switch of the second P-type MOSFET.

Description

1241769 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a general-purpose bus pumping circuit (charge pumping circuit), and in particular U refers to a general-purpose method that can prevent electronic components from being damaged due to high voltage. Step-up circuit for serial bus. [Prior Art] A charge pumping circuit provides an output voltage higher than a voltage source voltage (VDD) by increasing the charge voltage. This step-up circuit is needed in non-volatile memory (such as flash memory) to provide the high voltage required to program the floating gate of the non-volatile memory. FIG. 1 is a circuit diagram of a conventional booster circuit 10. As shown in FIG. 1, the boost circuit 10 includes an input terminal 12, an output terminal 14, a series transistor group 20 disposed between the input terminal 12 and the output terminal 14, and an electrical connection to the Shenlian transistor. The capacitor 30 of the group 20 and an inverter 16 electrically connected to the capacitor 30. The series transistor group 20 is composed of a first P-type MOS field effect transistor 22 and a second P-type MOS field effect transistor 24, and the two are connected in series by a series terminal 26. One end of the capacitor 30 is electrically connected to the series terminal 26, and the other end is electrically connected to the output terminal 18 of the inverter 16. The output terminal 14 is electrically connected to a load 32, and the input terminal 12 is electrically connected to a voltage source (VDD) 34. FIG. 2 is a simplified circuit diagram of a conventional booster circuit 10 for a charging process. The gate of the first P-type MOS field-effect transistor 22 applies a high-level 1241769 quasi-voltage (such as VDD), and the second P-type MOS The gate of the crystal 24 applies a low level voltage (for example, ground), and the input terminal of the inverter 16 applies a high level voltage. The first P-type MOS field effect transistor 22 is in an off state, and the second P-type MOS field effect transistor 24 is in an on state. Since the inverter 16 has its output terminal 18 as grounded, the series terminal 26 will be charged to the voltage of the voltage source 34. FIG. 3 is a simplified circuit diagram of a conventional booster circuit for performing a discharge procedure. The gate of the first P-type MOS field-effect transistor 22 applies a low level voltage, and the second P-type MOS field-effect transistor 24 The gate is applied with a south-level voltage, and the input terminal of the inverter 16 is applied with a low-level voltage. The first P-type MOS field-effect transistor 22 is in an on state, and the second P-type MOS field-effect transistor 24 is in an off state. Since the inverter 16 makes its output terminal 18 as electrically connected to Vdd, the voltage of the series terminal 26 will be doubled to the voltage source voltage (ie, 2VDD) due to charge balance. Furthermore, the first p-type MOS field effect transistor 22 is in a conducting state, so the voltage at the output terminal 14 will be equal to the private voltage at the terminal 26 of the Shenlian. The voltage (Vdd) of the source 34 is doubled before being output. The above charging / discharging procedure is performed in a continuous switching manner. The speed of the odor can provide a uniform high output voltage (2VDD). . ^ 7 "One, only four I · Because the series terminal 26 of the booster circuit 10 must experience about 2 times the voltage source voltage ', so the booster circuit is implemented using high-voltage CMOS. Clear reference Figure i, when the voltage at the end of the series is 1241769 2Vdd 'and the gate of the P-type MOS field effect transistor 22 is also applied with a low level voltage (generally set to 0 volts) to make it conductive to output high Voltage, so that the voltage difference (VSG) between the source and the gate of the first P-type MOS field effect transistor 22 is about 2Vdd. If the voltage (Vdd) of the voltage source 34 is 3.3 volts, the source and the gate The voltage difference VSG between the electrodes is about 6.6 volts, and the oxide layer between the source and the gate of the first P-type MOS field effect transistor 22 will be easily damaged by the high voltage. Therefore, the implementation of the booster circuit 10 Both adopt high voltage CMOS process. 2. When the voltage of the output terminal 14 is higher than the sum of the voltage of the voltage source 34 and the threshold voltage (VTP) of the first P-type MOS field effect transistor 22 (ie VDD + | VTP |), the high-level voltage applied to the first P-type MOS field-effect transistor 22 must be raised to the first P-type MOS field-effect transistor 22 Fully closed to avoid current backflow or leakage. [Summary of the invention] The main purpose of the present invention is to provide a universal serial bus booster circuit, which can prevent electronic components from being damaged due to high voltage. To achieve the above object, the present invention Provided is a general-purpose bus boost circuit including a voltage input terminal, a voltage output terminal, and a first P-type MOS field effect transistor disposed between the voltage input terminal and the voltage output terminal. The switch of the first P-type MOS field effect transistor can transmit the voltage of the voltage input terminal to the voltage output terminal. The boost circuit further includes an N-type MOS field effect transistor and a second P-type MOS field effect transistor. The transistor is used to control the gate voltage of the first P-type MOS field-effect transistor, and then control the switch of the first P-type MOS field-effect transistor. In addition, the booster circuit also includes a 1241769 containing a third P MOS field-effect transistor and a fourth P-type MOS field-effect transistor for controlling the drain voltage of the second P-type MOS field-effect transistor, and then controlling the switch of the second P-type MOS field-effect transistor Compared to the know-how, Ben Ming has the following advantages: 1. When the first P-type MOS field effect transistor is turned on, the voltage difference between the source and the gate is only equal to the voltage source voltage, not 2 times the voltage source voltage, so the first The oxide layer of the P-type MOS field-effect transistor will not be damaged due to the high voltage difference. 2. Because the voltage difference between the source and gate of the first known P-type MOS field-effect transistor is twice the voltage source voltage, The known boost circuit must use a high-voltage CMOS process. In contrast, since the voltage difference between the source and the gate of the first P-type MOS field effect transistor of the present invention can be reduced to the voltage source voltage, the boost circuit of the present invention Advanced processes can be used. 3. When the voltage at the voltage output terminal is higher than the sum of the voltage source voltage and the threshold voltage of the first P-type MOS field effect transistor, the second P-type MOS field effect transistor will be turned on to make the first The voltage of the gate of the P-type MOS field-effect transistor is equal to the voltage of the voltage output terminal, so that the first P-type MOS field-effect transistor is completely turned off without current reverse flow. [Embodiment] Since the introduction of the universal serial bus (USB) interface in 1986, it has become the most common and most convenient standard interface for personal computers. With the popularity of the Internet and multimedia, the USB 2.0 version officially launched in April 2000 has greatly increased the transmission speed from the original 12 Mbps to 480 Mbps. In addition, in response to the demand and growth of portable products, the USB 2.0 1241769 version of the additional specification (USB On-The-Go (USB OTG)) can achieve the function of peer-to-peer (Peer to Peer) connection, that is, two electronic devices do not Data can be transmitted through a server.

FIG. 4 is a structural diagram of an electronic device 110 supporting a USB OTG transmission interface. As shown in FIG. 4, the electronic device 110 includes a USB control circuit 112, a physical layer circuit 114 and an OTG circuit 120. The physical layer circuit 114 includes two data transmission pins 116 and 118, and the OTG circuit 120 includes a booster circuit 40 and a voltage output pin 122. According to the regulations of the USB 0TG transmission interface, the voltage output pin 122 must provide an output voltage of 5.0 volts. However, the voltage of the USB voltage source is only about 3.3 volts or less, so this potential must be assisted by a boost circuit.

FIG. 5 is a circuit diagram of the booster circuit 40 of the present invention. As shown in FIG. 5, the boost circuit 40 includes a voltage input terminal 42, a voltage output terminal 44, and a first P-type MOS field effect transistor 50 disposed between the voltage input terminal 42 and the voltage output terminal 44. . The voltage output pin 122 is electrically connected to the voltage output terminal 44. The voltage of the voltage input terminal 42 can be transmitted to the voltage output terminal 44 through the switch of the first P-type MOS field effect transistor 50. The voltage of the voltage input terminal 42 is higher than a voltage source voltage, that is, the voltage input terminal 42 is electrically connected to a boost circuit (for example, the second P-type M0S field effect transistor 24, the capacitor 30, and the inverter in FIG. 1). 16 step-up circuit). The boost circuit 40 further includes an N-type M0S field-effect transistor 60, a second P-type M0S field-effect transistor 70, a third P-type M0S field-effect transistor 80, and a fourth P-type M0S field-effect transistor. The crystal 90 is used to control the switch of the first P-type M0S field G3999087871 -9-1241769. A source 54 of the first P-type MOS field effect transistor 50 is electrically connected to the voltage input terminal 42, and a drain 56 thereof is electrically connected to the voltage output terminal 44. A gate 62 of the N-type MOS field effect transistor 60 is electrically connected to the voltage input terminal 42, a source 64 thereof is electrically connected to the gate 52 of the first P-type MOS field effect transistor 50, and a drain 66 thereof Electrically connected to a voltage source. The gate 72 of the second P-type MOS field-effect transistor 70 is electrically connected to the voltage input terminal 42, and its drain 76 is electrically connected to the gate 52 of the first P-type MOS field-effect transistor 50. The gate 82 of the third P-type MOS field-effect transistor 80 is electrically connected to a voltage source, its source 84 is electrically connected to the voltage output terminal 44, and its drain 86 is electrically connected to the second P-type MOS field effect. Source 74 of transistor 70. The fourth P-type MOS field-effect transistor 90 and the second P-type MOS field-effect transistor 70 are connected in series at a series connection point 100, and the substrates 78 and 98 of the two are electrically connected to the third P The drain 86 of the MOS field effect transistor 80. A gate electrode 92 of the fourth P-type MOS field effect transistor 90 is electrically connected to the voltage output terminal 44, and a source electrode 94 thereof is electrically connected to the voltage source voltage. Fig. 6 is a simplified circuit diagram of one of the booster circuits 40 of the present invention, wherein the voltage of the voltage output terminal 44 is between 0 and vDD-| VTP |. Since the voltage of the gate electrode 92 is lower than the voltage of the source electrode 94, the fourth P-type MOS field effect transistor 90 is in an on state, and the voltage at the series connection point 100 is equal to the voltage of the voltage source. Furthermore, since the voltage of the gate 82 is higher than the voltage of the source 84, the third P-type MOS field effect transistor 80 is in an off state. The third P-type MOS field effect transistor 1241769 80 in the off state is equivalent to a parasitic diode (shown in dashed lines in FIG. 6), and the parasitic diode does not affect the boost circuit due to reverse bias Operation of 40.

When the voltage at the voltage input terminal 42 is the voltage of the voltage source, the N-type MOS field-effect transistor 60 is in an on state, and the second P-type MOS field-effect transistor 70 is in an off state. Since the N-type MOS field-effect transistor 60 is in a conducting state, the voltage of the gate 52 of the first P-type MOS field-effect transistor 50 is equal to Vdd-V ^ V ^ for the N-type MOS field-effect transistor 60 Threshold voltage). Since the voltage difference between the source 54 and the gate 52 is equal to the threshold voltage of the N-type MOS field-effect transistor 60 (that is, ==), the first P-type MOS field-effect transistor 50 is in an off state.

When the voltage at the voltage input terminal 42 is twice the voltage source voltage, the N-type MOS field-effect transistor 60 is in an on state, and the second P-type MOS field-effect transistor 70 is in an off state. At this time, the voltage of the gate 52 of the first P-type MOS field effect transistor 50 is equal to the voltage source voltage, and the voltage difference between the source 54 and the gate 52 is equal to the voltage source voltage (VSQ = 2VDD-VDD = VDD) instead of 2 times the voltage source voltage. Therefore, the oxide layer of the first P-type MOS field-effect transistor 50 is not damaged by the high voltage difference, and the first P-type MOS field-effect transistor 50 is in an on state, and a high-voltage charge can flow from the voltage input terminal 42 to the Voltage output 44 (ie, load 32). Fig. 7 is another simplified circuit diagram of the booster circuit 40 of the present invention, wherein the voltage of the voltage output terminal 44 is between vDD-| VTP | to VDD + | VTP |. As shown in FIG. 6, the third P-type MOS field-effect transistor 80 and the fourth P-type MOS field-effect transistor 90 are both in an off state and are equivalent to two parasitic diodes G39990 87145 -11-1241769. Because the voltage of the rate connection point 100 will be maintained between vDD —% and vDDi (% is the voltage drop when the diode is turned on), the two parasitic diodes will not affect the operation of the boost circuit 40 . Fig. 8 is another simplified circuit diagram of the booster circuit 40 of the present invention, in which the voltage at the voltage output terminal 44 is higher than vDD + | VTP |. Due to the voltage of this source 84

It is equal to the voltage of the voltage output terminal 44, so the third P-type MOS field effect transistor 80 is in the on state. Moreover, the voltage of the series connection point 100 is also equal to the voltage of the voltage output terminal 44. When the voltage at the voltage input terminal 42 is equal to the voltage source voltage, the second P-type MOS field-effect transistor 70 is in an on state, and the voltage of the gate 52 of the first P-type MOS field-effect transistor 50 is equal to the The voltage at the voltage output terminal 44. Since the voltage of the gate electrode 52 is higher than the voltage of the source electrode 54, the first P-type MOS field effect transistor 50 will be completely turned off without a reverse current flow.

When the voltage at the voltage input terminal 42 is twice the voltage source voltage, the second P-type MOS field-effect transistor 70 will be turned off, and the N-type MOS field-effect transistor 60 will be turned on to enable the first P-type MOS The voltage of the field effect transistor 50 is equal to the voltage source voltage. At this time, since the voltage difference between the source 54 and the gate 52 of the first P-type MOS field effect transistor 50 is equal to the voltage source voltage (VSG = 2VDD-VDD = VDD), the high-voltage charge can be supplied from the voltage input terminal 42 Flow to this voltage output terminal 44. Since the substrates 78 and 98 of the second P-type MOS field-effect transistor 70 and the fourth P-type MOS field-effect transistor 90 are electrically connected to the second P-type MOS field-effect transistor 80 8 6 ′ Therefore, the voltage of the substrates 78 and 98 can be maintained at the highest voltage G39990 87145 -12-1276969 that the booster circuit 40 can provide. Compared with the conventional art, the present invention has the following advantages: 1. When the first P-type MOS field effect transistor 50 is turned on, the voltage difference between its source 54 and gate 52 is only equal to the voltage source voltage, and It is not twice the voltage source voltage, so the oxide layer of the first P-type MOS field effect transistor 50 will not be damaged by the high voltage difference.

2. Since the voltage difference between the source and the gate of the first known P-type MOS field effect transistor 22 is twice the voltage source voltage, the high-voltage CMOS process must be used to make the booster circuit 10 of FIG. 1. In contrast, since the voltage difference between the source 54 and the gate 52 of the first P-type MOS field effect transistor 50 of the present invention can be reduced to 1 times the voltage source voltage, the booster circuit 40 of the present invention can adopt an advanced process (Eg 0.25 micron, 2.5 / 3.3 volt logic process).

3. When the voltage of the voltage output terminal 44 is higher than the sum of the voltage source voltage and the threshold voltage of the first p-type MOS field effect transistor 50, the second p-type MOS field effect transistor 70 will be turned on. The voltage of the gate 52 of the first P-type MOS field-effect transistor 50 is equal to the voltage of the voltage output terminal 44, so that the first P-type MOS field-effect transistor 50 is completely turned off without a reverse current. . The technical content and technical features of the present invention are disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications without departing from the present invention, and should be covered by the following patent application parks. [Brief description of the diagram] G3999〇87145 -13- 1241769 Figure 1 is a circuit diagram of a conventional booster circuit; Figure 2 is a simplified circuit diagram of a conventional booster circuit for charging; Figure 3 is a conventional booster circuit for discharging Simplified circuit diagram of the program; Figure 4 is a structural diagram of an electronic device supporting a USB OTG transmission interface; Figure 5 is a circuit diagram of the booster circuit of the present invention; Figure 6 is a simplified circuit diagram of a booster circuit of the present invention;

FIG. 7 is another simplified circuit diagram of the booster circuit of the present invention; and FIG. 8 is another simplified circuit diagram of the booster circuit of the present invention. [Description of component symbols]

10 Boost circuit 12 Input terminal 14 Output terminal 16 Inverter 18 Output terminal 20 Series transistor group 22 First P-MOS field effect transistor 24 Second PSMOS field effect transistor 26 Series contact 30 Capacitor 32 Load 34 Voltage Source 40 Boost circuit 42 Voltage input 44 Voltage output 50 First first MOS field effect transistor 52 Gate 54 Source 56 Drain 60 N type MOS field effect transistor 62 Gate 64 Source 66 Drain 70 Second P-type MOS field-effect transistor 72 Gate 74 Source 76 No pole 78 Substrate 80 Third P-type MOS field-effect transistor 82 Gate 84 Source 86 Drain G39990 87145 -14-12412769 90 Fourth type MOS field effect transistor 92 gate 94 source 98 substrate 100 series contacts 110 electronic device 112 USB control circuit 114 physical layer circuit 116, 118 data transmission pin 120 OTG circuit 122 voltage output pin

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Claims (1)

1241769 Patent application scope: 1. A general-purpose application bus boost circuit, including: a voltage input terminal; a voltage output terminal; a first P-type MOS field effect transistor, the source of which is electrically connected to the A voltage input terminal and its drain electrode are electrically connected to the voltage output terminal; an N-type MOS field effect transistor whose gate is electrically connected to the voltage input terminal and its source is electrically connected to the first P-type MOS field effect transistor; The gate of the crystal; and the drain of the N-type MOS field effect transistor is electrically connected to a voltage source voltage, and the voltage at the voltage input terminal is greater than the voltage source voltage. . 2. For example, the boost circuit of a general-purpose serial busbar in the first patent application scope, which further includes a second P-type MOS field effect transistor, the gate of which is electrically connected to the voltage input terminal and the drain of which is electrically connected. At the gate of the first 卩 -type MOS field effect transistor. 3. For example, the boost circuit for a general-purpose serial bus in the second patent application scope, which further includes a third P-type MOS field effect transistor, the source of which is electrically connected to the voltage output terminal and the drain of which is electrically connected. At the source of the second P-type MOS field effect transistor. 4. For the step-up circuit of the general-purpose busbar of item 3 of the patent application, wherein the gate of the third P-type MOS field effect transistor is electrically connected to the voltage source voltage. 5. For the boost circuit of a general-purpose tandem bus according to item 3 of the patent application, wherein the substrate of the second P-type MOS field-effect transistor is electrically connected to the drain of the third P-type MOS field-effect transistor. . 1241769 6. If the step-up circuit of the universal serial bus of item 2 of the patent application scope further includes a fourth P-type MOS field-effect transistor connected in series with the second P-type MOS field-effect transistor, and The gate of the fourth P-type MOS field effect transistor is electrically connected to the voltage output terminal. 7. For the boost circuit of a general-purpose serial bus, such as the item 6 of the scope of patent application, wherein the source of the fourth P-type MOS field effect transistor is electrically connected to the voltage source voltage. 8. For the boost circuit of a general-purpose serial bus according to item 6 of the patent application, wherein the substrate of the second P-type MOS field effect transistor is electrically connected to the substrate of the fourth P-type MOS field effect transistor.