TWI241646B - Substrate with a flattening film, display substrate, and method of manufacturing the substrates - Google Patents

Abstract

The invention involves: the forming of a dummy pattern for planarization between convex portions (for example, between lead electrodes and a signal wire pattern) of irregularities caused by a patterned layer on a surface on which at least one interlayer; insulating film is formed, so as to be separated by a predetermined distance from the convex portions; the forming of interlayer insulating films 7a-7d so as to fill up gaps between the dummy pattern and the convex portions; and the planarizing of a surface. Thereby, the invention is capable of relaxing requirements on uniformity in the thickness of the film to be polished and the thickness of the polished portion.

Description

1241646 发明 Description of the invention: The present invention relates to a method for manufacturing a substrate having a substrate such as a substrate of a flat film, a substrate for a display device, and the prior art. The liquid crystal display device of the crystal display device is widely used as a flat panel display due to the advantages of the thin and thin. Recently, the use of a liquid crystal display device as a light valve for a high-precision display for a conference presentation, a home theater, or the like has been increasing. , 罝 < and the device for seeking and showing also has, for example, a plurality of signal lines and scanning lines arranged in an intersecting manner, and each of the intersections of the signal lines and the scanning lines has a control pixel electrode and a pair of The pixel f pole writes an active moment board of a switching element such as a human signal, and a structure in which liquid crystal is sandwiched between opposite substrates on which all pixel common electrodes are formed. In addition, in order to improve the aperture ratio of the m display device, an interlayer insulating film may be provided to cover the formation surface of the signal line and the scanning line, and a pixel electrode is formed on the interlayer insulating film. The electrodes are enlarged and formed by overlapping the signal lines and the scanning lines, thereby improving the aperture ratio. In terms of the above-mentioned switching elements, a thin film transistor (TFT: Thin Film TransistQr) is mostly used. However, due to its characteristics, TFTs will produce leakage mud as soon as they encounter light. Such light leakage currents will cause the contrast of liquid crystal display devices to decrease and picture panels to deteriorate, especially for liquid crystal display devices for liquid crystal projection. The above problem is significant because it is used under a large amount of light.

83666.DOC 1241646 In order to solve the above problems, that is, to suppress light leakage current, a structure in which a light-shielding film (light-shielding layer) such as a metal is provided above the TFT and below the pixel electrode has been conventionally used. In the illegal structure, because wiring and TFTs are formed under the light-shielding film, the light-shielding film is provided on the bottom layer with unevenness caused by the wiring and TFT, etc., but the light-shielding film is provided on the bottom layer with unevenness. The light-shielding film in the inclined position becomes thinner, which impairs the light-shielding property of the light-shielding film. In addition, in such a structure provided with a light-shielding film, the bottom layer of the pixel electrode formed on the light-shielding film naturally has unevenness due to the unevenness of the wiring, TFT, and the like added to the light-following film. An alignment film is formed on the pixel electrode, and the alignment process is performed to align the liquid crystal in a predetermined direction. However, when such an unevenness exists, the alignment process cannot be performed properly due to the uneven position of the unevenness, resulting in poor alignment of the liquid crystal. In addition, in order to ensure the contrast, shading with poor alignment is used, and the liquid crystal display device for liquid crystal projection with a small pixel size may cause a large decrease in the aperture ratio, even if the brightness is reduced. In order to solve the above-mentioned problem caused by unevenness, various flat structures have been proposed in the past. For example, Japanese-Japanese Patent Application Laid-Open No. 20001-242443 (publication date: September 7, 2001) discloses The following structure. An example of the liquid crystal display device described in Japanese Patent Application Laid-Open No. 2001-242443 is shown in Fig. 13. The liquid crystal display device shown in FIG. 13 is a liquid crystal display device having a flattened film (planarized film). The first flattened film i 3 1 is used to bury the unevenness of the thin film transistor, and the second flattened film is flattened. The film 13 buried the unevenness of the light-shielding film 107. In addition, the first flattening film 131 and the second flattening film 130 form an insulating film 83666.DOC -6- 1241646, and then use chemical mechanical polishing to planarize the surface of the film (CMP (Chemical (Mechanical Polishing) method, or spin-coated smooth insulation material after calcination (SOG method). Hereinafter, a method for manufacturing the liquid crystal display device disclosed in the above-mentioned publication will be briefly described with reference to Figs. First, a polycrystalline silicon (Si) film doped with phosphorus (P) and a tungsten silicide (wSi) film are sequentially formed on the quartz glass 113, which is a substrate, and then these films are patterned to form a light-shielding film 112. Next, for example, a method such as cvD (Chemical Vapor Desposite) is used to form an interlayer insulating film-107b including a silicon oxide (Si02) film on the substrate. Next, for example, a polycrystalline silicon-containing film is formed on the entire surface of the substrate by a CVD method, and the formed film is patterned to form a polycrystalline silicon film (polycrystalline Si film) 114. Next, an oxidized oxide film is formed on the entire surface of the substrate by a CVD method, for example, to obtain an interlayer insulating film 117. Next, for example, after the P-doped poly-Sl film and WS1 film are sequentially formed on the entire surface of the substrate, the formed film is patterned to obtain the gate wiring 116 and the electrode for additional capacitance elements. The method "forms the entire surface of the substrate including Si02" and removes the interlayer insulating film 107a to form a contact hole 1 11a. Next, an interlayer insulating film 107a of a square film such as a CVD method is used. Next, a predetermined portion of the gate insulating film 114 is formed, or the aluminum (A1) film and the WSi film are formed to form the lead-out electrode 1 10 and the signal is distributed. Then, a WSi film is formed on the entire surface of the substrate, and the formed film is patterned. Then, the line 120 is followed by 'the entire surface of the substrate including Si0 in a portion not shown in the figure,' for example, an interlayer insulating film using a method 2 such as a normal pressure CVD method. Then, before

83666.DOC 1241646 Figure 717 shows how to use the plasma CVD method to form a nitride nitride (SiN) film on the entire surface of the substrate. This patterned SiN film is patterned. Next, for example, a plasma CVD method using TEOS as a source gas is used to form an entire Si02 film on the substrate, and this film is polished by a method such as the CMP method to form a first planarization film 31. In the example disclosed in the above publication, the film thickness before polishing was set to 2500 nm, and then was polished to 2200 nm by a CMP method for planarization. The residual step difference after flattening by this cmp method is 0 · 5 μιη or less, depending on the conditions, it is expected to be controlled to 0.1 or less. Next, a predetermined portion of the first planarizing film 131 and an interlayer insulating film (not shown) is removed by etching to form a contact hole lb. Next, for example, a titanium (Ti) film is formed on the entire surface of the substrate by a vapor deposition method or a sputtering method, and then the Ti film is patterned 'to form a conductive light-shielding film 109. Next, an intermediate film (not shown) is interposed on the light-shielding film 1009 to form a second planarizing film 130. The intermediate film is, for example, a Si0 film formed by a plasma CVD method using TE0s as a source gas. On this intermediate film, a second planarizing film 130 is formed by the SOG method, and the second planarizing film 130 may be used. Formed using CMP. Next, a predetermined portion of the second planarizing film 130 is engraved to form a contact hole 111c. Then, after the substrate is completely formed with, for example, a 70 nm thick WITO film, it is patterned to form a pixel electrode 106. Thereafter, an alignment film 105 is formed on the pixel electrode 106, and the alignment film 1 is formed. 〇5 Alignment processing is performed to obtain an active matrix substrate 201. Then, the active matrix substrate 201 formed as described above, and a counter electrode i 〇2 and an alignment film 103 including a transparent conductive film are sequentially formed on the quartz glass 113, and then an alignment process is performed on the alignment film 103. Substrate to make alignment

83666.DOC 1241646 The films 1 05 1 03 are oppositely bonded together, and a liquid crystal layer 封 is sealed between the substrates, thereby obtaining a liquid crystal display device. However, as described in the above publication, when the first and second planarizing films 131 and 130 are formed, planarization is performed by the CMP method. The method is to form the first and second planarizing films on an underlayer having unevenness.丨 3 i ^ for grinding the pancreas (film to be polished), and polishing the film to be polished; the thickness of the film to be polished is significantly larger than the film and etching formed in the film forming process in the manufacture of general liquid crystal display devices The thickness of the etching in the process, and the thickness (polishing amount) to be polished by CMP & must exceed the step of the bottom layer, so its thickness is significantly larger than the film formed in the film formation process in the manufacture of general liquid crystal display devices and The thickness of the etching in the etching step. For example, as shown in FIGS. 14 (a) to (d), when the first planarization film 131 is formed by polishing using the CMP method, the thickness of the Si02 film, that is, the polishing film 14o, is polished by the CMP method. The thickness (grinding amount) of the part 41 must exceed the step X of the bottom layer. Specifically, in the example of the first planarizing film 131 disclosed in the above publication, the thickness of the film 'to-be-polished 14o' is 2500 nm, and the thickness of the portion 141 polished by the CMP method is 2200 nm. In other words, compared with the film formed in the film formation step and the film etched in the etching step in the manufacture of a general liquid crystal display device, the film must be a significantly thicker film. In the case of planarizing the film by the CMP method, The larger the step X of the bottom layer, the more it is necessary to increase the thickness of the film 140 to be polished and the thickness of the portions 1 to 41 polished by the CMP method. In addition, when manufacturing a liquid crystal display device, it is required that the film thickness after polishing must be more than a certain degree of uniformity, in other words, the thickness of the polished film must be controlled to be less than a certain level. As described above, increasing the thickness of the film to be polished 140 and increasing the thickness of the polished portion 141 will make it difficult to maintain the uniformity of the film thickness after polishing. Specifically, in order to control the variation of the film thickness after polishing to a sufficient extent, 'the problem lies in the thickness uniformity of the film to be polished 14 and the CMP method' and even the thickness uniformity of the polishing shao 141 must be excellent. Value. It is assumed that the thickness of the film to be polished 140 is 2500 nm, and the thickness of Shao 141 polished by the CMP method is 2200 nm. The thickness of the film after polishing is controlled to 15 / ί > (3 0 0 土 4 5 (π m)) The following examples are explained below. In addition, for the sake of simplicity, it is assumed that the thickness of the film to be polished 140 and the thickness of the shawl 141 polished by the CMP method have the same variation, that is, assuming that the thickness of the film to be polished 14 is 2500 ± △ (nm), The thickness of the polished portion 141 is 2200 ± Δ (nm). At this time, / (△ 2 + △ 45 (nm) can be applied, and △ can be calculated by this formula, then △ is △ $ 32 (nm). In order to control the variation of the film thickness after polishing to ± 15%, according to the above △ When calculating the thickness uniformity of the film to be polished 140 and the thickness uniformity of the polished portion 141 by the CMP method, the result is as follows: The thickness uniformity of the film to be polished 丨 40 must be (: △ / 2500) X 100 = ( 32/2500) X 100 = 1.3 (%); In addition, the thickness uniformity of the portion 141 polished by the CMP method is (△ / 2200) X 100 = (32/2200) X 100 = 1.5 (%) In other words, according to the conventional method, in order to control the variation of the film thickness after polishing to ± 15% (300 ± 45nm), it is necessary to uniformize the thickness of the film to be polished 14 and the portion 141 to be polished by the CMP method. Both thickness uniformity is controlled below 1.5%. 83666.DOC -10-1241646 The pattern 'forms such a dummy pattern to form grooves on the bottom layer of the flattening film which are sufficiently smaller than the interval between the convex portion and the convex portion. By forming the concave and convex of the bottom layer into such a groove, even if the film to be polished is formed by burying the groove, it appears in the research The unevenness on the surface of the film also becomes shallow, in other words, the film to be polished can be flattened to some extent. As a result, a method for manufacturing a substrate for a display device can be provided, which can make the film to be polished and the film to be polished The polishing amount is smaller than the step size of the bottom layer, so that the requirements for the thickness of the film to be polished and the uniformity of the polishing amount can be reduced. The display device with a flattening film can be further improved by the method for manufacturing a substrate for a display device. In addition, the substrate for a display device of the present invention is characterized in that it is a formation surface of the planarizing film, and the substrate for a display device is provided on the substrate with a signal writing control circuit for a pixel electrode. An active element, and on the active element, a light-shielding film that prevents light from irradiating the active element is formed through a planarizing film; the planarizing film is used to bury the unevenness caused by the pattern existing under the light-shielding film; On the formation surface where the unevenness is caused by the pattern, a dummy pattern is formed between the convex portion and the convex portion for flattening with a predetermined interval spaced by the convex portion. The above-mentioned planarizing film is formed by burying the space between the dummy pattern and the convex portion. For example, in an active device in a display device using a TFT, a light-shielding film (light-shielding film) Layer) as a countermeasure. However, as described above, a problem occurs when a light-shielding film is formed on a bottom layer having unevenness. Therefore, there is a proposal for a planarization structure described in the aforementioned publication. However, as described above, planarization is formed by a CMP method. In the case of a film, at the step of polishing the surface of the film 83666.DOC -15-1241646, the step of forming a dummy pattern for the falsification, and the step of forming an interlayer insulating film by burying the 11 pattern and the convex portion; and The step of planarizing the surface of the interlayer insulating film. According to the above method, it forms a dummy pattern for planarization on the formation surface of at least one of the interlayer insulating films among the above-mentioned interlayer insulating films. Thus, when a pattern is formed on at least one of the interlayer insulating films, This layer flattens the bottom layer of the film, that is, it is in a state where grooves having a smaller interval than the interval between the convex portion and the convex portion are formed. In addition, after forming the grooves with such small intervals, when the film to be polished is formed by burying the grooves, the grooves appear on the surface of the film to be polished < Some level of flattening. As a result, the thickness of the film to be polished and the polishing amount can be made smaller than the step size of the bottom layer, the requirements for the uniformity of the thickness of the film to be polished and the polishing amount can be reduced, and the mass productivity of the substrate for a display device can be improved. Another example is the case where there are many interlayer insulating films, and when only a dummy pattern for planarization is formed on the formation surface of one of the interlayer insulating films, the step itself (the depth of the concave portion) caused by the unevenness of the substrate surface is large. When it becomes larger, it is better to form a dummy pattern for flattening on the formation surfaces of most interlayer insulating films because forming a dummy pattern for flattening on the formation surfaces of most interlayer insulating films can disperse the steps caused by the unevenness on the substrate surface. The poor size itself (the depth of the recess). Other further objects, features and advantages of the present invention are fully explained in the following. In addition, the benefits of the present invention can be obtained from the following description with reference to the attached drawings. Embodiment 83666.DOC -19- 1241646 Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2. Knowing the use of this embodiment, the shape-bearing, hard-panel-shaped hard crystal display device is a transmissive liquid day. Although it is a 7F device, the present invention is not limited to the use of a transmissive liquid crystal display device with its board. It can be obtained from the Putian Taijiao of the present invention. Various changes can be made, for example, it is also applicable to the shooting type. A substrate for a liquid crystal display device. The anti-Ben Beth liquid crystal display device, as shown in FIG. 1, is a structure in which the active vehicle soil plate 30 and the opposite substrate 31 are bonded through the liquid crystal layer 4. The active matrix substrate is On the transparent insulating substrate 13 including quartz glass, a pixel electrode pattern 6, an auxiliary capacitor electrode 15, a thin film transistor (TFT) 18, etc. are formed. The counter substrate material includes a transparent insulating substrate 1 including quartz glass. On this, a transparent counter electrode 2 and an alignment film 3 are formed. Also in FIG. 1, only a single pixel portion is shown. However, in the above-mentioned active moment vehicle substrate 30, the TFT 18, the pixel electrode pattern 6, and the auxiliary capacitor electrode 5 are orthogonal to each other on the insulating substrate 13. , Formed at the intersections of the gate wiring 16 and the signal line pattern 20 that have been formed in the majority. In the active matrix substrate 30 described above, a first light-shielding film pattern 12 for shielding the TFT 18 is formed on the insulating substrate 13, and an insulating film pattern is formed in a state separated from the first light-shielding film pattern 12. 8d. An interlayer insulating film 7d is formed on the first light-shielding film pattern 12 and the insulating film pattern 8d so as to bury the first light-shielding film pattern 12 and the insulating film pattern 8d. The surface of the interlayer insulating film 7d is flattened by the CMP method. In addition, regarding the CMP method in this embodiment, for example, it is described in the document "Detailed Semiconductor CMP Technology" (edited by Tomi Toro, published by the Japan Industrial Survey 2001 83666.DOC -20-1241646). Method, etc. When the film to be polished (interlayer insulating film) is formed on the upper layer of the insulating film " d, since the formation surface (bottom surface) of the film to be polished has a recess a, the film to be polished may also have irregularities (steps). The above-mentioned insulating film pattern 8 (1 is provided in order to reduce the ㈣ (step difference) formed when the film to be polished is formed on the upper layer of the insulating film pattern 8d. In other words, the above-mentioned insulating film pattern 8 (1 is formed between the layers formed on the upper layer) The unevenness (step difference) formed on the surface of the insulating film 7 (1) to be polished, that is, a dummy for flattening for reducing unevenness caused by the unevenness on the formation surface (bottom surface) of the interlayer insulating film 7d The details will be described later, and here, by providing the insulating film pattern 8d, which is a dummy pattern for planarization, on the insulating substrate 3, the first light-shielding film pattern 12 is separately formed on the insulating substrate 13. In the case that the unevenness in the surface of the to-be-polished film (the to-be-polished surface) formed after the to-be-polished film is formed can be reduced, and the interlayer insulating film 7d is obtained by polishing the to-be-polished film by the CMP method or the like. Since the unevenness at the time of forming the film to be polished is small, it means that the film to be polished has been flattened to some extent, and each thickness of the film to be polished and the polished portion can be reduced. 7 (1), a polycrystalline Si film pattern 14 as an active layer of the TFT 1 8 is formed; a gate insulating film is formed on the polycrystalline Si film pattern 14 so as to cover the polycrystalline Si film pattern 17. The above-mentioned gate wiring 16 and auxiliary capacitor electrode 15 are further formed. And on the interlayer insulating film 7d, these polycrystalline Si film patterns 14, gate insulating film 17, gate wiring 16 or auxiliary capacitor electrode 15 are covered. An interlayer insulating film 7c that is planarized by the CMP method is formed by the method of laminating patterns. Here, the planarization is further formed on the gate insulating film under the condition that the pattern is separated from the laminated 83666.DOC -21-1241646. Insulation film drawing of the dummy pattern used. Correct and J, the insulation film pattern § c is provided on the gate insulation film 17; the interlayer insulation film 7c is formed by burying the laminated pattern and the insulation film pattern 8c. On the planarized interlayer insulating film 7c, a lead-out electrode pattern 10 and a signal wiring pattern 20 connected to the pixel electrode pattern 6 through a second light-shielding film pattern 9 to be described later are further formed on the same layer. These lead-out electrode patterns 丨 〇 and 5 tiger wiring Case 20 is tied to the interlayer insulating film 7c and the underlying insulating film 17 and connected to the polycrystalline Si film pattern 14 at the contact holes 11a and Ua formed by sandwiching the gate wiring 16. Here, in On the interlayer insulating film 7c, an interlayer insulating film 7b flattened by the CMP method is also formed so as to cover these lead-out electrode patterns ^ 〇 and the signal wiring pattern 20. Also, as described above, the lead-out electrode patterns 丨 and In a state where the signal wiring pattern 20 is separated, a dummy pattern for planarization, that is, an insulating film pattern 8b is further formed. The interlayer insulating film ^ is a laminated pattern and insulation in which these lead-out electrode patterns 10 and the signal wiring pattern 2 are buried. The film patterns 8 b are formed and planarized. Furthermore, a second light-shielding film pattern 9 connected to the pixel electrode pattern 6 is further formed on the planarized interlayer insulating film; the second light-shielding film 9 is formed in a contact hole formed in the interlayer insulating film. ^ Is connected to the lead-out electrode pattern 10. Here, an interlayer insulating film planarized by the CMP method is also formed on the interlayer insulating film 7b so as to cover the second light shielding film pattern 9, as in the state where the iC is separated from the second light shielding film pattern 9 Down, formed flat

83666.DOC -22- 1241646 A dummy pattern for conversion, that is, an insulating film pattern ga. As for the interlayer insulating film, it is formed by burying the second light-shielding film pattern 9 and the insulating film pattern 8a, and planarizing it. In addition, the pixel electrode pattern 6 is further formed above the planarized interlayer insulating film, and the pixel electrode pattern 6 is connected to the second light-shielding film pattern 9 at the contact hole 11c where the interlayer insulating film is formed. Finally, an alignment film 5 is formed on the formation surface of the pixel electrode pattern 6. In the above structure, each of the insulating film patterns 8a to sd, which is a dummy pattern for planarization, is formed directly above these, as described above, to reduce the formation of each interlayer insulating film that is planarized by the CMP method ~ " The unevenness formed on the surface of the film to be polished is formed. The unevenness on the surface of each interlayer insulating film is ~ 7 (1, the unevenness on the surface of the film to be polished is subject to the bottom surface just below the formation surface of each interlayer insulating film ~ The thickness of each of the insulating film patterns 8 & 8 (1) should preferably match the level of the unevenness on the surface formed by each of the insulating film patterns 8a to 8d. Here, The insulating film pattern 8d is formed to have a thickness substantially the same as the thickness of the first light-shielding film pattern 12. The insulating film pattern 8c is formed to have a thickness substantially the same as that of the poly-Si film pattern 14 plus the thickness of the spring 16, and It is roughly the same as the polycrystalline film formed by the thickness of the film pattern 4 plus the thickness of the auxiliary private electrode i 5. Similarly, the insulating film ^ 8b is formed on the same layer as the lead-out electrode pattern 10 and the signal Wiring diagram wood 20 thickness The thickness; insulating film pattern 8a, the second line is formed with a thickness of the light shielding film pattern 9 of substantially the same thickness.

In addition, when forming each of the insulating film patterns 8a to 8d, it must be between it and a pattern that will cause unevenness, that is, between the insulating film pattern 8d and the first-light-shielding film 83666.DOC -23-12412646 at the end of the figure 12, Between the insulating film pattern 8c and each of the stacked patterns in the equivalent layer of the poly-Si film pattern 14 and the gate wiring 16 or the auxiliary capacitor electrode 15, the insulating film pattern 8b and the lead-out electrode pattern 10 formed in the same layer and A predetermined interval is formed between the signal wiring types, and between the insulating film pattern 8a and the second light-shielding film pattern 9. However, if the interval is too large, that is, if the width of the groove formed between each of the insulating film patterns 8a to 8d and the patterns that will cause unevenness is too large, the recesses formed on the surface of the film to be polished will not be shallower than each. The depth of the grooves formed between the insulating film patterns 8a to 8d and the respective patterns < also loses the significance of providing dummy patterns. -For another example, referring to Fig. 2 (b), the recessed portion formed on the surface of the film to be polished is referred to as the recessed portion 60; the recessed groove formed between each of the insulating film patterns 8a to 8d and each pattern is referred to as the recess 61.

Therefore, the interval (width) of the above-mentioned grooves, that is, the interval (width) of the grooves formed between each of the insulating film patterns 仏 ~ W and each pattern, should preferably be used for the insulating film of the electrode sidewall portion before the insulating film pattern processing. Among the film thicknesses, it is preferable to add an allowable amount (calibration accuracy) of the deviation of the insulation film pattern from the electrode position. Specifically, the groove interval (width) formed between each of the insulating film patterns 8a to 8d and each pattern has an upper limit value of 1 μm or less, and preferably 0.5 μm or less; and a lower limit value of μm or more, more preferably 0_2 μm or more. If it is smaller than this interval, a part of the insulating film of the electrode sidewall portion after the insulating film pattern processing will remain protruding, and as the situation expands, it will be difficult to bury the grooves flat, so that the groove portions become low-lying. In the liquid crystal display device 19 shown in FIG. I, an insulating film pattern 8a to 8d is provided on the entire surface of the interlayer insulating film to form ~ 83666.DOC -24-1241646 7d. For example, only one of the layers is interlayer insulated. When a dummy pattern for flattening is formed on the film formation surface, when the step size itself (the depth of the recessed portion) caused by the unevenness on the substrate surface becomes large, etc., it is suitable to follow the formation of most interlayer insulating films 7a to 7d as shown in FIG. 1 The insulating film patterns 8a to 8d on which a dummy pattern for planarization is formed on the surface are preferable, because the insulating film patterns 8a to 8d for the planarization dummy pattern are formed on the formation surfaces of most of the interlayer insulating films 7a to 7d. The step size itself (the depth of the recessed portion) due to the unevenness on the surface of the substrate is dispersed. In addition, based on considerations such as manufacturing costs derived from forming a large number of insulating film patterns, for example, a structure in which an insulating film pattern is provided on any one of the formation surfaces of the interlayer insulating films 7a to 7d may be used. Next, a method for manufacturing a liquid crystal display device in this embodiment will be described with reference to FIG. (Step 1) On the insulating substrate 13 which is a substrate, a polycrystalline Si film and a WSi film doped with phosphorus (p) are sequentially formed, and the formed film is patterned to obtain a first light-shielding film. Pattern 12. Next, the entire surface of the insulating film is formed. This insulating film is, for example, a film containing silicon oxide (_SiO2). In addition, the thickness of the insulating film is preferably the same as that of the film already formed on the insulating substrate 3, which is equal to the thickness of the first light-sensitive film pattern 12 here. Next, this insulating film is patterned to obtain an insulating film pattern 8d. Next, an insulating film, such as a film containing SiO2, is formed on the surface; the thickness of the insulating film formed here is preferably larger than the film thickness (thickness of the first light-shielding film pattern 12) already formed. Next, after the film is polished by a method such as the CMP method,

83666.DOC -25- 1241646 insulation film, so that the insulation film reaches the predetermined i ϋ female rainbow-aa r, the degree of fine grinding by the child, the / / interlayer insulation film with the existing thickness and flat surface Step 7) Step 2) Next, an active semiconductor film such as a film containing polycrystalline Si is formed on the surface of the substrate, and then the active semiconductor 丨 Wang Qian 'group (film containing polycrystalline Si) is patterned. To obtain a polycrystalline film 14. Next, an insulating film, such as a film containing SiO2, is formed on the surface to obtain a free insulating film 17. Then, a conductive film is formed on the surface of the substrate, and the film formation of the conductive film may be, for example, in A polycrystalline Si film, a WSi film doped with p, and the like are sequentially formed on the surface. Connection: Shu pattern: This pattern film is guided to obtain a gate wiring 16 and an auxiliary capacitor electrode 15 for an additional capacitor element. Next, an insulating film, such as a film, is formed on the surface of the substrate. The thickness of the insulating film is preferably the same as the thickness of the insulating film M already formed on the interlayer insulating film M. "The thickness is preferably about the same." The thickness of the film on the interlayer insulating film 7d is the thickness of the gate wiring} 6 plus the thickness of the polycrystalline film 14 and the thickness of the auxiliary capacitor electrode 15 plus the polycrystalline film 14. Next, this formed insulating film is patterned to obtain an insulating film pattern 8c. Next, an insulating film, such as a film containing SiO2, is formed on the substrate surface; the thickness of the formed insulating film is preferably thicker than the thickness of the film already formed on the interlayer insulating film 7d. Next, using a method such as the CMP method, the formed insulating film is polished so that the insulating film has a predetermined thickness. By this polishing, an interlayer insulating film 7c having a sufficient thickness and a flat surface is obtained. (Step 3) Next, the contact layer 11a is formed by removing four points of the interlayer insulating film 8 and the gate insulating film 17 by insect cutting. Next, a conductive film is formed. here

83666.DOC -26- 1241646 The guided boat <film formation as described in the example is formed by sequentially forming a Tiw film, a film, and a TiW film. Then, these films are patterned to obtain a lead-out electrode pattern 10 and a signal wiring pattern 20. Next, an insulating film, such as a film containing SiO2, is formed on the surface of the substrate. The thickness of the insulating film to be formed should preferably be approximately the same as the thickness of the film already formed on the interlayer insulating film. The film thickness already formed on the interlayer insulating film 7c here refers to the thickness of the electrode pattern 10 and the signal wiring pattern 20. Next, the formed insulating film is patterned to obtain an insulating film pattern 8b. Fig. 2 (a) shows a situation where the lead electrode pattern 10 and the signal wiring pattern 20 (conductive layer pattern) are separated from each other, and an insulating film pattern 8b is formed at a position on the interlayer insulating film 7c. In this way, an insulating film pattern 8b having a film thickness substantially the same as that of the conductive layer pattern is formed between the conductive layer patterns of the lead electrode pattern 10 similar to the signal wiring pattern 20 forming the step, and the conductive layer pattern is formed. FIG. 2 (b) is a film 40 to be polished in which the insulating film is formed as shown in FIG. 2 (a). As shown in FIG. 2 (b), the irregularities generated by the lead-out electrode pattern 10, the signal wiring pattern 20, the interlayer insulating film 7c, and the insulating film pattern 8b are buried to form a film to be polished 40 (interlayer dragon edge film). In this way, by continuing to form the polished film 40 ′ shown in FIG. 2 (a), the polished film 40 is used to bury the lead-out electrode pattern 10, the groove 61 between the signal wiring pattern 20 and the insulating film pattern 8 b. . In addition, in order to form a film to be polished 40 (an interlayer insulating film) to bury grooves (concavities and convexities), a film formation method and film forming conditions with a strong step coverage capability are preferably used to form the film to be polished 40. When the film to be polished 40 is formed on the uneven surface shown in FIG. 2 (a), as shown in FIG.

83666.DOC -27-1241646 2 (b) No, a small depression 60 will be formed on the polished film 40 at the groove 61. Since such a depression is formed on the groove, for example, a depression is formed. When the groove is formed, the size and depth of the recessed portion 60 of the film 40 to be polished need to be reduced. The size (I degree) of the groove 61 is determined according to the formation of the insulating film pattern 8b. Therefore, in the step of forming the insulating film pattern 8b, the shape of the groove 61 needs to be considered to form the I-bar edge pattern gb. . In this embodiment, the recessed portion 60 is formed at the position of the groove 61 when the film 40 to be polished is formed by forming the insulating film pattern 8b. However, when the polishing film 40 is formed without first forming the insulating film pattern 8b, for example, the polishing film 140 shown in FIG. I4 (b) is formed, that is, the concave portion of the polishing film 14 is deep and wide. In addition, as shown in FIGS. 2 (a) to (d), when the interlayer insulating films 7b to 7d are formed, by forming the insulating film patterns 8b to 8d one by one, it is possible to reduce the depth of the recesses formed when the interlayer insulating film is formed, especially the depth of the recesses. . By sequentially forming the insulating film pattern t before the interlayer insulating film is formed, the depth of the concave portion, especially the depth of the concave portion, can be made smaller than that of the insulating film pattern only once, because the film is formed by the insulating film pattern each time. It is possible to sequentially form the interlayer insulating film and disperse the unevenness (step difference) generated by the interlayer insulating film. Next, the to-be-polished film 40 is planarized, and this planarization is the purpose, for example, by grinding the to-be-polished film 40. In addition, this polishing method uses, for example, the cmp method to show the polished portion in the polished film 40 (shaved by Shao 41) and the remaining portion after polishing (the polished insulating film 42) using FIG. 2 (c). Fig. 2 (d) shows the state after π polishing. The insulating film after polishing is an interlayer insulating film.

83666.DOC -28- 1241646 When the unevenness is reduced like the film to be polished 40, when polishing the film to be polished (flattened), the film thickness of the film to be polished 40 and the amount of film to be polished (thickness) can be reduced. . Comparing the to-be-polished film 140 in FIG. 14 (b) with the to-be-polished film 40 in FIG. 2 (b), it can be seen that by forming the insulating film pattern 8b, the unevenness of the to-be-polished film 40 can be reduced, and the to-be-polished film 40 can be made smaller. The thickness becomes thinner. In addition, comparing the film to be polished 141 in FIG. 4 (b) and the portion 41 to be polished in FIG. 2 (b), it can be seen that the amount of polishing by the CMP method can be reduced by forming the insulating film pattern 8b. Furthermore, when polishing is performed by the CMP method to flatten the film to be polished 40, it is desirable to polish the film 40 to a certain extent and then use the CMP method to polish it. In this way, once a certain level of planarization is performed Later, the remaining unevenness is planarized by the Cmp method, which can further reduce the film thickness of the film to be polished 40 and the amount of polishing by the CMP method. The film thickness of each layer can be as shown in Table 1 ... (Table 1) The first light-shielding layer 12 150 nm TFT active layer (polycrystalline Si film 14) 50 nm Gate wiring 1 6 300 nm Signal wiring 20 650 nm The second light-shielding layer 9 125 nm pixel electrode 6 100 nm If the structure of FIG. 2 is applied with the thickness shown in Table 1, an insulating film pattern with a thickness of 700 nm is formed at a position about 0.7 μm away from the signal wiring pattern 20. Park, · Next, a film to be polished 800 nm was formed 40; then, the thickness of the portion to be polished was 500 nm, that is, the CMP method was used to grind it to about 500 nm.

83666.DOC -29- 1241646 It is known that the polished insulating film 42 (interlayer insulating film 7b). The following description also uses FIG. 1. (Step 4) Next, a predetermined portion of the interlayer insulating film 7b is removed by etching to form a contact hole 1 1 b. Next, for example, a film having a light-shielding property and a conductive property, such as a TiW film, is formed on the entire substrate by a method such as a vapor deposition method and a sputtering method. Next, this film was patterned to obtain a second light-shielding film pattern 9 having conductivity. Next, an insulating film, such as a film containing SiO2, is formed on the surface of the substrate, and the thickness of the insulating film is preferably the same as the film thickness already formed on the interlayer insulating film 7b, which is substantially the same as the second light shielding. The thickness of the film pattern 9. Next, the M insulating film is patterned to obtain an insulating film pattern 8a. Next, for example, a CVD method is used to form an insulating film on the substrate surface. Next, for example, the CMP method is used to grind it to a predetermined thickness to obtain an interlayer insulating film 7a having a flat surface. (Step 5) The predetermined portion of the interlayer insulating film &amp; is removed by etching to obtain a contact hole 11c. Then, for example, a thickness of 1 is formed on the entire surface of the substrate. After the ITO film is patterned, a pixel electrode pattern 6 is obtained, and the remaining alignment film 5, liquid crystal layer 4 ', alignment film 3, counter electrode 2', and insulating substrate may be formed by a known method. In addition, the first embodiment discloses the examples corresponding to the above steps 5 to 5; the embodiment, the second series reveals the examples corresponding to the above, ^ ^ ^ ^ ^, Ai% 23, and the 5 examples; the third series reveals the corresponding examples. The above steps 1, 2, 7 π &lt;, /, ^ 3, and 5 are another example. The fourth embodiment of the present invention discloses examples corresponding to the above steps 2 to 5. Next, #requires explanation on reducing the uniformity of the thickness of the film to be polished and the thickness of the polished portion. To control the variation of film thickness after polishing to ± 15%

83666.DOC -30-1241646 (3 00 ± 45 nm), if the thickness uniformity of the film to be polished and the thickness uniformity of the part polished by the CMP method are controlled according to the conventional method, both must be controlled at 1 _ 5% or less. In contrast, according to the method of this embodiment, the thickness uniformity of the film to be polished and the thickness uniformity of the portion to be polished by the CMP method may be about 3%. The thickness uniformity of the above-mentioned film to be polished and the thickness uniformity of the portion to be polished by the CMP method were determined by calculating the difference. For the sake of simplicity, it is assumed that the thickness of the film to be polished changes the same as the amount of polishing by the CMP method; assuming that the thickness of the film to be polished is 800 ± △ (nm), and the thickness to be polished by the CMP method is 500 ± △ (nm) At this time, / (△ 2 + △ 2) ^ 45 (nm) can be applied, that is, △ ^ 32. At this time, the thickness uniformity of the film to be polished may be Δ "⑼", which is 4%, and the thickness uniformity of the portion to be polished by the CMP method may be Δ / 5OO = 32/500 = 6.4%. Generally speaking, in the liquid crystal display device, as shown in Table I, the signal wiring pattern 20 is the thickest. However, the manufacturing method of the liquid crystal display device in this embodiment is the method for forming the signal wiring pattern 2 The planarization of the upper insulating film can have a considerable effect. In addition, in order to make the film to be polished 40 thinner and the thickness of the CMP method to be thinner, the effective method is to planarize the ground layer of the film to be polished to make it as flat as possible. Before forming the interlayer insulating film 7 among the two cubic and all interlayer insulating films 7, the insulating film pattern 8 is formed first, and then the irregularities generated by the insulating film pattern 8 are buried; thereafter, the interlayer insulating film is formed. 7, then the interlayer insulating film 7: preferably flattened / denier. However, for all the interlayer insulating films 7, the formation of the insulating pancreatic pattern 8 and the flattening of the interlayer insulating film 7 will be performed as described above.

83666.DOC -31- 1241646 If the process g is added, there may be problems in fragrance production cost and productivity. Therefore, it is necessary to consider the manufacturing cost and productivity to determine the 辕 :: fabrication of the interlayer insulation film 7. (Example 1) An example of the case where the interlayer insulating film in the liquid crystal head is not provided with an insulating film pattern, and the interlayer insulating film is planarized by the CMP method, as shown in FIG. 1; the liquid crystal display The device is located at each intersection where the gate wiring and the signal wiring intersect perpendicularly, and has a thin film transistor, an additional capacitor (electrode) and a transparent pixel electrode, and a first light-shielding film is interposed between the lower layers of the thin film transistor and an interlayer insulating film. An upper layer of the signal line is provided with a second light shielding film through an interlayer insulating film. In addition, due to the relationship between manufacturing cost and productivity, when an interlayer insulating film without an insulating film pattern is provided, the conventional interlayer insulating film processing may be performed by using a conventional technique such as forming an insulating film by a CVD method alone. (1) A polycrystalline silicon Si film (50 nm) and a WSi (100 nm) film doped with phosphorus (p) are sequentially formed on the insulating substrate 13 that is a substrate; then, these films are patterned to obtain the first A light-shielding film pattern 12. (2) For example, a plasma CVD method using TEOS as a source gas is used to form an insulating film including a Si02 film, and the thickness of the insulating film is approximately the same as that of the first light-shielding film pattern, for example, 150 nm. Next, this insulating film is patterned to form an insulating film pattern 8d. Next, for example, a CVD method is used to form an insulating film including a SiO 2 film on the entire surface of the substrate. The insulating film is thicker than the first light-shielding film pattern 12, for example, the film thickness is 650 nm. Next, it is ground to a predetermined thickness by a rubbing method, for example, to about 250 nm, to obtain an interlayer insulating film 7d having a flat surface with a predetermined thickness (650-250 = 400 nm) of 83666.DOC -32-1241646. In addition, the residual level difference after the planarization can be reduced to 50 nm or less. (3) For example, a CVD method is used to form a film including a polycrystalline Si film (50 nm) on the substrate; then, the film including polycrystalline Si is patterned to obtain a polycrystalline Si film 14; then, for example, A gate insulating film 17 (80 nm) including a Si02 film is formed on the substrate by using a CVD method or the like; then, a polycrystalline silicon Si film (150 nm) and a WSi film (150 nm) doped with phosphorous P are sequentially formed on the substrate. Next, these films are patterned to obtain the gate wiring 16 and an auxiliary capacitor electrode 15 for an additional capacitor element. (4) For example, a plasma CVD method using TEOS as a source gas is used to form an insulating film including a SiO 2 film on the entire surface of the substrate. The thickness of the insulating film is substantially the same as the thickness of the gate wiring 16 and the thickness of the polycrystalline Si film 14, for example, 350 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8c. Next, for example, an SiO 2 film-containing insulating film is formed on the substrate by a CVD method. The thickness of the insulating film is thicker than the thickness of the gate wiring 16 plus the thickness of the polycrystalline film 14 such as 800 nm. Next, the CMP method is used to polish to a predetermined thickness, for example, about 400 nm, to obtain an interlayer insulating film 7c having a flat surface. In addition, the residual-residual step difference after planarization can be reduced to below 100 nm. (5) The predetermined portion of the interlayer insulating film 9 and the gate insulating film 17 is removed by etching to form a contact hole 1 la; then, a Tiw film (150 nm), an A1 film (400 nm), and TiW are sequentially formed on the entire substrate. Film (100 nm); then, these films were patterned to obtain a lead-out electrode pattern 10 and a signal wiring pattern 20. (6) For example, a plasma CVD method can be used to form a silicon nitride (SiN) film containing a large amount of hydrogen on the substrate to terminate the floating bonds in the polycrystalline Si film (Dangiing 83666.DOC -33-1241646: ' The SiN film is not completely transparent under light. Therefore, in order to improve the brightness of the liquid crystal display device, the opening can be removed by etching. Also, the structure described in this item (6) is omitted in FIG. 1, and In the following other embodiments, the structure described in this item (6) is also omitted. ⑺ For example, by electropolymerization CVD method using TEOS as the source gas, a Si02 film is formed on the entire substrate and the thickness is approximately the same as the signal wiring. Film, such as a 0 nm, ', s edge film, and then patterning this insulating film to obtain an insulating film pattern 8b; and then, for example, using CVD to form a film with a thickness of 10 thousand thick and a large number on the substrate, For example, an insulating film with a thickness of 800 nm; and then, grinding to a sufficient thickness, for example, to about 500 nm, to obtain an interlayer insulating film 7b having a flat surface. In addition, the residual step after planarization is Value 'can be reduced to 100nm (8) Next, a predetermined portion of the interlayer insulating film is etched away to form a contact hole lib; then, for example, a TiW film (125 nm) is formed on the surface of the substrate by a vapor deposition method or a sputtering method; This Tiw film was patterned to obtain a conductive second light-shielding film pattern 9. (9) The plasma cvd method using, for example, TE0S as a raw material gas, was opened on the substrate surface to include &quot; Si. 2 film and a film having a thickness substantially the same as that of the second light-shielding film pattern 9, for example, an insulating film of 125 nm; then, the insulating film is patterned to obtain an insulating film pattern 8a; Film, the thickness of the insulating film is thicker than the signal line, for example, a thickness of 50 (1111) is then polished by a CMP method to a predetermined thickness, for example, about 200, to obtain an interlayer insulating film 7a having a flat surface. The residual step difference after planarization can be reduced to below 50 nm.

83666.DOC -34- 1241646 (ίο) A predetermined portion of the interlayer insulating film is removed by etching to obtain a contact hole 11c; and then a ITO film having a thickness of, for example, 100 nm is formed on the entire substrate, and then patterned to obtain the pixel electrode 6. Table 2 shows one of the polishing conditions in the CMP method. The insulating film patterns 8a to 8d in this embodiment are set as an insulating film including a SiO2 film. However, the insulating film patterns 8a to 8d may also be a silicon oxide film (stone oxide film), a nitrided film (dream nitrogen) Film), or a laminated film of an oxide film and a nitrided film. In the case of a silicon nitride film (silicon nitride film), for example, it is formed by a plasma CVD method. (Table 2) Polishing cloth IC-1400-050A2 CMP polishing cloth supremeRN-H24PJ Polishing liquid Semi-Sperse 12 (1/2 dilution of Semi-Sperse 25 manufactured by Cabot) Polishing liquid flow rate 15 0 seem Polishing head pressure 8 psi Carrier The number of rotations is 32 rpm. The number of rotations of the template is 28 rpm. In addition, the interlayer insulating films 7a to 7d in this embodiment are set to include an Si02 film. However, the interlayer insulating films 7a to 7d may be silicon oxide films (silicon Oxide film), silicon nitride film (silicon nitride film) 'or a laminated film of a silicon oxide film and a silicon nitride film. In the case of a silicon nitride film (silicon nitride film), for example, it is formed by a plasma CVD method. 83666.DOC -35-1241646 Figures 3 (a) to (e) show the formation of an insulating film pattern with a laminated structure. As shown in FIG. 3 (a), a silicon nitride film 5 丨 is formed on the interlayer insulating film, the lead-out electrode pattern 丨 0, and the signal wiring pattern 20, and silicon oxide is further laminated on the silicon nitride film 51. Film 50. Next, the silicon nitride film 5 丨 and the silicon oxide film 50 are patterned to obtain the one shown in FIG. 3 (b). In this case, it corresponds to the insulating film pattern 8b of FIG. 2, namely, FIG. 3 (b). The silicon nitride film 51 and the silicon oxide film 50. As shown in FIG. 3, when the lower layer of the laminated structure is used as a silicon nitride film 5 (silicon nitride film), when an insulating film pattern is formed by etching such as dry etching, a silicon oxide film 50 Film) faster than the broken nitride film 5 丨 (nitride broken film), the silicon nitride film will play the role of an etch stop layer, and improve the processing precision of the insulating film pattern. However, in general, since the silicon nitride film is inferior to the silicon oxide film, it is sometimes preferable to use the silicon oxide film alone. In addition, even if the entire insulating film is formed on the substrate before the formation of the insulating film pattern, and the insulating film is formed after being polished by the CMP method, the effect of planarization will not be affected. The application of the liquid crystal display shown in FIG. 1 and the liquid crystal display device shown in FIG. 4 and FIG. 5-an example 'its structure lies in the structure of the display pixel electrode pattern 6 and the connection structure between the non-polar regions of tft. The difference. The interlayer structure is the same as that of the above-mentioned embodiment (fig. Υ. FIG. 4 is a structure in which the pixel electrode pattern ㈣ is connected to the non-polar area of the TFT via metal (the same layer as the signal line). The structure of the electrode region connected to the pixel electrode in the polar region. (Embodiment 2) The edge film is provided with an insulating film pattern to isolate all interlayers in the liquid crystal display device. 83666.DOC -36-1241646 The embodiment is shown in Fig. 6. The liquid crystal display device is at each intersection where the gate wiring and the signal wiring intersect perpendicularly, and has a thin film transistor, an additional capacitor, and a transparent pixel electrode. It is also due to the relationship between manufacturing cost and productivity. When an interlayer insulating film without an insulating film pattern is provided, for the processing of the interlayer insulating film, as long as the prior art of forming an insulating film is used by a CVD method alone, (1) an insulating substrate on the substrate 13 On the substrate, for example, a CVD method is used to form a polycrystalline Si-containing film (50 nm) on the substrate. Then, the polycrystalline Si-containing film is patterned to obtain a polycrystalline Si film 14. Then, for example, the cvd method is used. To obtain a gate insulating film (80 nm) including a SiO2 film; then, a polycrystalline silicon doped film of phosphorus P (150 nm) and a WSi film (15 nm) were sequentially formed on the entire substrate in sequence; After the film is patterned, the gate wiring 16 and the auxiliary capacitor electrode 15 for the additional capacitor element are obtained. (2) For example, by a plasma CVD method using TEOS as a source gas, a film including a Si02 film is formed on the entire surface. The film thickness after the film formation is approximately the same as the thickness of the gate wiring 16 and the thickness of the polycrystalline film 14 such as an insulating film with a thickness of 350 nm. Next, the insulating film is patterned to obtain an insulating film pattern 8b. Next, for example, a CV-D method is used to comprehensively form an insulating film including a Si02 film, and the thickness of the insulating film is thicker than the thickness of the gate wiring 16 plus the thickness of the polycrystalline Si film 4 such as 800 nm. The CMP method is used to grind to a predetermined thickness, for example, grind it to about 400 nm to obtain an interlayer insulating film% with a flat surface. In addition, the residual step after planarization can be reduced to less than 100 nm. (3) The predetermined portions of the interlayer insulating film 7b and the gate insulating film 7 are removed by etching, and Contact hole 11a; Next, a Tiw film (150 nm), 83666.DOC -37-1241646 A1 film (400 nm), and a Tiw film (100 nm) are sequentially formed on the entire surface; then, these films are patterned An extraction electrode pattern 10 and a signal wiring pattern 20 are obtained. (4) For example, a plasma cvd method using TE0S as a source gas is used to form an insulating film including a Si02 film, and the thickness of the insulating film is approximately It is the same as the signal wiring, for example, 650 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8a ·, and then, for example, a CVD method is used to form the entire insulating film. The thickness of the insulating film is thicker than the signal wiring. For example 800 nm. Then, it is polished to a predetermined thickness by the CMP method, for example, to about 5000 to obtain an interlayer insulating film 7a having a flat surface. In addition, the residual step difference 'after planarization can be reduced to below 100 nm. (5) A predetermined portion of the interlayer insulating film 7a is removed by etching to form a contact hole ub, and then, for example, a 100 nm ITO film is formed on the entire surface. Then, the film is patterned to obtain a pixel electrode pattern 6. Fig. 7 is an application example of the liquid crystal display device shown in Fig. 6, which is a structure having a structure in which a pixel electrode pattern 6 is connected directly to a drain region of a TFT. (Embodiment 3) An embodiment in which all interlayer insulating films in the liquid crystal display device are provided with an insulating film pattern and planarized by the CMP method is shown in FIG. 8; the liquid crystal display device is connected to a gate line. Each intersection perpendicular to the signal line has a thin film transistor, an additional capacitor, and a transparent pixel electrode, and a first light-shielding film is provided through an interlayer insulating film under the thin film transistor. In addition, due to the relationship between manufacturing cost and productivity, when an interlayer insulating film without an insulating film pattern is provided, the conventional interlayer insulating film processing may be performed by using a conventional technique such as forming an insulating film by a CVD method alone.

83666.DOC -38- 1241646 (1) Phosphorus p-doped polycrystalline silicon is sequentially formed on the substrate, that is, the insulating substrate 13

Si film (50_) and WSi (100nm) film; then, these films are patterned to obtain a first light-shielding film pattern 12. (2) For example, a plasma CVD method using TEOS as a source gas is used to form an insulating film including a Si02 film. The thickness of this insulating film is approximately the same as that of the first light-shielding film pattern 12, for example, 150 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8c. Next, for example, a CVD method is used to form an insulating film including a SiO 2 film. The thickness of the insulating film is thicker than the first light-shielding film pattern 12, for example, 650 nm. Next, the CMP method is used to grind it to a predetermined thickness, for example, about 250 nm to obtain an interlayer insulating film 7c having a flat surface. In addition, the residual level difference after planarization can be reduced to 50 nm or less. (3) For example, a CVD method is used to comprehensively form a film (50 nm) containing polycrystals; then, a film containing polycrystalline si is patterned to obtain a polycrystalline film 14; and, for example, a CVD method is used. To obtain a gate insulating film 17 (80 nm) including a Si02 film; then, a polysilicon-containing film (150 nm) and a WSi film (150 nm) doped with phosphorous p were sequentially formed on the entire surface; and These films are patterned to obtain gate wiring 16 and auxiliary capacitor electrodes 5 for additional capacitor elements. (4) For example, a plasma CVD method using TEOS as a source gas is used to form an insulating film including a Si02 film. The thickness of the insulating film is approximately the same as the thickness of the gate wiring 16 and the polycrystalline silicon. The thickness of the film 14 is, for example, 35 μm. Next, the insulating film is patterned to obtain an insulating film pattern 8b. Then, for example, an insulating film including a SiO 2 film is formed by a CVD method. The thickness of the insulating film is greater than the thickness of the gate wiring plus polycrystalline silicon. The thickness of the Si film, for example, 800 nm, is then polished by a CMP method to a predetermined thickness, for example, 400 nm.

S3666.DOC -39- 1241646, and an interlayer insulating film 7b having a flat surface is obtained. In addition, the residual step after planarization can be reduced to below 100 nm. (5) A predetermined portion of the interlayer insulating film 7b and the gate insulating film 17 is removed by etching to form a contact hole 11a; then, a Tiw film (150 nm), an A1 film (400 nm), and a Ti W film ( 100nm); Then, these films are patterned to obtain the lead-out electrode pattern 10 and the signal wiring pattern 20. (6) For example, a plasma cvD method using TEOS as a raw material gas is used to form an insulating film including a Si02 film. The thickness of this insulating film is substantially the same as that of the signal wiring pattern 20, for example, 650 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8a. Next, for example, a CVD method is used to form an insulating film over the entire surface. The thickness of the insulating film is thicker than the signal wiring pattern 20, for example, 800 nm thick. Then, it is polished to a predetermined thickness by the CMP method, for example, to about 500 nm to obtain an interlayer insulating film 7a having a flat surface. In addition, the residual level after leveling can be reduced to less than 1000 nm. (7) A predetermined portion of the interlayer insulating film 7a is removed to form a contact hole nb: Next, an ITO film having a thickness of, for example, 100 nm is formed in its entirety; then, the film is patterned to obtain a pixel electrode pattern 6. The liquid crystal display device of Fig. 9 is an application example of the liquid crystal display device shown in Fig. 8 ', which shows a structure in which a pixel electrode pattern 6 is directly connected to a drain region of a TFT. (Embodiment 4) A conventional example of a case where all interlayer insulating films in a liquid crystal display device are provided with an insulating film pattern 'and planarized by the CMP method, as shown in FIG. 10. This liquid crystal display device' is based on Each intersection of the gate wiring and the signal wiring perpendicularly intersects 83666.DOC -40-1241646. It has a thin film transistor, additional capacitors, and transparent pixel electrodes. The upper layer of the signal line is interposed with an interlayer insulating film and a second light-shielding film. . In addition, due to the relationship between manufacturing cost and productivity, when an interlayer insulating film is provided without an insulating film pattern, for the processing of the interlayer insulating film, it is only necessary to use the CVD method alone to use the previous technology such as forming an insulating film. . (1) On the whole of the insulating substrate 13 of the substrate, for example, a film (50 nm) containing polycrystalline Si is formed by a CVD method; then, the film containing polycrystalline Si is patterned to obtain a polycrystalline Si film 14 Next, for example, a CVD method is used to obtain a gate insulating film 17 (80 nm) containing a Si02 film; then, a polysilicon Si-containing film (150 nm) and a WSi film (150 nm) are sequentially doped over the entire surface. ); Next, these films are patterned to obtain a gate wiring 16 and an auxiliary capacitor electrode 15 for an additional capacitor element. (2) For example, a plasma CVD method using TE0S as a source gas is used to form an insulating film including a Si02 film. The thickness of the insulating film is approximately the same as the thickness of the gate wiring plus the polycrystalline Si film. The thickness is, for example, 35 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8c. Next, for example, an insulating film including a SiO 2 film is fully formed by a CVD method, and the thickness of the insulating film is thicker than the thickness of the gate wiring 16—plus the thickness of the polycrystalline Si film μ, such as 800 nm. Next, the CMP method is used to polish to a predetermined thickness, for example, to about 400 nm to obtain an interlayer insulating film 7c having a flat surface. In addition, the residual level difference after planarization can be reduced to below 100 nm. (3) A predetermined portion of the interlayer insulating film 7c and the gate insulating film 17 is removed by contact etching to form a contact hole 11a; then, a TiW film (150 nm), an A1 film (400 nm), and a TiW film ( 100nm); Then, these films were patterned into 83666.DOC -41-1241646 to obtain an extraction electrode pattern 10 and a signal wiring pattern 20. (4) For example, a plasma CVD method using TEOS as a source gas is used to form an insulating film including a Si02 film, and the thickness of the insulating film is substantially the same as that of the signal wiring pattern 20, for example, 650 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8b. Next, an insulating film is formed on the entire surface by, for example, a CVD method, and the thickness of the insulating film is thicker than the signal wiring, for example, 800 nm thick. Next, the CMP method is used to polish to a predetermined thickness, for example, to about 500 nm, to obtain an interlayer insulating film 7b having a flat surface. In addition, the residual level difference after planarization can be reduced below 100 nm. (5) Next, a predetermined portion of the interlayer insulating film 7b is removed by etching to form a contact hole 1 lb. Then, a TiW film (125 nm) is formed on the entire surface by, for example, a vapor deposition method or a sputtering method; The TiW film is patterned to obtain a conductive second light-shielding film pattern 9. (6) For example, a plasma CVD method using TEOS as a source gas is used to form an insulating film including a Si02 film. The thickness of the insulating film is approximately the same as that of the second light-shielding film pattern 9, for example, 125 nm. Next, this insulating film is patterned to obtain an insulating film pattern 8a; then, for example, a CVD method is used to form an insulating film in its entirety—the thickness of the insulating film is thicker than the signal wiring pattern 20, such as 500 nm thick. Next, it is polished to a predetermined thickness by the CMP method, for example, to about 200 nm to obtain an interlayer insulating film 7a having a flat surface. In addition, the residual step after planarization can be reduced to below 50 nm. (7) A predetermined portion of the interlayer insulating film 7a is removed by etching to form a contact hole 11c. Then, an ITO film having a thickness of, for example, 100 nm is formed on the entire surface. Then, the film is patterned to obtain a pixel electrode pattern 6. 83666.DOC -42- 1241646 The liquid crystal display devices of FIGS. 11 and 12 are application examples of the liquid crystal display device shown in FIG. 10. Figure U is a structure in which a pixel electrode pattern 6 is connected to a drain region of a TFT through a metal (the same layer as a signal line). In addition, FIG. U is a structure having a structure in which the pixel electrode pattern 6 is directly connected to the non-polar region of the TFT. In the above embodiments and examples, 'the transmissive liquid crystal display device has been described, but the present invention is not limited to a substrate for a transmissive liquid crystal display device, and it can also be applied to a reflective liquid crystal display device, for example. Substrate. The specific implementation forms or examples described in the detailed description of the invention are all for clarifying the technical content of the present invention, and the present invention should not be limited to specific examples such as m in a narrow sense. Those within the scope of the patent application described below can be implemented with various changes. Brief Description of Drawings Figure 1 is a cross-sectional view of a liquid crystal display device. The liquid crystal display device is a liquid crystal display device using a substrate of the present invention. (TFT), electrodes, and pixel electrodes. Fig. 2 (a) is a schematic view showing a method for manufacturing a liquid crystal display device in this embodiment, and is a cross-sectional view after the insulating film pattern 8b is formed. Fig. 2 (b) is a schematic view of a method for manufacturing a liquid crystal display device in this embodiment, and is a cross-sectional view in which a film to be polished is formed in Fig. 2 (a). FIG. 2 (c) is a schematic diagram of a method for manufacturing a liquid crystal display device in this embodiment, which is in the film to be polished in FIG. 2 (b), and has a portion polished by polishing and a portion flattened after polishing. Section view. 83666.DOC -43 · 1241646 Fig. 2 (d) is a schematic view of a method for manufacturing a liquid crystal display device in this embodiment, and is a cross-sectional view of a polishing film after polishing. FIG. 3 (a) is a schematic diagram of a method for manufacturing a liquid crystal display device in an embodiment of the present invention (an example in which an insulating film pattern has a laminated structure), which is a cross-sectional view of a silicon nitride film and a stone oxide film laminated . FIG. 3 (b) is a schematic diagram of a method for manufacturing a liquid crystal display device in an embodiment of the present invention (an example in which an insulating film pattern has a laminated structure), which is a cross-section of a silicon nitride film and a silicon oxide film after patterning. Illustration. FIG. 3 (c) is a schematic diagram of a method for manufacturing a liquid crystal display device in an embodiment of the present invention (an example in which an insulating film pattern has a laminated structure), and is a cross-sectional view of a film to be polished formed on FIG. 3 (b). . FIG. 3 (d) shows the TF intention of the manufacturing method of the liquid-theta θ display device in the embodiment of the present invention (an example in which the insulating film pattern has a laminated structure), which is “the part to be polished in the film to be polished, and A cross-sectional view of the portion remaining after grinding. Fig. 3 (e) is a schematic diagram of a method for manufacturing a liquid crystal display device in an embodiment of the present invention (an example in which an insulating film pattern has a laminated structure), and is a cross-sectional view after being polished by a polishing film. FIG. 4 is an application example of the liquid crystal display device shown in FIG. 1, which is a cross-sectional view of a liquid crystal display device showing a structure in which a pixel electrode is connected to a drain region of a TFT via a metal (the same layer as a signal line). Fig. 5 is an application example of the liquid crystal display device tf shown in Fig. 1 and is a cross-sectional view of a liquid crystal display device showing a structure in which a pixel electrode is directly connected to a non-polar region of a TFT. 6 is a liquid crystal display device according to an embodiment of the present invention.

83666.DOC -44- 1241646 The signal lines intersect perpendicularly, and the liquid crystal display device with thin film customers and transparent pixel electrodes at each intersection is connected to all layers: the insulating film has an insulating film pattern, and then uses CMP A cross-sectional view of a crystal display device. 6. 'Night' FIG. 7 is an application example of the liquid crystal display device shown in FIG. 6, which is a cross-sectional view showing a liquid crystal display device having a structure in which a pixel electrode is directly connected to a TFTm region. FIG. 8 shows a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device intersects perpendicularly with respect to an electrode line and a signal line, and has thin film transistors, additional electrodes, and transparent pixel electrodes at each intersection, and an interlayer insulating film is interposed therebetween. A liquid crystal display device having a first light-shielding film on the bottom layer of a thin film transistor is a cross-sectional view of a liquid crystal display TF device having an insulating film pattern on all interlayer insulating films and then planarized by a CMP method. Fig. 9 is an application example of the liquid crystal display device shown in Fig. 8 and is a cross-sectional view of a liquid crystal display device showing a structure in which a pixel electrode is directly connected to a drain region of a TFT. FIG. 10 is a liquid crystal display device according to an embodiment of the present invention. The gate wiring and the signal wiring intersect perpendicularly and vertically, and each thin film transistor, an additional capacitor, and a transparent pixel electrode are provided at each intersection, and an interlayer insulating film is interposed therebetween. A liquid crystal display device having a second light-shielding film on the upper layer of the signal line is a cross-sectional view of a liquid crystal display device having an insulating film pattern on all interlayer insulating films and then planarized by a CMP method. FIG. 11 is an application example of the liquid crystal display device shown in FIG. 10, which is a liquid crystal display having a structure in which a pixel electrode is connected to a drain region of a TFT via a metal (the same layer as a signal line) 83666.DOC -45-1241646 Sectional view of the device. FIG. 12 is a cross-sectional view of a liquid crystal display device having a liquid crystal display device shown in FIG. 10 and having a pixel electrode directly connected to a drain region of a TFT. FIG. 13 is a cross-sectional view of a conventional liquid crystal display device. Fig. 14 (a) is a cross-sectional view showing a conventional liquid crystal display device and a coating of Wan Ling ', which is a cross-sectional view showing a state before a film to be polished is formed. Fig. 14 (b) is a cross-sectional view showing a conventionally manufactured garment for a liquid crystal display device &lt; Fig. 14 (c) shows a conventional spargerite 3 scraped surface of a conventional liquid crystal display device. It is shown in Fig. 14 (b), and shows the sharpness after polishing and flattening after polishing. Sectional view of the transformed part. Fig. 14 (d) is a w-shaped surface view showing the manufacturing method of a conventional liquid crystal display device, which is a cross-sectional view showing a polished film after being polished. Description of Symbols of Drawings 1 Insulating substrate 2 Counter electrode 3 Alignment film 4 Liquid crystal layer 5 Alignment film 6 Pixel electrode pattern 7 Interlayer insulation film 7a ~ 7d Interlayer insulation film 8 Insulation film pattern

83666.DOC -46- 1241646 8a ~ 8d insulating film pattern 9th; light shielding film pattern 10 lead-out electrode pattern 11 contact hole 1 la ~ 1 lc contact hole 12 first light shielding film pattern 13 insulating substrate 14 polycrystalline Si film pattern 15 Auxiliary capacitor electrode 16 Gate wiring 17 Gate insulating film 18 Thin film transistor (TFT) 19 Liquid crystal display device 20 Signal wiring pattern 30 Active matrix substrate 31 Opposite substrate 40 To be polished 41 To be polished 42 Insulating film 5 0 Silicon oxide film ( Silicon oxide film) 51 Silicon nitride film (silicon nitride film) -47-

83666.DOC

Claims (1)

124 ^ &amp; Φδ〇3289 Chinese Patent Application for Patent Application Replacement (August 1993) Pick up and apply for a patent park: 1 · A substrate with a flattening film, which is characterized by burying the surface of the substrate A flattening film is formed in a manner of unevenness caused by wood, and a predetermined space is formed from the convex portion between the convex surface and the convex surface on the substrate surface to form a dummy pattern for flattening; the flattening film is buried. The dummy pattern and the convex portion are formed. 2. If the substrate with a flattening film according to item 丨 of the patent application includes: a plurality of patterned layers; and a plurality of flat films, which are formed by laminating the patterned layers between the layers; The flat film formation surface of at least one of the flat films is between the convex 4 and convex projections generated by the pattern portion layer existing on the formation surface, that is, a predetermined interval is vacated from the convex portion to form a flattening. Used dummy pattern. 3. The substrate with a flattening film as described in the first patent application scope, which is a substrate for a display device. 4. The substrate with a flattening film as described in the first patent application scope, which is a substrate for a liquid crystal display device. 5. The substrate with a flattening film according to item 1 of the scope of the patent application, wherein the dummy pattern includes a silicon oxide film, a silicon nitride film, or a film laminated with a silicon oxide film and a silicon nitride film. 6 _ — A substrate for a head display device, which is characterized in that a pixel electrode is formed on the substrate through a flattening film; the flattening film is used to bury the unevenness generated by the pattern existing under the pixel electrode; On the formation surface of the flattening film described above, on the formation surface where the unevenness caused by the pattern 83666-930805 1241646 exists, between the convex portion and the convex portion, a space a is formed from the convex portion to form a dummy for planarization. Pattern; the planarizing film is formed by burying the dummy pattern and the convex portion. 7. A substrate for a head display device, which is characterized in that an active element for controlling signal writing to a pixel electrode is provided on the substrate, and on the active element, a flattening film is formed through the flat element to prevent light from being irradiated onto the substrate. A light-shielding film for an active element; the flattening film is used to bury the unevenness generated by the pattern underlying the pixel electrode; ^ it is the formation surface of the above-mentioned flattening film, and on the formation surface of the unevenness generated by the pattern, Between the convex portion and the convex portion, a predetermined space is formed from the convex portion to form a dummy pattern for planarization; the planarizing film is formed by burying the space between the dummy pattern and the convex portion. 8. A substrate for a display device, which is characterized by having a pixel electrode on the substrate, a moving element that controls writing of the signal to the pixel electrode, and a plurality of pattern layers that drive the active element. Wiring, etc .; and most interlayer insulating films, which are formed by laminating the interlayers of the pattern portion, and are formed on at least one of the above-mentioned interlayer insulating films. The unevenness between the convex part and convex part of the pattern part layer on the formation surface, that is, a predetermined space is vacated from the convex part, and a dummy image for flattening is formed; and the dummy pattern is buried with An interlayer insulating film is formed between the convex portions, and the surface of the interlayer insulating film has been flattened. 9. The substrate for a display device according to any one of items 6 to 8 of the scope of application for a patent, 83666-930805 1241646, which is a substrate for a liquid crystal display device. 10. The substrate for a display device according to any one of claims 6 to 8, in which the above dummy pattern includes a silicon oxide film, a silicon nitride film, or a silicon oxide film and a silicon nitride film laminated thereon. membrane. 11_ The substrate for a display device according to item 7 or 8 of the scope of patent application, wherein the active device is a thin film transistor (TFT). 12 · —A method for manufacturing a substrate with a flattening film, characterized in that a flattening film is formed by burying unevenness caused by a pattern on the surface of the substrate; it is a way of burying unevenness caused by a pattern on the surface of the substrate Before forming the flattening film, a predetermined space is formed in advance between the convex portion and the concave portion on the substrate surface, and a dummy pattern for flattening is formed in advance, and then the dummy pattern and the convex portion are buried. A planarization film is formed. 13. A method for manufacturing a substrate with a flattening film according to item 12 of the scope of the patent application, which is a method for manufacturing a substrate for a display device. 14. A method for manufacturing a substrate with a flattening film according to item 12 of the scope of the patent application, which is a method for manufacturing a substrate for a liquid crystal display device. 1 5 · The method for manufacturing a substrate with a flattening film according to item 2 of the patent application range, wherein the dummy pattern is formed by a silicon oxide film, a silicon nitride film, or a silicon oxide film and a silicon nitride layered Made of film. 16. The method for manufacturing a substrate with a flattening film according to item 12 of the scope of patent application, which uses a chemical mechanical polishing (CMP) method to perform a film formed by burying the space between the dummy pattern and the convex portion. The planarization is performed to form the planarization film. 1 7 · —A method for manufacturing a substrate for a display device, characterized in that a pixel electrode is formed on the substrate via a planarizing film; the planarizing film is used to bury 1241646 a pattern existing under the pixel electrode Concave and convex; it is formed before the flattening film is used to bury the unevenness generated at the bottom of the pixel electrode, and the formation surface of the above-mentioned flattening film, that is, the formation surface of the unevenness produced by the pattern i Between the convex portion and the concave portion, a predetermined space is provided from the convex portion to form a dummy pattern for flattening in advance, and then a planarization film is formed so as to bury the space between the dummy pattern and the convex portion. I8 · A method for manufacturing a substrate for a display device, which is characterized in that an active element for controlling the signal insertion of pixel electrodes is provided on the substrate, and on the active 7L part, a flattening M is formed to prevent light from being irradiated To the light-shielding film of the active 7C; the flattening film is used to bury the unevenness generated by the pattern existing under the pixel pen pole; 2 before the flattening film is formed by burying the unevenness generated by the pattern, Between the convex portion and the convex portion of the pattern, a predetermined space is provided from the convex portion to form a dummy pattern for planarization in advance, and a planarizing film is formed between the pattern and the convex portion. The mask is a manufacturing method of a substrate for a display device, which is characterized in that the substrate has: a pixel electrode; an active element that controls the signal input to the pixel electrode; and most pattern layers that drive the active Element wiring and the like, and a plurality of interlayer insulating films are formed by laminating the pattern portions between layers; f includes: forming an interlayer insulating film on at least one of the above-mentioned plurality of interlayer insulating films; The step of forming a flat dummy pattern between the convex and convex portions of the uneven portion generated by the pattern portion layer of the formation surface, ie, vacating a predetermined interval from the convex portion; 83666-930805 -4- 1241646 to bury the A step of forming an interlayer insulating film in a manner between the dummy pattern and the convex portion; and a step of planarizing a surface of the interlayer insulating film. 20. The method for manufacturing a substrate for a display device according to any one of claims 17 to 19, which is a method for manufacturing a substrate for a liquid crystal display device. 21. A method for manufacturing a substrate for a display device according to item 18 or 19 of the scope of patent application ', wherein the active element is a thin film transistor (TFT). 22. The method for manufacturing a substrate for a display device according to any one of claims 17 to 19, wherein the dummy pattern is formed by a silicon oxide film, a nitrided film, or an oxide layer; And nitride film. 23. · A method for manufacturing a substrate for a display device according to item 17 or 18 of the scope of application for a patent, which uses a chemical mechanical polishing (CMP) method to perform a film formed by burying the space between the dummy pattern and the convex portion. The planarization is performed to form the planarization film. 24. The method for manufacturing a substrate for a display device according to item 19 of the patent application, which is a step of planarizing the surface of the interlayer insulating film by planarizing the surface of the interlayer insulating film by a CMP method. 83666-930805