TW560005B - Method for forming smooth floating gate structure for flash memory - Google Patents

Abstract

A method for forming a smooth floating gate structure for a flash memory is disclosed. The method comprises the following steps. A substrate is firstly provided, and a first conductive layer and a second conductive layer are sequentially formed on the substrate. A first dielectric layer is then formed on the second conductive layer. A first hard mask layer and a second hard mask layer are formed sequentially on the first dielectric layer. A floating gate pattern is then transferred into the second hard mask layer to expose the first hard mask layer. The first hard mask layer is then etched to form a pattern and expose the first dielectric layer. A second dielectric layer is conformally formed over the second hard mask layer and the pattern. The second dielectric layer is etched back to form a spacer and expose the first dielectric layer. The first dielectric layer is then etched to expose the second conductive layer and the spacer, the second hard mask layer, the first hard mask layer and the first dielectric layer are finally removed.

Description

560005 V. Description of the invention (l)-5-1 Field of the invention: The present invention relates to a method for forming a floating gate structure of a flash memory, in particular to a method for forming a floating gate structure having a smooth floating gate structure. Flash memory method. 5-2 Background of the Invention: Both non-volatile memory (Electrical Erasable) and flash memory can be powered. Even after the power is turned off, logic integrated circuits can also use non-volatile memory. But non-volatile memory life is limited by program data. The lifetime of these components is that the non-volatile memory has a gate, and this floating gate is on the range—the control gate can be placed with another control gate. Therefore, the floating gate is erased by programmable read-only memory such as electrical (

Programmable Read Only Memory erases and rewrites data. These components store data. Similarly, the programmable volatile memory can be erased to execute the programmable logic function and the erasable programmable logic integrated circuit. The associated stress generated by the write and erase cycles is the number of data write and erase cycles. The important part is that the float in the field effect transistor is usually placed on a floating gate in a channel region connecting the source and the drain, and is isolated by a dielectric layer and insulated by a neighboring diffusion region isolated from the floating gate Surrounded by a dielectric material. Threshold voltage operation; & ', ",, required to turn on the transistor and make the source and drain conductive

560005 V. Description of the invention (2) The minimum voltage applied to the control gate. The threshold voltage is a function of the number of charges in the floating gate. The gate is controlled as a word line so that the selected memory cells in a two-dimensional memory array can perform read and write operations. Erasing data in a memory cell requires maintaining the control gate, source, and drain at an appropriate voltage to allow charges to pass from the substrate through the tunnel oxide layer to the floating gate. If enough electrons are accumulated in the floating gate, the channel conductivity of the field effect transistor of the memory cell will change. By measuring the conductivity of the memory cell, it can be determined whether the stored data is "1" or "0". Because the floating gate system is completely isolated, the memory cells are non-volatile and will retain the charge indefinitely without applying any power. Non-volatile memory cells are also programmable. When writing data, the control gate, source, and drain maintain an appropriate voltage to allow electrons to pass through the tunnel oxide layer to the substrate or source region of the substrate. This operation reverses the effect of the erase operation. Ensuring reliability is a costly, time-consuming, difficult but important task for the development and production of integrated circuits. This is especially true for non-volatile memories. In addition to the non-volatile memory that must withstand the failure tests of general integrated circuit components, such as package failure, electrostatic damage and oxide layer failure, it must also face more reliability requirements. For example, non-volatile memory must be able to effectively retain data for long periods of time and maintain normal operation during repeated write and erase operations.

560005 V. Description of the invention (3) The first A diagram to the first p-solid-time one-pole process flow. Second, the non-transmitting_floating gated silicon layer 102 forming a flash memory (the first > A picture shows that an oxide layer 106 and a multilayer 108 are formed in a stone) : F gate layer), -silicon nitride layer 104, and -photoresist layer 008, to expose the results on 彳 彳 10 /. A pattern is then transferred to the optical layer 104 and the polycrystalline silicon #f layer 104. As shown in FIG. 1B, the silicon nitride is formed to form a trench, and the etched layer 106 is separated from the silicon substrate 100 by an etched trench. The silicon nitride layer 〇 〇4 pile foundation 队 河 河 付 U _ formation shallow engraved to the polycrystalline stone evening sound 102 / surface Γ ΐ and the dielectric material 110 is etched / said 10 2 surface degree. Then, as in the first crystal: layer "2 (second floating idler layer)" and a nitride layer "4", a structure not shown in the figure B is formed. A pattern of floating gates is then entered into the stone layer 114 and the polycrystalline silicon layer 112. Then, as shown in FIG. 10, a chemical layer 116 is formed next, and is etched to form a spacer. As shown in the first figure E1, the polycrystalline silicon layer 112 is then etched to expose the dielectric material u. Two = F, the silicon nitride layer 11 4 and the silicon nitride layer i 丨 6 are then removed to form a floating gate. The floating gate shown in the first F figure contains many acute angles. These acute angles are very likely to cause the loss of charge during repeated writing and erasing operations, so it affects the long-term effective storage of data and reduces flash memory. Reliability. In addition, these extra sharp angles will also affect the configuration of the subsequent zigzag lines of the flash memory (Topo 1 ogy). s y Therefore, it is very necessary to propose a novel method for forming the gate structure of the flash memory, so that the above-mentioned traditional process ^ question f

Page 8 560005 V. Description of the Invention (4) was resolved. This is the purpose proposed by the present invention. 5-3 Object and Summary of the Invention: One object of the present invention is to provide a flash memory floating gate forming method which can eliminate the acute angle effect of the floating gate. Another object of the present invention is to provide a smooth floating gate structure of a flash memory. Another object of the present invention is to provide a smooth floating gate structure of a reliable flash memory. The floating gate structure has a good data storage ability. To achieve the above object, the present invention provides a method for forming a floating gate of a flash memory. The method includes the following steps. First, a substrate is provided, and a first conductor layer and a second conductor layer are formed on the substrate. A first dielectric layer is then formed on the second conductor layer, and a first mask layer and a second mask layer are sequentially formed on the first dielectric layer. Then, a floating gate pattern is transferred into the second mask layer to expose the first mask layer and the first mask layer is etched to form a pattern and expose the first dielectric layer. A second dielectric layer is then formed on the second masking layer and the pattern, and the second dielectric layer is etched back to form a gap wall and expose the first dielectric layer. The first dielectric layer is then etched to expose the second conductor layer and the gap is removed.

560005

5. Description of the invention (5) The wall, the second mask layer, the first mask layer and the first dielectric layer. The above brief description of the invention and the following detailed description are only exemplary and not limiting. Other equivalent changes or modifications that do not depart from the spirit of the invention should be included in the patent scope of the invention. Detailed description of the second 5-4 invention:

It must be noted here that the process steps and structures described below do not include a complete process. The present invention can be implemented by various integrated circuit process technologies, and only the process technologies required to understand the present invention are mentioned here. The following detailed description will be made according to the accompanying drawings of the present invention. Please note that the drawings are in simple form and not drawn to scale, and the dimensions are exaggerated to facilitate understanding of the present invention. Referring to the second figure A, a substrate 200 is shown. This substrate 200 has a shallow trench isolation 2 0 2 therein, and an oxide layer 2 0 4, a conductor layer 2 6 and 208, and a dielectric layer. Electrical layers 210, 21 2 and 21 4 and a photoresist layer 21 6 are formed thereon. The substrate 200 includes a silicon substrate having a < 10 〇 > lattice direction, but is not limited to a silicon substrate. An oxide layer 204, a conductor layer 206, and a dielectric layer (not shown) including a silicon nitride layer are first formed on the substrate 200. The oxide layer 2 0 4 can be formed by a conventional oxidation method. Next, a conventional lithography process is used to define an active area on the oxide layer 204, the conductor layer 206, and the dielectric layer, and expose a shallow trench to isolate the predetermined formation.

Page 10 560005 V. Description of the invention (6) " Then, the dielectric layer, the conductive layer 206, the oxide layer 204, and the substrate 200 are etched by the money engraving process to form a trench, and the dielectric layer 202 is filled in the trench. The lithography process is preferably performed by a reactive ion etching method, and the dielectric layer 202 is preferably a high density plasma oxide layer (High Density Plasma). Then, the surface of the dielectric layer 202 is planarized by a chemical mechanical polishing method, and the dielectric layer 202 is etched to the same height as the surface of the conductive layer 206 by a conventional etching process. The dielectric layer (not shown) is then removed. A conductive layer 208 is then formed on the dielectric layer 202 to the conductive layer 206. The conductive layers 206 and 208 are preferably a polycrystalline silicon layer, and can be formed by a conventional chemical vapor deposition method. The dielectric layers 2 1 0, 2 12 and 2 1 4 are sequentially formed by conventional deposition methods, and the dielectric layer 2 1 0 includes a silicon nitride layer: the dielectric layers 212 and 2 are used to define In the photolithography and etching granulation of the floating gate, as a hard mask, the dielectric layer 2 1 2 is preferably a photoresist layer and the dielectric layer 21 4 is a SOG layer. . The photoresist layer 21 6 is used for the area where the floating gate is sensed. Referring to the second β figure, the results of etching the dielectric layer 2 丨 4 to expose the dielectric layer 2 1 2 and removing the photoresist layer 2 1 6 are shown. The dielectric layer 2 1 4 can be traditionally etched, and the photoresist layer 2 6 is stripped in a conventional manner. The second figure C shows that the dielectric layer 2 1 2 is etched with the dielectric layer 2 1 4 as a mask to expose the dielectric layer 2 1 0, and a dielectric layer 2 1 8 is formed and etched back to form a gap wall. the result of. The dielectric layer 2 1 2 can be etched by a conventional etching process, and the dielectric layer 2 1 8 is preferably a polymer layer. The dielectric layer is etched back by Reactive Ion Etching. The second β diagram shows a result of etching the dielectric layer 210 with the dielectric layer 4 as an etching mask to expose the conductive layer 208. 560005 V. Description of the invention (7) The electrical layer 210 can be etched by a conventional etching process. Referring to the second figure E, the result of removing the spacers 2 1 8, the dielectric layers 2 1 4 and 2 1 2 and etching the conductor layer 2 08 by a conventional etching process to expose the shallow trench isolation 2 0 2 is shown. . The spacer 2 1 8 can be removed by hydrofluoric acid, and the dielectric layers 2 1 4 and 2 1 2 can be removed by a conventional etching process. As shown in FIG. 2f, after removing the dielectric layer 210, the floating gate structure of the flash memory of the present invention is formed. The next process is to form an oxide-nitride-oxide layer (Oxide-Nitride-Oxide Layer) in a conventional way on the floating gate structure of the flash memory shown in Figure 2F. The flash memory process then proceeds to complete the flash memory. The method for forming a flash memory with a smooth floating gate structure according to the present invention described above can eliminate the acute angle effect of the floating gate produced by the traditional process, and form a floating gate structure with no turning (sharp) angle. This floating gate structure can reduce the leakage of charge during repeated writing and erasing operations, so it has good data to be effectively kept. It knife is unknown

The above detailed description of the invention is merely an example and not a limitation. All equivalent changes or modifications that depart from the spirit of the present invention should be included in the scope of other patents. X

560005 Brief description of the drawings Brief description of the drawings: In order to make the other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is described below in conjunction with the accompanying drawings for detailed description. As follows: Figure A shows the results of forming an oxide layer, a polycrystalline stone layer, a nitride stone layer and a photoresist layer on a substrate; Figure B shows a worm-etched nitride stone layer, The polycrystalline silicon layer, the oxide layer and the substrate form a trench, and the trench is filled with a dielectric material to form a shallow trench isolation result. The first C diagram shows the formation of a polycrystalline silicon layer and a silicon nitride layer. The results on the structure shown in the first diagram B; the first diagram D shows the results of forming and etching a silicon nitride layer to form a spacer; the first diagram E shows the results of etching the polycrystalline silicon layer to expose the dielectric material; Figure 1F shows the result of removing the two silicon nitride layers to form a floating gate;

560005 Brief description of the diagram. The second diagram A shows a substrate with shallow trenches isolated therein and an oxide layer, two conductor layers, three dielectric layers, and a photoresist layer thereon. The second diagram B shows the etching process. The upper dielectric layer to expose the intermediate dielectric layer and remove the photoresist layer;

The second diagram C shows the results of using the upper dielectric layer as a mask to etch the middle dielectric layer to expose the lower dielectric layer, and forming and etching back a dielectric layer to form a spacer; the second diagram D shows the results The uppermost dielectric layer is the result of masking and etching the lower dielectric layer to expose the conductor layer. The second E diagram shows the removal of the spacer, the uppermost dielectric layer and the middle dielectric layer, and the conductor layer is etched to expose Results of shallow trench isolation; and Figure 2F shows the results of removing the lower dielectric layer to form the flash memory floating gate of the present invention.

Representative symbols of main parts: 1 0 0 substrate 102 polycrystalline silicon layer 10 4 silicon nitride layer

Page 14 560005 Brief description of the drawing 1 0 6 oxide layer I 0 8 photoresist layer II 0 dielectric material 11 2 polycrystalline silicon layer 11 4 silicon nitride layer 1 1 6 silicon nitride layer 2 0 0 substrate 2 0 2 shallow Trench isolation 2 0 4 oxide layer 2 0 6 conductor layer 2 0 8 conductor layer 2 1 0 dielectric layer 2 1 2 dielectric layer 2 1 4 dielectric layer 2 1 6 photoresist layer 2 1 8 dielectric layer

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Claims (1)

560005 6. Scope of patent application Patent scope: 1. A method for forming a floating gate of a flash memory, the method includes the following steps: providing a substrate; forming a first conductor layer and a second conductor layer on On the substrate; forming a first dielectric layer on the second conductor layer; sequentially forming a first mask layer and a second mask layer on the first dielectric layer; Transferring a floating gate pattern into the second mask layer to expose the first mask layer; etching the first mask layer to form a pattern and exposing the first dielectric layer; forming a second dielectric An electrical layer is formed on the second mask layer and the pattern; the second dielectric layer is etched to form a gap wall and the first dielectric layer is exposed; the first dielectric layer is etched to expose the second A conductor layer; and removing the spacer, the second mask layer, the first mask layer, and the first dielectric layer. 2. The method for forming a floating gate of a flash memory as described in item 1 of the scope of the patent application, wherein the first conductive layer and a second conductive layer described above include a polycrystalline silicon layer. Page 16 560005 6. Scope of patent application 3 · The method for forming a floating gate of a flash memory as described in item 1 of the scope of patent application, wherein the first dielectric layer includes a silicon nitride layer. 4. The method for forming a floating gate of a flash memory as described in item 1 of the scope of the patent application, wherein the first mask layer described above includes a photoresist layer. 5. The method for forming a floating gate of a flash memory as described in item 1 of the scope of patent application, wherein the forming of the floating gate pattern described above includes forming a photoresist layer having the floating gate pattern The second mask layer is etched on the second mask layer using the photoresist layer as a mask. 6. The method for forming a floating gate of a flash memory as described in item 1 of the scope of the patent application, wherein the second dielectric layer includes a polymer layer. 7. A method for forming a floating gate of a flash memory, the method comprising the following steps: providing a substrate having an oxide layer, a first conductor layer and a first dielectric layer on the substrate; Transfer a shallow trench isolation region pattern into the first dielectric layer, the first conductor layer, the oxide layer and the substrate to form a trench; fill a trench with a dielectric material to form a shallow trench isolation; move Remove the first dielectric layer; form a second conductor layer on the first conductor layer and isolate the shallow trench Page 17 560005 VI. Application scope Patent No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electricity No. 2 Electric Power No. The layers are exposed one by one, and the upper layer of the wall is covered with the first layer of the wall, and the gap between the two layers is covered. The first shape of the layer covers the layer, the second layer covers the cover, the second layer covers the layer, the second layer covers the layer, the second layer covers the dielectric layer, the first layer covers the dielectric layer, the first layer covers the third layer, and the second layer is placed on the third layer. The gap becomes the first, the first, the first, and the first; Sequential shift layer engraved into #; etch remove layer shape; transfer mask etch back to layer etch and transfer electricity; cover the dielectric layer; 8-pole gate, < > I, y /, i.e., flash memory forming, description of the layer of nitrogen silicide-cladding-containing dielectric-shape containment-buoyant core > cheng of / shape案 案->-= 口 图 闪-Ge Li Xing Zhe's description ζ Aso Soto Hai item J 7's description of the range of Fan Zhongli, please ask Fa Shenfang such as the 9. polar layer Conductive dielectrics one by one and the remaining layers in the first and second engraved areas of the resistive dielectric layer. The bottom canal that separates from the cover material is the trench layer and the shallow resistance layer. The photochemical has the oxygen device with the one ’’ upper layer to place the floating body. Page 18 560005 6. The method of applying for a patent, in which the above-mentioned dielectric material includes a high-density plasma oxide layer. The scope of the patent application is to apply for a body guide with a floating layer. Recalling a moment of the first # 闪 此 法 快 、 刻成 层 # The shape of the electron is separated from the first element of the above-mentioned one of the anti-9. The above is the bottom line of the material, and this method is related to the squared layer of chemical oxygen. Li Zhuan invited Zhongrufa's pole gates to be connected to the float. After the body canal ditch ditch ditch = mouth = mouth flashed into the material to fill the material. Etch and melt. The flat surface high table material is the same material as the electrical surface interfacial surface. The layer method body is ground and studied to the material. 3. The flash memory is formed as described in item 7 of the scope of patent application. The method for floating a gate, wherein the third dielectric layer includes a polymer layer. 1 4. A method for forming a floating gate of a flash memory, the method comprising the following steps: providing a substrate having an oxide layer, a first polycrystalline layer and a first intermediary layer on the substrate; Electrical layer; transferring a shallow trench isolation region pattern into the first dielectric layer, the first polycrystalline silicon layer, the oxide layer, and the substrate to form a trench; filling a dielectric material into the trench to form a trench Shallow trench isolation; removing the first dielectric layer; forming a second polycrystalline silicon layer to isolate the first polycrystalline silicon layer from the shallow trench Page 19 560005 6. The scope of the patent application is above; forming a second dielectric layer on the second polycrystalline silicon layer; sequentially forming a first mask layer and a second mask layer on the second dielectric layer Transferring a floating gate pattern into the second mask layer to expose the first mask layer; etching the first mask layer to form a pattern and exposing the second dielectric layer; forming a polymer Layer on the second mask layer and the pattern; etch back the polymer layer to form a gap and expose the second dielectric layer; etch the second dielectric layer to expose the second polycrystalline silicon layer ; And removing the spacer, the second mask layer, the first mask layer, and the second dielectric layer. Fan Li specially applied for the inclusion-inclusiveness of the poles of the French side. -Formed body ΗHidden case = mouth picture flash fast ㈣ 戋 separated into 鬲 shaped FU canal 4 of the 述 layer of the layer to cut the electric crystal medium more one one first Haiheshi δ = mouth in, layer by layer mlTl> g. In the case of ci Guangji, the area is etched away. The bottom trench of the cover material channel is the shallow layer and the barrier layer with the photochemical tools. The oxygen is formed by the upper layer and the upper layer. Fan Li specially requested to apply the floating body to remember the flash formation of the ancient mouth. After the power is connected, the channel will be etched and etched into the flat material surface. The meter will be used as a material for the material. The general of the material will be ground in the method. -^ Ask Page 20 560005 VI. Scope of patent application The material reaches the same height as the surface of the first polycrystalline silicon layer. Set the floating body to remember the flash formation of the item 4 1X Fan Li specially requested to apply the shape of the gate including the package forming the pole gate to float the above-mentioned pole gate of the method above the cover Second should be. The two cases of the layered masking cover are shown in the figure.