569301 A7 ___B7__ 五、發明說明（/ ) 本案指定代表圖為：第一圖。 本代表圖之元件代表符號簡單說明： (請先閱讀背面之注意事項再填寫本頁) (1 0 )第一基板 （1 0 1 )犧牲層 (1 0 2)蝕刻/研磨保護層 (1 0 3 )半導體元件保護層 (11)半導體薄膜 (1 2 )畫素電極 （1 3 )透明絕緣層 (1 3 a )閘極絕緣層 （1 4)閘極電極 (1 4 1 )絕緣層 （1 5 )光學元件 (2 0 )第二基板 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 569301 A7 B7 五、發明說明（二） 〔發明所屬之技術領域〕 (請先閱讀背面之注意事項再填寫本頁) 本發明係關於一種薄膜電晶體顯示面板之製法， 供製程簡化且良率高的顯示器面板製法。 ’、 〔先前技術〕 請參閱第十二圖所示，係為目前一種薄膜電晶 面板的轉載製法，並宣稱具有高品質的半導體元件 特性，其包括下列步驟： 提供一表面形成有犧牲層（5 0 1 )的基板（5 〇)，該犧牲層（501)上端面形成一氫爆保護層（5 U，再於該氫爆保護層（51)上依序形成有一半導體 薄膜（5 2)、-第一透明絕緣層（5 3 )、一間極電極 (5 6) ’以構成—半導體元件（薄膜電晶體），再於半 導體元件上依序覆蓋一第二絕緣層（54)及芦 (55)； 形成一畫素電極（5 7)，係於該保護層（5 5 )覆 蓋一畫素電極層（57)，再以黃光、钱刻製程形圖畫素 電極（57) ’其中該畫素電極（57)以連接半導體薄 膜（5 2 )，如第十二圖A所示； 形成-暫時披覆層（6〇)並鍵合—支撐基板（6 1)，係於保護層（55)與晝素電極（57)上形成一 暫時彼覆層（6 0 )，再於該暫時披覆層（6 〇 )上鍵合 该支撲基板（6 1)，如第十二圖b所示； 由基板（5 0 )入射雷射光至該犧牲層（5 〇丄）， 由於犧牲層（5 〇 1 )為一含有氫原子的非晶石夕膜，配合 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公爱 569301 A7 I—----------- 五、發明說明（>) 照射雷射光的產生的熱，會產生爆裂使基板（5 0)與半 導體元件脫離，如第十二圖C及第十二圖D所示； 鍵合一第二基板（7 0 )，該第二基板（7 〇 )係供 轉移半導體元件的基板，如第十二圖E所示； 去除支撐基板（6 1 )及暫時披覆層（6 〇 )，令上 端的畫素電極（57)外露，如第十二圖f所示。 以上製程係預先於可成長良好電氣特性的第一基板 (50)上完成半導體元件之製作，再轉載至第二基板 (70)上，令第二基板（7〇)上具有良好電氣特性之 半導體元件（TFT、MIM、TFD)，然而，此製程於實際施例 時仍具有下列各項缺點： 1·使用過多基板：由完成製作半導體元件的製程 中，共計使用至少三基板。 2 ·成本過高··由於使用基板數量多，令製程步驟相 對複雜，又，製程中的支撐基板與披覆層通常為消耗性材 料，係提供半導體元件進行氫爆轉載時一支撐力，於二次 轉載後，即去除不用，有成本過高之虞，而前揭製程僅形 成面板的半導體元件，之後還需進行光學元件之製程，增 加光學元件與半導體元件對位的程序，可推知使用之設備 亦會增加製程成本。 3 ·晝素電極之外露面為不平坦面··由於畫素電極經 高溫製程形成，故其表面無法達到完全的平坦面，故會產 生尖知放電造成畫面出現不正常光點，因而影響顯示α569301 A7 ___B7__ 5. Description of the Invention (/) The designated representative picture in this case is: the first picture. A brief description of the component representative symbols in this representative map: (Please read the precautions on the back before filling this page) (1 0) the first substrate (1 0 1) sacrificial layer (1 0 2) etching / grinding protective layer (1 0 3) semiconductor element protective layer (11) semiconductor thin film (1 2) pixel electrode (1 3) transparent insulating layer (1 3 a) gate insulating layer (1 4) gate electrode (1 4 1) insulating layer (1 5) Optical element (2 0) Second substrate The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 569301 A7 B7 V. Description of the invention (2) [Technical field to which the invention belongs] (please first (Please read the notes on the back and fill in this page again.) The present invention relates to a method for manufacturing a thin film transistor display panel, which provides a method for manufacturing a display panel with a simplified process and a high yield. ', [Prior art] Please refer to the twelfth figure, which is a current method for reproducing a thin-film transistor panel and claims to have high-quality semiconductor device characteristics, which includes the following steps: providing a surface with a sacrificial layer ( 5 0) substrate (50), a hydrogen explosion protection layer (5 U) is formed on the upper end surface of the sacrificial layer (501), and a semiconductor film (5 2) is sequentially formed on the hydrogen explosion protection layer (51). The first transparent insulating layer (5 3) and an interelectrode (5 6) are used to form a semiconductor element (thin film transistor), and then a second insulating layer (54) and a semiconductor element are sequentially covered on the semiconductor element. (55); forming a pixel electrode (5 7), the protective layer (5 5) is covered with a pixel electrode layer (57), and the pixel electrode (57) is formed in a process shape with yellow light and money The pixel electrode (57) is connected to the semiconductor thin film (5 2), as shown in FIG. 12A; forming-temporary coating layer (60) and bonding-supporting substrate (61), tied to the protective layer (55) forming a temporary coating layer (60) on the day electrode (57), and bonding on the temporary coating layer (60) The support substrate (61) is shown in FIG. 12b; the laser light is incident from the substrate (50) to the sacrificial layer (505), because the sacrificial layer (501) contains a hydrogen atom Amorphous stone evening film, in accordance with the paper size applicable to China National Standard (CNS) A4 specifications (210 X 297 public love 569301 A7 I --------------- 5. Description of the invention (>) The heat generated by irradiating the laser light will cause the substrate (50) to detach from the semiconductor element, as shown in Fig. 12C and Fig. 12D; a second substrate (70) is bonded to the second substrate (70). The two substrates (70) are substrates for transferring semiconductor elements, as shown in Fig. 12E; the supporting substrate (61) and the temporary coating layer (60) are removed, and the upper pixel electrode (57) is exposed. , As shown in Figure 12f. The above process is to complete the fabrication of semiconductor elements on a first substrate (50) that can grow good electrical characteristics in advance, and then reprint it on a second substrate (70) to make the second substrate ( 7〇) semiconductor devices (TFT, MIM, TFD) with good electrical characteristics, however, this process still has the following disadvantages in actual implementation: 1 · Using too many substrates: A total of at least three substrates are used in the process of manufacturing semiconductor devices. 2 · Excessive cost. · Because of the large number of substrates, the process steps are relatively complicated, and the supporting substrates and coatings in the process. It is usually a consumable material. It provides a supporting force for semiconductor components for hydrogen explosion reprinting. After the second reprinting, it is removed and not used. There is a risk of excessive cost. The previous lift-off process only forms the semiconductor elements of the panel. During the manufacturing process of optical elements, the process of aligning optical elements with semiconductor elements is increased. It can be inferred that the equipment used will also increase the manufacturing cost. 3 · The exposed surface outside the day electrode is uneven. · Since the pixel electrode is formed by a high-temperature process, its surface cannot reach a completely flat surface, so sharp discharges will cause abnormal light spots on the screen, which will affect the display. α
Lr_, 張尺度適用干國國家標準（CNS)A4規格（21〇 χ 297公釐） ------Lr_, Zhang scale is applicable to National Standard of Dryland (CNS) A4 (21 × 297 mm) ------
II— I I I I I · I I (請先fla.讀背面之注意事項再填寫本頁) 訂·- ，線· 569301 A7 ------2Z____ 五、發明說明（/ ) (請先閱讀背面之注意事項再填寫本頁) ^是以，上述製程仍存在製程步驟複雜、高成本等問 題，不具實用性，故而此種轉載方式的薄膜電晶體顯示器 之面板應可再進一步改善，以降低其製程成本。 〔發明内容〕 為此，本發明的主要目的係提供一種低成本且易實施 的薄膜電晶體顯示器之面板製法，其可於一次氫爆棒載 時，即有效地將半導體元件整合光學元件移轉至適合的基 板上，而無使用消耗性基板等材料，又，因半導體元件已 與光學元件預先整合，故無後續精密對準兩元件的問題， 加上，本發明之畫素電極具有平坦的外露表面，以提高晝 面顯示品質。 •線· 欲達上述目的所使用之主要技術手段係將畫素電極直 接形成在一表面形成有犧牲層的第一基板的上端面，亦 即，於其上進行半導體元件製程，待完成良好電氣等性之 半導體元件後，再向上依序形成光學元件（如濾光材料、 色轉換材料、偏極片、增亮片、擴散片、配向膜、廣視角 層、抗反射層、反射層、光吸收層等），至此完成第一基 板單面整合半導體與光學兩元件之製作，爾後，取一第二 基板覆蓋於第一基板上端面的光學元件，並對第一基板另 一端面加熱使其表面的犧牲層爆裂，而令第一基板脫離其 上的半導體元件、光學元件及第二基板，此時，原形成於 第一基板的畫素電極再利用黃光、蝕刻製程使之外露或直 接外露，至此完成一薄膜電晶體的顯示面板； 由上述可知，晝素電極外露的端面相當平坦，再者， ___ _6 本紙張尺度適用中國國家標準（〇siS)A4規格（21G X 297公髮)" " --- 569301 A7 ----------Β7 —___ 五、發明說明（广） ^~^ 由於第一基板預先整合半導體元件及光學元件，故當轉載 至第二基板上，將無兩元件間對準之問題；是以，本發明 係為一僅具有簡單製程且低成本的製程。 〔資施方式〕 本發明係提供一種低成本薄膜電晶體顯示器之面板的 製法，首先請參閱第一圖A至F所示，係為本發明第一較 佳實施例的薄膜電晶體顯示器之面板製程，其包括有： 提供一第一基板（1〇)，其可為矽、塑膠、破璃、 石英#材質基板，其上端面形成有一犧牲層（1〇1)， 該犧牲層（1〇1)係為非晶矽材質，但内含有許多氮原 子於其中，當處於高溫環境下會產生氫爆現象； 形成一蝕刻/研磨保護層（1 〇 2)，該蝕刻/研磨 保護層（1 0 2)覆蓋於該犧牲層（1 〇 1 )上，其材質 可為氧化石夕、氮化矽、鑽石（Diamond )或類碳鐵石 (Diamond Like Carbon; DLC )等； 形成一半導體元件保護層（1 〇 3 )，係覆蓋於蝕刻 /研磨保護層（1 〇 2 )上； 形成一半導體薄膜（1 1 )，係將一半導體薄膜（1 1 )覆蓋於半導體元件保護層（1 〇 3 )上，再予圖形化 作為半導體元件的主動區，如欲製作薄膜電晶體則需摻雜 汲、源極區； 形成一閘極絕緣層（1 3 a )，係以一第一透明絕緣 層（13)覆蓋於半導體元件保護層（1〇3)及半導體 薄膜（1 1 )上，再經圖樣化成為位於半導體薄膜（1 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Μ--------^---------^ * * ，一 (請先閱讀背面之注意事項再填寫本頁) 569301 A7 B7 五、發明說明（心） 1 )上的閘極絕緣層（1 3 a )，該閘極絕緣層（1 3 a )上再形成有一閘極電極（1 4 )，該閘極電極（1 4)覆蓋有一絕緣層（141); 形成晝素電極（1 2 )’係形成於半導體元件保護層 (1 0 3 )上’並與半導體薄膜（1 1)構成電連接； 形成光學元件（15) ’係可為色轉換材料（螢粉、 磷粉等）、滤光材料、有機電激發光二極體（qLed )、高 分子發光二極體（PLED )偏光片、增亮片、擴散片、視角 膜片、抗反射膜等元件； 鍵合一第二基板（2 0)至該第一基板（1 〇)頂端 的光學元件（1 5 )上，係以各種鍵合方式將第二基板 (2 0 )結合至光學元件（丨5 )上；其中鍵合方式係可 為直接鍵合（direct bonding)、陽極鍵合（an〇dic bonding)、低鍵合（i〇w temperature b〇ndin㈡中間 介質鍵合（Intermediate bonding )、粘著鍵合 (Adhesive bonding)、雷射熔融鍵合等，又，各種鍵: 方式可分為整接合或選擇性接合，如第一圖B所示；口 加熱第-基板（10)，係可採用各種加熱方式（如 快速南溫退火技術、脈衝式快速高溫退火技 熱技術）對該第一基板（1〇)背面採漸進照射式 式照射加熱，如第一圖C所示，使第 = 端面的犧牲層（1〇1)姦士今植 的内 護層（…），亦元：τ刻/研磨保 — — — — — — — — — — — — — · I I *- (請先閱讀背面之注意事項再填寫本頁) 訂· · -線_ -n H 1 基板(20)，如第-:+Ε導體70件、光學元件及第二 本紙張尺度適用中國國家標準（CNS)A4規运" (210： 297公釐） 569301 A7 五、發明說明（ 移除蝕刻/研磨保護層（i 〇 2 )並圖樣化半導體元 件保護層（1 0 3 )，僅留下對應半導體元件位置的半導 體π件保護層（103)，使畫素電極（12)的下端平 坦面外露，如第一圖F。 上述第一實施例係主要將半導體電子元件（如TFT' MOS、MIM、TFD)於一般半導體製程所使用的矽、玻璃等基 板與高溫製程下形成，如此以獲得良好電氣特性之電子元 件，又，光學元件於半導體元件形成後，依照不同顯示器 形式規格之需求，繼續形成於半導體元件上，如此，在一 次轉移至第二基板（2 〇 )時，即可將光、電元件整合於 同第二基板（2 0 )上，同時達到兩元件之精確對位功 效，此外，由於畫素電極（i 2 )儘可能的靠近 美 (1 0) ’當去除第一基板（2 〇)時，該畫素電極$工 2)具有相當平坦的外露面。 請參閱第二圖A〜C所示，係為本發明第二較佳實施 例’其大多製程步驟與第一實施例相同，惟，咳第一某板 (1 0)上僅依序形成有犧牲層（1 〇 1 )及^導體^件 保護層（1 0 3 )’而未形成蝕刻/研磨保護層（圖中： 示）及配向層（圖中未示），故當第一基板（^ 後，經圖樣化形成半導體元件保護層（Ί Ω 、丄U 3 )後，即可 令畫素電極（1 2)外露。 再請參閱第三圖A〜C所示，係為本發 个赞明第三較佳實 施例，其大多製程步驟與第一實施例相间 U ’惟，該形成間 極絕緣層（1 3 a )步驟中，不再蝕刻锈楚 取甲1 4遗第一透明絕緣層 (請先閱讀背面之注意事項再填寫本頁) -裝 訂-- 9 569301II— IIIII · II (please fla. Read the notes on the back before filling this page) Order ·-, line · 569301 A7 ------ 2Z____ 5. Description of the invention (/) (Please read the notes on the back first (Fill in this page again) ^ Yes, the above process still has problems such as complicated process steps and high cost, and it is not practical. Therefore, the panel of the thin film transistor display with this reprinting method should be further improved to reduce its process cost. [Summary of the Invention] To this end, the main object of the present invention is to provide a low-cost and easy-to-implement panel method for a thin-film transistor display, which can effectively transfer semiconductor elements and integrate optical elements when a hydrogen burst is carried. To a suitable substrate without using consumable substrates and other materials, and because the semiconductor element has been integrated with the optical element in advance, there is no problem of subsequent precision alignment of the two elements. In addition, the pixel electrode of the present invention has a flat Exposed surface to improve the quality of daytime display. • Wires The main technical means used to achieve the above purpose is to directly form the pixel electrode on the upper end surface of the first substrate on which a sacrificial layer is formed on the surface, that is, a semiconductor element process is performed thereon, and a good electrical circuit is to be completed. After isotropic semiconductor elements, optical elements (such as filter materials, color conversion materials, polarizers, brighteners, diffusers, alignment films, wide viewing angle layers, anti-reflection layers, reflective layers, light absorption, etc.) are sequentially formed upward. Layers, etc.), so far, the production of the single-sided integration of semiconductor and optical elements on the first substrate is completed, and then, a second substrate is used to cover the optical element on the upper end surface of the first substrate, and the other end surface of the first substrate is heated to make its surface The sacrificial layer of the semiconductor substrate bursts, so that the first substrate is separated from the semiconductor element, the optical element, and the second substrate thereon. At this time, the pixel electrode originally formed on the first substrate is exposed or directly exposed by using yellow light and an etching process. At this point, a thin-film transistor display panel is completed. From the above, it can be seen that the exposed end face of the day element electrode is quite flat, and ___ _6 This paper is applicable National Standard (〇siS) A4 Specification (21G X 297 issued) " " --- 569301 A7 ---------- Β7 —___ V. Description of Invention (Wide) ^ ~ ^ The substrate integrates the semiconductor element and the optical element in advance, so when reprinted onto the second substrate, there will be no problem of alignment between the two elements; therefore, the present invention is a process with a simple process and low cost. [Information] The present invention is a method for manufacturing a panel of a low-cost thin-film transistor display. First, please refer to the first figures A to F. It is a panel of a thin-film transistor display according to a first preferred embodiment of the present invention. The manufacturing process includes: providing a first substrate (10), which can be a substrate made of silicon, plastic, broken glass, or quartz #; a sacrificial layer (101) is formed on an upper end surface of the sacrificial layer (10); 1) It is made of amorphous silicon, but contains many nitrogen atoms therein. When it is in a high temperature environment, a hydrogen explosion phenomenon will occur; an etching / grinding protective layer (1 02) is formed, and the etching / grinding protective layer (1) 0 2) Covering the sacrificial layer (101), the material of which can be stone oxide, silicon nitride, diamond or diamond like carbon (DLC), etc .; forming a protective layer for semiconductor elements (1 03), which is covered on the etching / grinding protective layer (10 2); forming a semiconductor thin film (1 1), which is a semiconductor thin film (1 1) covered on the semiconductor element protective layer (1 0 3) On the other hand, pre-patterning is the active In order to make a thin film transistor, the drain and source regions need to be doped; a gate insulating layer (1 3 a) is formed, and the semiconductor element protective layer (103) is covered with a first transparent insulating layer (13). ) And semiconductor film (1 1), and then patterned to be located on the semiconductor film (1 7 paper size applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) M -------- ^ --------- ^ * *, one (please read the precautions on the back before filling this page) 569301 A7 B7 V. Description of the invention (heart) 1) Gate insulation layer (1 3 a) A gate electrode (1 4) is further formed on the gate insulating layer (13a), and the gate electrode (14) is covered with an insulating layer (141); a day element electrode (12) is formed. On the semiconductor element protective layer (103) and forming an electrical connection with the semiconductor thin film (11); forming the optical element (15) 'can be a color conversion material (fluorescent powder, phosphor powder, etc.), a filter material, Organic electroluminescent diode (qLed), polymer light emitting diode (PLED) polarizer, brightness enhancement film, diffusion film, viewing angle film, anti-reflection film and other components; bonding From the second substrate (20) to the optical element (15) at the top of the first substrate (10), the second substrate (20) is bonded to the optical element (5) by various bonding methods; The bonding method can be direct bonding, anodic bonding, low bonding (intermediate bonding), adhesive bonding (low bonding) Adhesive bonding), laser fusion bonding, etc., and various bonds: The method can be divided into full bonding or selective bonding, as shown in the first figure B; mouth heating substrate-(10), can use various heating methods (Such as rapid south temperature annealing technology, pulsed rapid high temperature annealing technology), the back surface of the first substrate (10) is subjected to progressive irradiation radiation heating, as shown in the first figure C, so that the sacrificial layer at the end surface (101) The inner cover of the adulterer Imae (…), also Yuan: τ 刻 / 磨 保 — — — — — — — — — — — II *-(Please read the precautions on the back first (Fill in this page again.) Order · · -line_ -n H 1 substrate (20), such as-: + E 70 conductors, optical elements And the second paper standard is applicable to China National Standard (CNS) A4 regulations (210: 297 mm) 569301 A7 V. Description of the invention (removal of the etching / grinding protective layer (i 〇2)) and patterned semiconductor element protection Layer (103), leaving only the semiconductor π protective layer (103) corresponding to the position of the semiconductor element, so that the flat surface of the lower end of the pixel electrode (12) is exposed, as shown in the first figure F. The above-mentioned first embodiment mainly forms semiconductor electronic components (such as TFT 'MOS, MIM, TFD) on substrates such as silicon and glass used in general semiconductor manufacturing processes and high-temperature processes, so as to obtain electronic components with good electrical characteristics. After the optical element is formed, the optical element continues to be formed on the semiconductor element according to the requirements of different display form specifications. In this way, when transferring to the second substrate (200) at one time, the optical and electrical elements can be integrated in the same stage. On the two substrates (20), the precise alignment effect of the two elements is achieved at the same time. In addition, since the pixel electrode (i2) is as close as possible to the beauty (1 0), when the first substrate (20) is removed, the The pixel electrode (2) has a relatively flat exposed surface. Please refer to the second figures A to C, which are the second preferred embodiment of the present invention. Most of the manufacturing steps are the same as those of the first embodiment. However, only the first certain plate (10) is formed in order. The sacrificial layer (101) and the conductor protective layer (103) are not formed with an etching / grinding protective layer (shown in the figure) and an alignment layer (not shown in the figure). Therefore, when the first substrate ( ^ After the protective layer of the semiconductor element (Ί Ω, 丄 U 3) is formed by patterning, the pixel electrode (1 2) can be exposed. Please refer to the third figures A to C, which are for this application. Praise the third preferred embodiment, most of the process steps of which are the same as the first embodiment. However, in the step of forming the interlayer insulation layer (1 3 a), the rust is not etched and the nail is removed. The first is transparent. Insulation (please read the notes on the back before filling this page)-Binding-9 569301
B7 五、發明說明（2 ) (13)，而令該晝素電極（12)直接形成於第一、 絕緣層（1 3 )之上，是以，當進行畫素電極（工^明 露時，則需分別對蝕刻/研磨保護層（i 〇 2 )、 外 凡件保護層（1 〇 3 )以及第一透明絕緣層（J :，導體 蝕刻。 w 3 )進行 又，請參閱第四圖A〜C所示，係為本發明第四 實轭例，係綜合第二實施例與第三實施例的特徵，亦^佳 相較於第一較佳實施例，並無半導體元件保護層（圖=， 示）及配向層（圖中未示）結構，而畫素電極（ 未 形成於第一透明絕緣層（1 3 )上。 則 請參閱第五圖A〜C所示，係為本發明第五較 例，其大多製程步驟與第一實施例相同，惟，节包 上僅依序形成有犧牲層（10 1)、配向層反 已經圖樣化的半導體元件保護層（103)，其 及 極（1 2 )形成於配向層（；[〇 4 )之上。、旦’、電 再請參閱第六圖A、B所示，係為本發明第六較 施例，其大多製程步驟與第一實施例相同，惟，該第一I 板（1 0 )上僅依序形成有犧牲層（ ：： ((=，電極(…係形成於該::： 再請參閱第七圖A〜C所示’係為本發明第七較佳 施例，其大多製程步驟與第一實施例相同，惟，1第一美 板]◦)上依序形成有犧牲層（1〇1)、二研‘ 保Μ (102) '配向層（1〇4)、已圖樣化的半導 569301B7 V. Description of the invention (2) (13), and the day electrode (12) is formed directly on the first, insulating layer (1 3), so when the pixel electrode (work exposed) , It is necessary to perform an etching / grinding protective layer (i 〇2), a protective layer of an exotic piece (103), and a first transparent insulating layer (J :, conductor etching. W3). Please refer to the fourth figure As shown in A to C, this is the fourth actual yoke example of the present invention, which combines the features of the second embodiment and the third embodiment. It is also better than the first preferred embodiment without a semiconductor element protection layer ( Figure =, shown) and alignment layer (not shown) structure, and the pixel electrode (not formed on the first transparent insulating layer (1 3). Please refer to the fifth figure A to C, which is based on In the fifth comparative example of the invention, most of the manufacturing steps are the same as those of the first embodiment. However, only the sacrificial layer (101) and the alignment layer are patterned on the semiconductor element protection layer (103). The electrode (1 2) is formed on the alignment layer (; [〇4). As shown in Figures A and B of the sixth embodiment, please refer to Figure 6 and Figure 6, which is the sixth embodiment of the present invention. In this embodiment, most of the manufacturing steps are the same as those of the first embodiment, but only the sacrificial layer is sequentially formed on the first I-plate (1 0) (:: ((=, the electrode (...) is formed on the ::: Please refer to the seventh diagram A to C shown in FIG. 7 is the seventh preferred embodiment of the present invention, and most of the process steps are the same as those of the first embodiment, except that 1 is the first US board. Layer (101), ERKEN 'M (102)' alignment layer (104), patterned semiconductor 569301
五、發明說明（7 ) 體70件保瘦層（1〇3)，其中畫素電極（12)形成於 配向層（1 0 4)上。 以上為說明製作半導體元件的各種可能實施例，以下 進一步揭不數例以說明另一種實施半導體元件： 下列介紹各實施例與前揭各實施例不同乃為部份製作 流程相反’亦即，該晝素電極係提早覆蓋於基板上，爾後 再進行薄膜電晶體之製作，其可能的實施方式首先請參閲 第八圖A〜C所示，第一基板（1〇)同樣預先覆蓋一層 犧牲層（1 〇 1 )，再覆蓋一層蝕刻/研磨保護層（1 〇 2 )，而畫素電極（i 2 )隨即覆蓋於蝕刻〆研磨保護層 (1 0 2)上’再覆蓋一層半導體元件保護層（1 〇3) 於其上，以於半導體元件保護層（i 〇 3 )上製作薄膜電 曰曰體，待薄膜電晶體製作完成後，即進行光學元件（1 5 )的製作及後續氫爆及蝕刻製程。又，請參閱第九圖所 示，此一實施例相較第八圖實施例相異處為省略使用蝕刻 /研磨保護層（圖中未示）；再請參閱第十圖所示，其相 較第八圖實施例相異結構即以一配向層（i 〇 4 )取代蝕 刻/研磨保濩層（1 〇 2)，或直接形成於餘刻/研磨保 護層（102)，如第十一圖所示。 由上述各實施例說明可知，本發明的特徵係為： 1·半導體元件與光學元件係整合於同一基板上。 2 ·具良好光、電特性之面板，其轉載製程僅一次反 轉動作’即將半導體元件與光學元件係整合於合適基板 上，而第一基板可再重新使用，不造成成本之浪費。 ________ 11 本紙張尺度週用甲國國家標準（CNS)A4規格（210 X 297公f ) ---- (請先閲讀背面之注意事項再填寫本頁) I . •線· 569301 五、發明說明（丨ο) 3 ·畫素電極於形成半導體元件的製程中，係採内連 接形式’並令畫素電極儘量接近第一基板，以令轉載完成 後依半導體元件結構（如前揭各實施例）可直接外露，或 待氫爆保護層或/及半導體元件保護層圖形化後，即可外 露’特別是畫素電極並無需再經過圖形化即可外露平坦 面，以利之後搭配液晶、有機發光二極體層（〇LED)或高 分子發光二極體層（P〇lymer_LED)等發光材料時，具有 平坦化的效果，進而提高顯示品質。 由上述可知，本發明利用基板雙面加工方式，令半導 體元件可整合光學元件於同一基板上，此外，為生長較佳 光、電特性的元件，而使用氫爆轉載製程，亦僅需一次轉 移，即可完成製作咼品質之顯示器的面板，同時，供光、 電元件生長的基板可再重覆利用，相較習知氫爆製程，本 發明確實具有製程簡單、低成本及高品質等諸多優點，故 確實具有產業上的利用性、新穎性與進步性，並且符合發 明專利之要件，爰依法具文提出申請。 〔圖式簡單說明〕 (一）圖式部份： 第一圖A〜F ·係本發明第一較佳實施例的流程圖。（代 表圖） 第一圖A〜C ·係本發明第二較佳實施例的流程圖。 第二圖A〜C ·係本發明第三較佳實施例的流程圖。 第四圖A〜C ·係本發明第四較佳實施例的流程圖。 第五圖A〜C:係本發明第五較佳實施例的流程圖。 569301 A7 _B7_ 五、發明說明) (6 1 )第二基板 （7 0)第三基板 (8 0)光學元件 (請先閱讀背面之注意事項再填寫本頁) ••裝 -線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (7) A body of 70 thin-layers (103), wherein the pixel electrode (12) is formed on the alignment layer (104). The above are the description of various possible embodiments for manufacturing semiconductor devices, and the following are further examples to illustrate another implementation of semiconductor devices: The following description of each embodiment is different from the previous embodiments, which is the opposite of part of the manufacturing process. The day element electrode is covered on the substrate in advance, and then the thin film transistor is manufactured. For a possible implementation method, please refer to FIGS. 8 to 8C. The first substrate (10) is also covered with a sacrificial layer in advance. (101), and then cover with an etching / grinding protective layer (102), and the pixel electrode (i2) is then covered on the etching / grinding protective layer (102), and then cover with a semiconductor element protective layer (1 〇3) On this, a thin-film electric body is made on the semiconductor element protective layer (i 〇3). After the thin-film transistor is completed, the production of the optical element (1 5) and subsequent hydrogen explosion are performed. And etching process. Also, please refer to the ninth figure, and the difference between this embodiment and the eighth figure is that the use of an etching / grinding protective layer (not shown in the figure) is omitted; Compared with the embodiment of the eighth figure, the etching / grinding protection layer (102) is replaced by an alignment layer (i 〇4), or directly formed on the etching / grinding protection layer (102), as in the eleventh embodiment. As shown. As can be seen from the description of the above embodiments, the features of the present invention are: 1. The semiconductor element and the optical element are integrated on the same substrate. 2 · For panels with good optical and electrical characteristics, the reprinting process only requires one reversal action. That is, the semiconductor element and the optical element are integrated on a suitable substrate, and the first substrate can be reused without causing cost waste. ________ 11 The national standard (CNS) A4 specification (210 X 297 male f) of this paper standard weekly (Please read the precautions on the back before filling this page) I. • Line · 569301 V. Description of the invention (丨 ο) 3 · In the process of forming a semiconductor element, the pixel electrode adopts an internal connection form, and the pixel electrode is as close to the first substrate as possible, so that after the reprinting is completed, the structure of the semiconductor element (as described in the previous embodiments) ) Can be exposed directly, or after the hydrogen explosion protective layer or / and semiconductor element protective layer is patterned, it can be exposed. Especially the pixel electrode can be exposed without the need to be patterned, so that it can be used later with liquid crystal, organic When a light emitting material such as a light emitting diode layer (0LED) or a polymer light emitting diode layer (Polymer_LED) has a flattening effect, the display quality is further improved. It can be known from the above that the present invention utilizes a double-sided processing method of a substrate, so that a semiconductor element can be integrated with an optical element on the same substrate. In addition, in order to grow a component with better optical and electrical characteristics, a hydrogen explosion transfer process is also used, and only one transfer is required. In this way, it is possible to complete the production of a panel of high-quality display, and at the same time, the substrate for the growth of light and electrical components can be reused. Compared with the conventional hydrogen explosion process, the present invention does have many simple processes, low cost, and high quality. Advantages, so it does have industrial applicability, novelty, and progress, and meets the requirements of invention patents, apply according to law and documents. [Brief Description of the Drawings] (1) Drawings: The first drawings A to F are flowcharts of the first preferred embodiment of the present invention. (Representative drawings) The first drawings A to C are flowcharts of the second preferred embodiment of the present invention. The second figures A to C are flowcharts of the third preferred embodiment of the present invention. The fourth figures A to C are flowcharts of the fourth preferred embodiment of the present invention. Fifth Figures A to C are flowcharts of the fifth preferred embodiment of the present invention. 569301 A7 _B7_ V. Description of the invention) (6 1) Second substrate (7 0) Third substrate (80) Optical components (Please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) A4 (210 X 297 mm)