TW536812B - Dynamic random access memory and manufacturing method thereof - Google Patents

Abstract

A dynamic random access memory (DRAM) and manufacturing method are provided for manufacturing a capacitor structure in DRAM by utilizing a metal-insulator-metal (MIM) procedure. After forming a node contact, the method is characterized in manufacturing a bit-line contact followed by manufacturing a capacitor and its top electrode plate. Not only the height of the DRAM can be descended, but also the etched depth of the bit-line contact is reduced. Further, the top electrode plate is self-aligned, that means the top electrode plate is the same wide as the capacitor, thus the capacitor's capacitance could be gained more. The invention is prevented from the disadvantages of that is needed to ensure the height of embedded DRAM to have enough capacitor for storing charge, of that it is difficult to etch high aspect ratio (HAR) openings and to fulfill the metal materials into them during manufacturing the bit-line contact, and of that the sizes of the top electrode plate and the bit-line contact are limited because the reticles for defining the both above are overlapped so easily during the exposure procedure.

Description

536812 A7 B7 Excellent [L γ% / Burning Dagger No. 5 · Description of the invention (Field of the invention: The present invention relates to a structure of a Dynamic Random Access Memory (Dynamic Random Access Memory; Embedded DRAM) and a method for manufacturing the same, In particular, it is related to the use of a metal-insulator-metal (MIM) method to fabricate a capacitor structure of a dynamic random access memory, but its application is not limited to this field. BACKGROUND OF THE INVENTION: Complementary metal-oxide-semiconductor (Complementary Metal-Oxide Semiconductor; CMOS) technology continues to shrink in size, whether in industrial or consumer fields, provides the opportunity of System-On-A-Chip (SOC), that is, can be integrated more Multifunctional on the same chip. Recently, the area of the Central Processing Unit (CPU) has been shrinking. The remaining space on a chip will be filled with memory and peripheral circuits. In the past few years, internal DRAM It has become a very important field. The characteristics of this intrinsic technology is to combine logic circuits and DRAM on the same integrated circuit. The performance of the two is still maintained. In many cases, the internal DRAM can be composed of two independent chips (logic chip plus DRAM chip), or replaced by a multi-chip module (MCM). However, this must be determined by the choice of cost and function. However, the unique advantages created by intrinsic DRAM have great potential. These advantages include high frequency, more flexible structure, low energy consumption, small size, etc. This paper size is applicable to Chinese homes; ^ quasi (CNS) A4 size (210χ 297 public attack) Γ L ---.--- 1 pack ......... 'Order ..... .... line < Please read the precautions on the back before filling this page) 536812 1X h) Five invention descriptions ((Please read the precautions on the back before filling this page) Because logic circuits and dram have their own processes Its requirements and characteristics are a great challenge to integrate these two processes. Recently, efforts in process development have focused on how to integrate logic circuits and dram processes, such as common components, capacitor electrode plates and component lines. To reduce the number of masks and save costs. Recently, one _ Insulating layer-metal (MIM) method for making DRAM capacitors has received great attention in the development of internal DRAM. Because this method of capacitor production can reduce the manufacturing process and is similar to the latter stage of logic circuits, this This greatly increases the acceptance of internal DRAM. Please refer to FIG. 1, which is a cross-sectional structure diagram of an internal-type ram using a conventional technique. First, a substrate 10 is provided, and the material is silicon. The substrate 10 has a logic region 1 and a DRAM region 2, and a plurality of Shallow Trench Isolation (STI) structures 1 have been provided in the substrate 10. A plurality of lightly doped anodes ( Light Doped Drain) 15 and a plurality of Source / Drain17. A plurality of gate oxide layers 12 and a plurality of gate polycrystalline silicon layers 13 are sequentially arranged on the substrate 10, and a part of the shallow trench isolation structure 1 is exposed. The electrodes 15 and the surface of the source / induction electrode 17 are provided with a spacer 16 on both sides of the gate oxide layer 12 and the gate polycrystalline silicon layer 13. Then, a Resistor Protective Oxide Layer (RP0 Layer) 18 is formed on the gate polycrystalline silicon layer 13, the spacer wall 16, and the exposed shallow trench isolation structure u, the lightly doped drain electrode 15, and the source. On the surface of / Waiji 17, the photoresist protective oxide layer 18 can protect the DRAM area 2 during the subsequent fabrication of logic elements in the logic area 1. After that, cover the DRAM area 2 with a thick photoresist layer (not shown), and use the wet paper standard to apply China National Standard (CNS) A4 specification (210X 297 public attack) 536812

Five :, · Description of the invention ((Please read the precautions on the j side first, and then use this page)) to remove the photoresist protective oxide layer 18 in the logic region 1 and align it in the logic region 1 by itself The process of metal-silicide (Self-Aligned Silicide; Salicide) forms a metal silicide layer 20 on the gate polysilicon layer 13 and the source / drain I ?, and the material of the metal silicide layer 20 is, for example, Shi Xihua ( Cobalt Silicide; CoSix). Next, the thick photoresist layer on the DRAM area 2 is removed, and an etch stop layer 21 is formed conformally on the logic area 1 and the DRAM area 2 and then covered with the oxide layer 22 and the etch stop layer 23 in the logic. Area 1 and DRAM area 2. Then, the point contact of the DRAM capacitor is made by defining a plurality of openings 24 to expose a part of the lightly doped drain electrode 15, where the opening 24 is, for example, the point of a capacitor. Node Contact. After that, a barrier layer (not shown) is deposited in the point contact window, wherein the material of the barrier layer is, for example, titanium / titanium nitride, and chemical vapor deposition (Chemical Vapor Deposition) is used. Vapor Deposition; CVD) and Chemical Mechanical Poli (shing; CMP) flattening, and a tungsten plug (Tungsten Plug; W Plug) 25 is filled in the opening 24 to form a partial structure as shown in FIG. 1. In the first figure, the tungsten plug 25 is used as The capacitor is in point contact. Then, the process of metal-insulating layer-metal capacitor is performed, and the oxide layer 26 is first covered on the logic region 1 and the DRAM region 2, and then the oxide layer 26 is defined, and a part of the etching stop layer 23 is exposed. And a tungsten plug 25 to form a storage node contact (not shown) in the DRAM area 2. Then, a barrier layer 27 and a dielectric layer are sequentially conformally deposited in the contact window of the healthy point. Electrical layer 28 and barrier layer 29, and chemical vapor deposition method and chemical machine paper size apply Chinese National Standard (CNS) A4 specification (210 x 297 public love) 536812 A7 B7

Correction I 濡 J V. Description of the invention (Mechanical grinding and flattening, filling tungsten contact plug 30 into the storage point contact window to form

Please read the notes on the back of Γ before filling in this page Metal-Insulation-Metal Capacitor Structure, where the barrier layer 2 7 is used as the bottom electrode plate (Bottom Electrode Plate). After that, the process of the upper electrode plate is performed. The process of lithography and etching is used to define the 鸰 plug 30, the barrier layer 29, and the dielectric layer 28, and a tungsten plug 30 and a barrier layer 29 are formed. Top electrode plate 31, wherein the width of the top electrode plate 31 is larger than the width of the capacitor, and a part of the structure shown in FIG. 1 is formed. Next, the process of bit line contact is to cover the oxide layer 32 on the logic region 1 and the DRAM region 2 and use the lithography and etching process to define a plurality of openings 33 to expose a part of the logic region 1 The metal silicide layer 20 and a portion of the lightly doped drain 15 in the DRAM region 2, wherein the opening 33 is, for example, a bit line contact window. Then, a barrier layer (not shown) is deposited in the opening 33. The material of the barrier layer is, for example, titanium / nitride, and a tungsten plug 34 is formed by chemical vapor deposition and chemical mechanical polishing. A part of the structure shown in FIG. 1 is formed in the opening 33. In the first figure, the crane plugs 3 and 4 are connected as bit lines. After that, the silicon carbide (Silicon Carbide; SiC) layer 35 and the dielectric layer 36 are sequentially covered on the oxide layer 32 and the crane plug 34, and the material of the dielectric layer 36 is a low-dielectric constant dielectric. Next, the process of the single metal damascene structure of logic region 1 and dram region 2 is to first define a dielectric layer 36 and a silicon carbide layer 35 to form an opening 49 and expose the tungsten plugs of logic region 1 and dRAM region 2 34, wherein the opening 49 is a metal wire opening. Then, a barrier layer 50 is deposited in the opening 49, in which the material of the barrier layer 50 is, for example, a nitrogen paper standard applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536812 A7 B7 5. Description of the invention

Please read the “Notes on Back Φ” before writing the page group and fill in the opening 49 and cover the barrier layer 50 by the chemical vapor deposition method, where the metal layer 51 is a metal wire. After that, the metal layer 51 and the barrier layer 50 are planarized by chemical mechanical polishing to form a structure as shown in FIG. As shown in the cross-sectional structure diagram of the internal DRAM of the conventional technology, after the point contact of the capacitor is formed, the capacitor of the DRAM area 2 and its upper electrode plate 31 are first made, and then the bit line contact window (ie, the opening 33) is made. The process. However, when the line width of the process is gradually shortened with the increase of the component accumulation degree, the capacitance of the DRAM area is limited by the structure, and it cannot provide sufficient capacitance. First, within a limited unit element area, a considerable height is required to ensure sufficient capacitance to store charge. This extra height makes subsequent bit line contact windows more difficult to etch. If you want to increase the surface area by increasing the height of the capacitor to obtain more capacitance in the dram region, the opening of the metal wire as the bit line contact window is bound to be deeper. It is equivalent to filling metal into the bit line contact window. South challenge. Secondly, the capacitor in the conventional dram area still has an upper electrode plate 31 ′. When defining the upper electrode plate 31 and the bit line contact window, the exposed masks of the two are likely to overlap, which makes the upper electrode plate 3 The size of the 1 and bit line contact windows is limited. Object and summary of the invention: In view of the above-mentioned background of the invention, not only does the capacitor in the dram region need to have a considerable height to ensure sufficient capacitance to store the charge, but the additional height will affect the etching of the bit line contact window. It also raises the challenge of filling metal into the bit line contact windows. Secondly, the capacitance of the dram area is suitable for the Chinese standard (CNS) A4 (210 X 297 mm).

536812 A7 -----— B7 V. Description of the invention () There is still an upper electrode plate, which defines the areas where the exposed masks of the upper electrode plate and the bit line contact window easily overlap when the upper electrode plate and the bit line contact window are defined. As a result, The size of the upper electrode plate and the bit 70 line contact window are limited. Therefore, one of the main objects of the present invention is to provide a method for manufacturing a dynamic random access memory, which is characterized in that after the point contact of the capacitor is formed, the bit line contact of the capacitor is first made, and then the capacitor and the upper electrode plate are manufactured. It can reduce the height of the dynamic random access memory, and also reduce the etch depth of the bit line contact window. Therefore, the present invention avoids the disadvantage that the conventional technique requires a considerable height to ensure that there is sufficient capacitance to store the charge. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory, which is further characterized by controlling the thickness of the first oxide layer, thereby reducing the depth of the engraving of the bit line contact window. Therefore, the present invention avoids the difficulty in etching the high aspect ratio (High 邛 ⑽ Ratio) HAR opening and filling the metal into the high aspect ratio opening when the bit line contact window is manufactured by the conventional technology. Another object of the present invention is to provide a structure of a dynamic random access memory, which is characterized in that the upper electrode plate of the capacitor used is self-aligned, that is, the width of the upper electrode plate and the capacitor, etc. Therefore, more capacitance can be obtained. The present invention avoids that conventionally, when the upper electrode plate and the bit line are in contact with the window, the photomasks exposed by both are prone to overlap, and the size of both is restricted.

I

[According to the above-mentioned purpose, the present invention provides a method for dynamically and randomly storing f. Memory fetching, at least including: firstly providing a substrate, wherein the substrate has at least a first etch stop layer and is exposed. Plural points of contact; r This paper size is applicable to the CNS A4 specification (2 ^ 297 ^^ ............, -¾ ........ It ......... $ < Please read the notes on the back before writing this page) 536812

V :, · Description of the invention ((Please read the precautions on the back before filling in the text.) Then, the-oxide layer is formed on the _ etch stop layer and the point contact is made; then the bit line contact process is performed; , Sequentially covering the first dielectric layer and the third #etched stop layer of the carbide fossil layer on the second oxide layer and the second tungsten plug; and then, the metal is treated by the mysterious genus 疋 · insulation layer- The manufacturing process of metal capacitors is to form a plurality of capacitors in the first dielectric culvert, a few kilograms ~ θ ^) 丨 the electrical layer, the silicon layer and the first oxide layer, where the electrode plate above the capacitor is self-aligned According to the above, the width of the upper electrode plate and the capacitor, etc .; and the first layer of metal wires are made using a single metal damascene technique to form the first layer of metal wires on the bit line contacts. For the stated purpose, the present invention further provides a structure of a dynamic random access memory, including at least a base material, wherein at least a first etch stop layer is provided on the base material, and a plurality of point contacts are exposed; An oxide layer is set to terminate at the first moment The layer is in contact with these points; a plurality of bit line contacts; the silicon carbide layer and the first dielectric layer are sequentially disposed on the first oxide layer and the bit line contact; a plurality of metal · insulating layers-metal type capacitors It is located in the first dielectric layer, the silicon carbide layer and the first oxide layer, wherein the electrode plate above the capacitor is self-aligning type, that is, the width of the upper electrode plate and the capacitor is equal; In the first dielectric layer and the carbide layer. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figure 1 is a drawing Shows the cross-section and spider composition of the internal DRAM using the conventional technology; and this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) 536812 A7 B7 5: 'Explanation of invention (-P (Please read the precautions on the back before filling in this page} Figures 2 to 19b are cross-sectional views of an internal DRAM process in accordance with a preferred embodiment of the present invention, of which Figure 13a is The top views of Figures 13b and 13c are shown, and the Figure 14a shows the 14b and 14 Top view of Figure c, Figure 15a shows top views of Figures 15b and 15c, Figure 16a shows top views of Figures 16b and 16c, and Figure 17a shows Figure 17b and The top views of Figures 17c and 17d and the edge of Figure 19a show the top view of Figure 19b. The comparison of French horns: 1 Logic area 2 DRAM area 10 Substrate 11 Shallow trench isolation junction 12 Gate oxidation Layer 13 Gate polycrystalline layer 14 Hard cover curtain layer 15 Lightly doped drain 16 Spacer 17 Source / inverted 18 Photoresistive protective oxide layer 19 Photoresistive layer 20 Metal silicide layer 21 Termination stop layer 22 Oxide layer 23 End stop layer 24 Opening 25 Tungsten plug 26 Oxide layer 27 Barrier layer 28 Dielectric layer 29 Barrier layer 30 Tungsten plug 31 Upper electrode plate 32 Oxide layer 33 Opening 34 Bright plug 35 Carbide layer 36 Electric layer 37 Money engraved termination layer 10 This paper size is applicable to China. Furniture standard (CNS) A4 (210 X 297 public attack), 3., 536812 A7 B7 ^ \\ (ψ V. Description of the invention (

(Please read the precautions on the back before writing this page} 38 Barrier layer 40 Photoresist layer 42 Trench 44 Barrier layer 46 Upper electrode plate 48 Photoresist layer 50 Barrier layer t Predetermined thickness e Area Η Detailed description of the invention : The present invention discloses a method for manufacturing a dynamic random access memory, which uses a metal 'insulating layer-metal method to make a capacitive structure of an internal dynamic random access memory, which is characterized by forming a point contact of a capacitor, First make the cable connection of the electric valley _ 'and then make the capacitor and the upper electrode plate. In order to make the description of the present invention more detailed and complete, you can refer to the following description and cooperate with Figures 2 to 19b, which are shown in green according to the present invention. A preferred embodiment is a cross-sectional view of an internal carbon-type dram process, wherein FIG. 13a, FIG. 14 & FIG. 15a, FIG. 16a, FIG. 17a, and FIG. Top view of the preferred embodiment of the internal DRAM process. The present invention is suitable for the manufacture of internal dynamic random access memory, but is not limited to this. It can also be applied to the manufacture of other types of dynamic random access memory. . please According to Fig. 2 ', the base material 10 is provided first, and its material is Shi Xi. 1 base 11 This paper size is applicable to the Chinese country. Home_Jun (3 ~ 3) 6 4 specifications (210X297 public meeting) 536812 5 :, · Description of the invention (A7 B7

If you read it first. The meaning of the memorandum and then fill in this page. The material 10 has defined the logic area 1 and the DRAM area 2 and has a plurality of shallow trench isolation structures 11 in the base material 10. Then, a plurality of gate oxide layers 12, a plurality of gate polycrystalline silicon layers 13 and a plurality of hard mask layers 14 are sequentially arranged on the substrate 10 in sequence, and a part of the shallow trench isolation structure is exposed. 11. The structure shown in FIG. 2, wherein the material of the hard cover curtain layer 14 is, for example, Silicon Oxynitride (SiOxNy). Next, the hard mask layer 14 'is removed, and a plurality of lightly doped drain electrodes 15 are formed in the substrate 10 by an ion implantation (ion implantation) method, as shown in FIG. 3. Then, a spacer 16 is formed on both sides of the gate oxide layer 12 and the gate polycrystalline silicon layer 13, and a source / drain 17 is formed in the substrate 10 by an ion implantation method, as shown in FIG. 4. The structure. Thereafter, conformally covering the photoresist protective oxide layer 1 8 on the gate polycrystalline silicon layer 1 3, the spacer 16 and the exposed shallow trench isolation structure 1 1, the lightly doped drain 15 and the source / drain 17 On the surface, a structure as shown in FIG. 5 is formed, so that when a subsequent logic element is manufactured in the logic region 1, the photoresist protection oxide layer 18 can protect the DRAM region · 2. Subsequently, the DRAM area 2 is covered with a thick photoresist layer 19, and the photoresist protection oxide layer 18 of the logic area 1 is removed by a wet etching method, and in the logic area 1, by a process of self-aligning the metal oxide compound, A metal oxide layer 20 is formed on the gate polycrystalline silicon layer 13 and the source / drain electrode 7 as shown in FIG. 6, and the material of the metal silicide layer 20 is, for example, cobalt silicide (CoSix). Next, remove the thick photoresist layer 19 on the DRAM area 2 and conformally cover the etch stop layer 2 1 on the spacer 16 of the logic area 1, the metal silicide layer 20, and the exposed lightly doped drain electrode 15 And exposed shallow trench isolation structure n, 12 This paper size is applicable to China; ^ Standard (CNS) A4 size (210 X 297 mm > 536812

V. Description of the invention (

I! F P and the photoresist protective oxide layer 18 of the DRAM region 2, wherein the material of the etch stop layer 21 is, for example, silicon oxynitride. Then, for example, a chemical vapor deposition (Chemical Vapor Deposition; CVD) method is used to form an oxide layer 22 on the etch stop layer 21, wherein the material of the oxide layer 22 is, for example, Inter Poly Oxide (IPO) or Boro-Phospho-Silicate Glass (BPSG), as shown in Figure 7. Afterwards, the dry etching method is used to carry out the last name engraving of the oxide layer 22 and control the oxide layer 22 remaining on the gate polycrystalline stone layer 13 of the DRAM region 2 to a predetermined thickness t, wherein the predetermined thickness t is between about Between 100,000 and ± 400 people. Subsequently, an etch stop layer 23 is formed on the oxide layer 22, and the material of the etch stop layer 23 is, for example, silicon oxynitride or silicon nitride (SiN1Nitride; SiNx). Next, the point contact production of the DRAM capacitor is defined by defining the etch stop layer 23, the oxide layer 22, the etch stop layer 21, and the photoresist protection oxide layer 18 to form a plurality of openings 24, and expose a portion of the light. The doped drain 15 is formed, wherein the opening 24 serves as a point contact window, for example. Afterwards, a barrier layer (not shown) is deposited conformally in the opening 24. The material of the barrier layer is, for example, titanium / titanium nitride, and is planarized by chemical vapor deposition and chemical mechanical polishing. The tungsten plug 25 covers the barrier layer and fills the opening 24, thereby forming a partial structure as shown in FIG. The tungsten plug 25 in Fig. 8 serves as a point contact of the capacitor 'and is connected to the lightly doped electrode 15 of the part of the DRAM region 2. Then, the process of bit line contact is performed, and the oxide layer 26 is first covered on the logic area 1 and the DRAM area 2. The lithography and etching processes are used to define the logic 13. The paper size is applicable to the China National Standard (CNS) A4 specifications (210X 297 public love) ............ Γ ---, (Please read the precautions on the back before writing this page) Order. Line ^ 36812

', · Description of the invention (Edition region 1 ㉟26, money etch stop layer 23, oxide layer 22, narration stop layer 21 and metal dream ㈣2G, and define the oxygen ❹% of DRAM area 2 and the etch stop layer 23 , Oxide layer 22, hafnium termination layer 21 and photoresist: follow the oxide layer 18 to form a plurality of openings 33 and expose a portion of the metal dream layer 20 in the logic region i and a light doping in the region _ The electrode 33 is, for example, a bit line contact window. Then, a barrier layer (not shown) is conformally deposited in the opening 33, and the material of the barrier layer is, for example, titanium / nitride. Titanium is planarized by chemical vapor deposition and chemical mechanical polishing. The tungsten plug 34 is covered on the barrier layer and filled in the opening 33 to form a partial structure as shown in FIG. 9. The tungsten plug 34 in FIG. 9 serves as a bit line contact, and is connected to the lightly doped drain 15 of the other part of the DRAM region 2 and the metal silicide layer 20 of the logic region 丨. Cover silicon carbide layer 3, dielectric layer 3, and etch stop layer 37 on oxide layer 26 and tungsten plug 34 in sequence. The material of dielectric layer 36 is low dielectric. Dielectrics (L0wk Dielectrics) to form a structure not shown in Figure j. Next, the metal_insulation layer_metal capacitor is made. This capacitor is, for example, a capacitor type dynamic random access under the bit line. Metal (Capacitor Under Bit Line-DRAM; CUB-DRAM)

I SF P f Please read the back side > ± Matters first, then the rim of the edge-metal capacitor, which defines the etch stop layer 37, the dielectric layer 30, the silicon carbide layer 35 and the oxide layer in the DRAM area 2. 26 to form a storage point contact window 39 and expose a part of the etch stop layer 23 and the tungsten plug 25. Then, a barrier layer 38 is conformally formed in the storage point contact window 39, as shown in the structure shown in FIG. 11, wherein the material of the barrier layer 38 is titanium nitride (Titanium 14) (CNS) A4 Regulations (210X297 Public Love) 536812

Five :, · Description of invention (

Nitride; TiN) or nitrided group (Tantalum Nitride; TaN)

Please read the note of memorandum before reading: 装 I is better. Subsequently, the photoresist layer 40 is used to fill the storage point contact window 39, and the photoresist layer 40 and the barrier layer 38 in the storage point contact window 39 are recessed to a predetermined depth d by dry etching. The predetermined depth d is about 1000 A, as shown in FIG. 12, wherein the barrier layer 38 is used as the lower electrode plate. After ordering, please refer to FIG. 13a, which shows a top view of an internal DRAM process after removing the photoresist layer 40 and the etch stop layer 37 according to a preferred embodiment of the present invention. In the DRAM area 2, For the dielectric layer 36, the storage point contact window 39, and the barrier layer 38, the process cross-sectional view of the section line AA is the i3b figure, and the process cross-section view of the section line BB is the 13c figure. Next, please refer to FIG. 13b, which is a cross-sectional view taken along the section line A-A, in which the barrier layer 38 has been recessed to a predetermined depth. Then, please refer to FIG. 1 c, which is a cross-sectional view taken along the section line B-B, in which the barrier layer 38 has also been recessed to a predetermined depth. The line connector 'please refer to Figure 14a' shows a preferred embodiment of the present invention to cover the logic area 1 and DRAM area 2 with a Twist Line type photoresist pattern after the lithography process. Top view of the internal carbon DRAM process, where the twisted photoresist pattern is used to form the pattern of the upper electrode plate, and the area u is the unexposed area, and the area e is the exposed and surnamed engraved twist and line. In the area of the trench, the cross-sectional view of the process of section line AA is FIG. 14b, and the cross-sectional view of the process of section line BB is FIG. 14c. Then, please refer to FIG. 14b, which is a cross-sectional view taken along the section line A-A, in which the twist-type groove 42 is defined in the photoresist layer 41 that forms the twist-type pattern. After that, 15 paper sizes are applicable to China National Standard (CNS) A4 specification (210X 297 mm) 536812 A7 B7 / < / V. Description of the invention (please refer to Figure 14C) The cross-sectional view of line bB, in which the dielectric layer 36 forming the trench 42 in the region e · has been removed, and the barrier layer 38 in the region 6 has been etched to approximately the same height as the silicon carbide layer 35. According to the present invention, In another preferred embodiment, the silicon carbide layer 35 and the oxide layer 26 in the area e can also be removed, so as to increase the area of the capacitor in the subsequent process. The process of this another preferred embodiment is described in detail in the following section.丨 7d. Then, please refer to FIG. 15a, which shows a top view of the internal DRAM process after removing the photoresist layer 41 in a preferred embodiment of the present invention, where the area e is a twisted line In the trench area, the process cross-section view of section line a_a is Figure 15b, and the process cross-section view of section line BB is Figure 15c. After that, please refer to Figure 15b, which shows the section obtained along section line a_a. Figure, after the photoresist layer 41 is removed, the storage point is exposed to the contact point 39. Furthermore, 'please refer to section 1 5c The system edge shows the cross-sectional view along the section line b-b. After the photoresist layer 41 is removed, the storage point contact window 39 is also exposed. * After that, please refer to FIG. 16 a. A preferred embodiment is a top view of an internal DRAM process after the copper layer 45 is formed, wherein the process cross-sectional view of the section line AA is FIG. 16b, and the process cross-sectional view of the section line BB is FIG. 16c. Next, Please refer to Figure 16b, which is a cross-sectional view taken along AA. A dielectric layer 43 and a barrier layer 44 are sequentially conformally formed on the barrier layer 38 of the storage point contact window 39, and then covered with a steel layer. 45 on the barrier layer 44 and filled in the storage point contact window 39, wherein the material of the dielectric layer 43 is a high dielectric constant dielectric, and the high dielectric constant dielectric is, for example, 16 .Home; ^ quasi (CNS) A4 specification (210X297 public love) ---- install: (Please read the precautions on the back before writing this page) 丨 order · line 536812 V. · description of the invention ()

Five-emulsion two buttons (Ta205), and the material of the barrier layer 44 is, for example, nitride nitride. Furthermore, please refer to FIG. 16e, and show the cross-sectional view taken along the section line BB. After the photoresist layer 41 is removed, the dielectric layer 43 | a and the barrier layer 44 are sequentially conformally formed at the storage point contact window. The copper layer is covered on the barrier layer 44 and fills the storage point contact window 39. Subsequently, please refer to Section 17a_, which is a preferred embodiment of the invention, which is planarized by chemical mechanical polishing. In the top view of the internal carbon DRAM process, the copper layer 45 is transformed by chemical mechanical polishing and planarization. It is a twisted copper layer 45a, the cross-sectional view of the process of section line AA is FIG. 17b, and the cross-sectional view of the process of section line BB is FIG. 170. Next, please refer to FIG. 17b, which is a cross-sectional view taken along the cross-section line AA. The copper layer 45 is transformed into a copper layer 45a after being planarized by chemical mechanical polishing, so that the entire internal-type ram is transformed to a height of Η twice. . At the same time, part of the barrier layer 44 and part of the copper layer 45a form the upper electrode plate 46 perpendicularly, wherein the upper electrode plate 46 is self-aligned, that is, the upper electrode plate 46 and the storage point contact window 39 are as wide as The copper layer 45a constitutes a twisted upper electrode plate 46. Then, please refer to FIG. I7c, which is a cross-sectional view taken along the section line BB. The copper layer 45 is converted into a copper layer 45a after chemical mechanical polishing, so that the overall height of the internal DRAM is changed to a height Η ', where the height Η 'is approximately equal to height Η. After that, please refer to FIG. 17d, which is a cross-sectional view taken along section line BB according to another preferred embodiment of the present invention. The silicon carbide layer 35 and the oxide layer 26 are removed to expose a part. The etch stop layer 23. Subsequently, a dielectric layer 43 and a barrier layer 44 are formed conformally in order. The barrier layer 38 and the etch stop layer 17 are formed on this paper. The paper size is applicable to China National Standard (CNS) A4 (210 X 297).

536812 V. Explanation of the invention ()

23, and the steel layer 45 is covered on the barrier ^ φ $ Λ and filled in the contact point 39 of the storage point. After chemical mechanical research / Yunshan 4 ^ ^, the steel layer 45 is transformed into a steel layer 45a, the overall height of the internal dRam becomes two degrees Η ', in which the high-pitched Η is approximately equal to the height ，, and forms a structure such as the history of FIG. 17d, and the capacitance of i7d in FIG. The surface area of the structure is larger than that of the eighth high school.帛 ... The surface of the capacitor structure is followed by the formation of an etch stop layer in sequence • w 47 and photoresist layer 48 on the dielectric layer 36, the dielectric layer 43, the barrier layer 44 and the steel s—install red w by 45a The photoresist layer 48 is used as a mask, the etching stop layer 47, the dielectric layer 36, and the silicon carbide layer 35 are formed, thereby forming a plurality of openings 49, and exposing the ballast plug 34, as shown in FIG. The structure not shown in the figure. M ^ < opening 49 in Fig. 18 is used for subsequent single metal damascene process. After τ ', please refer to FIG. 19a, which is a top view of an internal DRAM process after a barrier layer 50 and a metal layer s ^ 30 are sequentially added to a preferred embodiment of the present invention. Among them, the steel layer 45a serving as the thunder plate on the capacitor is twisted, and the cross-sectional view of the process line AA is shown in FIG. 19b. Next, please refer to FIG. 19b; it is a cross-sectional view taken along the section line a Λ. First, a barrier layer 50 is conformally formed at the opening 49 Φ ^ τ 'wherein the material of the barrier layer 50 is, for example, nitride. group. Then, the metal layer was deposited by the pseudo-G pre-rolled phase deposition method.

51 is filled in the opening 49 and covers the barrier layer L5050, wherein the metal layer 51 is a metal wire. After that, the planarization metal layer 51 and the barrier layer 50 are polished by a chemical machine and ammonium oxide to form a sister structure as shown in FIG. 19b. The manufacturer of dynamic random access / memory body provided by the present invention 18 This paper size is applicable to China. Furniture Standard (CNS) A4 (210X297 mm) Α7

= The touch is to form a point contact of the capacitor, first make a bit line contact (Phe plug 34), and then make a thunder & (ie, metal dwelling. The electrode plate 46 and the metal wire ^ ^), by controlling the oxidation The thickness of the layer 22 is to reduce the height of the dynamic memory. Please compare Figure 1. The conventional technology is to make the electric valley first and then to make the bit line contact. Therefore, it is necessary to form an oxide layer to deodorize. In order to: The production of metal wires not only increases dynamic random access memory = back The degree 'increases the difficulty of etching high aspect ratio openings and filling metal into high aspect ratio: mouth. On the contrary, please refer to the 帛 m diagram. In the present invention, first, the bit, ·, and the electrode are made, and then the valley, the upper electrode plate 46, and the metal wire are produced, and the thickness of the oxide layer 22 is controlled. Under the conditions, metal wires can be made, of course, the height of the dynamic random access memory is reduced. The method for manufacturing a dynamic random access memory provided by the present invention is further characterized in that the upper electrode plate 46 of the capacitor used has a twisted line pattern instead of a full surface type, and the upper electrode plate of the present invention 粍It has the same height as the capacitor structure, metal layer 51 and dielectric layer 36, as shown in the structure shown in FIG. 19b. Compared to the conventional electrode plate 31, not only does it protrude from the capacitor structure, but the metal layer 51 is higher than the upper electrode plate 31, as described above! The structure shown in the figure.

IP According to the structure of the dynamic random access memory provided by the present invention, another feature is that the upper electrode plate 46 of the capacitor used is self-aligning, that is, the width of the upper electrode plate 46 and the capacitor is equal, and part The barrier layer 44 and a portion of the copper layer 45a form the upper electrode plate 46 perpendicularly. The structure shown in FIG. I9b 'When defining the upper electrode plate 46 and the opening of the metal wire (ie, the opening 49), 19 paper sizes Applicable to China National Standard (CNS) A4 specification (21 × 297 reputation) 536812 A7 B7

XT V. Description of the invention () The exposed masks of the two are not likely to produce overlapping areas, so more capacitance can be obtained. Please read it first. Note on the back · Items and then write this page So 'One of the advantages of the present invention is to provide a method for manufacturing a dynamic random access memory, which is characterized by the formation of a point contact of a capacitor, and the capacitor is first made. The element line contact 're-produces the capacitor and the upper electrode plate, so that the dynamic random access can be reduced to two degrees, and at the same time, the depth of the bit line contact window is reduced. The present invention therefore avoids the disadvantages of conventional techniques that require considerable height to ensure sufficient capacitance to store charge. Another advantage of the present invention is to provide a method for manufacturing a dynamic random access memory, which is further characterized by controlling the thickness of the first oxide layer, thereby reducing the engraving depth of the bit line contact window. Therefore, the present invention avoids the difficulty of the conventional technique when making the bit line contact ® to make a high aspect ratio opening and fill a metal with a high aspect ratio opening. Another advantage of the present invention is to provide a structure of a dynamic random access memory, which is characterized in that the upper electrode plate of the capacitor used is self-aligned, that is, the width of the upper electrode plate and the capacitor, so that more can be obtained. Capacitor. The present invention avoids that when the upper electrode plate and the bit line contact window are defined by the conventional technique, the exposed masks of the two are likely to produce overlapping areas, so that the sizes of both are limited. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention. Equivalent changes or modifications made under the spirit disclosed by the invention should be included in the scope of patent application described below. This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

536812 B3 C3 D8 6. Scope of patent application1. A manufacturing method of dynamic random access memory (DRAM). It includes at least: providing a substrate, wherein the substrate has at least a DRAM area defined, And a first etch stop layer has been set on the substrate, and a plurality of first tungsten plugs are exposed; a first oxide layer is formed on the first etch stop layer and the first tungsten plugs; a plurality of A plurality of second tungsten plugs contacted by a Huayuan line; sequentially covering a Silicon Carbide (SiC) layer, a first dielectric layer and a second etch stop layer on the first oxide layer and the Forming a plurality of capacitors in the first dielectric layer, the silicon carbide layer, and the first oxide layer of the DRAM region, wherein the capacitors are a metal-insulating layer-metal type Capacitors, and the capacitors have a self-aligned upper electrode plate; and a plurality of first layer metal wires are formed on the second tungsten plugs. Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 2 · The method for manufacturing a dynamic random access memory as described in item 1 of the scope of patent application, wherein the material of the first etch stop layer is selected from silicon oxynitride And silicon nitride (Silicon Nitride; SiNx). B8 C3 D8 536812 6. Jiaqing Patent Scope 3. The manufacturing method of dynamic random access memory described in item 1 of the patent application scope, wherein the first oxide layer and the second etch stop layer are sequentially formed. Before the first etch stop layer, the method further includes: providing the substrate, wherein at least a logic region has been defined in the base phase 1 and at least a plurality of shallow trench isolation structures and a plurality of light regions have been provided in the substrate. Doped drains and multiple sources / dimers, and multiple gates with multiple gaps have been formed on the logic region and the dram region, and some of the shallow trench isolation structures and parts are exposed. Part of the lightly doped drains and part of the sources / drains; conformally covered with a Resistor Protective Oxide (RPO) layer on the gates, the spacers, and the storm The shallow trench isolation structures fogged out, the lightly doped drain electrodes exposed, and the source / drain electrodes exposed; a thick photoresist layer is covered on the DRAM area, and the logic area is removed from the Photoresist protects oxide layer; forms multiple metal silicides Layered on the gates and source / drain electrodes of the logic area; removing the thick photoresist layer; and printing a conformal covering of an etch stop layer on the logic area by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The spacers, the metal silicide layers, the exposed lightly doped drain electrodes and the exposed shallow trench isolation structures are conformally covered with the photoresist protective oxide layer in the DRAM area. An oxide layer and the first etch stop layer are sequentially formed at the etch stop 536812 '.I:' u The scope of the patent application is on the printed layer of the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the oxide layer has a predetermined thickness; and a plurality of point contacts (Node contact) First tungsten plugs (Tungsten Plug; W Plug) 'wherein the first crane plugs are connected to the lightly doped' drain electrodes of a part of the DRAM area. ≪ 4. The manufacturing method of the dynamic random access memory as described in item 3 of the patent application park ', wherein the gates are sequentially stacked by another oxide layer and a polycrystalline silicon layer. 5. The method for manufacturing dynamic random access memory as described in item 3 of the scope of the application, wherein the material of the metal silicide layers is Cobalt Silicon (CoSix). The method for manufacturing a dynamic random access memory according to item 3, wherein the material of the etch stop layer is silicon nitride oxide (Silk Nitride; SiOxNy). 7. The method for manufacturing a dynamic random access memory as described in item 3 of the scope of the patent application, wherein the step of forming the metal silicide layers uses a self-aligned metal silicide (Self-Aligned Silicide; Salicide) Method to proceed. 8. The dynamic random access memory described in item 3 of the scope of patent application 536812 B8 C8 D8 The method of manufacturing scope of patent application, wherein the predetermined thickness is between about 1000A ± 400A. 9. The method for manufacturing a dynamic random access memory as described in item 3 of the scope of the patent application, wherein the material of the oxide layer is selected from the group consisting of internal polycrystalline silicon oxide (Inter Poly Oxide; IP0) and boron phosphorus A group of silica glass (B〇ΓΟ-Phospho-Silicate • Henry Glass; BPSG). 10. The manufacturing method of the dynamic random access memory described in item 3 of the patent application scope, wherein the steps of forming the point contacts include at least: defining the first etch stop layer, the oxide layer of the DRAy region 2. The remaining stop layer and the photoresist protective oxide layer to form a plurality of first openings and expose a part of the lightly doped drain electrodes; and filling the first tungsten plugs in the first In an opening. 11. The method for manufacturing a dynamic random access memory as described in item 10 of the scope of the patent application, wherein before forming the first tungsten plugs, it further comprises forming a first τ «barrier layer conformally on the first An opening, and the material of the first barrier layer is titanium / titanium nitride. Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs12. The manufacturing method of dynamic random access memory as described in item 1 of the scope of patent application, wherein the steps of forming the bit line contacts include at least: defining the first An oxide layer, the first etch stop layer and the substrate to form a plurality of second openings and expose a portion of the substrate; and B8, C3, and D8 patent claims cover the second tungsten plugs in Those second openings are late for March / (// $ 多 -it Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Cooperative Printed Body \ 3 · The manufacturing method of dynamic random access memory 2 as described in item 12 of the scope of patent application, wherein before filling the second tungsten plugs, it further includes: Spread formation—a second barrier layer is in the f two openings, and the material of the second barrier layer is titanium / nitride. Titanium. 14. The dynamic random access record as described in item 1 of the scope of the patent application: manufacturing method, " The first dielectric layer is made of a low dielectric constant; low-k dielectrics. a 15. The method for manufacturing a dynamic random access memory according to item 丨 of the patent application scope, wherein the steps of forming the capacitors include at least: defining the second etch stop layer, the first dielectric layer, the A silicon carbide layer and the first oxide layer to form a multiple contact point window, and a portion of the first remaining stop layer and the first tungsten plugs are exposed; a third barrier is formed conformally Layer in the storage point contact windows; dry etching back the third barrier layer in the storage point contact windows to a predetermined depth; covering a photoresist pattern on the first dielectric layer and the first Three barrier layers are filled in the storage point contact windows, and the photoresist pattern has an exposed area; the first dielectric layer in the exposed area is removed; the photoresist pattern is removed; 25 (Please read the back first Please note! F Fill in this book again. · Order · Line II i J Application The storage sequentially conformally forms a second dielectric layer and a fourth barrier layer on the third barrier layer in the point contact window; ^ covers a copper layer on the fourth barrier layer and fills it In the contact windows of these storage points; and "" chemical mechanical polishing and planarization 'to form the upper electrode plate, please read it first, and read "16. The winter dynamics as described in item 15 of the scope of patent application are random In the method for accessing a memory port, in the step of removing the first dielectric layer of the exposed area, the silicon carbide layer and the first oxide layer of the exposed area can be further removed. Item 15 · The method for manufacturing a dynamic random access memory, wherein the material of the third barrier layer is composed of a nitride button (Tantalum Nitride; TaN) and a nitride nitride (Titanium Nitride; TiN) One group. Note · Intentions; Item |: I pack 3 order 1 8 · Method for manufacturing dynamic random access memory as described in item 15 of the scope of patent application, wherein the predetermined depth is about 1 000 A Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 19. The method for manufacturing a dynamic random access memory as described in claim 15 of the patent scope, wherein the material of the second dielectric layer is a high-dielectric constant dielectric. Dynamic random access memory 2 1. The method for manufacturing a dynamic random access memory according to item 15 of the scope of patent application, wherein the material of the fourth barrier layer is tantalum nitride (TaN). 22. The method for making a winter dynamic random access memory as described in item 15 of the scope of the patent application, wherein the upper electrode plate is composed of a portion of the fourth barrier layer and a portion of the copper layer in sequence. I first I read and read the two & notes and then fill in% on this page 23. The manufacturing method of the dynamic random access memory described in the first item of the scope of patent application, wherein the first layer of metal wires is formed The steps at least include: forming a third etch stop layer on the first dielectric layer and the capacitors to define the third etch stop layer and the third dielectric layer and a plurality of third openings! The second tungsten plugs are exposed; the first metal layers are filled in the third openings so as to form the seal of the Intellectual Property Bureau of the Ministry of Economic Affairs, the Bayer Consumer Cooperative, 24. As described in item 23 of the scope of patent application A method for manufacturing a dynamic random access memory, wherein before the first metal layers are filled, a fourth barrier layer is conformally formed in the third openings, and the fourth resistor The material of the barrier layer is tantalum nitride. 27 536812 B8 C8 D8 j Mi / ri Γίν 6. Application scope of patent 25. A method for manufacturing dynamic random access memory, including at least providing a substrate, wherein at least a first etch stop is provided on the substrate Layer, and a plurality of point contacts are exposed; forming a first oxide layer on the seventh etching stop layer and the point contacts; forming a plurality of bit line contacts; sequentially covering a silicon carbide layer, a first A dielectric layer and a second etch stop layer are in contact with the first oxide layer and the bit lines; so as to form a plurality of guests in the first dielectric layer, the silicon carbide layer and the first oxide In the layer, the capacitors formed therein are a metal-capacitive layer-metal capacitor, and the capacitors have a self-aligning upper electrode plate. 26. The method for manufacturing a dynamic random access memory according to item 25 of the scope of patent application, wherein before the first oxide layer and the second etch stop layer are sequentially formed on the points, the method further includes at least Provide the substrate, wherein the substrate has at least one logic region and the DRAM region defined, and the substrate has at least a plurality of shallow trench isolation structures, a plurality of lightly doped drains, and a plurality of sources / A drain electrode, and a plurality of gates having a plurality of spacers have been formed on the substrate; a photoresist protective oxide layer is conformally covered on the substrate; the photoresist protective oxide layer of the logic region is removed; forming A plurality of metal silicide layers on the gates of the logic area; 28 536812 6. The patent application area conformally covers an etch stop layer on the logic area and the DRAM; an oxide layer and the first An etch stop layer is on the button stop layer, and the oxide layer has a predetermined thickness; and a plurality of point contacts are formed, wherein the point contacts are connected to the lightly doped portions of the portion of the dram pole. 27. However, the method for manufacturing the dynamic random access memory described in item 26 of the patent application scope, wherein the predetermined thickness is between about 100 厶 ± 400 Å. Printed by the Employees' Cooperative of the Intellectual Property Bureau, Ministry of Economic Affairs A group consisting of phosphosilicate glass. % 9. The method of dynamic random access memory as described in item 26 of the patent application: manufacturing method, wherein the steps of forming the point contacts include at least defining the H-th stop layer, the oxide layer, and the # 刻In the end, the photoresist is protected. The W L wb layer forms a plurality of first openings to expose the lightly doped drain electrodes; and the first = Γ: the first tungsten plug in In the first openings, the first and second openings are the point contacts. Silicon Department ib 29 536812 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, B8 C3 D8 VI. Patent application scope 30. The method of manufacturing dynamic random access memory described in item 29 of the patent application scope \ Before forming the first tungsten plugs, a first barrier layer is conformally formed in the first openings, and the material of the barrier layer is titanium / titanium nitride. 3 1. The method of manufacturing a dynamic random access memory according to item 25 of the patent application, wherein the step of forming the bit line contacts includes at least: defining the first oxide layer, the first etching termination Layer and the substrate to form a plurality of second openings, and expose a portion of the substrate; and fill a plurality of second tungsten plugs in the second openings, wherein the second tungsten plugs The plug is the bit line contact. 32. The method for manufacturing a dynamic random access memory as described in item 31 of the scope of patent application, wherein before filling the second tungsten plugs, it further comprises forming a second barrier layer conformally on the second tungsten plug. In the second openings, the material of the second barrier layer is titanium / titanium nitride. 33. The manufacturer 1 of the dynamic random access memory described in item 25 of the scope of patent application, wherein the material of the first dielectric layer is a low-dielectric constant dielectric. 34. The method for manufacturing a dynamic random access memory as described in item 25 of the scope of patent application, wherein the steps of forming the capacitors include at least: 536812 The Intellectual Property Bureau of the Ministry of Economic Affairs, Bei X Consumer Cooperative printed the scope of the patent application. The second name is engraved with the termination layer, the second dielectric layer, the silicon carbide layer and the oxide layer. The storage point contacts the window, and the second #etch stop layer is exposed to contact the bit lines; a third barrier layer is formed in the storage point contact windows; the storage point contact windows are etched, The third barrier layer covers a predetermined photoresist pattern on the first dielectric layer and the third barrier layer, and the acoustic storage point contact window, and the photoresist pattern has an exposure area; The first dielectric layer in the exposed area; the photoresist pattern is removed; a second dielectric layer and a fourth barrier layer are sequentially conformally formed on the third barrier layer in the contact windows; A copper layer is covered on the fourth barrier layer and filled with the storage point contacts and the upper electrode plate. 35. The method for manufacturing a dynamic random access memory according to item 34 of the scope of the patent application, wherein in the step of removing the first dielectric layer of the exposed area, the silicon carbide layer and the exposed area can be removed. The first oxide layer. 36. The method for manufacturing a dynamic random access memory according to item 34 of the scope of the patent application, wherein the material of the third barrier layer is a group consisting of a nitride button and a titanium nitride. 31 The total depth of Yiding and the first part; Overfilling should go to the storage window according to the storage point; Shape 536812 B8 C8 D8 Six applications for patent park 37. If you apply, please refer to item 34 of the patent scope. The method of manufacturing a body, wherein the predetermined depth is about 1000A. The manufacturing method of the random memory described in the sub-pending memory 38 · ^ application patent 34f, wherein the hidden dielectric of the second dielectric layer is homogeneous dielectric. Dijie 39 · The manufacturing method of the dynamic random access body as described in item 38 of the scope of patent application, the high dielectric constant dielectric material is pentoxide: installed · {Please read «I first, pay attention to the back If If: Refill this page J * 1 Printed by the Ministry of Intellectual Property Bureau of Japan ’s Shellfish Consumer Cooperative 40. The method for manufacturing a dynamic random access memory as described in Item 34 of the scope of patent application for printing, where the fourth resistance The material of the barrier layer is tantalum nitride. ° 4 1 · The method for manufacturing a dynamic random access memory as described in claim 34, wherein the step of forming the upper electrode plate further includes performing a chemical mechanical polishing and planarization to form the upper electrode plate. . 42. The method for manufacturing a dynamic random access memory as described in item 34 of the scope of the patent application, wherein the upper electrode plate is sequentially composed of a part of the fourth barrier layer and a part of the copper layer.馑 Advance resistance 43 · Order the dynamic random access recorder as described in item 25 of the scope of patent application% 32 536812 B3 C8 D8 6. Manufacturing method of the scope of patent application, which includes the formation of the capacitor after the process A plurality of first-layer metal wires, and the steps of forming the first-layer metal wires at least include: forming a third etch stop layer on the first dielectric layer and the capacitor upper layers to define the third etch. Stop layer The first dielectric layer and the silicon carbide form a plurality of third openings, and the bit line contacts are exposed; the plurality of first metal layers are filled in the third openings. Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 44. A structure of dynamic random access memory 'at least includes: a substrate, wherein at least a first dielectric layer has been provided in the substrate to contact a plurality of points; And the first dielectric layer exposes the point contacts; a first oxide layer, a silicon carbide layer, and a second dielectric layer are sequentially disposed on the substrate; and a plurality of capacitors are disposed on the second The dielectric layer, the silicon carbide layer and the first oxide layer are located on the point contacts, wherein the capacitors are composed of a self-aligned upper electrode plate, a third dielectric layer, and a lower electrode. And the upper electrode plate has a twisted pattern and is the same height as the capacitors. 45. The structure of the dynamic random access memory according to item 44 of the scope of the patent application, wherein the substrate further includes at least: a logic region and a DRAM region are defined in the substrate, and at least It has a plurality of shallow trench isolation structures, a plurality of doped & poles and complexes B8 536812 6. A number of source / non-poles in the scope of patent application; a second oxide layer and a first etch stop layer are sequentially arranged on the substrate "Wherein the second oxide layer and the first etch stop layer constitute the first dielectric layer, and the second oxide layer has a predetermined thickness, wherein the second oxide layer has at least a plurality of gates in the second oxide layer. Extremely noisy on the logic region and the DRAM region of the substrate 'wherein the gates have a plurality of gaps on both sides of the gates; and a plurality of metal silicide layers are disposed on the gates of the logic region And the lightly doped anodes connected to the point of contact with the DRAM area 0.46. The structure of the dynamic random access memory as described in item 45 of the patent application scope, wherein the The material of the second oxide layer is selected from the group consisting of internal polycrystalline silicon oxide and One group consisting of phosphorus silicon glass. Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs 47. The structure of the dynamic random access memory described in item 44 of the scope of patent application, which further includes a plurality of first-layer metal wires provided on the second dielectric layer And a plurality of bit line contacts are connected to the silicon carbide layer and below the first metal wires, wherein the bit line contacts are provided on the first oxide layer, the first dielectric layer and the base Material. 48. Dynamic random access memory as described in item 47 of the scope of patent application 536812 B3 C8 D8 6. The scope of the patent application body structure, wherein the bit line contacts are a plurality of second tungsten plugs. 49. The structure of the dynamic random access memory according to item 44 of the scope of the patent application, wherein the predetermined thickness is between about 1000A ± 400A. 50. The structure of the dynamic random access memory according to item 44 of the patent application, wherein the point contacts are a plurality of first tungsten plugs. 5 1 · The structure of the dynamic random access memory according to item 44 of the scope of the patent application, wherein the material of the second dielectric layer is a low-dielectric constant dielectric. Please read the back of the note first and fill in the% book 3