經濟部智慧財產局員工消費合作社印製 521551 A7 ________B7_ 五、發明説明（） 本發明係與電子產業有關，特別是關於一種用以在印 刷電路板（PCB)之電路佈局上電鍍導接層之方法。 在習知的印刷電路板80的製造流程中，請參閱第一 圖，首先先預製一基板(substrate) 81，其上具有一電路佈局 5 (conductor pattern) 82以及複數個電鍍通孔（PTH)822。該電 路佈局82係由複數個銅導線821所構成。該基板81上具 有一匯電導線(bus trace) 83，藉以導接各該銅導線821。在 完成預定程序後，可在該匯電導線83通電，藉以在各該銅 導線821之預定位置電鍍導接層84(即業界習稱之金手指 10 (g〇lden finger))。完成電鍍導接層84之程序後，該匯電導 線Μ會被移除，該印刷電路板8〇即形成如第二圖所示之 型態。 由圖中可很清楚地瞭解，該基板81在二銅導線Mb 821b之間必須保留預定之空間821 ,讓其他鋼導線之無效 15段821c，821d，821f通過。所謂的無效段為使該等銅導線 821與該匯電導線83導接之區段，藉以電鍍該等導接層 84。但在該電路佈局82運作時，該等無效段是沒有兩、、六I 過的。換言之，該基板81上具有許多無效區域，而 無效區域是不能避免的。因此，該基板81無法有嗲、/茨等 20 本發明之主要發明目的在於提供一種用以在^的 板之電路佈局上電鍍導接層之方法，其 17刷電路 «導線即可完成電鍍導接層。 要"置前述的 為達成前接之發明目的，本發明所提供之〜 ㈣電路板之電路佈局上電鍍導接層之方法，：：以在印 I含有下列步 _3_ 本紙張尺度適用中ΪΪ家標準(--— (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521551 A7 ________B7_ V. Description of the Invention () This invention is related to the electronics industry, especially a method for plating a conductive layer on the circuit layout of a printed circuit board (PCB) . In the conventional manufacturing process of the printed circuit board 80, please refer to the first figure. First, a substrate 81 is prefabricated, which has a conductor pattern 82 and a plurality of plated through holes (PTH). 822. The circuit layout 82 is composed of a plurality of copper wires 821. The substrate 81 is provided with a bus trace 83 for conducting the copper wires 821. After the predetermined procedure is completed, the power-conducting wire 83 may be energized, so that the conductive layer 84 is plated at a predetermined position of each of the copper wires 821 (namely, a gold finger 10 in the industry). After the process of electroplating the conductive layer 84 is completed, the conductive wire M will be removed, and the printed circuit board 80 will be formed as shown in the second figure. It can be clearly understood from the figure that the substrate 81 must reserve a predetermined space 821 between the two copper wires Mb 821b, so that the invalidity of other steel wires 15 sections 821c, 821d, 821f pass. The so-called ineffective section is a section where the copper wires 821 and the bus wire 83 are connected, and the conductive layers 84 are plated. However, when the circuit layout 82 is operating, there are no two, six, or six invalid sections. In other words, the substrate 81 has many invalid regions, and the invalid regions cannot be avoided. Therefore, the substrate 81 cannot have a substrate, a substrate, or the like. The main object of the present invention is to provide a method for plating a conductive layer on the circuit layout of a board. The method can be completed by brushing the circuit with 17 wires.接 层。 Then layers. In order to achieve the aforementioned purpose of the invention, the present invention provides a method for electroplating a conductive layer on a circuit layout of a circuit board: so that the following steps are included in the stamp: Family Standards (--- (Please read the notes on the back before filling out this page)
521551 A7 B7 五、發明説明（） 驟： (請先閲讀背面之注意事項再填寫本頁) A. 預製一基板，其上具有一電路佈局，其中該電路佈 局具有導接部以及電鍍部。 B. 在該基板上設置一防焊層，以覆蓋該電路佈局，且 5 將該防焊層的預定部位打開，令該電路佈局之導接部以及 電鍍部暴露。 C. 在該防焊層上設置一導電層，令該導電層經由該等 導接部與該電路佈局電性導接。 D. 在該導電層上設置第二防焊層，並將該第二防焊層 10 之預定部位打開，藉以令該電路佈局之電鍍部暴露。 E. 通電力至該導電層，藉以在該電路佈局之電鍍部電 鍍導接層。 F. 移除該第二防焊層，以及 G. 移除該導電層。 15 以下茲舉一較佳實施例，配合圖示，對本發明作進一步 之說明，其中 第三圖係本發明一較佳實施例之製造流程示意圖； 第四圖係本發明較佳實施例之成品外觀圖； 經濟部智慧財產局員工消費合作社印製 第五圖為另一種以本發明之方法所製造出之成品外觀 20 圖，以及 第六圖為第三種以本發明所提供之方法所製造出之成 品外觀圖。 請參閱第三圖所示，本發明一較佳實施例所提供之一種 用以在印刷電路板之電路佈局上電鍍導接層之方法，包含 -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 521551 A7 B7 五、發明説明（ 15 經濟部智慧財產局員工消費合作社印製 20 有下列步驟： A.預製一基板10,其上具有一電路佈局2〇: 請參閱圖3 A，該基板10係由多功能環氧樹(multi-function ep0Xy resin)所製成，其上設置有兩 q 电鑽通孔 ll(PTH)，且該電路佈局2〇設置於基板1〇之二侧。該電路佈局20具有導接部22以及電鍍部24 ^ 電鍍部24係為後續步驟電鍍導接層於該電路佈局Ν預定位置，而各該導接部22可經由該電路怖局2〇遍〈之電鍍部24電性導通。 一 /、疋 Β·在該基板1〇上設置一防焊層30，以霜坌、、 復现舔電路佈 局20 ’且將該防焊層30的預定部位打開，令兮兩 2〇之導接部22以及電鍍部24暴露： " 請參閱圖3 Β1至圖3 Β4，本步驟具有四個予步驟八 述如下： 77 Β1 ·設置二背膠金屬络於該基板10之二侧.本較佳實施例中’該背膠金屬落為背膠鋼荡 Coated Copper foil，RCC foil)，其具有一輪 ％ 硐泊40以及一樹 脂層30，其中該樹脂層30之材料與該基板1〇相同，為夕 功能環氧樹脂。 j該二背膠銅、預定烘烤溫度與時間貼附於 該基板10之二側’其間該樹脂層30會融化並填滿該電鍵 通孔1卜當該樹脂層30固化後，該二背膠铜络會固=== 基板10上，且該樹脂層30即形成前述之防坪展 ^ Β2·移除該銅箔4〇對應於該電路佈届、曰$ J <導接部 -5- 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇><297公釐） (請先閱讀背面之注意事項再填寫本頁j -訂 22 521551 A7 B7 五、發明説明（ 5 15 經濟部智慧財產局員工消費合作社印製 20 以及電錢部24之部分·· 本步驟係主要利用光影之技術達成^首先，塗佈一 光阻層（未顯示)㈣二鋼上，之後設置光罩並以f 光顯影，驗祕刻掉料_定之部分， 在 應於該電路佈局2〇之導接部22以及電 = 露，接著崎湖40暴露之部分 =暴 光阻。在蚀刻該光阻時所使用之藥劑為余:餘广 比重為i讓，溫度為心〜机。關該鋼2 〇3) ’ 為三氯化鐵(Fecl3)，濃度為4〇〜4伽， 吏用《樂劑 亦可使用氣化铜（CuCl、、曲 又為4〇C〜50°C， ^ ( 2)，⑻35〜45心〜_ 當完成前段所述之程序後，該防焊層3 路佈局2〇之導接部22以及電鍵部24部分^I於該電 如圖3 B2所示之型態。 |路’而形成 B3.移除祕焊層3G暴露之部分，藉以 20之導接部22以及電鍍部24被暴露： μ电路佈局 電漿触刻的技術配應用於本步驟，藉以 3〇暴露之部分，令該電路佈局20之導接部22掉賴焊層 24被暴露。 以及電鍵部 Β4·移除殘餘的銅箔40 : 最後餘刻掉雌的_4G，該印刷電路板 3 B4所示之型態。 即形成 C·在該防焊層30上設置_導電層5〇，人 經由該等導接部24與該電路佈局2〇之電C層 22電 圖 50 性導 (請先聞讀背面之注意事項再填寫本頁} ( CNS ) Μ規T( _6- 經濟部智慧財產局員工消費合作社印製 521551 A7 B7 五、發明說明（） 接。 首先利用化學沉積的方法在該防焊層30上設置一厚度 大約為0.05um〜0.5um之化學銅層（electroless copper)，接著 再於該化學銅層電鍍一厚度大約為lum〜3um之電鍍銅層 5 (electrolytic copper)，以形成前述之導電層50。該電鍍銅所 使用之藥劑為硫酸銅（CuS04)，電流密度為10〜100 Amp/dm2，電鍍時間大約為1〜10 min。 此時，該導電層50會與該電路佈局20之導接部22以 及電鍍部24電性連接，而形成圖3 C所示之型態。 10 我們發現鹼性化學銅溶液會侵蝕習用的防焊綠漆，但本 發明所使用之環氧樹脂防焊層之抗鹼性十分優秀。這也就 是我們選用環氧樹脂為該防焊層30之主要材料之原因。 D·在該導電層50上設置第二防焊層60，並將該第二 防焊層60之預定部位打開，藉以令該電路佈局20之電鍍 15 部24暴露。 本步驟與步驟B類似，請參閱圖3 D1與圖3 D2，包含 有二個子步驟： D1.設置一光阻層於該導電層50上，並對該光阻層進 行曝光、顯影等步騾，以移除該光阻層之不需要部分，令 20 該導電層50在對應於該電路佈局20之電鍍部24的部分暴 露，而該光阻層即形成前述之第二防焊層60。 D2.對該導電層50進行微蝕刻（quick etch)，以移除該 導電層50暴露之部分，使該電路佈局20之電鍍部24暴 露。微蚀刻的藥劑為硫酸與雙氧水之混合溶液。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂·--------線邊 A7521551 A7 B7 V. Description of the invention () Step: (Please read the precautions on the back before filling out this page) A. Prefabricate a substrate with a circuit layout on it, where the circuit layout has a lead section and a plating section. B. A solder mask is provided on the substrate to cover the circuit layout, and 5 a predetermined portion of the solder mask is opened to expose the lead portion and the plating portion of the circuit layout. C. A conductive layer is provided on the solder mask layer, so that the conductive layer is electrically connected to the circuit layout through the conductive portions. D. A second solder mask layer is provided on the conductive layer, and a predetermined portion of the second solder mask layer 10 is opened to expose the plating portion of the circuit layout. E. Apply power to the conductive layer, thereby electroplating the conductive layer in the plating section of the circuit layout. F. remove the second solder mask, and G. remove the conductive layer. 15 The following is a more detailed description of the present invention with a preferred embodiment. The third diagram is a schematic diagram of the manufacturing process of a preferred embodiment of the present invention; the fourth diagram is a finished product of the preferred embodiment of the present invention. Appearance drawing; the fifth drawing printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is another appearance drawing 20 of the finished product produced by the method of the present invention, and the sixth drawing is the third made by the method provided by the present invention The appearance of the finished product. Please refer to the third figure, a method for electroplating a conductive layer on a circuit layout of a printed circuit board provided by a preferred embodiment of the present invention includes: -4- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 521551 A7 B7 V. Invention description (15 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 Printed in 20 steps as follows: A. Prefabricate a substrate 10 with a circuit layout 20: Please refer to the figure 3 A, the substrate 10 is made of multi-function epoxy resin (multi-function ep0Xy resin), two q electric drill through holes 11 (PTH) are provided on the substrate, and the circuit layout 20 is disposed on the substrate 10. The second side. The circuit layout 20 has a lead portion 22 and a plated portion 24. The plated portion 24 is a plated conductive layer at a predetermined position in the circuit layout N for subsequent steps, and each of the lead portions 22 can pass through the circuit. The electroplating portion 24 is electrically connected 20 times. First, 疋 Β · A solder resist layer 30 is provided on the substrate 10, and the circuit layout 20 is reproduced with frost, and the solder resist layer 30 is reproduced. The predetermined portion is opened, so that the two lead portions 22 and the plated portion 24 are exposed. " Please refer to FIG. 3B1 to FIG.3B4. This step has four pre-steps and eight steps are described as follows: 77 Β1. Set two adhesives on the two sides of the substrate 10. In the preferred embodiment, the adhesive The metal is a Coated Copper foil (RCC foil), which has a round of anchorage 40 and a resin layer 30. The resin layer 30 is made of the same material as the substrate 10 and is a functional epoxy resin. j The two-sided adhesive copper, the predetermined baking temperature and time are attached to the two sides of the substrate 10 ', during which the resin layer 30 will melt and fill the key through-hole 1 When the resin layer 30 is cured, the two backs The plastic-copper network will be solidified === on the substrate 10, and the resin layer 30 will form the aforementioned apron ^ Β2 · Remove the copper foil 40 corresponding to the circuit cloth, said $ J < 5- This paper size applies to Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm) (Please read the precautions on the back before filling out this page j-order 22 521551 A7 B7 V. Description of the invention (5 15 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, and printed by the Consumer Cooperatives 20 and 24 of the Electricity Money Department. This step is mainly achieved by the use of light and shadow technology. ^ First, apply a photoresist layer (not shown) to Ergang, and then set up. The photomask is developed with f light, and the material is cut out. The lead part 22 and the electrical part exposed to the circuit layout 20 should be exposed, and then the exposed part of the lake 40 is exposed to photoresistance. The photoresist is etched. The medicine used at the time of resistance is Yu: Yu Guang's specific gravity is i let, the temperature is heart ~ machine. Off the steel 2 03) 'is trichloride Iron (Fecl3), with a concentration of 40 ～ 4 gallium, can also be used with gaseous copper (CuCl, Koji, 40 ° C ~ 50 ° C, ^ (2), ⑻35 ~ 45 heart ~ _ When the procedure described in the previous paragraph is completed, the solder resist layer 3 layout 20 of the lead portion 22 and the key portion 24 ^ I in the form shown in Figure 3 B2. | Road to form B3. Remove the exposed part of the 3G solder layer, and expose the lead 22 and the electroplated part 24 by 20: μ circuit layout technology of plasma etching is applied to this step, and the circuit layout is based on 30% of the exposed part. The lead portion 22 of 20 is removed from the solder layer 24 and the key portion B4 · Residual copper foil 40 is removed: Finally, the female _4G is etched away, and the type shown in the printed circuit board 3 B4 is formed. C · Set the _ conductive layer 50 on the solder resist layer 30, and the person through the lead 24 and the circuit layout 20 C layer 22 electrical diagram 50 (Please read the precautions on the back before reading Fill out this page} (CNS) M Regulation T (_6- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521551 A7 B7 V. Description of the Invention () First, the chemical deposition method is used at An electroless copper layer having a thickness of about 0.05um to 0.5um is provided on the solder resist layer 30, and then an electroplating copper layer 5 (electrolytic copper) having a thickness of about lum to 3um is plated on the chemical copper layer. The aforementioned conductive layer 50 is formed. The agent used for the copper plating is copper sulfate (CuS04), the current density is 10 to 100 Amp / dm2, and the plating time is about 1 to 10 minutes. At this time, the conductive layer 50 is electrically connected to the conductive portion 22 and the electroplated portion 24 of the circuit layout 20 to form the shape shown in FIG. 3C. 10 We found that the alkaline chemical copper solution will attack the conventional solder resist green paint, but the epoxy solder resist used in the present invention has excellent alkali resistance. This is why we chose epoxy resin as the main material of the solder resist layer 30. D. A second solder resist layer 60 is provided on the conductive layer 50, and a predetermined portion of the second solder resist layer 60 is opened to expose the plating 15 portion 24 of the circuit layout 20. This step is similar to step B. Please refer to FIG. 3 D1 and FIG. 3 D2. It includes two sub-steps: D1. A photoresist layer is disposed on the conductive layer 50, and the photoresist layer is exposed and developed. In order to remove unnecessary portions of the photoresist layer, the conductive layer 50 is exposed at a portion corresponding to the plating portion 24 of the circuit layout 20, and the photoresist layer forms the aforementioned second solder resist layer 60. D2. Perform a quick etch on the conductive layer 50 to remove the exposed portion of the conductive layer 50 and expose the plated portion 24 of the circuit layout 20. The micro-etching agent is a mixed solution of sulfuric acid and hydrogen peroxide. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) -Line edge A7
521551 五、發明說明（） 在完成步驟D後，該電路佈局2〇之電鍍部以被暴露， 且該導電層50經由該等導接部22與該等電鍍部％電性導 通。 E.通電力至Μ導電層50，藉以在該電路佈局2〇之電 5鍍部24上電鍍導接層70。該導接層70即為業界通稱之金 手指（golden finger)，為一鎳_金合金層。 在此要提出說明的是，在步驟D中，該第二防焊層6〇 被打開的孔徑會比該電路佈局2〇之電鍍部的面積大，藉此 可使步騾E之導接層70可被電鍍於該等電鍍部的全部面積 10 上。 F·蝕刻掉殘餘之該第二防焊層6〇。此處所使用之蝕刻 劑為氫氧化鋼（NaOH)，比重2〜5 wt%，溫度50°C〜8〇°C， 或者亦可使用氫氧化鉀(KOH)微蝕刻溶劑。 G·使用驗性蚀刻法（alkali etching treatment)，藉以移除 15殘餘之導電層50。在進行本步驟之同時，該電路佈局20 之導接部22之暴露之部分亦一同被移除。 在完成步驟G後，請參閱第四圖，該防焊層3〇尚在對 應於該電路佈局20之導接部22之位置會留有微孔34。該 等微孔34大多會位於電路佈局2〇之銅導線之末端，或位 20於電鍍穿孔ii(pth)或是焊墊(solderballpad)的旁邊。 由前接的製造方法可知，本方法可在無須在基板上設置 匯電銅導線的狀況下，在電路佈局之預定位置電鍍導接 層。如此，以本方法所製作的印刷電路板上，無須為該電 路佈局之無效段預留空間，換言之，以本方法所製作的印 -8- (請先閱讀背面之注意事項再填寫本頁) _裝--------訂---------線· 經濟部智慧財產局員工消費合作社印製521551 V. Description of the invention () After completing step D, the electroplated portion of the circuit layout 20 is exposed, and the conductive layer 50 is electrically connected to the electroplated portions via the conductive portions 22. E. Apply electricity to the M conductive layer 50, thereby electroplating the conductive layer 70 on the electroplated portion 24 of the circuit layout 20. The conductive layer 70 is a golden finger commonly known in the industry, and is a nickel-gold alloy layer. It should be mentioned here that, in step D, the aperture of the second solder resist 60 is opened to be larger than the area of the plating portion of the circuit layout 20, thereby enabling the conductive layer of step 骡 E. 70 can be plated on the entire area 10 of these plating sections. F. Etching away the second solder resist 60. The etchant used here is steel hydroxide (NaOH), with a specific gravity of 2 to 5 wt%, a temperature of 50 ° C to 80 ° C, or a potassium hydroxide (KOH) micro-etching solvent. G. Use an alkaline etching treatment to remove the remaining conductive layer 50. When this step is performed, the exposed portions of the lead portions 22 of the circuit layout 20 are also removed. After step G is completed, please refer to the fourth figure. The solder mask 30 still has micro-holes 34 at positions corresponding to the lead portions 22 of the circuit layout 20. Most of these micro-holes 34 will be located at the ends of the copper wires in the circuit layout 20, or 20 next to the plated through holes (pth) or solderball pads. It can be known from the manufacturing method of the front connection that the method can electroplat a conductive layer at a predetermined position in the circuit layout without the need to provide a copper wire on the substrate. In this way, the printed circuit board produced by this method does not need to reserve space for the invalid section of the circuit layout. In other words, the printed circuit board produced by this method is -8- (Please read the precautions on the back before filling this page) _Installation -------- Order --------- line · Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs
WfUit« t 規格咖 X 297 公iT 521551 A7 B7 五、發明說明（） 刷電路板，請比較第二圖與第四圖’可達成縮小尺寸工 效。 工为 第五圖係為另一種以本發明所提供之方法所製造 5 15 經濟部智慧財產局員工消費合作社印製 20 印刷電路板之外觀圖，其與前述之差異在於該電路体局= 具有複數個傳導部23，用以電性導通複數個電鍍部2/。= 此，在經由該傳導部23導通之銅導線上，僅需要有〜個， 二個導接部22，即可達成在該等·部24上電鍍導= 70之目的。 ’要層 此種態樣之主要實施步驟與第一較佳實施例相同，惟 (1) 在步騾A中，該等傳導部23即預先形成在該電 佈局20中。 ％ (2) 步驟B中該防焊層30在對應於該等傳導部23之部 分亦被移除。 (3) 在步騾D中，該光阻層在對應於該等傳導部之 部分亦被移除，使位於該等傳導部23與該等電鍍部Μ上 的導電層50 —並被移除。然後再設置另一光阻層，藉以覆 蓋該等傳導部23。 3 ' (4) 在步驟G中，該等傳導部23同時也被移除。 第六圖係顯示第三種經由本發明所提供之方法所製造 出之印刷電路板，其中該導接部23係位於該基板1〇上， 使該導電層（未顯示）可經由該電路佈局2〇的導接部23、電 鍍部24與傳導部23，與-火線(ρ〇· .)25減一地線 (ground Hne)26形成一迴路。該基板丨〇在製作完成後會沿 著圖中所示的虛線15切割，使該基板1〇上形成一凹穴 •9-本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公复） 521551 A7 __B7 _ 五、發明說明（） (cavity)，用以在其中裝設一晶片（die)(未顯示）。由圖中可 清楚得知，該導接部22係位於該基板10被切除的部分。 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 521551 A7 B7 五、發明說明（） 圖示之簡單說明： 第一圖係傳統在印刷電路板上設置匯電銅導線之示意 圖， 第二圖係第一圖中該匯電銅導線被移除後之示意圖； 5 第三圖係本發明一較佳實施例之製造流程示意圖； 第四圖係本發明較佳實施例之成品外觀圖； 第五圖為另一種以本發明之方法所製造出之成品外觀 圖，以及 第六圖為第三種以本發明所提供之方法所製造出之成 10 品外觀圖。 主要成分代表圖號： (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 10基板 11電鍍通孔 15切割線 20電路佈局 22導接邵 23傳導部 15 24電鍍部 25火線 26地線 30防焊層 34微孔 40銅箔 50導電層 60第二防焊層 70導接層 20 80習用印刷電路板 81基板 82電路佈局 821銅導線 822電鍍通孔 83匯電導線 84導接層 -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）WfUit «t size coffee X 297 male iT 521551 A7 B7 V. Description of the invention () Brush the circuit board, please compare the second picture and the fourth picture 'to achieve the effect of reducing the size. The fifth figure is another manufactured by the method provided by the present invention. 5 15 Printed on the printed circuit board of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 20 The printed circuit board is different from the previous one in that the circuit board = has The plurality of conducting portions 23 are used for electrically conducting the plurality of plating portions 2 /. = Therefore, on the copper wire that is conducted through the conducting portion 23, only ~ 2 and two conducting portions 22 are needed to achieve the purpose of electroplating conducting on the portion 24 = 70. The main implementation steps of this aspect are the same as those of the first preferred embodiment, but (1) In step 骡 A, the conductive portions 23 are formed in the electrical layout 20 in advance. % (2) In step B, the solder resist 30 is also removed in portions corresponding to the conductive portions 23. (3) In step 骡 D, the photoresist layer is also removed in the portions corresponding to the conductive portions, so that the conductive layers 50 on the conductive portions 23 and the plating portions M are removed. . Then, another photoresist layer is provided to cover the conductive portions 23. 3 '(4) In step G, the conductive portions 23 are also removed. The sixth diagram shows a third printed circuit board manufactured by the method provided by the present invention, wherein the conductive portion 23 is located on the substrate 10, so that the conductive layer (not shown) can pass through the circuit layout. The 20 conductive portion 23, the electroplated portion 24, and the conductive portion 23 form a loop with the ground wire (ρ0 ·.) 25 minus one ground line (ground Hne) 26. After the substrate is completed, it will be cut along the dotted line 15 shown in the figure, so that a recess is formed on the substrate 10. 9- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Re) 521551 A7 __B7 _ 5. The invention description () (cavity) is used to install a die (not shown) in it. As can be clearly seen from the figure, the connecting portion 22 is located at a portion where the substrate 10 is cut away. (Please read the precautions on the back before filling out this page.) -------- Order --------- line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is suitable for China Standard (CNS) A4 specification (210 X 297 mm) 521551 A7 B7 V. Description of the invention () Brief description of the diagram: The first picture is a schematic diagram of a conventional copper wire on a printed circuit board, and the second picture is The first diagram is the schematic diagram of the copper copper wire after removal; 5 The third diagram is a schematic diagram of the manufacturing process of a preferred embodiment of the present invention; the fourth diagram is the appearance of the finished product of the preferred embodiment of the present invention; the fifth The figure is another appearance of the finished product manufactured by the method of the present invention, and the sixth figure is the third appearance of 10 finished products manufactured by the method of the present invention. The main component represents the drawing number: (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, printed on 10 substrates, 11 plated through holes, 15 cutting lines, 20 circuit layouts, 22 lead connections, and 23 conductive parts. Plating section 25 hot wire 26 ground wire 30 solder resist layer 34 micro hole 40 copper foil 50 conductive layer 60 second solder resist layer 70 conductive layer 20 80 custom printed circuit board 81 substrate 82 circuit layout 821 copper wire 822 electroplated through hole 83 sink Electrical wire 84 guide layer-11- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)