TW502165B - System and method for effectively utilizing a cache memory in an electronic device - Google Patents

Abstract

A system and method for effectively utilizing a cache memory in an electronic device comprises a processor that operates in response to a software program to insert a marker in isochronous data that is stored in the cache memory. The marker may then be utilized to identify the isochronous data as special information that is protected from removal from the cache device without the occurrence of a predetermined rollout exception event.

Description

502165

V. Description of the invention (1) Background description 1. Field of the invention (please read the precautions on the back before filling out this page) The present invention is generally related to the technology of implementing memory devices, especially the effective use of cache in electronic devices System and method of memory. 2. Description of the Background Art An effective implementation method for performing various data transfer operations in electronic devices is an important consideration for designers and manufacturers of modern electronic devices. For example, an electronic device can communicate with other electronic devices and share data with an electronic interconnection system, thereby increasing the performance and use of individual devices in the electronic interconnection system. In some examples, an electronic interconnection system can be implemented in the host environment so that it can flexibly and advantageously share data and device resources between various consumer electronic devices, such as personal computers, Digital video disc (DVD) device, digital set_top boxes for digital broadcasting, large televisions, and audio reproduction systems. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Effectively managing data transmission in the interconnection system of electronic devices is a major challenge for the designers of electronic devices. For example, strong demands on device functionality and performance may require more system processing power and additional resources. An increase in computational processing or hardware conditions may result in a relatively cost-effective impact due to increased manufacturing costs and operational irregularities. The size of the interconnection system is also a factor that affects the operation of data transfer in an electronic device. China Unicom in an electronic interconnection system generally applies the Chinese National Standard (CNS) A4 specification (210 X 297 issued) with this paper size -4-502165 A7 ________ B7 V. Description of the invention (2) Individual device or The increase in the number of nodes becomes more complicated. Assuming that a particular device on an electronic interconnection system is defined as a local device with local software components, other devices on an electronic interconnection system are defined as remote devices with remote software components. Therefore, the local software module on the local device may need to transmit data to various software components on the remote device through the electronic interconnection system. However, the successful management of a number of electronic devices through an interconnected system can provide considerable benefits to system users. Furthermore, enhancing the performance of the device to perform various in-depth processing tasks can provide system users with additional benefits, but this will increase the demand for the control and management of various components in the electronic interconnection system. For example, an enhanced electronic interconnection system that can effectively acquire, process, and display digital television pictures can benefit from adequate interconnection communication technology, because it must use a large amount of complex digital data. As the demands on system processor resources continue to increase, and the amount of data continues to increase, it is clear that developing new and effective methods for data transfer operations is a very important matter for related electronic technologies. Therefore, based on the above reasons, an effective method of data transmission in electronic devices' is still an obvious demand for designers, manufacturers, and users of current electronic devices. SUMMARY OF THE INVENTION In accordance with the present invention, a system and method for effectively utilizing cache memory in an electronic device are disclosed herein. In an embodiment, the paper size is initially applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) {Please read the precautions on the back before filling this page) ——Order ------- ——Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -5- 502165 A7 B7 V. Invention Description (3) A processor is a program instruction that sequentially executes a device application software. In some states, the above-mentioned program instructions may include one or more synchronization load instructions, which may instruct the processor to load one or more time-related synchronization data from a memory to a specific cache device. Corresponds to the mapping position. According to some embodiments, the processor may be quite advantageous to instruct the cache device to generate a tag attached to a particular storage section to indicate that the information stored therein includes special information, such as synchronized data. In some embodiments, the tag prevents the cache device from removing synced data before the scheduled volume exception event does not occur. For example, in one embodiment, if a target position in a cache device includes a section, which includes initial synchronization data marked by a tag, and if other synchronization load instructions When the source memory is transferred to the same target location in the cache device and a conflict occurs, the processor may preferably roll off the initial synchronization data so that subsequent synchronization data obtained from the source memory can be marked and the load Into a specific section of the cache device. In addition, the device application software can also instruct the processor to roll out a selectable marked section in the cache device in response to the state change in the main electronic device. For example, if a synchronization process is interrupted, the corresponding synchronization data no longer needs to exist in the cache device, and the application software of the device can quite advantageously issue a volume removal command to enable the cache The device has optimized performance. Similarly, when a specific synchronization process is completed, you can provide the paper size applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) (please read the note on the back first? Matters before filling out this page ) n · n ^ aJ · MM am · I Μ · ΜΗ I stupid _ · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • 0-502165

V. Description of the invention (4) {Please read the notes on the back before filling this page) A volume of exceptions, in which the device application software will issue a volume of removal commands to make one of the cache devices correspond to the marked area Duan Kong stayed. For example, in the case where the segment includes 64-bit synchronization data, when the final or 64-bit synchronization data can be obtained and used from the marked segment, the device application software can have considerable advantages To be notified. Accordingly, the device application software can then issue a volume removal command to return the cached synchronized data to the corresponding location in the source device. • Line • In some embodiments, if the device application software system performs a time-dependent synchronization process and requires precise judgment behavior, the device application program can quite advantageously issue various different types of synchronous pre-capture loading instructions To complete synchronization in an efficient and timely manner. For example, if the device application knows that a specific block of synchronized data must be moved to the cache device, the device application can issue a synchronized pre-capture load command in advance to notify the memory to store all of the synchronized data. Or partial conversion, rather than sending individual synchronization load instructions for individual rows of blocks of synchronized data. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, using synchronous pre-capture loading instructions can also transfer the synchronized data more efficiently and in time, because the processor does not need to wait for the memory to complete a line of synchronized data transfer. Transfer the synchronization data of the next row. The processor, memory, and cache device may also use any suitable and effective technology to execute the above-mentioned synchronous pre-capture load instruction to ensure that a part of a given synchronized data is transferred, which is aimed at processing or using the synchronized data. It takes place before the specified time of the given part. The present invention can therefore provide quite an advantage in an electronic device to effectively utilize a cache. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). B7 V. Invention Description (5) Memory technology. Figure 1 is a block diagram showing an embodiment of an electronic interconnection system according to the present invention; ； 2 is a block diagram showing an embodiment of an exemplary device according to the present invention shown in FIG. 1 Circle 3 is a schematic diagram of one embodiment of the memory of FIG. 2 of the present invention; Circle 4 is a schematic diagram showing FIG. 2 according to an embodiment of the present invention; An embodiment of a section of a cache device according to the present invention; FIG. 6 is a block diagram showing a flow chart for effectively utilizing a cache device according to an embodiment of the present invention; and circles 7 A and 7 B This is a flowchart of method steps that can effectively utilize a cache device according to an embodiment of the invention. Comparison table of main components

110 Electronic interconnection system 112 Electronic device 112 (a) Device A

112 (b) Device B

112 (c) Device C

112 (d) Device D (Please read the notes on the back before filling this page)

502165 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Invention Description (6) 112 (e) Device E 114 Root Device 132 Bus Connector 132 (a) Path 132 (b) Path 132 (c) Path 132 (d) Path 132 (e) Path 2 12 Processor 2 14 Interface 2 16 Memory 220 Bus Interface 226 Device Bus 230 Cache Device 312 Device Software 314 Synchronous Data 3 16 Asynchronous Data 5 12 Position 5 12 (a ) Position 1 5 12 (b) Position 2 5 12 (d) Position N 5 14 Section 5 14 (a 1) Section 5 1 4 (a 2) Section (Please read the precautions on the back before filling in this Page) Order! !!线 __ This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) -9-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 502165 A7 B7 V. Description of the invention (7) 5 1 4 ( a 3) Section 5 1 4 (a 4) Section 5 2 0 Mark 6 12 Path 6 16 Detailed description of the preferred embodiment of the present invention The present invention relates to an improvement of an electronic device. The following description is to enable a person with ordinary knowledge of this technology to make and use the invention, and to explain the content of patent applications and their conditions. Those skilled in the art can make various modifications to the preferred embodiment, and the basic principle of the present invention can be applied to other embodiments. Therefore, the present invention is not limited only to the illustrated embodiments, but rather a broad interpretation of the principles and features described in this specification. The present invention includes a system and method capable of effectively utilizing cache memory in an electronic device, and includes a processor operable corresponding to a software program to synchronize data stored in the cache memory. Insert a detectable mark. The tag can then be used to identify the synchronized data as special information, where the special information is protected from being removed from the cache device when a predetermined volume exception exception does not occur. Referring now to FIG. 1, there is shown a block diagram of an embodiment of an electronic interconnection system 110 according to the present invention. In the embodiment of FIG. 1, the interconnection system 110 preferably includes a plurality of electronic devices 112 (device A 112 (a), device B 112 (b), and root device 114). The paper size is applicable to the Chinese National Standard (CNS) A4. Specifications (210 X 297 mm) (Please read the precautions on the back before filling this page) Order- 丨 丨 ^ ------ line »-10- 502165 A7 ____B7 V. Description of the invention (8) (please first Read the notes on the back and complete this page), device C 112 (c), device D 112 (d), and device E 112 (e)). In another embodiment, the electronic interconnection system 110 can be easily designed to include various other devices 1 12 or components, and the functions thereof can be added to or replace the functions of the device described in FIG. 1. In another embodiment, the interconnect system 110 can be connected and designed in any other and appropriate manner. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the embodiment of FIG. 1, the device 1 1 2 of the interconnection system 110 can be implemented with any type of electronic device, including (but not limited to) a personal computer, Printers, digital video disc devices, televisions, audio systems, cassette recorders, and set-top boxes for digital broadcasting. In the embodiment of Fig. 1, the devices 1 12 are preferably connected by using the bus link members 1 2 2. The bus link 1 3 2 preferably includes a path 1 3 2 (a), a path 132 (b), a path 132 (c), a path 132 (d), and a path 132 (e). For example, in one embodiment, device B 112 (b) is connected to device A 112 (a) via path 132 (a) and is connected to the root device 1 1 4 via path 132 (b). Similarly, the root device 1 1 4 is connected to the device C 112 (c) * via a path 132 (b), and is connected to the device D 112 (d) via a path 132 (d). In addition, the device D 1 1 2 (d) is connected to the device E 112 (e) via the path 1 2 2 (e). In the embodiment of FIG. The IEEES td 1394-1995 standard for performance serial buses is incorporated herein for reference. However, in other embodiments, the interconnect system 110 can also adopt its own paper size to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm). -11-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 502165 A7 ^ .. B7 V. Description of the invention (9) Other interconnection technology to easily communicate with each other, which also falls within the scope of the present invention. In the embodiment of FIG. 1, among the interconnection systems 1 1 0 Each device is preferably connected to any other device in the interconnection system 110. For example, device E 112 (e) can be connected to device B 1 1 2 (b) via the retransmission data transmitted by cable 132 (d), and then retransmit the data via cable 1 3 2 (d ) To the root device 1 1 4. Accordingly, the root device 1 1 4 can then transmit the forwarding data to the device B 112 (b) via the cable 132 (b). In the embodiment of Fig. 1, the root device 1 1 4 is preferably provided with a main control loop signal to the device 112 of the interconnection system 110 for simultaneous and simultaneous processing. In another embodiment of the interconnection system 110, any one of the devices 1 12 can be designated as a root device or a cycle master. Referring now to FIG. 2, there is shown a block diagram of an embodiment of an exemplary device 1 12 of the interconnection system 11 of the present invention. Device 1 1 2 preferably includes (but is not limited to) a processor 2 1 2, an input / output (I / O) interface 2 1 4, a memory 2 1 6, a device bus 226, and a bus排 surface 220. The processor 212, the I / O interface 2 1 4, the memory 2 16, and the bus interface 2 2 0 are preferably connected to each other through a shared device bus 2 2 6. In the embodiment of Fig. 2, the processor 2 12 can be implemented in any suitable multi-function microprocessor device. Memory 2 1 6 can be ~ or more suitable storage devices, including (but not limited to) read-only memory, random access memory, and various types of non-volatile memory. This paper is applicable to China Standard (CNS) A4 Regulations (210 X 297 mm) (Please read the notes on the back before filling this page)

P order ii! Line · -12- 502165 A7 _ B7 V. Description of the invention (such as magnetic disk device or hard disk device. I / O interface 214 is best to provide an interface to compatible with a variety of supply sources and According to the present invention, the bus interface 2 2 0 preferably provides an interface between the device 1 12 and the interconnection system 110. In the embodiment of FIG. 2, the bus interface 2 2 0 It is best to communicate with other devices 1 1 2 on the interconnection system 1 1 0 via the bus connector 1 3 2. The bus interface ^ 2 2 0 is also preferably processed through the shared device bus 2 2 6 The device 212, the I / O interface 214, and the memory 216 are in communication. In the embodiment of FIG. 2, the device 1 12 preferably includes a variety of tasks related to synchronization data and synchronization processing. Synchronization data usually includes time Relevant information, so it needs a decisive transmission operation to ensure that the synchronized data is transmitted in a timely manner. For example, the image data to be displayed in a timely manner must arrive accurately in a timely manner to avoid being displayed The corresponding image during the period jumps or hits In order to achieve this goal, the device 1 1 2 is preferably capable of performing synchronization or other types of processing in the so-called "loop" time zone. The synchronization process usually requires a limited time, which is sometimes called Is the "time expense". When the cycle time is reduced, the time expense becomes a more important factor, because the reduced amount of time still needs to perform the actual synchronous transmission. In the embodiment of Fig. 2, the cycle time is about 1 25 microseconds, and the frequency of the cycle is about eight terahertz. In the embodiment of FIG. 2, the processor 2 1 2 preferably includes a cache device 2 3 0, which allows the processor 2 1 2 to be stored in the memory. The information is stored locally in 2 1 6 for quick and easy access to local data. In another embodiment, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back first) Fill out this page again) -nn I nin ol_ tt n ft— mml line * Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Cooperatives -13- 502165 A7 __ B7 V. Description of the invention (y (Please read the precautions on the back before Fill this page ) The "cache device 230" can be implemented in an appropriate position and in a proper way. The function and shape of the cache device 230 will be further explained below with reference to Figs. 5 to 7. Now please refer to the figure 3, which shows an embodiment of the memory 2 1 6 of FIG. 2 of the present invention. In the embodiment of FIG. 3, the memory 2 1 6 preferably includes, but is not limited to, the device software 3 1 2. Synchronization The data 3 1 4 and the asynchronous data 3 1 6. In another embodiment, the memory 2 1 6 may also include various other elements to add or replace various elements described in the embodiment of FIG. 3. Line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the embodiment of FIG. 3, the device software 3 1 2 includes software instructions, which are preferably executed by the processor 2 1 2 and by the device 1 1 2 To perform various functions and operations. The specific functions of the device software 3 1 2 are best determined by factors such as the type and purpose of the corresponding main device 1 12. According to the present invention, the device software 3 1 2 may also include various instructions, which may cause the processor 2 12 to bidirectionally convert the synchronized data 3 1 4 between the memory device 2 16 and the cache device 2 3 0 and / Or asynchronous data 3 1 6. The operation and application of the device will be further described below in conjunction with FIG. 6 and FIG. 7. Please refer to FIG. 4, which shows an embodiment of the cache device 230 according to the present invention. In the embodiment of FIG. 4, the cache device 230 preferably includes a position 1 (512 (a)) to a position N (512 (d)). In the embodiment of FIG. 4, the cache device 230 is preferably implemented by using a four-wire connection technology, where each position 5 1 2 (a) to 5 1 2 (d) preferably includes four separate sections, And make the processing _14_ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 502165 A7 B7 V. Description of the invention (the device 212 can selectively load information from the address in the memory 216塡 to four segments. Therefore, position 1 (5 1 2 (a)) preferably includes segments 514 (al), 514 (a2), 51 (a3), and 514 (a4). Similarly, the position 2 (512 (b)) preferably includes sections 514 (bl), 514 (b2), 514 (b3), and 514 (b4), and position 3 (512 (c)) preferably includes 514 (cl) , 514 (c2), 514 (c3), and 514 (c4). Finally, position N (512 (d)) preferably includes segments 5 1 4 (d 1), 5 1 4 (d 2), 514 ( d3) and 514 (d4). In another embodiment, the 'cache device 230' can be easily designed to include a variety of different elements, locations and / or regions to add or replace the ones shown in the embodiment of FIG. 4. Those elements. For example, in other different embodiments, fast Each position 5 1 2 of the device 2 3 0 may include any suitable number of storage sections 5 1 4. During the operation of the embodiment of FIG. 4, the processor 2 1 2 preferably uses a four-wire connection technology to The data is mapped from various addresses of the memory 2 1 6 and stored to the cache device 2 3 0. Compared with the cache device 2 3 0, the memory 2 1 6 generally has a larger storage capacity. Storage capacity. Therefore, the multiple storage addresses obtained from the memory 2 1 6 can be mapped to the same position of the cache device 2 3 0. However, each position 5 1 2 of the cache device 2 3 0 is preferably Includes multiple storage sections 5 1 4 so that the multiple memory locations obtained from memory 2 1 6 can be adapted to Chinese paper standard (CNS) A4 (210 X 297 mm) for this paper size (please read first (Notes on the back then fill out this page)

P --- — Order_ I Oh Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-15- 502165 A7 _______________ B7 V. Description of the invention (13) Store to one of the cache devices 2 3 0 5 1 2 . In the embodiment of FIG. 4, when one of the cache devices 2 3 0 is given at all positions 5 1 2, all the segments 5 1 4 already contain the data obtained by the memory device 2 1 6, and the processor 2 1 2 is at position 5 1 2 Requires additional storage space to perform time-related synchronization processing, including transferring synchronized data 3 1 4 from memory 2 1 6 to cache device 2 3 0, which can cause problems. The present invention is quite advantageous and includes a technology that increases the performance of synchronization processing by preferentially storing synchronization data in the cache device 230. According to the present invention, the processor 2 1 2 can therefore mark a specific section 5 1 4 of the cache device 2 3 0 to indicate the content containing the marked section 5 1 4, where the marked section 5 1 4 It contains specific information (such as synchronized data 3 1 4) that should not be removed or “scrapped” (back to memory 2 1 6) to make room for other data, unless certain specific exceptions exist. The marking of a section 5 1 4 and the identification of the exceptions that allow for volume removal will be described below with reference to FIGS. 5 to 7. The cache architecture and technology are further explained in I E E S t d 1 5 9 6 — 1 9 9 2 and its name is “IEEE Standard For Scalable Coherent Interface (SCI)”, the contents of which are incorporated herein by reference. Please refer to FIG. 5, which shows an embodiment of the segment 5 1 4 of the cache device 2 3 0 of FIG. 4 according to the present invention. In the embodiment of Fig. 5, the segment 2 1 4 preferably includes a capacity of 64 bits of information that can be obtained, for example, from the memory 2 1 6. However, in another embodiment, the section 2 1 4 is designed to be stored by any suitable source. Any suitable category of paper size is applicable to Chinese National Standard (CNS) A4 Regulation (210 X 297 mm) (Please Read the notes on the back before filling out this page) Order! !! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -16- 502165 A7 B7__ V. Information on Invention (14). (Please read the note on the back? Matters before filling out this page.) The embodiment of Figure 5 preferably includes a mark 5 2 0 ', which is used to indicate the section 5 1 4 ° that has been designated as a specific state. In the embodiment of FIG. 5, the mark 5 2 0 is preferably the segment 2 1 4, which includes time-correspondence information to provide continuous and timely performance for synchronization processing. In the embodiment of _5, the mark 5 2 0 may also include a digital "bit", and the processor 2 1 2 is preferably set to one of the binary digits 以 to set the corresponding section 5 1 4 is marked as synchronized information. However, in another embodiment, the segment 5 1 4 may be labeled using any other technique to indicate any desired labeling and appropriate status. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics Please refer to the block diagram of FIG. 6, which shows a procedure for using the cache device 230 according to an embodiment of the present invention. In the embodiment of FIG. 6, the processor 2 1 2-starts to sequentially obtain and execute the program instructions of the device application 3 1 2 via the path 6 1 2. In some examples, the aforementioned program instructions of the device application 312 may indicate one or more synchronous load instructions, which enables the processor 2 1 2 to load time-sensitive synchronous data from the memory 216 via the path 6 1 6 to One of the cache devices 2 3 0 specifies a corresponding mapping position 5 1 2. In the embodiment of FIG. 6, the address of each memory 2 16 can be stored in a single section 5 1 4 of the mapping position 5 1 2 of the cache device 2 30. In the embodiment of FIG. 6, according to the present invention, the processor 2 1 2 can instruct the cache device 2 3 0 with considerable advantage to generate a mark 5 2 0 existing in the specific storage of the cache device 2 3 0 Section 5 1 4 indicates that the information stored therein includes synchronous data 3 1 4. China National Standard (CNS) A4 specification (210 X 297 mm) applies to a certain paper size -17 502165 A7 B7____ 5. Description of the invention (id (please read the notes on the back before filling this page) In some examples, The mark 5 2 0 may simply prevent the cache device 2 3 0 from removing the synchronized data 3 1 4 without receiving a specific instruction transmitted by the processor 212. In some states, if there is an excessive number of sections When 5 1 4 is marked by the mark 5 2 0, the performance of the cache device 2 3 0 will be damaged or weakened due to the decrease of the storage section 51 4 available in the cache device 2 3 0. In order to solve this A problem, in some embodiments of the present invention, it is possible to implement certain volume exceptions, so that the cache device 230 has optimized performance. For example, in one embodiment, if the The target part 5 1 2 in the cache device 2 3 0 currently includes a section 5 1 4 which includes the initial synchronization data marked by an initial mark 5 2 0, and if another synchronization load instruction will be recorded due to The subsequent synchronization data of 3 billion 4 2 are mapped to the phase in the cache device 2 3 0 When the same target position is 5 1 2, the processor 2 1 2 can preferably remove the initial synchronization data, so that the subsequent synchronization data obtained by the memory 2 1 6 can be marked with a mark 5 2 0 And loaded to a specific area 5 1 4. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In addition, in a state related to other volumes except exceptions, the device application 3 1 2 can also instruct the processor 2 1 2 to be fast Take one of the optional segments 514 of the device 2 3 0 and delete them corresponding to different changes in the status of the device 112. For example, if a synchronization process is suspended, the corresponding synchronization data is no longer It needs to exist in the cache device 230, and the electronic device application 312 can issue a roll-off instruction with considerable advantages, so that the cache device 230 has the advantages of optimization. This paper size is applicable China National Standard (CNS) A4 Specification (210 X 297 mm) " ~ -18- 502165 A7 — B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy When synchronization is complete, its A volume exception can be provided, in which the device application 3 1 2 issues a volume removal instruction so that one of the cache devices 2 3 0 corresponding to the marked section 5 1 4 can be left blank. For example, in In the example where the segment 5 1 4 includes synchronization data of 64-bit components, the device application 3 1 2 can determine the final or 64-bit synchronization data with considerable advantages. 4 to obtain and use. Correspondingly, the device application 3 1 2 can also issue a volume division instruction, so that the cached synchronized data can be returned to the corresponding position in the record billion 2 16. In the embodiment of FIG. 6, if the device application 3 1 2 performs time-related synchronization processing and requires accurate judgment behavior, the device application 3 1 2 can issue various types of synchronization pre-emptions quite favorably. Capture load instructions to efficiently and successfully complete synchronous processing. For example, if the device application 3 1 2 knows the synchronization data of a specific block 3 1 4 must be moved to the cache device 2 3 0 *, then the device application 3 1 2 can issue a synchronized pre-capture load in advance Instructions to notify the memory 216 to convert all or part of the above-mentioned synchronization data 314, instead of transmitting individual synchronization load instructions for individual rows of the blocks of synchronization data 314. Using the synchronous pre-capture loading instruction can also transfer the synchronized data more efficiently and in time, because the processor 2 1 2 does not need to wait for the memory 2 1 6 to complete a line of synchronized data transfer, it can start the transfer from the memory 2 1 6 Sync data for the next line. Processor 2 1 2. Memory (Please read the precautions on the back before filling this page)

P · ----This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) -19- 502165 A7 B7 _ ___ V. Description of the invention (17) < Please read the precautions on the back first (Fill in this page) 2 1 6 and cache device 2 3 0 can also use any appropriate and effective technology to execute the above-mentioned synchronous pre-capture load instruction to ensure that the transfer of a part of a given synchronized data is Or do it before a specified time using a given part of the sync data. For example, the device application 3 1 2 can provide synchronization "implies that one of the compilers can translate it into a corresponding synchronous pre-capture load instruction. Alternatively, the device application 3 1 2 can include various different pre-loading instructions. Capture parameters to calculate the synchronous pre-capture load instruction, or the device application 312 may also provide a specific synchronous pre-capture load instruction to the processor 2 1 2 under appropriate predetermined conditions. Please refer to FIG. An embodiment of the invention uses the initial part of a flowchart of the method steps of a cache device 230. Initially, the method steps of FIG. 7A show an embodiment in which one of the cache devices 230 The specific target position 5 1 2 is a blank segment 5 1 4 to store the extra information obtained from the memory 2 1 6. The processor 2 1 2 therefore needs to perform a roll-out process to make a segment 5 1 4 is left blank, and additional information is loaded by the memory 2 1 6. The embodiment of Figures 7 A and 7 B printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics is used to explain some principles and features of the present invention However, in other embodiments, in addition to the method shown in Figs. 7A and 7B, the present invention can still be implemented using a variety of different steps and techniques. Furthermore, in another embodiment, Figs. 7A and 7B The method steps can be performed in a different order than shown in the embodiment of Figs. 7A and 7B. In the embodiment of Fig. 7A, the processor 212 is preferably composed of a Software programs (such as device applications 312) This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) -20- 502165 A7 B7 ) Receive a program instruction, and then determine the received program instruction accordingly. If the type of the received instruction is a load or store data instruction, in step 7 2 4, the processor 2 1 2 will determine the The specific data in the load data instruction is already located in the cache device 230. If the specific data in the load data instruction is already located in the cache device 230, the processing of FIG. 7A proceeds to flowchart 7B. . However, if at step When the data classified in the load data instruction of 7 2 0 does not exist in the cache device 2 3 0, the processor 2 1 2 will judge the instruction in step 7 2 8 (step 7 2 0) It is a synchronous load or a storage instruction. If the instruction is not a synchronous load or storage instruction, in step 7 32, the processor 2 1 2 is preferably the target portion 5 1 2 of the cache device 2 3 0 The unmarked section 5 1 4 is removed. In step 7 3 6, the processor 2 1 2 then captures and loads the appropriate section 5 transferred from the memory device 2 1 6 to the cache device 2 3 0 1 4 and the flow of Fig. 7 A goes to Fig. 7 B. However, if the instruction is a synchronous load or storage instruction, the processor 2 1 2 preferably judges the synchronous data 3 1 4 (to switch between the memory device 2 1 6 and the cache device 2 3 0). To one of the target positions 5 1 2 (including those marked by the mark 520), the cache device 2 3 0 includes a mark section 5 1 4. If the transferred data does not map to the location 512 of one of the cache devices 230 having a marked section 514, then in step 7 4 2 the processor 2 1 2 is preferably to remove the cache device 2 3 0 Any section 5 1 4 in the target position 5 1 2. The flow of FIG. 7A then proceeds to step 748. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) -H ϋ nn nn One: ° 4 «n ft— I * n line_ _ -21-502165 A7 ________ .. B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (19) However, in step 7 40 above, if the transferred synchronized data is mapped to the cache device When 2 3 0 includes the marked position 5 1 2 of the segment 5 1 4, then in step 744, the processor 2 1 2 preferably removes the information in the segment 5 1 4 to generate an empty space. The subject sector 5 1 4. Next, in step 748, the processor 2 1 2 preferably captures and loads the specific synchronization data from the memory 2 1 6 into the empty target segment 5 1 4 in the cache device 2 3 0. In step 7 5 2, the processor 2 1 2 may also advantageously mark the above-mentioned target section 5 1 4 with a mark 5 2 0 to indicate its special status. In the above step 7 2 0, if the instruction type includes a “Central Flash” instruction, which is marked in a special flashable markable section 514 in the cache device 2 3 0, then in step 776 The processor 212 preferably removes the special flashable mark segment 5 1 4 in the cache device 230, so that it can freely apply other data transfer operations. The flow of FIG. 7A then proceeds Proceed to FIG. 7B. In the previous step 7 2 0, if the instruction type includes any instruction other than a “load data” instruction or a “flash” instruction, the flow of _ 7 A proceeds to FIG. 7 Step B of Process Park Η β ”. Please refer to FIG. 7B, which shows the last part of the flow of the method steps of using the cache device 230 according to the present invention. In the flowchart of FIG. 7B, at the beginning, in step 7 64, if necessary, as in the previous step 7 2 0 of FIG. 7 A, the processor 2 1 2 preferably executes any "other" program. instruction. Next, in step 7 6 8 the processor 2 1 2 is best to judge the one marked with the mark 5 2 0 in the cache device 2 30 or the {Please read the precautions on the back before filling this page) · # IC— a ^ * 0 n IE nnn line. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -22- 502165 A7 B7 V. Final area on the description of the invention (20) Whether all the information in paragraph 5 1 4 has been obtained and used. As described above with respect to FIG. 6, in some embodiments, the processor 212 can also determine whether it is in the final section 5 1 4 by monitoring whether the final storage location or address has been obtained from a marked section 514 and used. Have all the information in it been used. If all the information in the section 5 1 4 of the cache device 2 3 0 is not used, the flow of FIG. 7B can proceed to step 756. However, if all the information has been used in the final section 5 1 4 of the cache device 2 3 0, then in step 7 72, the processor 2 1 2 is preferably removed from the cache device 2 3 0 Baoxun in the special final segment 5 1 4 so that the final segment 5 1 4 can be used by other different data transfer operations. Next, in step 7 56, the processor 2 1 2 is preferably capable of executing an upgrade procedure in a program counting device. Finally, in step 7 60, the processor 2 1 2 is preferably a software program (such as the device application 312) to capture the next program instruction, and the processing flow of FIG. 7B returns to the previous step of FIG. 7A. 7 2 0 to analyze other program instructions. 0 The present invention has been described above for the preferred embodiment. However, after reading the above description, those skilled in the art can make other modifications to the present invention. For example, the present invention can also be implemented using designs and techniques different from the above embodiments. In addition, the present invention can also cooperate with other systems different from the above-mentioned preferred embodiments. Therefore, these and other changes in the preferred embodiments should be covered by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling this page) Order ----- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- twenty three ·

Claims (1)

502165 A8 B8 C8 D8 6. Scope of patent application 1. A system that can effectively perform a data transfer operation 'It contains: Is (Please read the precautions on the back before filling this page) A cache device, which is used to store specific information Storage to one or more storage locations; a software program to identify and manage specific information on one or more storage locations; and a processor corresponding to the software program to control the cache Device, thereby performing the data transfer operation. 2. The system according to item 1 of the scope of patent application, wherein the special information includes synchronous data, which has a decisive and guaranteed transmission. 3. The system according to item 1 of the patent application, wherein the data transfer operation is performed in an electronic device on an electronic interconnection system, which is based on the IEEES td 1 3 9 4 serial bus interconnection technology Standards to implement. The smart money of the Ministry of Economic Affairs is printed by the ^ M Industrial and Consumer Cooperatives. For example, the system of the first scope of patent application, wherein the data transfer operation is performed on an electronic device, which includes an electronic device at the customer's end, One of an audio-visual device, a set-top box device, and a computer device. 5. The system according to item 1 of the patent application, wherein the cache device is implemented by a processor cache device used by the processor. -kn n ·· — I · 6 · The system according to item 1 of the patent application scope, wherein the cache device is implemented using a four-wire connection technology. 7. The system according to item 1 of the scope of patent application, wherein the processor uses a mark to mark a storage section in the cache device to identify the storage • 24-This paper size applies Chinese National Standard (CNS) M specifications (210X29? Mm) 502165 AB BB C8 DB VI. Patent application scope The storage section includes synchronization data that cannot be removed from the storage section of the cache device until a predetermined volume except for an exception event occurs. The volume Exception events include subsequent synchronization transfer events in the storage segment, specific volume removal instructions that are rolled out by the processor for the storage segment, and final data usage events for synchronized data in the storage segment. An event. 8. The system according to item 1 of the patent application scope, wherein the cache device includes at least one cache location, which includes at least one storage section, and the storage section contains priority processing information. 9 · The system according to item 8 of the patent application, wherein the software program includes a device application software, and it includes a data loading instruction which can be executed by a processor. 10 • If the system of item 9 of the patent application is applied, the processor judges whether the load data instruction contains one by one the synchronization data transferred from the source memory to the cache device. 1 1 · If the system of item 10 of the patent application scope, wherein the processor executes a volume division program, so that when the load data instruction does not perform a synchronous data transfer one by one, the priority information can be returned to the source Memory. 1 2. If the system of item 10 of the patent application scope, wherein when the load data instruction specifies a synchronous data transfer one by one, the processor determines whether the at least one cache location includes a mark storage section. 1 3 · If the system according to item 12 of the patent application scope, wherein when the at least one cache location does not include the mark storage section, the processor executes a volume removal process to return priority information to the source memory body. This paper size applies to China National Samples (CNS) A4 specification (210X297 mm) _ 25-—UK immmmmmw MmmmmmmmMB —Βϋ ·: (Please read the precautions on the back before filling this page) Order ^-Ministry of Economic Affairs Printed by the Bureau of ts Industrial and Consumer Cooperatives f 502165 Printed by the Consumers ’Cooperatives of the Ministry of Economics and Smart Finance 4 Bureau A8 BS C8 D8 6. Apply for a patent scope 1 4. If the system of the patent scope No. 12 is applied, where the at least one quick When the fetch location includes the tag storage section and the tag storage section then becomes a vacant storage section, the processor executes a volume removal procedure to return priority information from the tag storage section to the source memory . 15. The system according to item 14 of the scope of patent application, wherein the processor loads subsequent synchronization data to the empty storage section, and the processor marks the subsequent synchronization data with a mark to generate a protective property. Storage section 016. The system of item 1 of the patent application scope, wherein the processor executes a volume exception event by executing a flash instruction, wherein the flash instruction causes the specific information to be transferred from the flash memory. Take a marked section of the device and return it to a source memory device. 17. The system according to item 1 of the scope of patent application, wherein the processor executes a roll exception event by executing a roll instruction, wherein the roll instruction is when all specific information has been used by a software program , Which enables the specific information to be returned from a marked section of the cache device to a source memory device. 18. The system according to item 1 of the patent application scope, wherein the processor transmits a synchronous pre-capture instruction to a source memory device, thereby capturing the synchronized data to the cache device in advance. 19 · If the system of item 18 of the scope of patent application, the synchronous pre-capture instruction enables the processor to capture a block of synchronized data to the cache device, and the block of the synchronized data is targeted at The use time of the synchronization data is stored in the cache device before. This paper size is applicable to Chinese national standard umbrella (€%) 8 size (210/297 mm) miscellaneous 26 ^ " " " (Please read the precautions on the back before filling WHI) 11 0! * Ili— — — ΒΒβ Printed by the Ministry of Economy ’s Smart Financial Co., Ltd. P ’Industrial Cooperative Cooperative 502165 AB BB C8 DB VI. Application scope of patent 2 0 · For the system of scope 19 of patent application, the synchronous pre-capture instruction uses a pre-capture technology It includes one of the following software programs: a software program that can provide synchronization hints to an editing program to convert them into corresponding synchronous pre-capture load instructions, and can provide predetermined pre-capture parameters to calculate the synchronous pre-capture load instructions A software program and a software program that can provide the synchronous pre-capture load instruction to the processor in a specified state. 2 1 · — A method for effectively performing a data transfer operation, the method includes the following steps: storing specific information in one or more storage locations of a cache device; using a software program to manage the one or more Special information in the storage location; and a processor to control the cache device corresponding to the software program to perform the data transfer operation. 2 2 · If the method according to item 21 of the patent application scope, wherein the special information includes synchronous data, it requires a decisive and guaranteed transmission. 2 3 · The method according to item 21 of the patent application, wherein the data transfer operation is performed in an electronic device on an electronic interconnection system, which is performed in accordance with the IEEES td 1 3 9 4 serial bus Even technical standards. 2 4 · If the method according to item 21 of the patent application scope, wherein the data transfer operation is performed on an electronic device, the electronic device includes an electronic device at the customer end, an audio-visual device, and a set-top box device Applicable to China National Standard (CNS) A4 specification (210X 297 mm) in Zhang scale · 〇7-" " " (Please read the precautions on the back before filling this page) 502165 AB B8 CB D8 Printed by the Ministry of Economic Affairs Smart Assets 4AP 'Industrial and Consumer Cooperatives 6. Scope of patent application and a computer device. 25. The method according to item 21 of the patent application scope, wherein the cache device is implemented by a processor cache device used by the processor. 26. The method according to item 21 of the patent application scope, wherein the cache device is implemented using a four-wire connection technology. 27. The method according to item 21 of the scope of patent application, wherein the processor marks a storage section with a mark in the cache device to identify that the storage section includes up to a predetermined volume except for exception events Synchronous data occurred that could not be removed from the storage section of the cache device. The volume exception event includes a specific volume that is subsequently synchronized with the storage section, and is deleted by the processor for the storage section. One of an event, a delete command, and a final data usage event for synchronized data in the storage section. 28. The method of claim 21, wherein the cache device includes at least one cache location, which includes at least one storage section, and the storage section includes priority processing information. 29. The method according to item 28 of the scope of patent application, wherein the software program includes a device application software and includes a data loading instruction that can be executed by a processor. 30. The method according to item 29 of the patent application scope, wherein the processor judges whether the load data instruction executes the synchronized data transferred from the source memory to the cache device one by one. 31. The method of claim 30, wherein the processor executes a volume division program, so that when the load data instruction does not perform a synchronous data transfer one by one, the priority information can be returned to the source Note (Please read the notes on the back before filling this page) -I ftn m In ml * i. This paper size applies to China National Standard (CNS) A4 specification (2 丨 0X297 mm) * 28-502165 A8 B8 C8 D8 A. Memory of patent application scope. Bristles (please read the precautions on the back before filling this page) 3 2. If the method of the scope of patent application No. 30, where the load data instruction one by one synchronous data transfer, the processor judges that at least Whether a cache location includes a marker storage section. 3 3 · The method according to item 32 of the scope of patent application, wherein when the at least one cache position does not include the mark storage section, the processor executes a volume removal process to return priority information to the source memory body. 34. The method according to item 32 of the scope of patent application, wherein when the at least one cache location includes the mark storage section and the mark storage section then becomes a vacant storage section, the processor executes A volume removal process to return priority information from the marked storage section to the source memory. 35. The method according to item 34 of the scope of patent application, wherein the processor loads subsequent synchronization data to the empty storage section, and the processor marks the subsequent synchronization data with a mark to generate a protective property. Storage section 0 The Ministry of Economics ’wisdom is printed by Θ Baygong Consumer Cooperative 3 6 · If the method of the scope of patent application No. 21, wherein the processor executes a volume of exceptions by executing a flash instruction, The flash command returns the specific information from a marked section of the cache device to a source memory device. 37. The method according to item 21 of the scope of patent application, wherein the processor executes a volume exception event by executing a volume removal instruction, wherein the volume removal instruction is when all specific information has been used by the software program , It can return the specific information from a marked section of the cache device to a source memory device. Applicable for paper and towel size (CNS) A4 size (210x297 mm) ^ ~ 502165 A8 B8 C8 D8 VI. Application for patent scope 3 8 · If the method of the scope of patent application No. 21, where the treatment The device sends a synchronization pre-capture instruction to a source memory device, so as to capture the synchronization data to the cache device in advance. 39. The method of claim 38, wherein the synchronous pre-capture instruction enables the processor to capture a block of synchronized data to the cache device, and the block of the synchronized data is The use time of the synchronization data is stored in the cache device before. 40. The method according to item 39 of the scope of patent application, wherein the synchronous pre-capture instruction is implemented by using a pre-capture technology, which includes one of the following software programs: can provide synchronous hints to an editing program to convert it into Corresponding software program for synchronous pre-capture load instruction, software program that can provide predetermined pre-capture parameters to calculate the synchronous pre-capture load instruction, and software that can provide the synchronous pre-capture load instruction to the processor in a specified state Program. 4 1. A computer-readable medium, which is a program instruction that can use a cache to record billions of bytes, which includes the following steps: Store specific information to one or more storage locations of a cache device. A software program to manage the specific information of the bit in one or more storage locations; and a processor corresponding to the software program to control the cache device 'to perform the data transfer operation. 4 2 · —A system that can effectively perform a data transfer operation 'includes: ϋϋ -1 -----— i In —ϋ —ill fen ml US. • # (Please read the precautions on the back before filling out this Page) Ordered by the Ministry of Economy ’s Smart Finance is printed by the Bureau ’s Consumer Cooperatives. 0 H— ϋ · — * This paper size is applicable to the Chinese National Standard (CNS) Α4 specification (2 丨 0X297 mm) -30- Ministry of Economy ’s Smart Finance 4¾ Staff consumption Cooperative printed 502165 A8 B8 CB D8 6. Applicable devices for storing specific information to one or more storage locations; devices for managing specific information located at one or more storage locations; and for controlling In the storage device, the control device can perform data transfer operation corresponding to the management device. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) _ 31 (Please read the precautions on the back before filling this page)