經濟部智慧財產局員工消費合作社印製 451349 A7 _______B7 五、發明說明（） 發明頜域」_ ’ 本發明與一種半導趙製程中介電層之平坦化程序 有關’特別是一種在製造雙重鑲丧結構（dual damascene) 時，用以使金屬間介電層（inter-metal dielectric layer; IMD)平坦化（planarization)之方法。 瘀明背景： 隨著半導«工業進步至超大型積體電路（ULSI)，所 製造之積體電路亦日趨密集，而包含於積體電路中之各種 元件其尺寸亦更趲缩小，么使在同樣面精的晶圈底材上可 以容納更複雜精密之電路元件。為了達成此目的’一般需 在晶圓上製作各式沉積薄膜及微影圖案β但是，如此繁雜 的製程，卻也經常造成晶圓表面產生相當程度的落差。更 者，隨晶片表面膜層之高低起伏’亦導致在後續形成沈積 層時，微影，曝光聚焦等程序之困難，並且也影響進行蝕 刻或沈積的品質。因此’平坦化製程於半導艘製程中格外 重要。 此外，在多重金屬内連線的微影製程中，由於受制 於微影製程其解析度，以及影像傳遞的精_度’再加上金 屬沉積與蝕刻所遭遇的諸多因難，使得雙重鑲嵌結構 (Dual damascene structure)之技術，被大量應用於多重金 本紙張尺度適用中a國家標準（CNS>A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -------- 訂--I ----- ·線· 451349 經濟部智慧財產局員工消f合作社印製 A7 B7 五、發明說明（） 属内連線中。但是由於雙重鑲嵌結構往往需反復的沉積介 電層與金屬連線層，是以位於底下膜層之表面形狀 (topography)往往會對後續沉積的膜層造成影響。 請參照第一圏，該圈顯示了傳統製程中，製作雙重 鎮彼結構於半導體底材上之相關步驟。其中，在製作雙重 鎮兹：結構時’可先形成一介電層4於半導體底材2上。接 著’可對此介電層4進行蝕刻程序，以定義如溝渠之開σ 圖案於其上》例如，在第一圖中，形成於介電層4上之開 口圖案’包括了密集（dense)的接觸孔與較大尺寸之溝 渠。然後’可進行金屬沉積程序，以形成金屬層於此介電 層4之表面上’且填滿所有的開〇圈案中a接著，可進行 一化學機械研磨程序（chemicall.y mechanical polishing; CMP)，以移除位於介電層4上表面之金屬材料。如此’可 在密集接觸孔中，形成所需之速線結構6。同時，在溝渠 開口中形成所需之溝渠連線結構7。 值得注意的是，在進行CMP製程，以移除不需要之 金屬材料時，由於金屬材料之特性，往往會造成所製造金 屬連線其表面，產生碟盤（dishing)效應。亦即，如第一圖 中之溝渠連線結構7，其上表面會呈現一弧狀的凹陷。並 且’對位於密集接觸孔中之連線結構6而言，除了造成這 些密集連線結構6，亦具有碟狀表面的形狀外，位在比些 密集連線結構6間之介電層4，亦會在CMP程序中，遭受侵 本紙張尺度適用1»國a家標準（CNS)A4規格⑽x 297公釐） ΐ --------------J11 . (請先閱讀背面之注意事項再填冩本頁) A7Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 451349 A7 _______B7 V. Description of the invention () Invention of the jaw field "_" The present invention is related to a flattening process of a dielectric layer in a semi-conductor Zhao process, especially a method of manufacturing a double insert In a dual damascene structure, a method for planarizing an inter-metal dielectric layer (IMD). Background of stasis: With the advancement of semi-conductor industry to ultra large integrated circuits (ULSI), the integrated circuits manufactured have become increasingly dense, and the size of various components included in integrated circuits has also become smaller. It can accommodate more complicated and precise circuit components on the same crystal substrate. In order to achieve this purpose, various types of deposited films and lithographic patterns β are generally produced on the wafer. However, such a complicated process often causes a considerable difference in the surface of the wafer. Furthermore, the fluctuation of the film layer on the surface of the wafer also causes difficulties in processes such as lithography, exposure and focusing during the subsequent formation of the deposited layer, and also affects the quality of the etching or deposition. Therefore, the 'flattening process' is particularly important in the semi-ship process. In addition, in the lithography process with multiple metal interconnections, due to the resolution of the lithography process and the precision of image transmission, coupled with many difficulties encountered in metal deposition and etching, the dual mosaic structure has been made. (Dual damascene structure) technology has been widely used in multiple gold paper standards for a national standard (CNS > A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) --- ----- Order--I ----- · Line · 451349 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 B7 Cooperative Fifth, the description of the invention () is in the internal connection. However, due to the double mosaic structure often requires The repeated deposition of the dielectric layer and the metal wiring layer is based on the topography of the underlying film layer, which often affects the subsequent deposited film layer. Please refer to the first section. This circle shows the traditional manufacturing process. Relevant steps of double ballasting the structure on the semiconductor substrate. Among them, when making the double ballasting structure: a dielectric layer 4 can be formed on the semiconductor substrate 2 first, and then the dielectric layer 4 can be etched. Procedures to define For example, in the first figure, the opening pattern formed on the dielectric layer 4 includes a dense contact hole and a trench of a larger size. Then, a metal can be formed. A deposition process to form a metal layer on the surface of the dielectric layer 4 and fill all the openings a. Then, a chemical mechanical polishing process (chemicall.y mechanical polishing; CMP) can be performed to remove The metal material on the upper surface of the dielectric layer 4. In this way, the required speed line structure 6 can be formed in the dense contact holes. At the same time, the required trench connection structure 7 is formed in the trench opening. It is worth noting that When the CMP process is performed to remove unwanted metal materials, due to the characteristics of the metal materials, the surface of the manufactured metal wire is often caused to have a dishing effect. That is, as shown in the trench in the first figure The connecting structure 7 will have an arc-shaped depression on its upper surface. 'For the connecting structures 6 located in the dense contact holes, in addition to causing these dense connecting structures 6, they also have the shape of a dish-like surface. In the ratio The dielectric layer 4 between these densely connected structures 6 will also be subjected to intrusion in the CMP process. The paper size applies 1 »National Standard (CNS) A4 specification (x 297 mm) ΐ ------- ------- J11. (Please read the notes on the back before filling this page) A7
451349 五'發明說明（） 轴（erosion)，而同樣產生下*陷之情形。如此一來，後續所 形成之介電層8,會由於位於其下介電層4與連線結構6、7 之表面形狀（topography)之不平均，而產生相對應之凹陷 區域10於介電層8之上表面β 然後，請參照第二圖，在介電層8具有不平坦上表 面之情形下’往往容易導致後續所形成導電結構之良率大 幅下降。其中，在形成了介電層8之後，接著如同前述， 可藉著進行蝕刻程序，來定義開口圖案於此介電層8上。 隨後，沉積金屬材料層於此介電層8上，以填充於開口圈 案，並進行CMP製程以移除位於介電層8上表面之金屬材 料，以便定義出所需之導電结構12。但值得注意的是，由 於介.電層8之上表面具有凹陷區域10，是以在進行後績 CMP程序，以移除不需要之金屬材料時，由於位在連線結 構12間之部份介電廣8’具有低陷的上表面，是以依然會 有殘餘的金屬材料14存在°如此一來，將會導致原本應該 分離之導電结構12，由於殘餘的金屬材料14，而彼此連结 在一起，造成所製造之溝渠連線12’產生短路（sh〇rt)之現 象，且造成後續所製造半導艘元件之可靠性下降。 (請先閱讀背面之注意事項再填寫本1> 經濟部智慧財產局MK工消费合作社印製 述 概 及 的 i 明 發 明 發 本 程 化 坦 平 行 供 提 在 的 目方 之之 序 〇 法 進 層 膜 程 製 體 導 半 對 種 本紙張尺度適用令ffl國家標準（CNS>A4規格（210 * 297公釐） 451349 經濟部智慧財產局具工消費合作社印製 A7 B7 五、發明說明（） ， 本發明之又一目的在提供一種在雙重鑲嵌結構製 程令’對金屬間介電層進行平坦化程序，以避免殘存金層 材料造成鑲嵌結搆短路之方法。 本發明之再一目的在提供一種清除所形成膜層表 面上污染微粒之方法。 在本發明中提供了一種利用新的平坦化程序，來製 作雙重鑲嵌結構之方法。其令，首先提供—半導體底材， 其令半導體底材上具有第一介電層。接著，蝕刻第一介電 層’以形成第一開口圖案;^第一介電層上β再沉精第一金 屬層於第一介電層表面上，且填充至第一開口囷案中。然 後1回蝕刻第_金屬層至第一介電層上表面為止，以形成 第一金屬内連線結構於第一開口圖案中β隨後，沉積第二 介電層於第一介電層舆第一金屬内連線結構上，並將半導 體底材置於自旋轉姓刻機台（spin etcher)中，以便對第二 介電層進行自旋轉蝕刻程序，以達成平坦化之目的。其中 使用包含有研磨微粒（abrasive particle)之反應蝕刻溶液 (react丨ve etching solution)，喷邐於旋轉中之該半導想底 材上，以對該第二介電層上表面進行研磨。接著，姓刻第 二介電層，以形成第二開口圖案於第二介電層上，並沉積 第二金屬層於第一介電層表面上’且填充至第二開口圖案 之中。然後，移除部份第二金屈層，直到啄露出第二介電 本紙張尺度適用中S國家揉準（CNS)A4規格<210 X 297公釐） ί請先閱讀背面之注意事項再填寫本頁)451349 Five 'invention description () axis (erosion), and the same situation occurs. In this way, due to the unevenness of the topography of the lower dielectric layer 4 and the connection structures 6, 7 formed in the dielectric layer 8 formed subsequently, a corresponding recessed area 10 in the dielectric is generated. Upper surface β of layer 8 Then, referring to the second figure, in the case where the dielectric layer 8 has an uneven upper surface, it often tends to cause a significant decrease in the yield of the conductive structure formed subsequently. After the dielectric layer 8 is formed, as described above, an opening pattern can be defined on the dielectric layer 8 by performing an etching process. Subsequently, a metal material layer is deposited on the dielectric layer 8 to fill the opening pattern, and a CMP process is performed to remove the metal material on the upper surface of the dielectric layer 8 so as to define the required conductive structure 12. However, it is worth noting that because the dielectric layer 8 has a recessed area 10 on the upper surface, the post-CMP process is performed to remove unwanted metal materials. The dielectric surface 8 'has a low recessed upper surface, and there is still a residual metal material 14 °. As a result, the conductive structure 12 that should have been separated will be connected to each other due to the residual metal material 14 Together, this causes a short circuit (short) of the manufactured trench connection 12 ', and reduces the reliability of the semi-conductor components manufactured subsequently. (Please read the precautions on the back before filling in this 1 >> The outline of the printing process outlined by the MK Industrial and Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and the development of this process is parallel to the objective of the process. Membrane guide system is applicable to the standard of paper type ffl national standard (CNS > A4 specification (210 * 297 mm) 451349 Printed by A7 B7, Industrial Property Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs Another object of the present invention is to provide a method for planarizing the intermetal dielectric layer during the dual damascene structure process order, so as to avoid the short-circuit of the damascene structure caused by the residual gold layer material. Another object of the present invention is to provide a method for removing A method for forming contaminated particles on the surface of a film layer. A method for making a dual damascene structure by using a new planarization process is provided in the present invention. First, a semiconductor substrate is provided. A dielectric layer. Next, the first dielectric layer is etched to form a first opening pattern; β is first deposited on the first dielectric layer and the first metal layer is deposited on the first dielectric layer. On the surface of the dielectric layer and filled into the first opening pattern. Then the _ metal layer is etched up to the upper surface of the first dielectric layer 1 time to form a first metal interconnect structure in the first opening pattern β Subsequently, a second dielectric layer is deposited on the first dielectric layer and the first metal interconnect structure, and the semiconductor substrate is placed in a spin etcher to spin the second dielectric layer. A self-rotating etching process is performed to achieve the purpose of planarization. A reactive etching solution containing abrasive particles is used to spray the semi-conductive substrate under rotation to The upper surface of the second dielectric layer is polished. Next, the second dielectric layer is engraved to form a second opening pattern on the second dielectric layer, and a second metal layer is deposited on the surface of the first dielectric layer. 'And fill it into the second opening pattern. Then, remove a portion of the second gold flexion layer until the second dielectric paper size is exposed. Applicable S-country standard (CNS) A4 specification < 210 X 297 male Li) Please read the notes on the back before filling in this page)
451349 A7 B7 五'發明說明（） 層上表面為止’以形成第二金屬内速線結構於第二開口圖 案_。 圖式簡箪說明 藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述内容及此項發明之諸多優點，其中： 第一圖為半導艘晶片之截面圖，顯示根據傳統製 程’形成雙重鑲嵌結構於半導醴底材上之步驟； 第二圈為半導艘晶片之截面圖，顯示根據傳統製 程’形成雙重鑲嵌結構於半導艘底材上時，殘餘的金層材 料會造成導電結構間之短路現象； ，第三«為半導體晶片之截面圖，顯示根據本發明形 成第一介電層於半導體底材上之步麻； 第四圖為半導想晶片之載面圖，顯示根據本發明形 成第一介電層中金屬内連線之步驟； 第五圖為半導髏晶片之截面圈，顯示根據本發明形 成第二介電層於半導體底材上之步棘； 第六圖為自旋轉蝕刻機台之配置圖，顯示根據本發 明用來對半導體底材上之第二介電層，進行平坦化製程之 自旋轉蝕刻機台相關元件； 第七圏為半導想晶片之截面圖，顯示根據本發明方 法，進行平坦化製程後之半導逋底材； 第八圖為半導體晶片之截面圖，顯示根據本發明形 本紙張尺度適用争國國家標準（CNS)A4規格（210 X 297公釐） <請先閱讀背面之注意事項再填寫本頁) · III---11 --11--.線^ 經濟部智慧財產局員工消費合作社印製 4513 49 A7 B7 五、發明說明（） 成開口圈案於苐二介電廣Jb之步称；及 第九圈為半導體晶片之截面圖，顯示根據本發明形 成第二介電層間金屬内連線结構之步驟。 發明詳細說明： 本發明提供一個新方法用以對半導艘製程中之膜 層進行平坦化程序。藉著將此半導逋底材放於自旋轉蝕刻 機台令’並在半導想底材進行自旋轉時，對其膜層表面嗔 灑包含了研磨微粒（abrasive particle)之蝕刻反應溶液，將 可有效的對膜層表面進行研磨’使其達到平坦化之效果。 有關本發明之詳細說明如下搿述。 首先’在·"較佳之具《實施例中，如第三圖所示， 提供一具<100>晶向之單晶矽作為半導體底材1〇〇。一般 而言，其它種類之半導體材料，諸如砷化鎵（gauium arsenide)、鍺（germanium)或是位於絕緣層上之梦底材 (silicon on insulator，SOI)皆可作為半導體底材使用。另 外’由於半導艎底材表面的特性對本發明而言，並不會造 成特別的影响’是以其晶向亦可選擇<11〇>或<111〉。 接著’形成第一介電層102於此半導體底Mi 00之 上，以作為金屬問介電層（IMD)。此處要特別說明的是在 形成介電層102之前，此半導ft底材1〇〇之表面上，可先形 本紙張尺度適用中Ba家標準（CNS)A4规格<210 X 297公釐> (請先閱讀背面之注意事項再填寫本頁) ---1-----訂-------I -線. 經濟部智慧財產局員工消费合作社印製 451349 Λ7 B7 五、發明說明（） 成積體電路所需之各式主動•元件、被動元件、與週圍電路 等等。亦即，此半導艘底材100表面上，已具有各式所需 之功能層與材料層〃在一較佳實施例中，第一介電層102 之材料可選擇氧化矽、氮化矽或其任意組合。其中，此第 一介電層102可以是使用化學氣相沈積法所形成之二氧化 矽’該化學氣相沈積法是以正矽酸乙酯（TE0S)在溫度600 至8 00°C間且壓力約〇」至lOtorr時形成。或著，也可在大 約400至45 0。C的爐中形成氮化矽來作為此第一介電層 102，製程中的反應氣體是siH4，N20及NH3。 然後，蝕刻第一介電層102，以形成數個密集的接 觸孔106與溝渠開口圖案1〇4於其上。一般而言，此蝕刻程 序可.使用非均向性的電漿蝕刻技術，如反應離子蝕刻術 (reactive ion etching; RIE)，來加以進行。且當第一介電 層102為氧化矽層時，可用蝕刻劑cci2f2、chf3/cf4、chf3/ 〇2、 ch3chfi ' cf4/os;至於當使用氮化矽來作為第一介電 層102時，則可藉由CF4/H2、 CHF 3或CH3CHF2來作為 蝕刻劑。 隨後，可沉積第一金屬層於第一介電層102表面 上，且填充至密集的接觸孔106與溝渠開口圖案104之中。 在一較佳貧施例中，可使用物理氧相沉積（physical vapor deposition; PVD)法，先形成一薄銅原子層於第_介電層 102之表面’以作為铜晶種（Cu seeding)層。接著，再使用 8 本紙張尺度適用中a a家標準(CNS)A4规格(210 X 297公《 ). (請先閱讀背面之注意事項再填寫本頁) I l·--i I I ---- I----^ . 經濟部智慧財產局員工消费合作社印製 451349 Α7 Β7 五、發明說明（） 電化學（electrical chemical deposition; ECD)製程，形成銅 接觸結搆’以填充於上述接觸孔1〇6與溝渠開口圖案1〇4 之中。 接著，請參照第四圖，藉著進行諸如化學機械研磨 製程（CMP)，來移除部份第一金屬層，直到抵達第—介電 層102上表面為止》如此，可形成導電連線結構1〇9於接觸 孔106之中，同時形成溝渠連線結構1〇8於溝渠開口圈案 104之中。然而，值得注意的是，在使用CMP製程，來移 除部份第一金屬層時，依舊會在溝渠連線結構1〇8的表 面，產生弧狀凹陷之碟盤效應（dishing effect)。並且，對 密集接觸孔106中之導電連線結構109而言，除了會產生同 樣的.碟盤效應外，亦會導致位於這些密集導電連線結構 109間之第一介電層102，蓋生侵姑現象（erosion)，從而造 成整個密集導電連線結構109區域，亦產生凹陷112。 請參照第五圖，接著沉積第二介電層U4於第一介 電層102、導電連線結構109與溝渠連線結構108之上，以 作為金屬間介電層（IMD)使用》其中，第二介電層1 14之 材料，同樣可選择氧化矽、氮化矽或其任意组合'並且， 如同第五圖中所示，此第二介電層114之上表面，亦會反 應出其上第一介電層1〇2之表面形狀（topography)。亦即， 在第二介電層114之上表面，亦會有反映出第一介電層層 102上凹陷（112與110)之凹陷區域'116。 本紙張尺度適用中國0家標準（CNS)A4規格（210 X 297公« ) (請先閲讀背面之注意事項再填寫本頁) • ---'I! — 訂·一 一 ---—--線 . 經濟部智慧財產局貝工消费合作社印製 4 經濟部智慧財產局員工消費合作社印製 5 13^3 A7 _B7 ------------------------_丨一 —--------- 五、發明說明（） 接著’可將此半導避底材100,置於__自旋轉蚀刻 機台（spin etcher) 120令之承接盤（chock) 122上，以對半導 艘底材100上之第二介電層114進行自旋轉蝕刻程序，而達 成平坦化第二介電層114之效果。其中，該承接盤in上表 面’具有數量極多，且口徑極小之喷射孔。藉著喷出高麈 気氧’可使其上之半導體底材1〇〇，半懸浮於此承接盤122 之表面*同時，固定腳124由半導«底材j 00的邊緣，抓住 (holding)此半導體底材1〇〇以進行自旋轉（spin^在半導艎 底材100進行自旋轉的同時，一喷嘴126由半導艘底材1〇〇 之上方’噴瀧包含研磨微粒（abrasive particle)之反應蝕刻 溶液（reactive etching solution) 1 2 8，以便對第二介電層 114+表面進行研磨。其令，此反應蝕刻溶液可以化學反 應之方式，對第二介電簷進行侵蝕.並且，夾雜於反應蝕 刻溶液中之研磨微粒，則由於其喷灑速度，可對第二介電 層表面進行撞擊，而連到物理研磨效果。 在一較佳實施例中，此半導《I底材100在自旋轉蝕 刻機台120中，是以約2000至8000 rpm之速率旋轉。並且， 此自旋轉蝕刻機台120之溫度，控制於約15至40 °C的環境 中。至於上述反應蝕刻溶液，則是以約0.5至4.01iter/min 的速率，喷灑於第二介電層114之上表面。值得注意的是， 上述研磨微粒是由多角形微粒（polygon particie)所構 成，且在較佳實施例中，可選擇ai2o3來構成。並且，此 本紙張尺度適用中國國家標準（CNS)A4规格（21〇 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -1K-----訂----------線 _ 451349 A7 B7 五、發明說明（） (請先閱讀背面之注意事項再填窵本頁) 研磨微粒約佔整各反應蝕刻•溶液1 2 8體積之0.1 %至5 %。如 此一來，喷遴於第二介電層114上表面之研磨微粒，除了 可在喷灑過程申，對第二介電層114表面，產生垂直方向 的研磨效果外，更可藉著半導邇底材100進行自旋轉所產 生的離心力（centrifugal force)作用，而對第二介電層114 表面，產生橫向的機械研磨效果，而達到平坦化之目的。 當所使用之第二介電層114材料，為氧化矽、氮化矽或氮 氣化矽時，上述反應蝕刻溶液可選擇約49°/。之稀釋氫氟酸 (HF)溶液。 在完成自旋轉杜刻程序（spin etching)之後，該第一 介電層Π4將具有如第七圖中所顯示極平坦之上表面。然 後，.參照第八圖，蝕刻第二介電層1 14，以形成開口 a案 130於第二介電層114之上。並且，沉積第二金屬層於此第 二介電層114表面上，並填充至開〇圖案130之中。在較佳 實施例中，此第二金眉之材料可使用上述製程，沉精銅層 來構成。接著，再回蝕刻第二金眉層，直到抵達第二介電 層114上表面為止。如此，可以形成金屬内連線結構132 於該開口圈案中，如同笫九圖所顯示。其中，在較佳賞施 例t，可使用CMP程序來移除位於第二介電層U4上表面 之第二金屬材料。 經濟部智慧財產局員工消費合作社印製 要特別說明的是在上述實施例中，雖然列舉了利用 自旋轉蝕刻機台（spin etcher)，東對第二介電層進行平坦 11 本紙張尺度適用中a國家標芈（CNS)A4規格（210 X 297公复) 451 349 Α7 Β7 五、發明説明（） 化程序之應用賞例。但對熟，悉此項技藝之人士而言，當可 輕易了解可應用此種自旋轉杜刻程序（sPin etching)於任 何膜層的平坦化程序之中。亦即，藉著使用本發明所提供 之方法，在所喷瀧的反應#刻溶液中’加入多角狀 (pdygon)研磨微粒，可藉著半導碰底材自旋轉所產生之 離心力，使此些研磨微粒沿著膜層表面，由内向外移動， 而達到橫向研磨媒層之效果。如此一來，除了使用反應蝕 刻溶液·，來對旗層進行化學反應之研磨外，更可藉著研磨 微粒噴灑於膜層表面之垂直研磨效果’以及受離心力所產 生之水平研磨效果，而使膜層之研磨效果大幅增加。 本發明具有相當多的優點。例如’在應用自旋轉蝕 刻機台與具有研磨微粒之反應钍刻溶液，於雙重鑲嵌結構 之平坦化製程時，可有效解決由於膜層不平坦，導致殘餘 金屬材料造成短路之問題*特別是使用本發明之方法，來 進行膜層之平坦化程序，遠較使用傳統CMP製程來得方便 與便宜，是以可大幅降低成本且提高產值•此外，由於本 發明之方法，可藉著調整反應飪刻溶液之濃度、研磨微粒 之比率、半導Λ底材之旋轉速度（可影赛離心力之大小） 及製程溫度，而有效的控制膜層研磨之速率與效果。是以 對曰趨精密且微細之半導«元件而言，在使用本發明方法 進行平坦化製程時，可避免使用傳统CMP製程進行機械研 磨時，容易發生的應力不均、棋層龜裂破損、元件損壞等 問題。更者，由於本發明之方法，’如同上述，可藉著控製 12 本紙張尺度適用中國國家標準（CNS)A4规格（210 * 297公；*〉 (請先閱讀背面之注意事項再填寫本頁) 訂-------!線·^· 經濟部智慧財產局員工消费合作社印製 451349 A7 五、發明說明（） 相關參數，而調整對膜層研，磨之效果，是以亦可用來進行 膜層表面之清潔程序。亦即，在沉積一膜層後，位於膜廣 上方之各種微粒，皆可藉著本發明之自旋轉蝕刻程序’而 加以移除。例如，對上述所舉實施例中之介電層而言’亦 可使用自旋轉蝕刻機台，對膜層進行極輕微的研磨，以移 除位於介電層表面上之顆粒與污染物，而達到清潔介電層 之目的。如此一來，更可有效提昇整個半導醴製程之良率 與所製作元件之可靠性。 本發明雖以一較佳實例闡明如上，抹篡衽 热兵·並非用以限 定本發明精神與發明實艘，僅止於此一訾烯也丨^ T施例爾。對熟痄 此領域技藝者，在不脫離本發明之精神斑 兴範圍内所作之铬 改，均應包含在下述之申請專利範圍内。 珍 (請先閱讀背面之注意事項再填寫本頁) ie· •線ί· 經濟部智慧財產局具工消t合作社印製 本紙張尺度適用中國a家標準（CNS)A4規格（210 X 297公爱）451349 A7 B7 Five 'Invention (up to the upper surface of the layer)' to form a second metal internal velocity line structure in the second opening pattern. Brief description of the drawings The above description and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, where: The first figure is a cross-sectional view of a semi-conductor wafer, showing the traditional process 'The step of forming a dual mosaic structure on the semiconducting sampling substrate; The second circle is a cross-sectional view of the semiconducting wafer, which shows the remaining gold layer material when the dual mosaic structure is formed on the semiconducting substrate according to the traditional process' Will cause a short circuit between conductive structures;, the third «is a cross-sectional view of a semiconductor wafer, showing the step of forming a first dielectric layer on a semiconductor substrate according to the present invention; the fourth figure is the carrying surface of a semiconducting wafer Figures, showing the steps of forming metal interconnects in the first dielectric layer according to the present invention; Figure 5 is a cross-section circle of a semiconductor wafer, showing the steps of forming a second dielectric layer on a semiconductor substrate according to the present invention The sixth figure is a configuration diagram of the spin-etching machine, showing related elements of the spin-etching machine used to planarize the second dielectric layer on the semiconductor substrate according to the present invention;圏 is a cross-sectional view of a semiconducting wafer, showing the semiconducting 逋 substrate after the flattening process according to the method of the present invention; FIG. 8 is a cross-sectional view of a semiconductor wafer, showing the size of the paper according to the present invention is applicable to the country Standard (CNS) A4 specification (210 X 297 mm) < Please read the notes on the back before filling out this page) · III --- 11 --11-. Line Manufacturing 4513 49 A7 B7 V. Description of the invention () Steps of opening the case in the second dielectric dielectric Jb; and the ninth circle is a cross-sectional view of a semiconductor wafer, showing the formation of a second dielectric interlayer metal interconnection according to the present invention Line structure steps. Detailed description of the invention: The present invention provides a new method for performing a planarization process on a film layer in a semi-conductor craft. By putting this semiconducting substrate on a spin-etching machine, and spraying the etching reaction solution containing abrasive particles on the surface of the semiconducting substrate during self-rotation, The surface of the film layer can be effectively polished to achieve a flattening effect. The detailed description of the present invention is described below. First, in a preferred embodiment, as shown in the third figure, a single crystal silicon with a crystal orientation of < 100 > is provided as the semiconductor substrate 100. Generally speaking, other types of semiconductor materials, such as gauium arsenide, germanium, or silicon on insulator (SOI), can be used as the semiconductor substrate. In addition, 'the properties of the surface of the semiconducting hafnium substrate do not have a special influence on the present invention', depending on the crystal orientation, it is also possible to select < 11〇 > or < 111>. Next, a first dielectric layer 102 is formed on the semiconductor substrate Mi 00 as a metal interlayer dielectric layer (IMD). It should be particularly noted here that before the formation of the dielectric layer 102, the surface of the semiconducting ft substrate 100 can be shaped in accordance with the paper standards applicable to the Chinese Standard (CNS) A4 < 210 X 297. &> (Please read the notes on the back before filling this page) --- 1 ----- Order ------- I-line. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 451349 Λ7 B7 V. Description of the invention () Various active components, passive components, peripheral circuits, etc. required for integrated circuits. That is, on the surface of the semi-conductor substrate 100, there are already various functional layers and material layers required. In a preferred embodiment, the material of the first dielectric layer 102 can be selected from silicon oxide and silicon nitride. Or any combination thereof. The first dielectric layer 102 may be silicon dioxide formed using a chemical vapor deposition method. The chemical vapor deposition method is based on ethyl orthosilicate (TE0S) at a temperature of 600 to 800 ° C and It is formed at a pressure of about 0 "to 10torr. Alternatively, it can be at about 400 to 45 °. Silicon nitride is formed in the furnace of C as the first dielectric layer 102, and the reaction gases in the process are siH4, N20, and NH3. Then, the first dielectric layer 102 is etched to form a plurality of dense contact holes 106 and trench opening patterns 104 thereon. Generally speaking, this etching process can be performed using an anisotropic plasma etching technique, such as reactive ion etching (RIE). And when the first dielectric layer 102 is a silicon oxide layer, an etchant cci2f2, chf3 / cf4, chf3 / 〇2, ch3chfi 'cf4 / os can be used; as for the silicon dielectric used as the first dielectric layer 102, CF4 / H2, CHF 3 or CH3CHF2 can be used as an etchant. Subsequently, a first metal layer may be deposited on the surface of the first dielectric layer 102 and filled into the dense contact holes 106 and the trench opening patterns 104. In a preferred lean embodiment, a physical oxygen vapor deposition (PVD) method can be used to first form a thin copper atomic layer on the surface of the first dielectric layer 102 as a Cu seeding Floor. Then, use 8 paper standards to apply the Chinese Standard AA (CNS) A4 specification (210 X 297 male "". (Please read the precautions on the back before filling this page) I l · --i II ---- I ---- ^. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 451349 Α7 Β7 V. Description of the invention () Electrochemical chemical deposition (ECD) process to form a copper contact structure 'to fill the above contact hole 1〇 6 and trench opening pattern 104. Next, referring to the fourth figure, a part of the first metal layer is removed by performing a chemical mechanical polishing process (CMP) until it reaches the upper surface of the first dielectric layer 102. Thus, a conductive connection structure can be formed. 109 is formed in the contact hole 106, and a trench connection structure 108 is formed in the trench opening circle 104 at the same time. However, it is worth noting that when using the CMP process to remove part of the first metal layer, the dishing effect of arc-shaped depressions will still be produced on the surface of the trench connection structure 108. In addition, for the conductive connection structures 109 in the dense contact holes 106, in addition to the same disk effect, the first dielectric layer 102 located between these dense conductive connection structures 109 is also covered. The erosion phenomenon causes the entire densely conductive connection structure 109 region and also generates a depression 112. Please refer to the fifth figure, and then deposit a second dielectric layer U4 on the first dielectric layer 102, the conductive connection structure 109, and the trench connection structure 108 for use as an intermetal dielectric layer (IMD). Among them, The material of the second dielectric layer 114 can also be selected from silicon oxide, silicon nitride, or any combination thereof ', and, as shown in the fifth figure, the upper surface of the second dielectric layer 114 will also reflect The topography of the first dielectric layer 102 thereon. That is, on the upper surface of the second dielectric layer 114, there will be a recessed area '116 reflecting the recesses (112 and 110) on the first dielectric layer layer 102. This paper size applies to 0 Chinese Standards (CNS) A4 specifications (210 X 297 male «) (Please read the precautions on the back before filling out this page) • --- 'I! — Order · One One ---—- -Line. Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 13 ^ 3 A7 _B7 ------------------- -----_ 丨 A —--------- 5. Description of the invention () Then 'this semiconductor can be avoided from the substrate 100 and placed in the __spin etcher spin etcher 120 It is made to receive a choke 122 to perform a spin-etching process on the second dielectric layer 114 on the semi-conductor substrate 100 to achieve the effect of planarizing the second dielectric layer 114. Among them, the upper surface ′ of the receiving plate in has a large number of injection holes with extremely small diameters. By spraying high oxygen, the semiconductor substrate 100 on it can be semi-suspended on the surface of the receiving plate 122 * At the same time, the fixed foot 124 is grasped by the edge of the semi-conductive «substrate j 00 ( holding) this semiconductor substrate 100 for spin (spin ^ while the semiconductor substrate 100 is spinning, a nozzle 126 is sprayed from above the semiconductor substrate 100 to contain abrasive particles ( abrasive particle) reactive etching solution 1 2 8 in order to polish the surface of the second dielectric layer 114+. This allows the reactive etching solution to erode the second dielectric eaves by chemical reaction In addition, the abrasive particles contained in the reactive etching solution can impact the surface of the second dielectric layer due to its spraying speed, which is connected to the physical abrasive effect. In a preferred embodiment, this semiconductor " The I substrate 100 is rotated in the spin etching machine 120 at a rate of about 2000 to 8000 rpm. Moreover, the temperature of the spin etching machine 120 is controlled in an environment of about 15 to 40 ° C. As for the above The reactive etching solution is about 0.5 to 4.01. The rate of iter / min is sprayed on the upper surface of the second dielectric layer 114. It is worth noting that the above-mentioned abrasive particles are composed of polygonal particles, and in a preferred embodiment, ai2o3 can be selected. In addition, this paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) (Please read the precautions on the back before filling this page) -1K ----- Order --- ------- Line_ 451349 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) The abrasive particles account for about 0.1% of the total volume of each reactive etching solution. In this way, the abrasive particles sprayed on the upper surface of the second dielectric layer 114 can be applied in the spraying process to produce a vertical abrasive effect on the surface of the second dielectric layer 114. The centrifugal force generated by the self-rotation of the semiconducting holmium substrate 100 causes a lateral mechanical grinding effect on the surface of the second dielectric layer 114 to achieve the purpose of flattening. When the second used When the material of the dielectric layer 114 is silicon oxide, silicon nitride or silicon nitride, The reactive etching solution can be selected from a diluted hydrofluoric acid (HF) solution at about 49 °. After the spin etching process is completed, the first dielectric layer Π4 will have a thickness as shown in the seventh figure. The upper surface is extremely flat. Then, referring to the eighth figure, the second dielectric layer 114 is etched to form an opening 130 on the second dielectric layer 114. Further, a second metal layer is deposited on the second dielectric layer 114. The dielectric layer 114 is filled on the surface of the dielectric layer 114 and filled in the open pattern 130. In a preferred embodiment, the material of the second gold eyebrow can be formed by using the above-mentioned process and a fine copper layer. Then, the second gold eyebrow layer is etched back until it reaches the upper surface of the second dielectric layer 114. In this way, a metal interconnect structure 132 can be formed in the opening circle, as shown in Figure 29. Among them, in the preferred embodiment t, a CMP process can be used to remove the second metal material on the upper surface of the second dielectric layer U4. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the above-mentioned embodiment, although the use of a spin etcher is listed, the second dielectric layer is flattened. 11 a National Standard (CNS) A4 specification (210 X 297 public reply) 451 349 Α7 Β7 V. Examples of application of the invention description () program. However, for those who are familiar with this technology, it is easy to understand that this spin etching process (sPin etching) can be applied to any film planarization process. That is, by using the method provided by the present invention, adding polypyridine abrasive particles to the sprayed reaction solution, the centrifugal force generated by the self-rotation of the substrate can be used to make this These abrasive particles move along the surface of the film layer from the inside to the outside to achieve the effect of laterally grinding the medium layer. In this way, in addition to using a reactive etching solution to chemically polish the flag layer, it is also possible to use the vertical grinding effect of abrasive particles sprayed on the surface of the film layer and the horizontal grinding effect generated by centrifugal force, so that The polishing effect of the film layer is greatly increased. The invention has considerable advantages. For example, 'In the application of a self-rotating etching machine and a reaction etching solution with abrasive particles, in the planarization process of a dual damascene structure, it can effectively solve the problem of short circuits caused by residual metal materials due to uneven film layers. The method of the present invention is used to perform the planarization process of the film layer, which is much more convenient and cheaper than using the traditional CMP process, which can greatly reduce the cost and increase the output value. In addition, the method of the present invention can adjust the reaction time The concentration of the solution, the ratio of the abrasive particles, the rotation speed of the semiconducting Λ substrate (the amount of centrifugal force that can be played), and the process temperature can effectively control the rate and effect of film grinding. For the semi-conductor «components which are becoming more precise and finer, when using the method of the present invention for the planarization process, the stress unevenness and cracking of the chess layer that are easy to occur when using the traditional CMP process for mechanical polishing can be avoided. , Component damage, etc. Furthermore, due to the method of the present invention, 'as mentioned above, 12 paper sizes can be controlled by the Chinese National Standard (CNS) A4 specification (210 * 297); *> (Please read the precautions on the back before filling this page ) Order -------! Line · ^ · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 451349 A7 V. Description of the invention () Relevant parameters, and adjust the effect of film research and grinding, so it can also be used To clean the surface of the film layer. That is, after depositing a film layer, all kinds of particles located above the film can be removed by the self-rotating etching process of the present invention. For example, the above-mentioned As for the dielectric layer in the embodiment, a self-rotating etching machine can also be used to grind the film layer very slightly to remove particles and contaminants on the surface of the dielectric layer, thereby achieving a clean dielectric layer. Purpose. In this way, the yield of the entire semiconductor manufacturing process and the reliability of the components can be effectively improved. Although the present invention is explained above with a preferred example, it is not intended to limit the spirit of the present invention. And the invention of real ships, only This pinene is also an example. For those skilled in the art, the chromium modifications made within the scope of the spirit of the present invention should be included in the scope of patent applications described below. (Please read the notes on the back before filling in this page) ie · • Line ί · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives This paper is printed in accordance with the Chinese Standard (CNS) A4 (210 X 297 Public Love)