4 348 3 2 A7 B7 五、發明說明（） 5 - 1發明領域： 本發明與一種製作半導體元件有關，特別是有關於一 種製作互補金屬氧化物半導體場效電晶體之方法。 5-2發明背景： 金屬氧化物半導體場效電晶體（MOSFETs)，已經廣泛的 應用於半導艘領域。於深次微米（sub-micron)高功能之金 屬氧化物半導體超大型積體電路（ULSI)的應用方面，如引 文” B. Davari，IEDMTech· Dig.，p.555,1 996·” 所建議， 雙複晶矽閘極互補金氧半場效電晶體（CMOS)技術是必須 的。但是如引文’’Y. Taur，et al.，in IEDM Tech. Dig.， p. 901，1 992/所提，硼離子穿透過閘極氧化層進入石夕基 板中之效應將會將降低元件功能。對於如何抑制删離子穿 透問題，有幾種方式已經被提出，例如，（1)利用對閘 極氧化層做氮化處理，此方法已見於引文UE. Hasegawa，et al.，in IEDM Tech. Dig.，p327, 1995. ”，（2)以高劑量之 氮離子植入（劑量015cnr2)，將氮離子植入複晶;6夕中， 經濟部智慧財產局員工消費合作社印製 如引文"Shimizu, et al·， in IEM Tech. Dig.， p67, 1994.中所建義’以及（3)以堆叠非結晶破層（stacked- in IEDM Tech. Dig.，p329，1 993·，’所建議。 雖然以高劑量之氮離子植入複晶·ε夕中可有效抑制棚 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 — 五、發明說明（） 離子穿透玫應’但是無論是Π+或P +摻雜之複晶矽閘極其阻 值會隨著植入氮離子劑量增加而變大，尤其當劑量高於 4MOl5Cm-2 時。此一結果已經於引文，，S: shimizu，et al.， J. Appl. Phys‘，V〇I，P.802，1 996.”_示0 5-3發明目的及概述： 本發明之目的為在提供一種製作無硼離子穿透效應之 互補金屬氧化物半導體場效電晶體之製作方法。 本發明之目的為在提供一種製作無领離子穿透效應， 且不會產生額外副作用之互補金屬氧化物半導體場效電晶 體之製作方法。 本發明揭露了一種方法用以製作互補金屬氧化物夺導 體場效電晶體，而其閘極結構中具有多個擴散阻障層，用 以抑止閛極中的觸離子穿入閘極氧化廣與基板尹。 首先形成一層閘極氧化層於半導體基板之上。之後依 序沈積第一半導體矽層、第二半導體矽層，與第三半導體 矽層，並於形成第二半導體矽層的同時，摻入Ν型雜質於 其令。接著蝕刻並圖案化此堆疊之半導體矽層以形成閉極 結構’之後再透過離子植入的程序而形成具有輕掺雜區域 之源/汲極。最後，進行熱處理以形成汲/源極區域之淺接 面’以完成整個CMOS電晶體的製作。而於此同時，原先摻 入第二半導體矽層之N型雜質將會受到高溫的作用，而擴 4 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐〉 請 先 閱 讀， 背 面 之β 注 意 經濟部智慧財產局員工消費合作社印製4 348 3 2 A7 B7 V. Description of the invention () 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a complementary metal oxide semiconductor field effect transistor. 5-2 Background of the Invention: Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used in the field of semiconductors. For the application of deep sub-micron high-function metal oxide semiconductor ultra-large integrated circuits (ULSI), as suggested by the quote "B. Davari, IEDMTech · Dig., P.555,1 996 ·" CMOS technology is a must for dual multiplexed silicon gates. However, as mentioned in the citation `` Y. Taur, et al., In IEDM Tech. Dig., P. 901, 1 992 /, the effect of boron ions penetrating through the gate oxide layer into the Shixi substrate will reduce the component Features. Several methods have been proposed for how to suppress the penetration of deleted ions, for example, (1) the use of nitriding the gate oxide layer, this method has been found in the citation UE. Hasegawa, et al., In IEDM Tech. Dig., P327, 1995. "(2) Nitrogen ions were implanted at high doses (dose 015cnr2), and nitrogen ions were implanted into the polycrystal; on the 6th, the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed such a quotation & quot Shimizu, et al., In IEM Tech. Dig., P67, 1994. and '3. Stacked-in IEDM Tech. Dig., P329, 1 993 ·,' Suggestion: Although implanting compound crystals with high doses of nitrogen ions can effectively inhibit the shed 3 This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) A7 B7 — V. Description of the invention ( ) Ion penetration through the 'residue' but the extreme resistance of either Π + or P + -doped complex crystalline silicon gates will increase as the implanted nitrogen ion dose increases, especially when the dose is higher than 4MOl5Cm-2. The results have been quoted, S: shimizu, et al., J. Appl. Phys', VOI, P.802, 1 996. "_ Shows 0 5-3 Purpose and Summary of the Invention: The purpose of the present invention is to provide a method for manufacturing a complementary metal oxide semiconductor field effect transistor without boron ion penetration effect. The object of the present invention is to provide a method for manufacturing a collarless ion transistor. Method for manufacturing complementary metal oxide semiconductor field effect transistor without transmitting side effect and without generating additional side effects. The invention discloses a method for manufacturing a complementary metal oxide semiconductor field effect transistor, and the gate structure of the complementary metal oxide semiconductor field effect transistor has Multiple diffusion barrier layers are used to prevent the contact ions in the cathode from penetrating the gate oxide and the substrate. First, a gate oxide layer is formed on the semiconductor substrate. Then, a first semiconductor silicon layer, a first The second semiconductor silicon layer and the third semiconductor silicon layer are doped with N-type impurities while forming the second semiconductor silicon layer. Then the stacked semiconductor silicon layer is etched and patterned to form a closed-pole structure. The source / drain with lightly doped regions is formed through an ion implantation process. Finally, heat treatment is performed to form a shallow junction of the drain / source regions. Complete the production of the entire CMOS transistor. At the same time, the N-type impurity originally doped in the second semiconductor silicon layer will be affected by the high temperature, and the paper size is extended to the Chinese national standard (CNS > A4 specification (210 X 297 mm> Please read first, the back β Note printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 散至堆疊半導體矽層的界面之中形成擴散阻障層，以抑止 硼離子穿透效應的發生。 綜上所述本發明可以提供下列優點：（I )元件之可靠 度可透過雙複晶矽閘極CMOS技術而改善；（2 )對於具p + 播雜複晶梦閘極PM0SFET之棚離子穿透效應可以被完全 抑制；C 3)摻雜高劑量氮離子所產生升高閘極阻值的副作 用亦可加以避免。 5-4圖式簡單說明： 第一圖 為本發明中於半導體基板上形成閘極氧化層 之結構剖面示意圖。 第二圖 為本發明中於半導體基板上形成堆叠第—半 導體梦層、第二半導體石夕層，與第三半導體 矽層之結構剖面示意圖。 第三圖 為本發明中形成閘極結構，以及源/汲極之輕 摻雜區域的結構剖面示意圖。 第四圖 為本發明中形成間隙壁與源/汲極結構之剖 面示意圖。 第五圖 為本發明中對半導體結構施以熱處理以形成 淺接面之結構剖面示意圖》 5-5發明詳細說明： 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先間讀背面之注意事項每填寫本頁) I - - ------» 1-----I 1 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 本發明揭露了一種製作互補金屬氧化物半導體場效電 晶體（CMOSFET)的方法，而其中的閘極結構係由多層堆整的 半導體矽層所組成，而這些堆疊半導體矽層的界面之間堆 積有N型的雜質，因此可以防止硼離子穿透效應的產生。 而為了更请楚的介紹本發明之精神，以下將以一個具體實 施例加以說明。 參閱第一圖’在此較佳實施例中，首先提供—具有 <100>結晶方向之單結晶矽基板2，並於其上形成場氧化區 域（FOX) 4以定義出主動區域（Active Area)。以目前 業界的技術而言’場氧化區域4亦可以替換成淺溝渠 (Shallow Trench)以達成隔絕基板2上之主動區域的目 的。在此較佳實施例中’場氧化區域4可以利用習知技藝 而形成。首先依序於基板2上形成墊氧化層與氮化矽層（圖 中未顯示）’再經過微影製程蝕刻並圖案化此墊氧化層與 氮化矽層’以作為形成場氡化區域4之氧化幕罩。接著將 基板2置於含氧的環境中進行熱氧化製程（〇xidati〇n) ’ 而於基板2的表面上成長出厚度約為3〇〇〇〜8〇〇〇Λ的場氡 化區域4»隨後，為了製作互補金屬氧化物半導體場效電 晶體，於場氧化區域4形成後，再以習知的方式（如離子植 入法、擴散法）於基板2中形成雙井結構，而形成如圖中所 示之Ρ井12以及Ν井16。 請仍參閱第一圖，當場氧化區域4'ρ井12，以及Ν 井1 6形成之後，再將此氮化矽層與墊氧化層剝除並清洗基 板2的表面。接著，將基板2安置於溫度約7〇〇〜11〇〇〇c的 -----·------裝--------訂--------- rtll先閱讀背面之注意事項系填寫本頁) 4 3 4 8 3 2A7 B7 V. Description of the Invention (The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the diffusion barrier layer printed on the interface of the stacked semiconductor silicon layer to suppress the occurrence of boron ion penetration effect. In summary, the present invention can Provide the following advantages: (I) the reliability of the device can be improved by the dual-multi-crystal silicon gate CMOS technology; (2) the ion penetration effect of the PM0SFET with p + doped poly-crystal dream gate can be completely suppressed; C 3) The side effect of increasing the gate resistance caused by doping high-dose nitrogen ions can also be avoided. Figure 5-4 is a brief description: The first figure is a schematic cross-sectional view of a structure for forming a gate oxide layer on a semiconductor substrate in the present invention. The second figure is a schematic cross-sectional view of a structure in which a stacked first-semiconductor dream layer, a second semiconductor stone layer, and a third semiconductor silicon layer are formed on a semiconductor substrate in the present invention. The third figure is a schematic cross-sectional view of a structure for forming a gate structure and a lightly doped region of a source / drain in the present invention. The fourth figure is a schematic cross-sectional view of forming a spacer and a source / drain structure in the present invention. The fifth figure is a schematic structural cross-sectional view of a semiconductor structure subjected to heat treatment to form a shallow junction in the present invention. 5-5 Detailed description of the invention: This paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ( Please read the notes on the back first (please fill in this page first) I-------- »1 ----- I 1 A7 B7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A method for manufacturing complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) is disclosed, in which the gate structure is composed of a plurality of stacked semiconductor silicon layers, and N is deposited between the interfaces of the stacked semiconductor silicon layers. Type impurities, which can prevent the generation of boron ion penetration effect. In order to introduce the spirit of the present invention more clearly, a specific embodiment will be described below. Refer to the first figure 'In this preferred embodiment, First provided-a single crystalline silicon substrate 2 with < 100 > crystal orientation, and a field oxide region (FOX) 4 is formed thereon to define an active area. According to the current industry technology, 'field oxidation' The domain 4 can also be replaced with a shallow trench to achieve the purpose of isolating the active region on the substrate 2. In this preferred embodiment, the 'field oxidation region 4 can be formed by using known techniques. First, it is sequentially on the substrate 2 A pad oxide layer and a silicon nitride layer (not shown in the figure) are formed thereon, and then the pad oxide layer and the silicon nitride layer are etched and patterned through a lithography process to serve as an oxide curtain for forming the field-fluorinated region 4. Then, The substrate 2 is placed in an oxygen-containing environment to perform a thermal oxidation process (〇xidati〇n) ′ and a field-forming region 4 having a thickness of about 3000-8000 is grown on the surface of the substrate 2 » Subsequently, in order to produce a complementary metal oxide semiconductor field effect transistor, after the field oxide region 4 is formed, a double-well structure is formed in the substrate 2 in a conventional manner (such as an ion implantation method and a diffusion method), and formed as The P well 12 and the N well 16 shown in the figure. Please refer to the first figure again. After the on-site oxidation zone 4′ρ well 12 and the N well 16 are formed, the silicon nitride layer and the pad oxide layer are stripped off. And clean the surface of the substrate 2. Next, the substrate 2 is set at a temperature 〇〇 ～ １〇〇〇c ----- · ------ install -------- order --------- rtll first read the notes on the back to fill in (This page) 4 3 4 8 3 2
經濟部智慧財產局員工消費合作社印製 五、發明說明（） a氧的環境之中進行氡化，以於基板2的表面形成一層厚 度約介於1 5〜250A之間的二氧化矽層以作為閘極氧化層 18使用。附帶一提的是，上述之製程僅為目前常用的一種 方法，然而，諸如化學氣相沈積製程（CVD)亦可應用於軋 化層之製作。 參閲第二圖，依序於基板2表面形成第一半導體矽層 20a‘、第二半導體矽層2〇b‘，與第三半導體矽層2〇c‘，以 形成堆疊半導體矽層20而作為閘極中的導電層，其中各層 半導體矽層的厚度約在200〜1 000A之間。在此較佳實施例 中，首先利用化學氣相沈積製程將基板2置於45〇〜620 t 的環境中，並通入SiH4作為反應物以形成第一半導體矽層 20a 。接著於同一個反應室（chamber )中於相同的溫度範 圍與反應物的條件下，繼續沈積第二半導體矽層2〇b‘於第 一半導體矽層20a ‘的表面。而於此同時，再於反應室中通 入含有N型雜質的氣體，以同步（insitu)將這些N型雜 質摻入第二半導體矽層20b‘之中。最後再利用與沈積第一 半導體矽層20a‘相同的的製程條件沈積第三半導體矽層 20c‘’以形成堆疊半導體矽層20。由於第二半導體矽層 20b ‘之中的N型雜質將會於後續的熱製程中擴散至第一半 導體矽層20 a‘與第二半導體矽層20b‘之界面中，以及第二 半體矽層20b‘與第三半導體矽層20c‘之界面中，而形成擴 散阻障層（Diffusion Barrier)。因此位於CMOS電晶體 之閘極結構中的摻雜硼離子，將會受到這些擴散阻障層的 抑止，而不會穿入閘極氧化層或基板之中。 本紙張尺度適用令國國家標準（CNS)A4規格（210 x297公釐） (請先間讀背面之江意事項一^:填寫本頁) 厂•裝 ----訂·----I-- 434832 A7 五、發明說明（ 在此較佳實施例甲，所摻雜的N型雜質可以是磷或砷’ 而摻雜的環境則約在之間至於所沈積 的半導體砂層亦不限於複晶石夕或非結晶石夕。此外，所形成 的堆叠半導體石夕層20亦*限於三層，而超過三層的堆叠可 以參照本發明之精神，以相間隔的方式於堆疊層中摻N型 雜質，以形成擴散阻障層而抑制硼離子穿透效應。 接著參閱第三圖，回蝕堆叠半導體矽層2〇，以於1>井 12與N井16的上方分別形成閘椏結構2〇a與2〇b。再使 用一第一光阻層覆蓋於付井16的上方，並進行輕微離子 摻雜的程序，以於！>井12之中形成輕微摻雜源/汲極區域 2 2a。此一較佳實施例中，植入的雜質可以是磷、砷，或 麟/砰’其劑量則大約在1〇12〜l〇HCm-2之間，而能量則約 在5〜120KeV之間。當輕微摻雜源/汲極區域22a形成之 後，接著除去此第一光阻層。再於p井12的上方覆蓋一 第一光阻層作為離子植入時的幕罩，並以相似的步驟於N 井12中形成輕微穆雜源/汲極區域22b»其中植入雜質 如，硼、氟化硼之劑量約在10"〜1〇 "cm-2之間，而植入 能量則約在5〜1 2 0 KeV之間。當輕微摻雜源/汲極區域2 2b 形成之後’再接著除去此第二光阻層。 請繼續參閒第四圖，沈積一介電層2 4於堆疊非結晶 矽閘極20a、20b、場氧化區域4，與閘極氧化層18之上。 在此較佳實施例中，此介電層係以化學氣相沈積方式形 成。接著’施以一非等向性蚀刻於介電層24，以形成間 隙壁2 4於閘極結構2 0 a、2 0 b之側壁。間隙壁2 4形成之 本紙張尺度適用甲國國家標準<CNS)A4規格（21〇 x 297公釐） ----------IW 裝 - (請先閱讀背面之注意事味卑填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 A7 B7__ 五、發明說明（） 後，施以源/汲/閘極離子植入，利用覆蓋於N井上的第三 光阻層為幕罩，將離子植入位於P井1 2上之堆疊非結晶 矽閘極2 0 a中，以及P井1 2内以形成源汲與汲極結構 2 6 a，並隨後將第三光阻層去除。其中，植入的雜質可以 是磷、砷，或磷/砷，其劑量則大約在1 〇 14〜1 〇 16 cnT2之 間，而能量則約在0 · 5〜8 0 K e V之間。再以類似的製程， 以覆蓋於P井12上的第四光阻為幕罩，將離子植入位於 N井1 6上之堆疊非結晶矽閘極2Ob中，以及N井1 6内以 形成源汲與汲極結構2 6 b，並隨後將第四光阻層去除。相 類似的，其中，植入的雜質可以是硼或氟化硼，其劑量則 大約在10“〜10iecnT2之間，而能量則約在〇. 5〜80KeV之 間。 最後參閱第五圖，施以一高溫熱處理製程分別形成淺 接面26a與2 6b於P井12與N井1 6之中。在此較佳實施 例中，此高溫熱處理製程之溫度大約介於7 0 0〜I 0 5 0 °C之 間並持續約0 . 1〜6 0分鐘。若閘極結構2 0 a與2 0 b由非結 晶矽層堆疊而成，在此過程中將轉換成複晶矽結晶相，以 作為互補式金屬氧化物半導體場效電晶體之閘極使用。而 於此同時，原先摻入第二半導體矽層20b‘之N型雜質， 亦會擴散至閘極之半導體矽層的界面中而形成擴散阻障 層，以抑止硼離子穿透效應的發生。如圖中所示，一具有 雙複晶矽閘極之互補式金屬氧化物半導體場效電晶體於 焉形成，其中D +複晶矽係作為PM0SFET之閘極，而n +複 晶矽係則作為NM0SFET之閘極。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ' I --- (請先閱讀背面之注意事韋填寫本頁) 訂- 434832 A7 ______B7_五、發明說明（） 值得一提的是，在此較佳實施例中，互補式金屬氧化 物半導體場效電晶體之閘極結構中，具有多個分佈於堆疊 半導體矽層界面的擴散阻障層。因此將可以有效的抑止硼 離子穿透效應的發生，並進而提高閘極的可靠度。此外， 若閘極由堆疊非結晶矽層經高溫轉換而成多晶矽層，將可 使得閘極具有更佳的晶相而提供更低的閘極阻值。更有甚 者，本發明避免使用氮離子植入以抑止硼離子穿透效應， 因此將不會有因過高的氮離子劑量而造成閘極阻值上升 的問題。 綜上所述本發明可以提供下列優點：（1 )元件之可靠 度可透過雙複晶矽閘極CMOS技術而改善；（2)對於具P + 摻雜複晶矽閘極PM0SFET之硼離子穿透效應可以被完全 抑制；（3 )摻雜高劑量氮離子所產生升高閘極阻值的副作 用亦可加以避免。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可做些許更動潤飾及等同之變化替換’其專利 保護範圍當視後附之專利申請範圍及其等同領域而定° 請 先 閱 讀’ 背 © 之. 注 意. 事Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (a) a silicon dioxide is formed in the oxygen environment to form a silicon dioxide layer with a thickness of about 15 to 250A on the surface of the substrate 2. Used as the gate oxide layer 18. Incidentally, the above process is only a commonly used method at present, however, such as a chemical vapor deposition process (CVD) can also be applied to the production of rolled layers. Referring to the second figure, a first semiconductor silicon layer 20a ′, a second semiconductor silicon layer 20b ′, and a third semiconductor silicon layer 20c ′ are sequentially formed on the surface of the substrate 2 to form a stacked semiconductor silicon layer 20 and As the conductive layer in the gate, the thickness of each semiconductor silicon layer is between 200 ~ 1000A. In this preferred embodiment, the substrate 2 is first placed in an environment of 45-620 t using a chemical vapor deposition process, and SiH4 is passed as a reactant to form a first semiconductor silicon layer 20a. Then, the second semiconductor silicon layer 20b 'is continuously deposited on the surface of the first semiconductor silicon layer 20a' under the same temperature range and the conditions of the reactants in the same chamber. At the same time, a gas containing N-type impurities is introduced into the reaction chamber to insitu these N-type impurities into the second semiconductor silicon layer 20b '. Finally, a third semiconductor silicon layer 20c 'is deposited using the same process conditions as those used to deposit the first semiconductor silicon layer 20a' to form a stacked semiconductor silicon layer 20. Because the N-type impurity in the second semiconductor silicon layer 20b 'will diffuse into the interface between the first semiconductor silicon layer 20a' and the second semiconductor silicon layer 20b 'in the subsequent thermal process, and the second half of silicon A diffusion barrier layer (Diffusion Barrier) is formed in the interface between the layer 20b 'and the third semiconductor silicon layer 20c'. Therefore, the doped boron ions located in the gate structure of the CMOS transistor will be suppressed by these diffusion barrier layers, and will not penetrate into the gate oxide layer or the substrate. This paper size is applicable to the national standard (CNS) A4 specification (210 x 297 mm) (please read the Jiang Yi matters on the back first ^: Fill in this page) -434832 A7 V. Description of the invention (in this preferred embodiment A, the doped N-type impurity may be phosphorus or arsenic, and the doped environment is between about as much as that of the deposited semiconductor sand layer. Crystal stone or amorphous stone. In addition, the stacked semiconductor stone layer 20 is also limited to three layers, and stacks with more than three layers can refer to the spirit of the present invention and doped N in the stacked layers in a spaced manner. Type impurities to form a diffusion barrier layer to suppress the penetration of boron ions. Next, referring to the third figure, the stacked semiconductor silicon layer 20 is etched back to form gate structures 2 above the wells 12 and N, respectively. 〇a and 〇b. A first photoresist layer is used to cover the top of the well 16 and a procedure of light ion doping is performed to form a lightly doped source / drain region in the well 12! 2 2a. In this preferred embodiment, the implanted impurities may be phosphorus, arsenic, or lin / bang. The dosage is about 1012 ~ 10HCm-2, and the energy is about 5 ~ 120KeV. After the lightly doped source / drain region 22a is formed, this first photoresist layer is then removed. Then in p-well 12 A first photoresist layer is used as a cover for ion implantation, and a slightly heterogeneous source / drain region 22b is formed in the N well 12 in a similar procedure. Impurities such as boron and boron fluoride are implanted therein. The dosage is about 10 " ~ 10 " cm-2, and the implantation energy is about 5 ~ 120 KeV. When the lightly doped source / drain region 2 2b is formed, it is then removed. This second photoresist layer. Please continue to refer to the fourth figure, and deposit a dielectric layer 24 on the stacked amorphous silicon gates 20a, 20b, the field oxide region 4, and the gate oxide layer 18. In a preferred embodiment, the dielectric layer is formed by a chemical vapor deposition method. Then, an anisotropic etching is applied to the dielectric layer 24 to form a spacer 24 and a gate structure 2 0 a, 2 0 The side wall of b. The size of the paper formed by the partition wall 24 is applicable to the national standard A < CNS) A4 specification (21 × 297 mm) ---------- IW installed-(Please read the back first Of Please fill in this page.) Order · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumers ’Cooperatives of the Ministry of Economics and Intellectual Property Bureau printed by A7 B7__ 5. After the description of the invention (), the source / drain / gate ion implant The third photoresist layer covering the N well is used as a curtain, and ions are implanted into the stacked amorphous silicon gate 20 a located on the P well 12 and inside the P well 12 to form a source drain and The drain structure 26a, and then the third photoresist layer is removed. Among them, the implanted impurities may be phosphorus, arsenic, or phosphorus / arsenic, the dosage of which is between about 1014 ~ 1016 cnT2, and the energy is between about 0.5 · 8 ~ 80 KeV. In a similar process, the fourth photoresist covering the P well 12 is used as a mask, and ions are implanted into the stacked amorphous silicon gate 2Ob located on the N well 16 and the N well 16 is formed to form The source and drain structures 2 6 b are then removed, and then the fourth photoresist layer is removed. Similarly, the implanted impurity may be boron or boron fluoride, the dose of which is about 10 "~ 10iecnT2, and the energy is about 0.5 ~ 80KeV. Finally, referring to the fifth figure, Shi A high-temperature heat treatment process is used to form the shallow junctions 26a and 26b in the P wells 12 and N wells 16. In this preferred embodiment, the temperature of the high-temperature heat treatment process is about 7 0 ~ I 0 5 0 ° C and last for about 0.1 to 60 minutes. If the gate structure 20 a and 20 b are formed by stacking amorphous silicon layers, it will be converted into a crystalline phase of polycrystalline silicon in the process. Used as the gate of a complementary metal oxide semiconductor field effect transistor. At the same time, the N-type impurity originally doped into the second semiconductor silicon layer 20b 'will also diffuse into the interface of the semiconductor silicon layer of the gate. A diffusion barrier layer is formed to prevent the occurrence of the boron ion penetration effect. As shown in the figure, a complementary metal oxide semiconductor field effect transistor with a double complex silicon gate is formed on thorium, where D + complex The silicon system is used as the gate of PM0SFET, and the n + complex silicon system is used as the gate of NM0SFET. Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 'I --- (Please read the notice on the back and fill in this page) Order-434832 A7 ______B7_V. Description of the invention () Worth mentioning What is more, in this preferred embodiment, the gate structure of the complementary metal oxide semiconductor field effect transistor has a plurality of diffusion barrier layers distributed at the interface of the stacked semiconductor silicon layer. Therefore, boron can be effectively suppressed The ion penetration effect occurs, which further improves the reliability of the gate. In addition, if the gate is converted from a stacked amorphous silicon layer to a polycrystalline silicon layer at high temperature, the gate will have a better crystalline phase and provide lower In addition, the present invention avoids the use of nitrogen ion implantation to suppress the effect of boron ion penetration, so there will be no problem of an increase in the gate resistance value due to an excessively high nitrogen ion dose. The invention described above can provide the following advantages: (1) the reliability of the device can be improved by the dual-multi-crystal silicon gate CMOS technology; (2) the boron ion penetration of the PMOS transistor with P + doped poly-crystal silicon gate Effects can be completely suppressed (3) The side effect of increasing the gate resistance value caused by doping high-dose nitrogen ions can also be avoided. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, and is not intended to be limited. The spirit of the present invention, and those skilled in the art who understand the spirit of the present invention, without departing from the spirit of the present invention, can make a few changes and retouching and equivalent changes to replace the scope of its patent protection. The scope of a patent application and its equivalent are dependent ° Please read 'Back ©' Note. Attention.
賣 裝 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Sale Binding Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)