經濟部智慧財產局員工消费合作社印製 --463396 R7 --— -________ 五、發明說明（1 ) (發明之所屬技術領域） 本發明係關於一種半導體裝曹，m Λ 守菔衮置其可使用來作爲從浪涌 電壓保護内部電路之保護電路。 (習知之技術） 自以往，爲保護構成内部電路之例如M0S電晶體的問極 ，在内部電路所連接之輸入電路或輸出入電路，設有由電 阻、偶極體或電晶體等所構成之保護電路a 以下’有關習知之保護電路的一例，H暗圖7 —面 進行説明。 如圖7所示般，在p型半導體基板丨上，以互相間隔形成 一朝紙面垂直方向延伸之第1的11型高濃度擴散層2及第2 的η型高濃度擴散層3。第1及第2in型高濃度擴散層2、3 係被場氧化膜4分離，同時並於第丨及第2<η型高濃度擴 散層2、3上形成層間絕緣膜5 ’在該層間絕緣膜5之上形 成與第1之η型高濃度擴散層2平行延伸的第1之金屬層6、 及與第2之η型高濃度擴散層3平行延伸的第2之金屬層7。 第1之金屬層6係連接於對輸入電路或輸出入電路輸入訊號 之輸入墊片ΙΝΡ，同時並介由接觸與第1之η型高濃度擴散 層2連接。又，第2之金屬層7的兩端部，係連接於供給基 準電壓Vss之基準電壓墊片VSP，同時，第2之金屬層7的中 央部係與第2之η型高濃度擴散層3連接。 以下，説明有關習知保護電路之動作。 正的浪涌電壓乃從輸入墊片ΙΝΡ施加於保護電路時，介 由第1之金屬層6而連接於輸入墊片ΙΝΡ之第1的η型高濃度 本紙張尺度適用t國國家標準（CNS)A4規格（2〗0 X 297公釐） ---I---f I H 1 ----------1 訂· ----II — 1^. {請先閱讀背面之注意事項尸心寫本頁) 經濟部智慧財產局貝工消费合作社印製 __ 409J396_B7___ 五、發明說明（2 ) 擴散層2與半導體基板之PN接合會擊穿，故正孔乃流入p 坦半導禮基板1。若正孔流入p型半導體基板1，在p型半 導體基板】之第1的η型高濃度擴散層2附近的區域電位會 局部上昇，寄生雙極電極體qP會作動’雙極電流乃流入輸 入替片ΙΝΡ與基準電壓墊片VSP之間，故可使浪涌電流消失 於基準電壓墊片VSP。 另外，負的浪涌電壓從輸入塾片INP施加於保護電路時 ，P型半導體基板1與第型高濃度擴散層2會變成順偏 壓，二極體之順方向電流會流入基準電壓墊片vsp與輸入 整片INP之間’故可使浪涌電流消失於輸入墊片ΙΝρ。 依以上之動作原理，保護電路可迅速吸收浪涌電壓，而 避免高電壓施加於内部電路之事態，以防止半導體裝置之 内部元件的破壞。 (發明欲解決之課題） 與在第1之ti型高濃度擴散層2中的第丨金屬層6之連接部 正下方的區域，因乃低阻抗，正的浪涌電壓施加於輸入墊 片INP時，擊穿電流會集令於與在第型高濃度擴散層2 之第i金屬層6的連接部正下方區域。因此，恐怕第1之11 型高濃度擴散層2與p型半導體基板丨之間的pN接合會破壞 ，或，第1之η型高濃度擴散層2本身會被破壞。 又，若考慮第丨之^型高濃度擴散層2與第丨金屬層6之連 接部至Ρ型半導體基板i的電流流路，對第i金屬層6與第】 之η型高濃度擴散層2的連接面垂直的方向（上下方向）之電 流流路距離，會*對連接面平行方向（左右方向）之電流流 -5- 本紙張尺度 關家標i|t(CNS)A4 祕（210 29fi^)------- ---------^----- 裝--------訂------I--線 (請先W讀背面之注意事項寫本頁) . 經濟部智慧財產局員工消費合作社印製 459396 A7 —：——__B7______ 五、發明說明（3 ) 路距離還小’故擊穿電流會大幅流入第1金屬層6與第}之 η型高濃度擴散層2的連接面垂直方向，但，很難流入連接 而平行的方向。因此’寄生雙極電晶體Qp無法確實吸收浪 涌電流。 因此’爲提高保護電路吸收浪涌電流之能力，故必須增 大第1之η型高濃度擴散層2的面積，但，若第型高濃 度擴散層2的面積變大，輸入容量或輸出入容量會增大， 輸入訊號或輸出訊號之延遲時間會變大，而電路之動作速 度變遲。 鑑於刖述，本發明之目的在於不增大與輸入墊片電氣連 接t高濃度擴散層面積，而提昇吸收浪涌電流之能力。 (用以解決課題之方法） 爲達成前述之目的，本發明之半導體裝置係具備：形成 於第1導電型 <半導體基板的第2導電型之第1高濃度擴散 層，在半導m基板上與第！高濃度擴散層形成間隔，且施 加基準電壓之第2導電型的第2高濃度擴散層；用以對輸入 電路或輸出入電路輸入輸入.訊號之輸入塾片與^高滚度 擴散層電氣連接的導電層；形成於半導體基板中之第U 濃度擴散滑正下方區域的第2導電型之第！低濃度擴散層。 此處所謂之輸入塾片亦包含：用以輸入輸入訊號、或、輸 出輸出訊號之輸出入塾片。_ 若依本發明之半導體裝置，因在半導體基板中之第！高 濃度擴散層正下方區域形成第2導“之第i低濃度擴散層 ，故對於半導體基板主面垂直的方向（上下方向）之電流流 _____________ ~ 6 - 本紙張尺度適用中國國家標準（CNS)A4規& (21Q x 297 ^——---- ---：--'--^-----裝------— 丨訂--------線 • * (請先閱讀背面之注意事項厂\寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --463396 R7 --- -________ V. Description of the Invention (1) (Technical Field to Which the Invention belongs) The present invention relates to a semiconductor device, and m Λ Used as a protection circuit to protect internal circuits from surge voltage. (Known technology) In the past, in order to protect the interrogator of an M0S transistor that constitutes an internal circuit, an input circuit or an input / output circuit connected to the internal circuit is provided with a resistor, a dipole, or a transistor. Protection circuit a An example of a conventional protection circuit is described below with reference to FIG. As shown in FIG. 7, on a p-type semiconductor substrate, a first 11-type high-concentration diffusion layer 2 and a second n-type high-concentration diffusion layer 3 are formed at intervals from each other and extend in a direction perpendicular to the paper surface. The first and second in-type high-concentration diffusion layers 2 and 3 are separated by the field oxide film 4, and an interlayer insulating film 5 'is formed on the first and second < n-type high-concentration diffusion layers 2 and 3 to insulate between the layers. A first metal layer 6 extending parallel to the first n-type high concentration diffusion layer 2 and a second metal layer 7 extending parallel to the second n-type high concentration diffusion layer 3 are formed on the film 5. The first metal layer 6 is connected to the input pad INP of an input signal to an input circuit or an input / output circuit, and is also connected to the first n-type high-concentration diffusion layer 2 through a contact. Both ends of the second metal layer 7 are connected to the reference voltage pad VSP that supplies the reference voltage Vss, and the center of the second metal layer 7 is connected to the second n-type high-concentration diffusion layer 3. connection. The operation of the conventional protection circuit will be described below. When the positive surge voltage is applied from the input pad INP to the protection circuit, it is connected to the input pad INP through the first metal layer 6 with a high concentration of the first η-type. This paper is applicable to the national standard (CNS) ) A4 specification (2〗 0 X 297 mm) --- I --- f IH 1 ---------- 1 Order · ---- II — 1 ^. {Please read the back one first Cautions written on this page) Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs __ 409J396_B7___ V. Description of the Invention (2) The PN junction of the diffusion layer 2 and the semiconductor substrate will break down, so the positive hole flows into p. Guideli substrate 1. If a positive hole flows into the p-type semiconductor substrate 1, the potential in the area near the first n-type high-concentration diffusion layer 2 of the p-type semiconductor substrate] will locally rise, and the parasitic bipolar electrode body qP will act. 'Bipolar current flows into the input Between the chip INP and the reference voltage pad VSP, the inrush current can be eliminated in the reference voltage pad VSP. In addition, when a negative surge voltage is applied to the protection circuit from the input chip INP, the P-type semiconductor substrate 1 and the first high-concentration diffusion layer 2 become forward biased, and the forward current of the diode flows into the reference voltage pad. Vsp and the entire input INP 'can make the inrush current disappear in the input pad INP. According to the above operation principle, the protection circuit can quickly absorb the surge voltage, and avoid the situation where high voltage is applied to the internal circuit, so as to prevent the internal components of the semiconductor device from being damaged. (Problems to be Solved by the Invention) The area directly below the connection portion of the first metal layer 6 in the first ti-type high-concentration diffusion layer 2 has a low impedance, and a positive surge voltage is applied to the input pad INP. At this time, the breakdown current is concentrated in the area directly below the connection portion with the i-th metal layer 6 of the first-type high-concentration diffusion layer 2. Therefore, the pN junction between the first 11-type high-concentration diffusion layer 2 and the p-type semiconductor substrate 丨 may be broken, or the first n-type high-concentration diffusion layer 2 itself may be broken. In addition, if the current flow path from the connection between the ^ -type high-concentration diffusion layer 2 and the 丨 -type metal layer 6 to the P-type semiconductor substrate i is considered, the η-type high-concentration diffusion layer for the i-th metal layer 6 and The distance of the current flow path in the vertical direction (up and down direction) of the connection surface of 2 will * current the current flow in the parallel direction (left and right direction) of the connection surface. 5- This paper scales the house standard i | t (CNS) A4 secret (210 29fi ^ ) ------- --------- ^ ----- Install -------- Order ------ I-- line (please read the first Note on this page). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 459396 A7 —: __B7______ 5. Description of the invention (3) The distance is still small, so the breakdown current will flow into the first metal layer 6 and the first. The connecting surface of the η-type high-concentration diffusion layer 2 is perpendicular, but it is difficult to flow into the parallel parallel direction. Therefore, the 'parasitic bipolar transistor Qp cannot reliably absorb the inrush current. Therefore, in order to improve the ability of the protection circuit to absorb the surge current, the area of the first η-type high-concentration diffusion layer 2 must be increased. However, if the area of the first-type high-concentration diffusion layer 2 becomes larger, the input capacity or output The capacity will increase, the delay time of the input signal or output signal will increase, and the operation speed of the circuit will be delayed. In view of the foregoing, the object of the present invention is to improve the ability to absorb surge current without increasing the area of the high-concentration diffusion layer that is electrically connected to the input pad. (Method to solve the problem) In order to achieve the aforementioned object, the semiconductor device of the present invention includes a first high-concentration diffusion layer formed on a first conductivity type < semiconductor substrate and a second conductivity type, and a semiconductive m substrate Up and down! The high-concentration diffusion layer forms a gap, and the second high-concentration diffusion layer of the second conductivity type to which a reference voltage is applied; it is used to input or input the input circuit or the input-output circuit. The input diaphragm of the signal is electrically connected to the high-roller diffusion layer. The conductive layer; the second conductive type of the U-th concentration diffusion region formed in the semiconductor substrate! Low concentration diffusion layer. The so-called input cymbals here also include: input and output cymbals used to input input signals or output signals. _ If the semiconductor device according to the present invention is the first among semiconductor substrates! The i-th low-concentration diffusion layer 2 is formed in the area immediately below the high-concentration diffusion layer, so that the current flow in the vertical direction (up and down direction) of the main surface of the semiconductor substrate is _____________ ~ 6-This paper applies the Chinese national standard (CNS ) A4 gauge & (21Q x 297 ^ -------- ---: --'-- ^ ----- install ---------- 丨 order -------- line • * (Please read the notes on the back of the factory \ write this page)
409396 五、發明說明（ 路的阻抗會增大。 本發明之半導體裝置，宜 (請先J53讀背面之注意事項广、寫本頁) MΛ 進步具備在半導體基板中之 弟2呵濃度擴散層正下方區械 域所形成的第2導電型之第2低 濃度擴散層。 本發明之半導體裝置進— 卞且具備：相對於半導體基板 中之第1高濃度擴散層，形成 ^ 两於第2尚濃度擴散層相反侧區 施加基準電壓之第2導電型的第3高濃度擴散層：與 1形成於半導體基板中之第3高濃度擴散層.正下方區域的 弟2導電型之第3低濃度擴散層。 本發明之半導體裝置進一书— 钟 ^ 步且具備：形成於輸入墊片與 弟1高濃度擴散層之間而與導電層呈串聯連接，擁有比導 電層更高電阻値之高電阻導電層。 發明之半導體裝置中’第1之高濃度擴散層宜具有 k與弟2同很度擴散層相向之區域延伸至外側的非相向部 ，導電層與非相向部乃電氣連接。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 本發明之半導體裝£宜進—步具備第1導電型之高濃度 擴散層丨係形成於包圍半導體基板中之第1高濃度擴散 層及第2高濃度擴散層之區域，且施加基準電壓。 本發月<半導體裝置宜進—步具備第2導電型之雜質擴 散：其係形成於包圍半導體基板中之第1高濃度擴散層 及第2问;辰度擴散層之區域，五施加比基準電壓還高的電 壓。 (發明之實施形態） (第1實施形態） 109^96 A7 B7___ 五、發明說明（5 ) 以下，一面參照圖i，一面説明有關本發明第t實施形態 之半導體裝置。 圖1表示第1實施形態之半導體裝置的剖面構造，如圖1 所示，連接於基準電壓Vss之p型半導體基板1〇上，形成一 以預定間隔對紙面垂直方向延伸之第】之n型高濃度擴散層 21及第2之η型高濃度擴散層22。藉ρ型半導體基板1〇、第1 工η型高濃度擴散層21及第2<η型高濃度擴散層以，而構 成寄生雙極電晶體QP’ ρ型半導體基板1〇相當於基極：Β ’第1之η型高濃度擴散層21相當於集極：C ,第2之η型高 濃度擴散層22相當於射極：Ε。又，第1及第2之η型高濃 度擴散層21、22例如可以注入能量：20 KeV、劑量： 5 X 10 cm2之注入條件形成。 第1之實施形態的特徵’係在第1之η型高濃度擴散層21 之正下方區域形成第1之η型低濃度擴散層31，其係與第1 之η型高濃度擴散層21平行且延伸，並比第1之„型高濃度 擴散層21幅還稍小；同時在第2之η型高濃度擴散屠22之正 下方區域形成第2之η型低濃度擴散層32，其係與第2之η 型高濃度擴散層22平行且延伸，並比第2之η型高濃度擴散 層22幅還稍小。第1及第2之η型低濃度擴散層31、32的深 度例爲1.5〜1_75 μιη，第1之η型低濃度擴散層31與第 型低濃度擴散層32之間隔例如爲0.5〜1.0 μιη。又，第1及第 2之η型低濃度擴散層31 ' 32可以例如注入能量：7〇〇 KeV 、劑量：1 X 10I3cm2之注入條件來形成= 第1及第2之η型高濃度擴散層21、22係互被場氧化膜4〇 -8- 本紙張尺度遶用尹囤國家標準（CNS)A4規格（210 X 297公;^ > ----J---ί---—* -裝· -------訂·-------- <請先閱讀背面之注意事項寫本頁) 經濟部智慧財產局負工消費合作社印製 經濟部智慧財產局員工消費合作社印製 ^t _ 五、發明說明（β ) 分離，同時亦遠離其他之元件。第^及第2U型高濃度擴 散層21 22之上依次形成第1之層間絕緣膜41及第2之看間 絕緣膜42。 在第2 (屠間絕緣膜42之上乃形成與第型高濃度擴 傲層21平行且延伸之第】金屬層51、及 '與第2之^型高濃 度擴散層22平行丑延伸之第2金屬層52。第ι金屬層51之兩 端部係連接於對輸入電路或輸出入電路輸出輸入訊號之輸 入整片INP’同時，第！金屬層51之中央部，係介由一形成 於第1之層間絕緣膜41上呈與第丨金屬層51平行且延伸之高 電阻導電層60，而與第1之η型高濃度擴散層21連接。第2 金屬層521兩端部係連接於—可供給基準電壓之基準電 ，墊片vsp，同時，第2金屬層52之中央部係與第2之^型: 纸度擴散層52連接，此時，高電阻導電層6〇之電阻値設定 成比第1及第2之金屬層5丨' 52的電阻値稍高些。 若依第1之實施形態，在ρ型半導體基板1〇中之高電阻導 電層60與第1之11型高濃度擴散層21的連接部正下方區域乃 形成第1之η型低濃度擴散層31，故，對於高電阻導電層 與第1之11型高濃度擴散層21之連接面垂直的方向（上下方 向）’其電流流路的阻抗會增大。 因此，對輸入墊片ΙΝΡ施加正的浪涌電壓時，所發生之 擊穿電流不會局部集中於與在第型高濃度擴散層幻中 之咼電阻導電層60的連接部正下方區域，亦即，第】之打刑 呵濃度擴散層21流動之擊穿電流的電.流密度會變小，故， 可防止第1 型高濃度擴散層21的正下方區域與ρ型半導 —________ -9- 本纸張尺展適用中_冢標準（CNS)A4規格⑵Q χ挪 〉 —---- - ------裳--------訂---------線 (請先閱讀背面之注意事項IViK寫本頁) · 40^396 A7 經濟部智慧財產局員工消費合作社印製 B7 _五、發明說明（7 ) 體基板10之間的PN接合破壞、及、第1之η型高濃度擴散層 21本身的破壞。 又，擊穿電流係在第1之η型高濃度擴散層21的内部中， 在相對於高電阻導電層60與第1之η型高濃度擴散層21的連 接面平行方向（左右方向）之電流流路，比以往流動更多， 故，寄生雙極電晶體QP流動之雙極電流會增加，故，吸收 保護電路之浪涌電流的能力會提高，而半導體裝置之浪涌 对壓·會增大。 若依第1之實施形態，在ρ型半導體基板10中第2金屬層 52與第2之η型高濃度擴散層22的連接部正下方區域，形成 第2之η型低濃度擴散層32呈與第1之η型低濃度擴散層31 相向，故，與第1之η型高濃度擴散層21及第1之η型低濃 度擴散層31、與第2之η型高濃度擴散層22及第2之η型低濃 度擴散層32之相向面積會變大，而，寄生雙極電晶體QP之 電流能力會變大，故，吸收該保護電路之浪涌電流的能力 更提昇。 若依第1之實施形態，在第1金屬層51與第1之η型高濃 度擴散層21之間設有高電阻導電層60，故，如圖2所示之 等價電路可知，輸入墊片ΙΝΡ與寄生雙極電晶體QP之集極C 之間，高電阻導電層60之電阻成分呈串聯插入，故可抑制 流入保護電路之浪涌電流。因此，可更確實防止第1之η型 高濃度擴散層21的正下方區域與ρ型半導體基板10之間的 ΡΝ接合破壞及第1之η型高濃度擴散層21本身的破壞3 (第2之實施形態） -10- -----「---^-----農--------訂*------I*線 (靖先閱讀背面之注意事項厂ν'·寫本頁) _ _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 409396 =_ 五、發明說明（8 ) 以下’面參照圖j及圖4，一面説明本發明之第$實施 形遙的保護電路’但在第2實施形態中，有與第1實施形態 相同的構件’藉由賦予同—符號而省略説明。 圖3表示第2實施形態中之半導體裝置的剖面構造，圖4 表示第2實施形態中之半導體裝置的平面構造，圖3爲圖4 中之III - ΠΙ線的剖面圖。 如圖3所示般，連接於基準電壓vss之p型半導體基板1〇 上形成第1之η型高濃度擴散層21，同時並在第1 型高 濃度擴散層21之兩侧形成第2之η型高濃度擴散層22及第3 之η型高濃度擴散層23。在第2之層間絕緣膜42上，形成第 1金屬層51、第2金屬層Μ及第3金屬層53。第1金屬層51之 兩端部係連接於一可對輸入電路或輸出入電路輸出輸入訊 號之輸入墊片ΙΝΡ，同時，中央部係介由高電阻導電層6〇而 與第1之η型高濃度擴散層21連接，第2金屬層52的兩端部 係連接於一可供给基準電壓vss之基準電壓塾片vsp ,同時 ’中央邵係與第2之η型高濃度擴散層22連接，第3金屬廣 53之兩端部係連接於一可供給基準電壓vss之基準電譽整片 VSP ’同時’中央部係與第3之η型高濃度擴散層23連接。 若依第2實施形態，在由ρ型半導體基板1〇、與、第1之 η型高濃度擴散層21及第1之η型低濃度擴散層31所構成的 第1之二極體兩侧’形成第2之-二極體（由ρ型半導體基板10 、與、第2之η型高濃度擴散層22及第2之η型低濃度擴散 層32所構成的）、以及 '第3之二極體（由ρ型半導體基板10 、與' 3之η型高濃度擴散層23及第3之η型低濃度擴散層33 -11 - 本紙張尺度適用中國囤家標準（CNS)A4規格（210 X 297公釐） II I I ΙΊ I I Ί--- I * — — — — — — — [111! (請先閱讀背面之注意事項厂^寫本頁) A7 A7 經濟部智慧財產局員工消費合作杜印製 ——- 五、發明說明（9 ) 所構成的）。因此，藉由p型半導體基板10、與、第1之η型 高濃度擴散層21及第1之η型低濃度擴散層31、與、第2之η 型高濃度擴散層22及第2之η型低濃度擴散層32，而構成第 1之寄生雙極電晶體QP1，同時，藉由ρ型半導體基板10、 與、第1之η型高濃度擴散層21及第1之η型低濃度擴散層31 、與、第3之η型高濃度擴散層23及第3之η型低濃度擴散 層33，而構成第2之寄生雙極電晶體QP2，故，對輸入墊片 ΙΝΡ施加正的浪涌電壓時，第1及第2之寄生雙極電晶體QP1 、QP2會作動，而雙極電流乃流入輸入墊片ΙΝΡ與其兩側之 基準電壓墊片VSP之間，故，可使浪涌電流消失於兩側之 基準電壓墊片VSP。因此，吸收保護電路之浪涌電流的能 力乃倍增，故半導體裝置之浪涌耐壓會大大增昇。 保護電路之輸入容量係依連接於輸入墊片ΙΝΡ之二極體 來決定，亦即依由ρ型半導體基板10、與、第1之η型高濃 度擴散層21及第1之η型低濃度擴散層31所構成的第1之二 極體ΡΝ接合的接合容量來決定《因此，於第1之二極體的 兩側，即使設有前述第2之二椏體及第3之二極體，輸入容 量亦不會增加，故電路之動作速度無下降之虞。 如圖4所示般，第1之η型高濃度擴散層21係從第2之η型 高濃度擴散層22及第3之η型高濃度擴散層23延伸至兩端側 ，而具有不與第2及第3之η型高濃度擴散層22、23相向的 非相向部21，同時，第1之η型低濃度擴散層31係從第2之 η型低濃度擴散層32及第3之η型低濃度擴散層23延伸至兩 端側，而具有不與第2及第3之η型低濃度擴散層32、33相 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------- -----I--訂------— II {請先閱讀背面之注意事項tv^寫本頁) ， A7 A7 經濟部智慧財產局具工消費合作社印製 ---4-09396 R7__ 五、發明說明（1〇) 向的非相向部31a。又，第t之^型高濃度擴散層21與高電 阻導電層60(第1金屬層5】）連接之第！接觸體71，係亦形成 於第1之η型高濃度擴散層21的非相向部2ia。 又’於圖4中，71a係表示形成於第1之^型高濃度擴散層 21的非相向部21a的非相向部接觸體，π表示第2之^型高濃 度擴散層22與第2之金屬層52連接的第2接觸體，73表示第 3之η型高濃度擴散層23與第3金屬層53連接之第3接觸體。 如以上説明般’在非相向部接觸體71a的側方，不存在 第2之n型向濃度擴散層22及第3之n型高濃度擴散層23。因 此，從非相向部接觸體71 a與第1之^型高濃度擴散層21之 連接部至第2或第3之η型高濃度擴散層22、23的距離（相當 於第1及第2之寄生雙極電晶體QP1、qP2之基極長度），係 位於第1之η型鬲濃度擴教層21的中央部之第1接觸體71與 第型高濃度擴散層21的連接部至第2或第3tn型高濃 度擴散層22、23的距離亦會變長。因此，經由非相向部接 觸體71 a之電流流路的阻抗，係比經由位於中央部之第^接 觸體71的電流流路之阻抗還更大，故可抑制經由非相向部 接觸體71 a之電流流路流動的電流量。 形成於第1之η型高濃度擴散層21端部的第1接觸體71至 流動於第2或第3之η型高濃度擴散層22、23端部的電流之 氙路，係擴展至第1、第2及第3之η型高濃度擴散層21、22 、23外側的區域。因此，第i之η型高濃度擴散層21的長度 相等於第2及第3之η型高濃度擴散層22、23的長度時，形 成於第1之η型而濃度擴散層21端邵的第1接觸體7〗至流動 ____ -13- 本紙張尺度时關家標準（CNS)A4現格㈣χ 297公爱） -- I ^------11---裝--------訂---------線 (請先閱讀背面之注意事‘'填寫本頁) Μ 經濟部智慧財產局員工消費合作社印制^ . A7 _B7_五、發明說明（11〉 於第2或第3之η型高濃度擴散層22、23端部的電流量，比 形成於第1之η型高濃度擴散層21的中央部之第一接觸體 71至流動於第2或第3之η型高濃度擴散層22、23的中央部 之電流量，電流流路擴散至第1、第2及第3之η型高濃度 擴散層21、22、23外側區域的分量更多，故，經由形成於 第1之η型高濃度擴散層21端部之第1接觸體71的電流流路 會發生電流集中。 如前述般，若依第2實施例，經由非相向部接觸體71a之 電流流路的阻抗，會比經由位於中央部之第1接觸體71的 電流流路阻抗還更大，可抑制經由非相向部接觸體71a之電 流流路流動的電流量，故，可缓和經由非相向部接觸體71a 之電流流路中的電流集中。因此，可迴避局部的電流集中 ，故能防止第1接觸體71及第1之η型高濃度擴散層21的破 壞，並提昇保護電路的浪涌耐壓。 又，於第2實施形態中，在第1之η型高濃度擴散層21之 兩側設有第2及第3之η型高濃度擴散層22、23，而於第1之 二極體兩側形成第2及第3之二極體，但，連接於輸入訊號 墊片ΙΝΡ之η型高濃度擴散層與連接於基準電壓墊片VSP之η 型高濃度擴散層亦可互相配置。若如此，連接於輪入訊號 墊片ΙΝΡ之η型高濃度擴散層的兩側，形成寄生雙極電晶體 ，故可確實提昇吸收浪涌電流之能力。 ' (第3之實施形態） 以下，一面參照圖5及圖6，一面説明本發明第3實施形 態的保護電路，但，在第3實施形態中，對於與第1或第2 -14- -----^丨丨一；11--ί --------訂--------- (請先閱讀背面之注意事琅 ' 填寫本頁) 本紙張尺度適用令國國家標準（CNS)A4規格（210x 297公釐） 經濟部智慧財產局員工消費合作社印製 409396 Λ7 -------1_ B7______ 五、發明說明（12) 實施形態的構件，賦予同一符號，以省略説明。 圖5表π第3實施形態之半導體裝置剖面構造，圖6表示 第2實施形態之半導體裝置的平面構造，圖5爲在圖6中之 V - V線的剖面圖。 如圖5所示，與第2實施形態同樣，連接於基準電壓 之P型半導體基板10上形成第i 型高濃度擴散層21，同 時，在第1之η型高濃度擴散層2丨的兩側，形成第2 高濃度擴散層22及第3之n型高濃度擴散層23。又，第1金 屬層51之兩端部係連接於輸入墊片INp，同時中央部係介由 而電阻導電層60而與第1之!!型高濃度擴散層？！連接，第2 金屬層52之兩端部係連接於基準電壓塾片vsp ,同時中央 部係與第2之η型高濃度擴散層22連接，第3金屬層53之兩 端部係連接於基準電壓墊片vsp，同時，令央部與第3之η 型高濃度擴散層23連接。第1金屬層51與輸入墊片ιΝρ係藉 第1金屬配線81連接，同時，第3金屬層53與基準電壓塾片 VSP係藉第2金屬配線82連接。又，第2金屬層52與基準電 壓整片VSP係藉第2金屬配線82連接，但圖示省略。 第3之實施形態特徵’於p型半導體基板1 〇上係形成正方 形框狀之p型高濃度擴散層91呈包圍第1、第2及第3之η型 (¾濃度擴散潛21 '22、23，同時’在ρ型高濃度擴散層91 之上侧形成第4金屬層Μ，第4·金屬層54係介由第2之金屬 配線82而連接於基準電壓墊片VSP β 又，在Ρ型高濃度擴散層91的外側形成正方形框狀之第4 之η型高濃度擴散層24，同時在第4之η型高濃度擴散層24 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) J ：--^ ---I--I ---------^ ί靖先閱讀背面之注意事項.填寫本頁> 、 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明說明（13 ) 之上側形成第5金屬層55，第5之金屬層55係使第4之η型高 濃度擴散層24、與、比基準電壓Vss更高之電壓，例如施加 電源電壓Vdd之高電位墊片VDP電氣連接。 從輸入電路或輸出入電路對輸入整片INP施加比基準電 壓Vss還低之電壓時，從第1之η型高濃度擴散層21或第1之 η型低濃度擴散層31電子流入ρ型半導體基板10。若電子流 入ρ型半導體基板10, ρ型半導體基板10之電位恐有完全變 動之虞，同時，流入ρ型半導體基板10之電子會擴散至形 成於ρ型半導體基板10之其他半導體元件，而恐引起其他 半導體元件的誤動作之虞。 然而，在第3實施形態中，係形成包圍第1、第2及第3 之η型高濃度擴散層2〗、22、23，爲設有一連接於基準電壓 墊片VSP之ρ型高濃度擴散層91，流入ρ型半導體基板10之 電子係介由ρ型高濃度擴散層91而流至基準電壓墊片VSP ，故對輸入墊片ΙΝΡ比基準電壓Vss還低之電壓時，亦可防 止ρ型半導體基板10之電位變動。 在第3之實施形態中，於ρ型高濃度擴散層91之外側，設 有一連接於施加比基準電壓Vss還高之電壓的高電位墊片 VDP之第4之η型高濃度擴散層24及第4之η型低濃度擴散層 34，故流入ρ型半導體基板10之電子會穿過形成於第4之η 型高濃度擴散層24或第4之η型也濃度擴散層34的附近之空 乏層，而被引入第4之η型高濃度擴散層24或第4之η型低 濃度擴散層34後，流至高電位墊片VDP，故對輸入墊片ΙΝΡ 施加比基準電壓Vss還低的電壓時，亦可防止其他的半導體 -16- ----—--'--- -裝 ------—訂 ---- - - -線 (請先閱讀背面之注意事項ί ί寫本頁) · 本紙張&度適用ΐ國國家標準（CNS)A4規格（210 X 297公釐〉 409396 A7 r._ B7 五、發明說明（14) 疋件引起誤動作之事態β此時，爲確實將從第〗之^型低濃 度擴散層31流入ρ型半導體基板1〇之電子引入第彳之^型低 濃度擴散層34，第4之η型低濃度擴散層34宜擁有與第】之^ 型低濃度擴散層31同程度以上的深度。 又，在第3實施形態中，雖於ρ型高濃度擴散層91的外側 故有第4m型鬲濃度擴散層μ及第4<η型低濃度擴散層34 ，但，取而代之，亦可僅設有第4 in型高濃度擴散層以或 第4之η型低濃度擴散層34。此時，第4tn型高濃度擴散 層24或第4之η型低濃度擴散層34宜擁有與第型低濃度 擴散層3 1相同程度以上的深度。 又，ρ型南濃度擴散層91、與、第4之η型高濃度擴散層 24及第4足η型低濃度擴散層34，係分別互相揭立而可發揮 各功能，故亦可只設有任—者。 在第1〜第3之實施形態中，於第itn型高濃度擴散層 21與第1金屬層51之間設有高電阻導電層6〇，但，設有高電 阻導電層有6〇之位置無特別限定，而於輸入墊片與第！ 之η型高濃度擴散層21之間，/只要與第丨金屬層51串聯連接 即可。又，不設高電阻導電層60,而亦可直接使第型 高濃度擴散層21與第1金屬層51連接。 進一步於第1〜第3實施形態中’係於ρ型半導體基板】〇 上设有第1之η型高濃度擴散脣21及第2之η型高濃度擴散 層22(或第3之η型咼濃度擴散層23)以及第1之η型低濃度擴 散層31及第2之η型低濃度擴散層32(或第3之η型低濃度擴 散層23),但，取而代之，亦可於η型半導體基板上設有第 -17- 本紙張尺度通用中國國豕標準（CNS)A4規格（210 X 297公爱） (請先閲讀背面之注意事項填寫本頁) -I華： t I5- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作杜印製 409396 A7 _B7 五、發明說明（15 ) 1之p型高濃度擴散層及第2之p型高濃度擴散層（或第3之p 型高濃度擴散層）以及第1之p型低濃度擴散層及第2之p型 低濃度擴散層（或第3之p型低濃度擴散層）。 (發明之效果） 若依本發明半導體裝置，相對於半導體基板主面垂直的 方向電流流路之阻抗會增大，故對輸入整片施加正的浪涌 電壓時，發生的擊穿電流不會局部集中於第1之高濃度擴 散層的正下方區域，亦即，第1之高濃度擴散層下方區域 流動的擊穿電流的電流密度會變小，故，可防止第1之高 濃度擴散層與半導體基板之間的PN接合破壞及第1之高濃 度擴散層本身的破壤。 擊穿電流係比習更多流動於與第1之高濃度擴散層内部 中的半導體基板主面平行方向的電流流路，藉半導體基板 '第1之高濃度擴散層及第2之高濃度擴散層而形成之寄生 雙極電晶體流動之雙極電流會增加，故吸收浪涌電流之能 力會提高，而半導體裝置之浪涌耐壓乃提昇。 本發明之半導體裝置若於第2之高濃度擴散層正下方區 域具備第2導電型的第2之高濃度擴散層，則第1之高濃度 擴散層及第1之低濃度擴散層、與、第2之高濃度擴散層及 第2之低濃度擴散層的相向面積會變大，故很容易形成寄 生雙極電晶體，故，雙極電晶體會增加，藉此，吸收浪涌 電流之能力更進一步提昇。 本發明之半導體裝置乃相對於第1之高濃度擴散層而形 成於第2之高濃度擴散層的相反側區域，具備施加基準電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） !1.11!-----裝*-------訂---------線 (請先閱讀背面之注意事項κ 寫本頁) f . 經濟部智慧財產局員工消費合作社印 409396 A7二_B7五、發明說明（16 ) 壓之第2導電型的第3高濃度擴散層、與、形成於第3高濃 度擴散層正下方區域之第2導電型的第3低高濃度擴散層， 藉由丰導體基板、與、第1之高濃度擴散層及第1之低濃度 擴散層、與、第2之高濃度擴散層及第3之低濃度擴散層， 而構成第1之寄生雙極電晶體，同時並藉由半導體基板、 與、第1之高濃度擴散層及第1之低濃度擴散層、與、第3 之高濃度擴散層及第3之低濃度擴散層，而構成第2之寄生 雙極電晶體，故，對輸入墊片施加正之浪涌電壓時，第1 及第2之寄生雙極電晶體會作動，雙極電流會從第1之高濃 度擴散層及第1之低濃度擴散層朝兩側流動。因此，吸收 浪涌電流之能力會倍增，故半導體裝置之浪涌耐壓會大大 地提昇。 本發明之半導體裝置乃於輸入墊片與第1之高濃度擴散 層之間而與導電層串聯連接，若具備比導電層更高之電阻 値的高電阻導電層，在輸入墊片與寄生雙極電晶體之集極 之間，電阻成分呈串聯插入，可抑制流入保護電路之浪涌 電流，故可更確實防止第1之高濃度擴散層與半導體基板 之間的PN接合破壞及第1之高濃度擴散層本身的破壞。 在本發明之半導體裝置中，第1之高濃度擴散層乃具有 從與第2之高濃度擴散層相向之區域延伸至外側之非相向 部，導電層與非相向部乃電氣-連接，經過導電層與第1之 高濃度擴散層的非相向部之連接部的電流流路阻抗，會比 經過導電層與第1之高濃度擴散層相向部的連接部之電流 流路阻抗還大，故可抑制經過導電層與第1之高濃度擴散-19- ιιί1-!··!·裝 ij—i — 訂· — 線 (請先閱讀背面之注意事項- 寫本頁) , 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 409396 A7 _B7 五、發明說明（17 ) 層非相向部的連接部之電流流路流動的電流量，並缓和在 電流流路中之電流集中。因此，可避免局部的電流集中， 故可防止導電層與第1之高濃度擴散層的連接部、及第1之 高濃度擴散層的破壞，藉此，半導體裝置之浪涌耐壓會增 高。 本發明之半導體裝置若具備一形成於包圍第1之高濃度 擴散層及第2之高濃度擴散層的區域，並可施加基準電壓 之第1導電型的高濃度擴散層，可對輸入墊片施加比基準 電壓更低的電壓，即使電子流入半導體基板，流入之電子 係介由第1導電型的高濃度擴散層而流至基準電壓側，故 可防止半導體基板的電位變動。 本發明之半導體裝置若具備一形成於包圍第1之高濃度 擴散層及第2之高濃度擴散層的區域，並施加比基準電壓 更高的電壓之第2導電型的不純物擴散層，則對輸入墊片 施加比基準電壓還低的電壓，即使電子流入半導體基板， 流入之電子被引入第2導電型的雜質擴散層後，流至高電 壓側，故可防止其他之半導體元件引起誤動作之事態。 (圖面之簡單説明） 圖1爲第1實施形態之半導體裝置的剖面圖。 圖2爲藉第1實施形態之半導體裝置所實現的保護電路之 等價電路圖。 - 圖3爲第2實施形態之半導體裝置的剖面圖，爲圖4之III -III線之剖面圖。 圖4爲第2實施形態之半導體裝置的平面圖。 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------r----裝·-------訂 *-------- (請先閱讀背面之注意事項寫本頁) ， 經濟部智慧財產局員工消費合作社印製 409396 A7 _B7五、發明說明（18 ) 圖5爲第3實施形態之半導體裝置的剖面圖，爲圖6之V -V線的剖面圖。 圖6爲第3實施形態之半導體裝置的平面圖。 圖7爲習知半導體裝置的剖面圖。 〔符號的説明〕 10 p型半導體基板 21 第1之η型高濃度擴散層 21a 非相向部 22 第2之η型高濃度擴散層 23 第3之η型高濃度擴散層 24 第4之η型高濃度擴散層 31 第1之η型低濃度擴散層 32 第2之η型低濃度擴散層 33 第3之η型低濃度擴散層 34 第4之η型低濃度擴散層 40 場氧化膜 41 第1之層間絕緣膜 42 第2之層間絕緣膜 51 第1金屬層 52 第2金屬層 53 第3金屬層 54 第4金屬層 55 第5金屬層 60 高電阻導電層 -21 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項埃寫本頁) 經濟部智慧財產局員工消費合作社印 409396A7 _二_B7五、發明說明（19 ) 71 第1接觸體 71a 非相向部接觸體 72 第2接觸體 73 第3接觸體 81 第1金屬配線 82 第2金屬配線 91 p型高濃度擴散層 LNP 輸入墊片 VSP 基準墊片 QP 寄生雙極電晶體 QP1第1之寄生雙極電晶體 QP2 第2之寄生雙極電晶體 (請先閱讀背面之注意事項寫本頁) -22- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）409396 V. Description of the invention (The impedance of the circuit will increase. The semiconductor device of the present invention is suitable (please read the precautions on the back of J53, write this page). The second conductive type and the second low-concentration diffusion layer formed in the lower region. The semiconductor device of the present invention is provided with: compared with the first high-concentration diffusion layer in the semiconductor substrate, ^ is formed two to two second. The third high-concentration diffusion layer of the second conductivity type with the reference voltage applied to the region on the opposite side of the concentration-diffusion layer: and the third high-concentration diffusion layer formed on the semiconductor substrate. The third low-concentration layer of the second conductivity type in the area directly below it. Diffusion layer. A further book of the semiconductor device of the present invention—Zhong ^ further includes: formed between the input pad and the high-concentration diffusion layer and connected in series with the conductive layer, and has a higher resistance than the conductive layer. Conductive layer In the semiconductor device of the invention, the 'first high-concentration diffusion layer should preferably have a non-opposing portion extending to the outside of a region where k and the same diffusion layer face each other, and the conductive layer and the non-opposing portion are electrically connected. The consumer device of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the semiconductor device of the present invention. It is advisable to further advance the first-conductivity type high-concentration diffusion layer. The first high-concentration diffusion layer and the second high-concentration layer formed in the surrounding semiconductor substrate. The area of the diffusion layer, and the reference voltage is applied. This issue < semiconductor device should further-impurity diffusion with a second conductivity type: it is formed in the first high-concentration diffusion layer and the second question surrounding the semiconductor substrate; In the region of the diffusive layer, a voltage higher than the reference voltage is applied. (Embodiment of the Invention) (First Embodiment) 109 ^ 96 A7 B7___ 5. Description of the Invention (5) Hereinafter, the description will be made with reference to FIG. A semiconductor device according to a t embodiment of the present invention is shown in Fig. 1. Fig. 1 shows a cross-sectional structure of the semiconductor device according to the first embodiment. As shown in Fig. 1, it is connected to a p-type semiconductor substrate 10 having a reference voltage Vss to form a predetermined interval. The first n-type high-concentration diffusion layer 21 and the second n-type high-concentration diffusion layer 22 extending perpendicular to the paper surface. By using the p-type semiconductor substrate 10 and the first η-type high-concentration diffusion layer, Layer 21 and the second < n-type high-concentration diffusion layer, which constitute a parasitic bipolar transistor QP 'p-type semiconductor substrate 10 corresponds to the base: Β' the first n-type high-concentration diffusion layer 21 corresponds to the collector : C, the second n-type high-concentration diffusion layer 22 corresponds to the emitter: E. The first and second n-type high-concentration diffusion layers 21 and 22 can be implanted with, for example, energy: 20 KeV, dose: 5 X 10 The implantation conditions of cm2 are formed. The feature of the first embodiment is that the first n-type low-concentration diffusion layer 31 is formed in the area immediately below the first n-type high-concentration diffusion layer 21, which is the same as the first n-type diffusive layer. The high-concentration diffusion layer 21 is parallel and extends, and is slightly smaller than the first „type high-concentration diffusion layer 21; at the same time, the second η-type low-concentration is formed in the area directly below the second η-type high-concentration diffusion layer 22. The diffusion layer 32 extends parallel to the second n-type high-concentration diffusion layer 22 and is slightly smaller than the second n-type high-concentration diffusion layer 22. Examples of the depths of the first and second n-type low-concentration diffusion layers 31 and 32 are 1.5 to 1-75 μm, and the interval between the first n-type low-concentration diffusion layer 31 and the second low-concentration diffusion layer 32 is, for example, 0.5 to 1.0 μm . In addition, the first and second n-type low-concentration diffusion layers 31 ′ 32 can be formed by, for example, implantation conditions of energy: 700 KeV and dose: 1 × 10 I 3 cm 2 to form the first and second n-type high-concentration diffusion layers. 21 and 22 series oxide film 4〇-8- This paper uses Yin Kun National Standard (CNS) A4 specification (210 X 297); ^ > ---- J --- ί ----- * -Installation · ------- Order · -------- < Please read the notes on the back to write this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative ^ t _ V. Description of the invention (β) Separate from other components. On the first and second U-type high-concentration diffusion layers 21 to 22, a first interlayer insulating film 41 and a second interlayer insulating film 42 are sequentially formed. On the second (the first insulating layer 42 is formed on the second insulating layer 42 parallel to the first type of high-concentration spreading layer 21 and extends the first) metal layer 51, and the second and the second type of high-concentration diffusion layer 22 extending parallel to the first 2 metal layer 52. Both ends of the first metal layer 51 are connected to the entire input INP 'for inputting or outputting an input signal to an input circuit or an input / output circuit. At the same time, the central portion of the first! Metal layer 51 is formed by a The first interlayer insulating film 41 has a high-resistance conductive layer 60 extending parallel to the first metal layer 51 and connected to the first n-type high-concentration diffusion layer 21. Both ends of the second metal layer 521 are connected to —The reference voltage can be supplied with the reference voltage, the gasket vsp, and at the same time, the central portion of the second metal layer 52 is connected to the second ^: paper degree diffusion layer 52. At this time, the resistance of the high-resistance conductive layer 60 is 値It is set to be slightly higher than the resistance 値 of the first and second metal layers 5 ′ and 52. According to the first embodiment, the high-resistance conductive layer 60 in the p-type semiconductor substrate 10 and the first 11 type The first n-type low-concentration diffusion layer 31 is formed in the area immediately below the connection portion of the high-concentration diffusion layer 21, so that it is conductive for high resistance The direction in which the layer is perpendicular to the connection surface of the first 11-type high-concentration diffusion layer 21 (up and down direction) will increase the impedance of the current flow path. Therefore, when a positive surge voltage is applied to the input pad 1NP, it occurs. The breakdown current does not locally concentrate in the area directly below the connection portion of the high-resistance conductive layer 60 in the first type high-concentration diffusion layer, that is, the breakdown current flowing through the concentration diffusion layer 21 The electric current density will become smaller, so it can prevent the area directly below the Type 1 high-concentration diffusion layer 21 and the ρ-type semiconductor —________ -9- This paper rule application is applicable _ Tsukazumi Standard (CNS) A4 specification ⑵Q χ Norwegian> ------------- Shang -------- Order --------- Line (Please read the precautions on the back of IViK first to write this page) · 40 ^ 396 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 _V. Description of the Invention (7) The PN junction failure between the body substrates 10 and the first n-type high-concentration diffusion layer 21 itself. The breakdown current is in the interior of the first n-type high-concentration diffusion layer 21 and is connected to the high-resistance conductive layer 60 and the first n-type high-concentration diffusion layer 21. The current flow path in the plane parallel direction (left-right direction) flows more than before. Therefore, the bipolar current flowing in the parasitic bipolar transistor QP will increase. Therefore, the ability to absorb the surge current of the protection circuit will be improved, and the semiconductor The surge pressure of the device will increase. According to the first embodiment, the area directly below the connection portion between the second metal layer 52 and the second n-type high-concentration diffusion layer 22 in the p-type semiconductor substrate 10 is formed. The second n-type low-concentration diffusion layer 32 faces the first n-type low-concentration diffusion layer 31. Therefore, it is opposite to the first n-type high-concentration diffusion layer 21 and the first n-type low-concentration diffusion layer 31, and The opposing areas of the second n-type high-concentration diffusion layer 22 and the second n-type low-concentration diffusion layer 32 will increase, and the current capability of the parasitic bipolar transistor QP will increase. Therefore, the absorption of the protection circuit Surge current capability is further enhanced. According to the first embodiment, a high-resistance conductive layer 60 is provided between the first metal layer 51 and the first n-type high-concentration diffusion layer 21. Therefore, as shown in the equivalent circuit shown in FIG. 2, the input pad Between the chip INP and the collector C of the parasitic bipolar transistor QP, the resistance component of the high-resistance conductive layer 60 is inserted in series, so that a surge current flowing into the protection circuit can be suppressed. Therefore, it is possible to more surely prevent the PN junction failure between the region immediately below the first n-type high-concentration diffusion layer 21 and the p-type semiconductor substrate 10 and the damage of the first n-type high-concentration diffusion layer 21 itself (second Implementation form) -10- ----- "--- ^ ----- Nong -------- Order * ------ I * line (Jing Xian read the precautions on the back) Factory ν '· Write this page) _ _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 409396 = _ 5. Description of the invention (8) or less 'The protective circuit according to the $ embodiment of the present invention will be described with reference to FIG. J and FIG. 4.' However, in the second embodiment, the same components as those in the first embodiment are used. Fig. 3 shows the cross-sectional structure of a semiconductor device in the second embodiment, Fig. 4 shows the planar structure of the semiconductor device in the second embodiment, and Fig. 3 is a cross-sectional view taken along the line III-III in Fig. 4. As shown in Fig. 3 As shown, the first n-type high-concentration diffusion layer 21 is formed on the p-type semiconductor substrate 10 connected to the reference voltage vss, and at the same time, the first type high-concentration diffusion layer 21 is formed. A second n-type high-concentration diffusion layer 22 and a third n-type high-concentration diffusion layer 23 are formed on both sides of the scattered layer 21. On the second interlayer insulating film 42, a first metal layer 51 and a second metal layer are formed. M and the third metal layer 53. Both ends of the first metal layer 51 are connected to an input pad INP capable of outputting an input signal to an input circuit or an input / output circuit, and at the same time, a central portion is provided with a high-resistance conductive layer 6 〇 It is connected to the first η-type high-concentration diffusion layer 21, and both ends of the second metal layer 52 are connected to a reference voltage diaphragm vsp that can supply a reference voltage vss, and at the same time, the 'central Shao system and the second η Type high-concentration diffusion layer 22 is connected, and both ends of the third metal film 53 are connected to a reference electric chip VSP which can supply a reference voltage vss. At the same time, the central portion is connected to the third n-type high-concentration diffusion layer 23 According to the second embodiment, the first diode is composed of a p-type semiconductor substrate 10, a first n-type high-concentration diffusion layer 21, and a first n-type low-concentration diffusion layer 31. On both sides, a second-diode (from the p-type semiconductor substrate 10 and the second n-type high-concentration diffusion layer 22 and the second Of the n-type low-concentration diffusion layer 32), and the third diode (consisting of the p-type semiconductor substrate 10, the n-type high-concentration diffusion layer 23, and the third n-type low-concentration diffusion layer) 33 -11-This paper size is in accordance with China Store Standard (CNS) A4 (210 X 297 mm) II II ΙΊ II Ί --- I * — — — — — — — [111! (Please read the Attention factory (write this page) A7 A7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs ——- 5. Composition of invention description (9)). Therefore, the p-type semiconductor substrate 10, the first n-type high-concentration diffusion layer 21 and the first n-type low-concentration diffusion layer 31, and the second n-type high-concentration diffusion layer 22 and the second The n-type low-concentration diffusion layer 32 constitutes the first parasitic bipolar transistor QP1, and simultaneously, the p-type semiconductor substrate 10, the first n-type high-concentration diffusion layer 21, and the first n-type low-concentration diffusion layer 21 The diffusion layer 31, the third n-type high-concentration diffusion layer 23, and the third n-type low-concentration diffusion layer 33 constitute the second parasitic bipolar transistor QP2. Therefore, a positive When the surge voltage occurs, the first and second parasitic bipolar transistors QP1 and QP2 will operate, and the bipolar current flows between the input pad INP and the reference voltage pad VSP on both sides, so the surge can be made. The current disappears in the reference voltage pad VSP on both sides. Therefore, the ability to absorb the surge current of the protection circuit is doubled, so the surge withstand voltage of the semiconductor device will greatly increase. The input capacity of the protection circuit is determined by the diode connected to the input pad INP, that is, by the p-type semiconductor substrate 10, the first n-type high concentration diffusion layer 21, and the first n-type low concentration. The junction capacity of the first diode PN junction constituted by the diffusion layer 31 determines "therefore, even if the second diode and the third diode are provided on both sides of the first diode, The input capacity will not increase, so the operating speed of the circuit is not likely to decrease. As shown in FIG. 4, the first η-type high-concentration diffusion layer 21 extends from the second η-type high-concentration diffusion layer 22 and the third η-type high-concentration diffusion layer 23 to both end sides, and has a non-compatibility The second and third n-type high-concentration diffusion layers 22 and 23 are opposed to the non-opposing portion 21, and the first n-type low-concentration diffusion layer 31 is formed from the second n-type low-concentration diffusion layer 32 and the third The η-type low-concentration diffusion layer 23 extends to both end sides, and has a phase that is not in line with the second and third η-type low-concentration diffusion layers 32 and 33. -12- This paper is in accordance with China National Standard (CNS) A4 specification (210 X 297 mm) --------------- ----- I--Order ------- II {Please read the notes on the back first tv ^ Write this page ), A7 A7 Printed by the Industrial Property Cooperative of the Intellectual Property Bureau of the Ministry of Economy-4-09396 R7__ 5. Description of the invention (1) Non-opposing part 31a to the direction. In addition, the t-th ^ -type high-concentration diffusion layer 21 is connected to the high-resistance conductive layer 60 (the first metal layer 5])! The contact body 71 is also formed in the non-opposing portion 2ia of the first n-type high-concentration diffusion layer 21. Also, in FIG. 4, 71 a indicates a non-opposing portion contact body formed on the non-opposing portion 21 a of the first ^ -type high-concentration diffusion layer 21, and π indicates the second ^ -type high-concentration diffusion layer 22 and the second The second contact body to which the metal layer 52 is connected, 73 represents a third contact body to which the third n-type high-concentration diffusion layer 23 and the third metal layer 53 are connected. As described above, the second n-type directional diffusion layer 22 and the third n-type high concentration diffusion layer 23 do not exist on the side of the non-opposing portion contact body 71a. Therefore, the distance from the connecting portion of the non-opposing portion contact body 71 a and the first ^ -type high-concentration diffusion layer 21 to the second or third η-type high-concentration diffusion layers 22 and 23 (equivalent to the first and second The base length of the parasitic bipolar transistors QP1 and qP2) is the connecting part of the first contact body 71 and the first-type high-concentration diffusion layer 21 located at the center of the first n-type ytterbium concentration diffusion layer 21 to the first The distance between the 2 or 3tn-type high-concentration diffusion layers 22 and 23 also becomes longer. Therefore, the impedance of the current flow path through the non-opposing portion contact body 71 a is greater than the impedance of the current flow path through the ^ -th contact body 71 located in the central portion, so that the impedance passing through the non-opposing portion contact body 71 a can be suppressed. The amount of current flowing through the current flow path. The xenon path from the first contact 71 formed at the end of the first n-type high-concentration diffusion layer 21 to the current flowing at the ends of the second or third n-type high-concentration diffusion layers 22 and 23 is extended to the first 1. Regions outside the second and third n-type high-concentration diffusion layers 21, 22, and 23. Therefore, when the length of the i-th η-type high-concentration diffusion layer 21 is equal to the lengths of the second and third η-type high-concentration diffusion layers 22 and 23, they are formed at the end of the first η-type and high-concentration diffusion layer 21. No. 1 contact body 7〗 To flow ____ -13- At the time of this paper's standard (CNS) A4 is now ㈣χ 297 public love)-I ^ ------ 11 --- installation ---- ---- Order --------- line (please read the notes on the back `` Fill this page first '') Μ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^. A7 _B7_ V. Description of the invention ( 11> The current amount at the ends of the second or third n-type high-concentration diffusion layers 22 and 23 is smaller than that of the first contact 71 formed at the center portion of the first n-type high-concentration diffusion layer 21 to flow to the first The amount of current in the central portion of the 2 or 3 η-type high-concentration diffusion layers 22 and 23, and the current flow path diffuses to the components of the first, second, and third η-type high-concentration diffusion layers 21, 22, and 23 More, therefore, current concentration occurs through the current flow path of the first contact body 71 formed at the end portion of the first n-type high-concentration diffusion layer 21. As described above, according to the second embodiment, through the non-opposing portion Current flow of contact 71a The impedance is larger than the resistance of the current flow path through the first contact body 71 located at the center portion, and the amount of current flowing through the current flow path of the non-opposing portion contact body 71a can be suppressed. Therefore, the contact through the non-opposing portion can be eased. The current concentration in the current flow path of the body 71a. Therefore, local current concentration can be avoided, so that the first contact body 71 and the first η-type high-concentration diffusion layer 21 can be prevented from being damaged, and the surge resistance of the protection circuit can be improved. In the second embodiment, second and third n-type high-concentration diffusion layers 22 and 23 are provided on both sides of the first n-type high-concentration diffusion layer 21, and on the first two poles, The second and third diodes are formed on both sides of the body. However, the n-type high-concentration diffusion layer connected to the input signal pad INP and the n-type high-concentration diffusion layer connected to the reference voltage pad VSP can also be arranged with each other. If so, it is connected to both sides of the n-type high-concentration diffusion layer of the wheel-in signal gasket INP to form a parasitic bipolar transistor, so the ability to absorb surge current can be improved. '(Third embodiment) Below, A third embodiment of the present invention will be described with reference to FIGS. 5 and 6. State protection circuit, however, in the third embodiment, for the first and second -14- ----- ^ 丨 丨 一; 11--ί -------- subscribe --- ------ (Please read the notes on the back first 'to fill in this page) This paper size applies the national standard (CNS) A4 (210x 297 mm). Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 409396 Λ7 ------- 1_ B7______ 5. Description of the invention (12) The components of the embodiment are given the same symbols to omit description. Fig. 5 shows a cross-sectional structure of a semiconductor device of the third embodiment, Fig. 6 shows a planar structure of the semiconductor device of the second embodiment, and Fig. 5 is a cross-sectional view taken along the line V-V in Fig. 6. As shown in FIG. 5, as in the second embodiment, an i-type high-concentration diffusion layer 21 is formed on a P-type semiconductor substrate 10 connected to a reference voltage, and at the same time, two of the first n-type high-concentration diffusion layer 2 are formed. On the other hand, a second high-concentration diffusion layer 22 and a third n-type high-concentration diffusion layer 23 are formed. Moreover, both end portions of the first metal layer 51 are connected to the input pad INp, and at the same time, the central portion is connected to the first !!-type high-concentration diffusion layer through the resistance conductive layer 60? !! Connected, both ends of the second metal layer 52 are connected to the reference voltage diaphragm vsp, while the central portion is connected to the second n-type high-concentration diffusion layer 22, and both ends of the third metal layer 53 are connected to the reference At the same time, the voltage pad vsp is connected to the central portion and the third n-type high-concentration diffusion layer 23. The first metal layer 51 is connected to the input pad iNρ via the first metal wiring 81, and the third metal layer 53 is connected to the reference voltage pad VSP via the second metal wiring 82. The second metal layer 52 is connected to the reference voltage-hardened sheet VSP via the second metal wiring 82, but the illustration is omitted. The third embodiment is characterized in that a p-type high-concentration diffusion layer 91 having a square frame shape is formed on the p-type semiconductor substrate 10 so as to surround the first, second, and third n-type (¾concentration diffusion potential 21 '22, 23. At the same time, a fourth metal layer M is formed on the p-type high-concentration diffusion layer 91, and the fourth metal layer 54 is connected to the reference voltage pad VSP β through the second metal wiring 82. A square frame-shaped fourth η-type high-concentration diffusion layer 24 is formed on the outer side of the high-type high-concentration diffusion layer 91, and a fourth η-type high-concentration diffusion layer 24 is formed at the same time. -15- This paper applies Chinese National Standard (CNS) A4 Specifications (210 X 297 Gt) J:-^ --- I--I --------- ^ ί Jingxian first read the notes on the back. Fill out this page > Intellectual Property Bureau, Ministry of Economic Affairs Printed by employee consumer cooperative A7 B7 V. Invention description (13) A fifth metal layer 55 is formed on the upper side. The fifth metal layer 55 makes the fourth n-type high-concentration diffusion layer 24 higher than the reference voltage Vss. Voltage, such as the electrical connection of the high-potential pad VDP to which the power supply voltage Vdd is applied. Apply the input voltage Vs to the entire input INP from the input circuit or input / output circuit. When s is still low, electrons flow from the first n-type high-concentration diffusion layer 21 or the first n-type low-concentration diffusion layer 31 into the p-type semiconductor substrate 10. If electrons flow into the p-type semiconductor substrate 10, the p-type semiconductor substrate The potential of 10 may be completely changed, and at the same time, the electrons flowing into the p-type semiconductor substrate 10 may diffuse to other semiconductor elements formed on the p-type semiconductor substrate 10, which may cause malfunction of other semiconductor elements. However, in the first In the third embodiment, n-type high-concentration diffusion layers 2, 22, and 23 are formed to surround the first, second, and third, and a p-type high-concentration diffusion layer 91 connected to the reference voltage pad VSP is formed and flows into The electron system of the p-type semiconductor substrate 10 flows to the reference voltage pad VSP through the p-type high-concentration diffusion layer 91. Therefore, when the input pad 1NP has a voltage lower than the reference voltage Vss, the p-type semiconductor substrate 10 can also be prevented In the third embodiment, on the outside of the p-type high-concentration diffusion layer 91, a fourth n-type high-concentration high-potential pad VDP connected to a high-potential pad VDP applied with a voltage higher than the reference voltage Vss is provided. Diffusion layer 24 and 4 The η-type low-concentration diffusion layer 34, so the electrons flowing into the p-type semiconductor substrate 10 will pass through the empty layer formed near the 4th η-type high-concentration diffusion layer 24 or the 4th η-type and high-concentration diffusion layer 34. When the fourth n-type high-concentration diffusion layer 24 or the fourth n-type low-concentration diffusion layer 34 is introduced, it flows to the high-potential pad VDP, so when a voltage lower than the reference voltage Vss is applied to the input pad INP, Can also prevent other semiconductors -16- -------'--- ----------------- Order----line (please read the precautions on the back first ί script Page) · This paper & degree applies the national standard (CNS) A4 specification (210 X 297 mm) 409396 A7 r._ B7 V. Description of the invention (14) The situation that the file caused the malfunction β At this time, it is true The electrons flowing from the ^ -type low-concentration diffusion layer 31 into the p-type semiconductor substrate 10 are introduced into the ^ -type ^ -type low-concentration diffusion layer 34, and the fourth η-type low-concentration diffusion layer 34 should have the same as the ^ The type low-concentration diffusion layer 31 has a depth of the same degree or more. In the third embodiment, although the 4m-type ytterbium-concentration diffusion layer μ and the 4 < n-type low-concentration diffusion layer 34 are provided on the outside of the p-type high-concentration diffusion layer 91, instead, only a A 4 in-type high-concentration diffusion layer or a 4th n-type low-concentration diffusion layer 34 is provided. At this time, it is preferable that the fourth tn-type high-concentration diffusion layer 24 or the fourth n-type low-concentration diffusion layer 34 has a depth equal to or greater than that of the first low-concentration diffusion layer 31. In addition, the ρ-type south concentration diffusion layer 91, the fourth η-type high concentration diffusion layer 24, and the fourth foot η-type low concentration diffusion layer 34 are respectively exposed to each other and can perform various functions, so they can be provided only. Have any—people. In the first to third embodiments, a high-resistance conductive layer 60 is provided between the itn-type high-concentration diffusion layer 21 and the first metal layer 51. However, the high-resistance conductive layer is provided at a position of 60. There is no special limitation, but the input gasket and the first! The n-type high-concentration diffusion layers 21 may be connected in series with the first metal layer 51. In addition, instead of providing the high-resistance conductive layer 60, the first high-concentration diffusion layer 21 and the first metal layer 51 may be directly connected. Furthermore, in the first to third embodiments, 'attached to a p-type semiconductor substrate], a first n-type high-concentration diffusion lip 21 and a second n-type high-concentration diffusion layer 22 (or a third n-type high-concentration diffusion layer 22) are provided on the substrate.咼 Concentration diffusion layer 23) and the first η-type low-concentration diffusion layer 31 and the second η-type low-concentration diffusion layer 32 (or the third η-type low-concentration diffusion layer 23), but may be replaced by η The type -17-type semiconductor substrate is provided with the -17- this paper standard common Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back first and fill in this page) -I Hua: t I5- Economy Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Du printed 409396 A7 _B7 V. Description of the invention (15) p-type high-concentration diffusion layer 1 and second p-type high-concentration diffusion layer (or The third p-type high-concentration diffusion layer) and the first p-type low-concentration diffusion layer and the second p-type low-concentration diffusion layer (or the third p-type low-concentration diffusion layer). (Effects of the Invention) According to the semiconductor device of the present invention, the resistance of the current flow path in a direction perpendicular to the main surface of the semiconductor substrate increases, so that when a positive surge voltage is applied to the entire input, the breakdown current does not occur. Partially concentrated in the area immediately below the first high-concentration diffusion layer, that is, the current density of the breakdown current flowing in the area under the first high-concentration diffusion layer becomes smaller, so the first high-concentration diffusion layer can be prevented. The PN junction with the semiconductor substrate is broken, and the first high-concentration diffusion layer itself is broken. The breakdown current is a current flow path that flows in a direction parallel to the main surface of the semiconductor substrate inside the first high-concentration diffusion layer than Xi. The semiconductor substrate is the first high-concentration diffusion layer and the second high-concentration diffusion. The bipolar current flowing from the parasitic bipolar transistor formed by the layer will increase, so the ability to absorb the surge current will be improved, and the surge withstand voltage of the semiconductor device will be increased. If the semiconductor device of the present invention includes a second conductivity type second high concentration diffusion layer in a region immediately below the second high concentration diffusion layer, the first high concentration diffusion layer and the first low concentration diffusion layer, and, The opposing areas of the second high-concentration diffusion layer and the second low-concentration diffusion layer will increase, so it is easy to form a parasitic bipolar transistor. Therefore, the bipolar transistor will increase, thereby absorbing the surge current. Further improvement. The semiconductor device of the present invention is formed on the opposite side of the second high-concentration diffusion layer with respect to the first high-concentration diffusion layer, and has a reference electric paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Mm)! 1.11! ----- install * ------- order --------- line (please read the notes on the back first κ write this page) f. Intellectual property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 409396 A7 II_B7 V. Description of the Invention (16) The third high-concentration diffusion layer of the second conductive type and the second conductive type formed in the area directly below the third high-concentration diffusion layer The third low-high-concentration diffusion layer includes a high-conductor substrate, and, the first high-concentration diffusion layer and the first low-concentration diffusion layer, and, the second high-concentration diffusion layer, and the third low-concentration diffusion layer. The first parasitic bipolar transistor constitutes a semiconductor substrate, and, the first high-concentration diffusion layer and the first low-concentration diffusion layer, and the third high-concentration diffusion layer and the third low. The concentration diffusion layer constitutes the second parasitic bipolar transistor. Therefore, when a positive surge voltage is applied to the input pad, the first and 2 of the parasitic bipolar transistor will be actuated, and a second bipolar current is diffused layer of a low-concentration diffusion layers on both sides in the flow from the first high concentration. Therefore, the ability to absorb the surge current will be doubled, so the surge withstand voltage of the semiconductor device will be greatly improved. The semiconductor device of the present invention is connected in series with the conductive layer between the input pad and the first high-concentration diffusion layer. If a high-resistance conductive layer having a higher resistance than the conductive layer is provided, the input pad and the parasitic Between the collectors of the electrode transistor, the resistance component is inserted in series, which can suppress the surge current flowing into the protection circuit, so it can more reliably prevent the PN junction damage between the first high-concentration diffusion layer and the semiconductor substrate and the first Destruction of the high-concentration diffusion layer itself. In the semiconductor device of the present invention, the first high-concentration diffusion layer has a non-opposing portion extending from an area facing the second high-concentration diffusion layer to the outside, and the conductive layer and the non-opposing portion are electrically-connected and electrically conductive. The impedance of the current flow path at the connection portion between the layer and the non-opposing portion of the first high-concentration diffusion layer is larger than the resistance of the current flow path through the connection portion of the conductive layer and the portion facing the first high-concentration diffusion layer. Inhibit the high-concentration diffusion through the conductive layer and the first -19- ιιί1-! ··! · Install ij—i — order · — line (please read the precautions on the back-write this page first), this paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 409396 A7 _B7 V. Description of the invention (17) The amount of current flowing in the current flow path of the connection part of the non-opposing part of the layer, and Alleviates current concentration in the current flow path. Therefore, local current concentration can be avoided, so that the connection portion between the conductive layer and the first high-concentration diffusion layer, and the first high-concentration diffusion layer can be prevented from being damaged, thereby increasing the surge withstand voltage of the semiconductor device. If the semiconductor device of the present invention includes a high-concentration diffusion layer of the first conductivity type that is formed in a region surrounding the first high-concentration diffusion layer and the second high-concentration diffusion layer, and can apply a reference voltage, the input pad can be used. When a voltage lower than the reference voltage is applied, even if electrons flow into the semiconductor substrate, the flowing electrons flow to the reference voltage side through the high-concentration diffusion layer of the first conductivity type, so that the potential variation of the semiconductor substrate can be prevented. If the semiconductor device of the present invention includes an impurity diffusion layer of the second conductivity type formed in a region surrounding the first high-concentration diffusion layer and the second high-concentration diffusion layer and applying a voltage higher than the reference voltage, The input pad applies a voltage lower than the reference voltage. Even if the electrons flow into the semiconductor substrate, the flowing electrons are introduced into the second conductivity type impurity diffusion layer and then flow to the high-voltage side. This prevents other semiconductor devices from causing malfunctions. (Brief Description of the Drawings) Fig. 1 is a sectional view of a semiconductor device according to a first embodiment. Fig. 2 is an equivalent circuit diagram of a protection circuit realized by the semiconductor device of the first embodiment. -Fig. 3 is a cross-sectional view of a semiconductor device according to a second embodiment, and is a cross-sectional view taken along the line III-III in Fig. 4. Fig. 4 is a plan view of a semiconductor device according to a second embodiment. -20- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------- r ---- packing ------------ order *- ------ (Please read the notes on the back first to write this page), printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 409396 A7 _B7 V. Description of the invention (18) Figure 5 shows the semiconductor device of the third embodiment. The cross-sectional view is a cross-sectional view taken along the line V-V in FIG. 6. Fig. 6 is a plan view of a semiconductor device according to a third embodiment. FIG. 7 is a cross-sectional view of a conventional semiconductor device. [Description of Symbols] 10 p-type semiconductor substrate 21 First η-type high-concentration diffusion layer 21a Non-opposing portion 22 Second η-type high-concentration diffusion layer 23 Third η-type high-concentration diffusion layer 24 Fourth η-type High-concentration diffusion layer 31 First η-type low-concentration diffusion layer 32 Second η-type low-concentration diffusion layer 33 Third η-type low-concentration diffusion layer 34 Fourth η-type low-concentration diffusion layer 40 Field oxide film 41 Section 1st interlayer insulation film 42 2nd interlayer insulation film 51 1st metal layer 52 2nd metal layer 53 3rd metal layer 54 4th metal layer 55 5th metal layer 60 high-resistance conductive layer-21-This paper size applies to China National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the notes on the back and write this page first) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 409396A7 _ 二 _B7 V. Description of Invention (19) 71 1 contact body 71a non-facing part contact body 72 second contact body 73 third contact body 81 first metal wiring 82 second metal wiring 91 p-type high-concentration diffusion layer LNP input pad VSP reference pad QP parasitic bipolar transistor QP1 parasitic bipolar transistor QP2 parasitic second Pole transistor (Please read the notes written on the back of this page) -22- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)