堉請tw明示'^年月*=^!坼提之 佟正本有無^眷^!>,;-.;:-;;--.':-'...;'.-.;&予.：^正。 經濟部中央標準局只工消费合作社印裝 年y月j日修正/要逢 第謂519號專繼明紐正頁、修正晴職28 S- 4謹01______________丨 — 五 '發明説明（2) 步階覆蓋能力的問題’並不易將介電層完全填滿溝槽， 導致元件的隔離效果受到影響。 為改善上述問題，一種高密度電漿化學氣相沈積 (HDPCVD)技術被提出’其主要以氧（〇2)和矽甲烷（3出4) 當作反應物來沈積介電層，同時以氬（Ar)電黎藏擊 (sputter)清除溝槽側壁上半部介電層的突出部 (overhang)，可排除沈積時的障礙，達到改善介電層填入 溝槽的效果。為了進一步清楚說明該技術的内容，以下 即參照第1A至1C圖’說明其製造流程。 首先，請參見第1A圖，在一半導體基底1〇上形成 一遮蔽層，例如是在一矽晶圓表面上，以化學氣相沈積 法（CVD)或熱氧化成長法形成一厚度介於5〇A和2〇〇入 的墊氧化層咖£1(^£16&61*)12，然後在墊氧化層12表面 上，以CVD法沈積一厚度介於5〇〇 A和2〇〇〇 A的氮 化石夕層14，二者共同構成遮蔽層。接著，以微影成像 (photolithography)和蝕刻程序，定義出氮化矽層14和墊 氧化層12的圖案，用以露出半導體基底1〇欲形成元件 隔離區的部分。 其次，請參見第1B圖，利用化矽層14和墊氧化層 12的圖案當作罩幕’施行一蝕刻程序而在半導體基底1〇 上形成溝槽15，其深度介於35〇〇 a和5〇〇〇 A之間。 然後’以熱氧化程序（thermal oxidation)成長一薄氡化層 16，覆蓋在溝槽15的底部和側壁上，用以當作襯裡 (liner)，其厚度約為。接著，施行高密度電漿化 本紙張尺度適用中國國家標準（ CNS ) ( 210χ297λ>^. A7 4〇40〇i 五、發明説明（i ) ' 本發明係有關於半導體積體電路的製造，且特別是 有關於一種改良式高密度電漿化學氣相沈積技術形成淺 溝槽隔離區（shallow trench isolation)之製程，以改善介電 層填入溝槽的效果’並避免產生溝槽側壁損傷和金屬污 染等影響元件性質的問題。 近年來’隨著半導體積體電路製造技術的發展，晶 片中所含元件的數量不斷增加，元件的尺寸也因積集度 的提昇而不斷地縮小’生產線上使用的線路寬度已進入 了次微米的細小範圍。然而’無論元件尺寸如何縮小化， 在晶片中各個元件之間仍必須有適當地絕緣或隔離，方 可得到良好的元件性質。這方面的技術一般稱為元件隔 離技術（device isolation technology) ’其主要目的係在各 元件之間形成隔離物，並且在確保良好隔離效果的情況 下’儘量縮小隔離物的區域，以空出更多的晶片面積來 容納更多的元件。 在各種元件隔離技術中，局部矽氧化方法（L〇c〇s) 和淺溝槽隔離區（shallow trench isolation)製程是最常被 採用的兩種技術’尤其後者具有隔離區域小和完成後仍 保持基底平坦性等優點，更是近來頗受重視的半導體製 造技術。傳統上’係先利用化學氣相沈積（CVD)程序，形 成一介電層以填入基底的溝槽中，之後再回餘刻（etch back)或是以化學性機械研磨程序（CMP)去除表面多餘的 介電層’以完成溝槽隔離區製程。但隨著積體電路密度 不斷提高而元件尺寸日漸縮小的發展，上述沈積技術因 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 、-口 經濟部中央標準局員工消費合作杜印製 堉請tw明示'^年月*=^!坼提之 佟正本有無^眷^!>,;-.;:-;;--.':-'...;'.-.;&予.：^正。 經濟部中央標準局只工消费合作社印裝 年y月j日修正/要逢 第謂519號專繼明紐正頁、修正晴職28 S- 4謹01______________丨 — 五 '發明説明（2) 步階覆蓋能力的問題’並不易將介電層完全填滿溝槽， 導致元件的隔離效果受到影響。 為改善上述問題，一種高密度電漿化學氣相沈積 (HDPCVD)技術被提出’其主要以氧（〇2)和矽甲烷（3出4) 當作反應物來沈積介電層，同時以氬（Ar)電黎藏擊 (sputter)清除溝槽側壁上半部介電層的突出部 (overhang)，可排除沈積時的障礙，達到改善介電層填入 溝槽的效果。為了進一步清楚說明該技術的内容，以下 即參照第1A至1C圖’說明其製造流程。 首先，請參見第1A圖，在一半導體基底1〇上形成 一遮蔽層，例如是在一矽晶圓表面上，以化學氣相沈積 法（CVD)或熱氧化成長法形成一厚度介於5〇A和2〇〇入 的墊氧化層咖£1(^£16&61*)12，然後在墊氧化層12表面 上，以CVD法沈積一厚度介於5〇〇 A和2〇〇〇 A的氮 化石夕層14，二者共同構成遮蔽層。接著，以微影成像 (photolithography)和蝕刻程序，定義出氮化矽層14和墊 氧化層12的圖案，用以露出半導體基底1〇欲形成元件 隔離區的部分。 其次，請參見第1B圖，利用化矽層14和墊氧化層 12的圖案當作罩幕’施行一蝕刻程序而在半導體基底1〇 上形成溝槽15，其深度介於35〇〇 a和5〇〇〇 A之間。 然後’以熱氧化程序（thermal oxidation)成長一薄氡化層 16，覆蓋在溝槽15的底部和側壁上，用以當作襯裡 (liner)，其厚度約為。接著，施行高密度電漿化 本紙張尺度適用中國國家標準（ CNS ) ( 210χ297λ>^. A7 404001 五、發明説明（3 ) 學氣相沈積程序，例如使用 便用〇2和S1H4當作反應物，同時 施以Ar電漿濺擊而沈藉— ^ 叩疋積介電層18，填滿溝槽15以形 成一元件隔離區，得到如第^圖所示之 ^^1 —^1» I— nf —^1 ______一―> 采 ,17 (請先閲讀背面之注意事項再填寫本頁) 很明顯地’如第1 C阁私Sk - h C圖所顯示者，在沈積過程中同時 施行Ar電聚濺擊，可清除溝槽側壁上半部介電層的突出 部（ον118)，使得介電層18不會因步階覆蓋不佳而產 生孔洞，因此能有效改善介電層填入溝槽的效果。然而， 高密度電聚化學氣相沈積程序中的Arf；装滅擊，卻也容 易造成溝槽侧壁的損傷（sidewaU如则㈣和金屬雜質的 污染，帶來影響元件性質的新問題。 有鑑於此，本發明之-個目的，在提供-種改良式 半導體元件隔離製程的’其可改善介電層填入溝槽的能 力，提昇元件的性質。 本發明另一個目的，在提供一種高密度電漿化學氣 相沈積技術形成淺溝槽隔離區之製程的改良，其可避免 造成溝槽侧壁損傷和金屬雜質污染等問題。 經濟部中央標準局貝工消费合作社印袋 為了達成上述目的，本發明提出一種改良式淺溝槽 隔離區之製造方法，其在施行高密度電漿化學氣相沈積程 序之前，先利用較溫和的沈積程序形成一介電材料底層， 以提昇覆蓋均一性並保護溝槽的側壁。藉此，除了可保有 高密度電漿化學氣相沈積程序的良好溝槽填入效果，並可 進一步避免溝槽側壁損傷和金屬雜質污染的問題。 更詳言之，本發明提出一種高密度電漿化學氣相沈 積技術形成淺溝槽隔離區之製程的改良，包括下列步 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）堉 Please tw clearly indicate '^ 年月 * = ^! 坼 提 之 佟 佟 有 本原 ^ 眷 ^ &&;;;-.;:-;;-.':-'...;'.-.; &Amp; ..: ^ Positive. Revised by the Central Standards Bureau of the Ministry of Economic Affairs only for the printing of consumer cooperatives on the date of y / j / Y / Y every month, the original page of the No. 519 special post Ming and New York, revised the post 28 S- 4 01____________ 丨-Five 'invention description (2) The problem of step coverage capability is that it is not easy to completely fill the trench with the dielectric layer, and the isolation effect of the device is affected. In order to improve the above problems, a high-density plasma chemical vapor deposition (HDPCVD) technology is proposed. 'It mainly uses oxygen (0 2) and silicon methane (3 out 4) as the reactants to deposit the dielectric layer, while using argon (Ar) Electro-spraying (sputter) removes the overhang of the dielectric layer on the upper half of the trench sidewall, which can eliminate obstacles during deposition and achieve the effect of filling the trench with the dielectric layer. To further clarify the content of this technology, the manufacturing process will be described below with reference to FIGS. 1A to 1C. First, referring to FIG. 1A, a shielding layer is formed on a semiconductor substrate 10, for example, on a silicon wafer surface, a thickness of between 5 and 5 is formed by chemical vapor deposition (CVD) or thermal oxidation growth. 〇A and 2000 入 of the pad oxide layer £ 1 (^ £ 16 & 61 *) 12, and then deposited on the surface of the pad oxide layer 12 by CVD method to a thickness between 500A and 2000. The nitride nitride layer 14 of A, the two together constitute a shielding layer. Next, a pattern of the silicon nitride layer 14 and the pad oxide layer 12 is defined by photolithography and etching procedures to expose the portion of the semiconductor substrate 10 where the device isolation region is to be formed. Secondly, referring to FIG. 1B, the pattern of the siliconized layer 14 and the pad oxide layer 12 is used as a mask to perform an etching process to form a trench 15 on the semiconductor substrate 10 to a depth of 3500a and Between 5000A. Then, a thin etched layer 16 is grown by a thermal oxidation process, covering the bottom and sidewalls of the trench 15 and used as a liner with a thickness of about. Next, the implementation of high-density plasmaization of this paper applies the Chinese National Standard (CNS) (210x297λ > ^. A7 4040). 5. Description of the Invention (i) 'The present invention relates to the manufacture of semiconductor integrated circuits, and In particular, it relates to a process for forming a shallow trench isolation region using an improved high-density plasma chemical vapor deposition technology to improve the effect of the dielectric layer filling the trenches, and to avoid damage to the trench sidewalls and Problems that affect the properties of components such as metal contamination. In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in wafers has continued to increase, and the size of components has been continuously reduced due to the increase in the degree of accumulation. The used line width has entered a fine range of sub-micron. However, no matter how the size of the component is reduced, there must still be proper insulation or isolation between the various components in the wafer to obtain good component properties. Techniques in this regard Generally referred to as device isolation technology (device isolation technology) 'The main purpose is to form a spacer between components, And in the case of ensuring a good isolation effect, 'the area of the spacer is minimized, and more components are vacated to accommodate more components. Among various component isolation technologies, the local silicon oxidation method (Locos) And shallow trench isolation (Shallow Trench Isolation) process is the two most commonly used technologies' especially the latter has the advantages of a small isolation area and maintains the flatness of the substrate after completion, etc., is a semiconductor manufacturing technology that has received much attention recently. Traditionally, a chemical vapor deposition (CVD) process is used to form a dielectric layer to fill the trenches of the substrate, and then it is etched back or removed by a chemical mechanical polishing process (CMP). The excess dielectric layer on the surface is used to complete the trench isolation region process. However, as the integrated circuit density continues to increase and the component size is gradually shrinking, the above deposition technology is applicable to the Chinese National Standard (CNS) A4 specification for this paper scale ( 210X297 mm) (Please read the precautions on the back before filling out this page) 、 -Printed by the consumer cooperation agreement of the Central Standards Bureau of the Ministry of Economy 堉 Please indicate '^ 年月 * = ^! 坼Is the original version of ^ ^ ^ ^! ≫,;-.;:-;;-. ': -'...;' .-.; &Amp; Y. ： ^ 正。 The Central Standards Bureau of the Ministry of Economic Affairs only works Revised / printed on the date of y / j / y of the consumer co-operative cooperatives. It is necessary to revise the main page of the No. 519 special Ming Ming New Page, and amend the sunny post 28 S-4. 01______________ 丨 Five. Description of the invention (2) The problem of step coverage ability. It is not easy to completely fill the trench with the dielectric layer, which affects the isolation effect of the device. In order to improve the above problem, a high-density plasma chemical vapor deposition (HDPCVD) technology is proposed, which mainly uses oxygen (〇2) and Silane (3 out of 4) is used as a reactant to deposit the dielectric layer, and at the same time, the upper part of the dielectric layer overhang on the trench sidewall is removed by argon (Ar) sputtering, which can eliminate the deposition Obstacles at the time can improve the effect of filling the trench with the dielectric layer. To further clarify the content of this technology, the manufacturing process will be described below with reference to FIGS. 1A to 1C. First, referring to FIG. 1A, a shielding layer is formed on a semiconductor substrate 10, for example, on a silicon wafer surface, a thickness of between 5 and 5 is formed by chemical vapor deposition (CVD) or thermal oxidation growth. 〇A and 2000 入 of the pad oxide layer £ 1 (^ £ 16 & 61 *) 12, and then deposited on the surface of the pad oxide layer 12 by CVD method to a thickness between 500A and 2000. The nitride nitride layer 14 of A, the two together constitute a shielding layer. Next, a pattern of the silicon nitride layer 14 and the pad oxide layer 12 is defined by photolithography and etching procedures to expose the portion of the semiconductor substrate 10 where the device isolation region is to be formed. Secondly, referring to FIG. 1B, the pattern of the siliconized layer 14 and the pad oxide layer 12 is used as a mask to perform an etching process to form a trench 15 on the semiconductor substrate 10 to a depth of 3500a and Between 5000A. Then, a thin etched layer 16 is grown by a thermal oxidation process, covering the bottom and sidewalls of the trench 15 and used as a liner with a thickness of about. Next, the high-density plasma is applied to this paper. The standard of China paper (CNS) (210x297λ > ^. A7 404001) V. Description of the invention (3) Learn the vapor deposition process. For example, use 〇2 and S1H4 as reactants. At the same time, the Ar plasma was used to splash and sink — ^ The dielectric layer 18 was filled, and the trench 15 was filled to form an element isolation region, and ^^ 1 — ^ 1 »as shown in the figure ^ was obtained. — Nf — ^ 1 ______ 一 — > Mining, 17 (please read the precautions on the back before filling this page) It is obvious that 'as shown in the first Sk-h C chart in the private room of the 1st C Pavilion, during the accumulation process At the same time, the Ar electrosputtering can be used to remove the protruding portion (ον118) of the dielectric layer in the upper half of the trench sidewall, so that the dielectric layer 18 will not generate holes due to poor step coverage, so the dielectric layer can be effectively improved. The effect of filling the trench. However, Arf in the high-density electropolymerization chemical vapor deposition process; loading and extinguishing, it is also easy to cause damage to the sidewall of the trench (sidewaU and other metal impurities pollution, which will affect the In view of this, an object of the present invention is to provide an improved half-type The conductor element isolation process can improve the ability of the dielectric layer to fill the trench and enhance the properties of the element. Another object of the present invention is to provide a process for forming a shallow trench isolation region with a high-density plasma chemical vapor deposition technology. In order to achieve the above-mentioned object, the present invention proposes an improved method for manufacturing a shallow trench isolation zone. Before performing the high-density plasma chemical vapor deposition process, a milder deposition process is used to form a bottom layer of a dielectric material to improve uniformity of coverage and protect the sidewalls of the trenches. In addition to maintaining a high-density plasma, The good trench filling effect of the chemical vapor deposition process can further avoid the problems of trench sidewall damage and metal impurity pollution. More specifically, the present invention proposes a high-density plasma chemical vapor deposition technology to form shallow trenches. The improvement of the manufacturing process of the quarantine area, including the following steps. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm
Ff年f月彳曰修正'·是壬Λ - ,Γ …一— 4 驟：形成-遮蔽層於-半導體基底表面上；定義出遮蔽 層的圖案，露出半導體基底欲形成元件隔離區的部分； 利用遮蔽層當作罩幕，㈣半導體基底以形成溝槽；施 行一熱氧化程序成長一薄氧化層，覆蓋於溝槽的底部和 側壁上；施行一溫和的沈積程序以形成一介電材料底 層，覆蓋在薄氧化層和遮蔽層之表面上；以及施行一高 密度電漿化學氣相沈積程序形成一介電層，用以填滿溝 槽而完成淺溝槽隔離區之製程。 根據本發明的較佳實施例，上述遮蔽層係包括一墊 氧化層和一氮化矽層；而製程中所述溫和的沈積程序， 疋_人常壓化學氣相沈積程序，例如於溫度約為 480°C、壓力約為60T〇rr條件下，利用臭氧加四乙氧基 石夕甲燒^作原料，以沈積形成一氧化物層當作上述之介 電材料底層，其厚度介於300 A和1〇〇〇 A之間；至於 局密度電漿化學氣相沈積程序，則係使用〇2和SiH4當 作反應物，並施以Ar電漿濺擊來沈積形成介電層。 為讓本發明之上述目的、特徵、和優點能更明顯易 經濟部中央標隼而負工消费合作社印策 (誚先閱讀背而之注意事項沔項艿本頁Ff year f month 彳 said the correction '· is non Λ-, Γ… one-4 steps: forming-the shielding layer on the surface of the-semiconductor substrate; defining the pattern of the shielding layer, exposing the part of the semiconductor substrate that is to form the element isolation area; Use a masking layer as a mask to pierce the semiconductor substrate to form a trench; perform a thermal oxidation process to grow a thin oxide layer covering the bottom and sidewalls of the trench; perform a gentle deposition process to form a dielectric substrate Covering the surface of the thin oxide layer and the shielding layer; and performing a high-density plasma chemical vapor deposition process to form a dielectric layer for filling the trench to complete the shallow trench isolation region process. According to a preferred embodiment of the present invention, the above-mentioned shielding layer includes a pad oxide layer and a silicon nitride layer; and the gentle deposition process described in the manufacturing process is a normal atmospheric chemical vapor deposition process, for example, at a temperature of about Under the conditions of 480 ° C and a pressure of about 60 Torr, ozone was used as a raw material for the formation of an oxide layer as the above-mentioned dielectric material, and the thickness was between 300 A and 300 Å. Between 100A and 1000A; as for the local density plasma chemical vapor deposition process, 02 and SiH4 are used as reactants, and Ar plasma sputtering is applied to form a dielectric layer. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious, the Ministry of Economic Affairs and the Central Government have set a policy for the consumer cooperatives.
,1T 崠 僅’下文特舉一較佳實施例’並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A至1C圖均為剖面圖，繪示以習知高密度電 楽化學氣相沈積技術形成淺溝槽隔離區的製造流程；以及 第2A至2C圖均為剖面圖，繪示根據本發明改良 方法一較佳實施例的製造流程。 A7 404001 五、發明説明（5 ) 實施例 n m I I --1 I - I 1 - I I - I 1 I、1T . β I (請先閲讀背面之注意事項再填寫本頁) 首先，知參見第2A圖，在一半導體基底2〇上形成 —遮蔽層，例如是在一矽晶圓表面上，以CVD法或熱氧 化成長法形成一厚度介於5〇 A和2〇〇人的墊氧化層 22，然後在墊氧化層22表面上，以cvd法沈積一厚度 介於500 A和2000 A的氮化矽層24。接著，以微影成 像和钮刻程序，疋義出氮化石夕層24和塾氧化層的圖 案，用以露出半導體基底2〇欲形成元件隔離區的部分。 其次，利用化矽層24和墊氧化層22的圖案當作罩 幕’施行一蝕刻程序而在半導體基底2〇上形成溝槽25， 其深度介於3500 A和5000 A之間。之後，以熱氧化程 序成長一薄氧化層26，覆蓋在溝槽25的底部和側壁上， 其厚度約為180 A 。 經濟部中央標牟局貝工消費合作杜印製 接著’ s青參見第2B圖’以溫和的沈積程序在薄氧化 層26和遮蔽層22、24表面上形成一介電材料底層27， 其厚度介於300 A和1000 A之間。例如，使用臭氧（〇3) 和四乙氧基矽甲烷（TEOS)當作原料，於溫度約為 480°C、壓力約為60Torr條件下，施行一次常壓化學氣 相沈積程序（SAC VD)而形成一氧化物層，均可用以形成 上述介電材料底層（underlayer)27。 接下來，為了進一步提昇底層27的抗蝕刻能力，可 増加施行一密化處理（densification)，例如，於溫度i〇〇〇°C 條件下，加熱處理約2小時處理後，即可使介電材料底 層27的結構更形敏密而对姓刻。之後。請參見第2C圖， -8- 本紙張尺度適用中國國家標準（CNS ) A## ( 210X297公釐） 經濟部中央標隼局員工消費合作社印製 404001 五'發明説明（6) 施行高密度電漿化學氣相沈積程序（HDpcvD)，例如使用 〇2和SiH4當作反應物，同時施以Ar電漿濺擊而沈積一 介電層28’藉以填滿溝槽25而形成所需之元件隔離區， 元成依據本發明改良製程一較佳實施例的製造。由於上 述經密化處理後的介電材料底層27，具有與高密度電漿 化學氣相沈積之介電層28相若的蝕刻率，因此在平坦化 製程之蝕刻或研磨程序後，並不會造成溝槽側壁凹陷的 問題。 與習知技術相比較，本發明高密度電漿化學氣相沈 積技術形成淺溝槽隔離區之改良製程，具有許多下列優 點：首先，由於在進行高密度電漿化學氣相沈積程序之 前，先形成一介電材料底層，可防止溝槽側壁在後續高 密度電漿化學氣相沈積程序時受到損傷，有助於提昇元 件性質。其次，由於上述介電材料底層係利用較溫和之 沈積程序所形成的，可避免電漿程序造成金屬雜質的污 染。再者’經密化處理後的介電材料底層，其抗蝕刻能 力已大幅提再至與高密度電漿化學氣相沈積程序者相 當’因此即使後續為去除遮蔽層中之墊氧化層，而將矽 晶圓浸泡於蝕刻液中’也不致於發生因抗蝕刻能力差異 而在溝槽邊緣產生非期望之凹陷的問題。 本發明雖以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之 精神和範圍内，當可作些許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) '-0, 1T 崠 only 'a preferred embodiment is given below' in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Figures 1A to 1C are cross-sectional views, which are shown in the conventional high-density electricity (2) A manufacturing process for forming a shallow trench isolation region by chemical vapor deposition; and FIGS. 2A to 2C are cross-sectional views illustrating a manufacturing process according to a preferred embodiment of the improved method of the present invention. A7 404001 V. Description of the invention (5) Example nm II --1 I-I 1-II-I 1 I, 1T. Β I (Please read the precautions on the back before filling this page) First, please refer to Section 2A In the figure, a shielding layer is formed on a semiconductor substrate 20, for example, a pad oxide layer 22 having a thickness of 50 A and 200 people is formed on the surface of a silicon wafer by a CVD method or a thermal oxidation growth method. Then, a silicon nitride layer 24 with a thickness of 500 A and 2000 A is deposited on the surface of the pad oxide layer 22 by cvd method. Then, using lithography and button-engraving procedures, the patterns of the nitride nitride layer 24 and the hafnium oxide layer are defined to expose the portion of the semiconductor substrate 20 where the device isolation region is to be formed. Secondly, a trench 25 is formed on the semiconductor substrate 20 by performing an etching process using the patterns of the siliconized layer 24 and the pad oxide layer 22 as a mask 'to a depth between 3500 A and 5000 A. After that, a thin oxide layer 26 is grown by a thermal oxidation process, covering the bottom and sidewalls of the trench 25, with a thickness of about 180 A. Printed by the Ministry of Economic Affairs of the Central Bureau of Standardization of the Ministry of Economic Affairs of the People's Republic of China, and then printed on the surface of the thin oxide layer 26 and the shielding layers 22 and 24 with a gentle deposition process. Between 300 A and 1000 A. For example, using ozone (〇3) and tetraethoxysilylmethane (TEOS) as raw materials, at a temperature of about 480 ° C and a pressure of about 60 Torr, an atmospheric pressure chemical vapor deposition process (SAC VD) is performed. The formation of an oxide layer can be used to form the underlayer 27 of the dielectric material. Next, in order to further improve the etching resistance of the bottom layer 27, a densification may be performed. For example, at a temperature of 1000 ° C, a heat treatment may be performed for about 2 hours to make the dielectric The structure of the material bottom layer 27 is more intimate and engraved with the surname. after that. Please refer to Figure 2C. -8- This paper size applies Chinese National Standard (CNS) A ## (210X297 mm) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 404001 Five 'Invention Description (6) Implementation of high-density plasma A chemical vapor deposition process (HDpcvD), for example, using O 2 and SiH 4 as reactants, and simultaneously applying an Ar plasma sputtering to deposit a dielectric layer 28 ′ to fill the trench 25 to form a desired element isolation region Yuan Cheng manufactures according to a preferred embodiment of the improved process of the present invention. Since the above-mentioned densified base material layer 27 has an etching rate similar to that of the high-density plasma chemical vapor deposition of the dielectric layer 28, it will not change after the etching or grinding process of the planarization process. Causes the problem of recessed sidewalls. Compared with the conventional technology, the improved process of forming the shallow trench isolation region by the high-density plasma chemical vapor deposition technology of the present invention has many advantages as follows: first, before the high-density plasma chemical vapor deposition process is performed, Forming a bottom layer of a dielectric material can prevent the sidewalls of the trench from being damaged during the subsequent high-density plasma chemical vapor deposition process and help improve the properties of the device. Secondly, since the underlying layer of the dielectric material is formed by a gentler deposition process, the contamination of metal impurities caused by the plasma process can be avoided. Furthermore, 'the densification of the bottom layer of the dielectric material after the densification process has been substantially improved to that of a high-density plasma chemical vapor deposition process'. Therefore, even if the subsequent step is to remove the pad oxide layer in the shielding layer, and Immersion of the silicon wafer in the etching solution does not cause the problem of undesired depressions at the edge of the trench due to the difference in the resistance to etching. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) '-0