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TW366565B - Manufacturing method of damascene interconnect structures - Google Patents

Manufacturing method of damascene interconnect structures

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Publication number
TW366565B
TW366565B TW087105025A TW87105025A TW366565B TW 366565 B TW366565 B TW 366565B TW 087105025 A TW087105025 A TW 087105025A TW 87105025 A TW87105025 A TW 87105025A TW 366565 B TW366565 B TW 366565B
Authority
TW
Taiwan
Prior art keywords
dielectric layer
interconnect
cavities
interconnect structure
layer
Prior art date
Application number
TW087105025A
Other languages
Chinese (zh)
Inventor
Cheng-Tung Lin
Yu-Hua Lee
Jen-Ming Huang
James Wu
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Priority to TW087105025A priority Critical patent/TW366565B/en
Application granted granted Critical
Publication of TW366565B publication Critical patent/TW366565B/en

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Abstract

Manufacturing method of damascene interconnect structures, including the following steps: provision of a substrate having interconnect structures, for depositing a first dielectric layer and a second dielectric layer on top of the substrate accordingly for interlayer dielectric layer covering the interconnect structure. Then defining a dielectric window pattern, with etching of the interlayer dielectric layer for forming of cavities exposing the interconnect structure. Then coating an anti-reflection layer for covering of the interlayer dielectric layer with stuffing of the cavities, then defining an interconnect structure pattern on which basis etching the anti-reflective layer and the second dielectric layer for forming the interconnect cavities. Removal of the remaining anti-reflection layer from the interlayer dielectric layer and in the cavity and having the cavity in the first dielectric layer as dielectric window, for forming another metal interconnect structure for stuffing of the dielectric layer and the interconnect cavities as a damascene interconnect structure.
TW087105025A 1998-04-02 1998-04-02 Manufacturing method of damascene interconnect structures TW366565B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW087105025A TW366565B (en) 1998-04-02 1998-04-02 Manufacturing method of damascene interconnect structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087105025A TW366565B (en) 1998-04-02 1998-04-02 Manufacturing method of damascene interconnect structures

Publications (1)

Publication Number Publication Date
TW366565B true TW366565B (en) 1999-08-11

Family

ID=57941147

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087105025A TW366565B (en) 1998-04-02 1998-04-02 Manufacturing method of damascene interconnect structures

Country Status (1)

Country Link
TW (1) TW366565B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732326B2 (en) 2004-02-25 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732326B2 (en) 2004-02-25 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
US8053359B2 (en) 2004-02-25 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method

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