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TW364976B - Input operand control in data processing systems - Google Patents

Input operand control in data processing systems

Info

Publication number
TW364976B
TW364976B TW085112296A TW85112296A TW364976B TW 364976 B TW364976 B TW 364976B TW 085112296 A TW085112296 A TW 085112296A TW 85112296 A TW85112296 A TW 85112296A TW 364976 B TW364976 B TW 364976B
Authority
TW
Taiwan
Prior art keywords
input operand
bit
size
data processing
flag indicating
Prior art date
Application number
TW085112296A
Other languages
Chinese (zh)
Inventor
Simon J Glass
David V Jaggar
Original Assignee
Arm Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9619826A external-priority patent/GB2317467B/en
Application filed by Arm Corp filed Critical Arm Corp
Application granted granted Critical
Publication of TW364976B publication Critical patent/TW364976B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

A data processing system having a plurality of registers and an arithmetic logic units includes program instruction words having a source register bit field Sn specifying one of the registers storing an input operand data word together with an input operand size flag indicating whether the input operand has an N-bit size or (N/2)-bit size together with a high/low location flag indicating which of the high order bit positions or low order bit positions stores the input operand if it is of the smaller size. It is preferred that the arithmetic logic unit is also able to perform parallel operation program instruction words operating independently upon (N/2)-bit input operand data words stored in respective halves of a register.
TW085112296A 1996-09-23 1996-10-08 Input operand control in data processing systems TW364976B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9619826A GB2317467B (en) 1996-09-23 1996-09-23 Input operand control in data processing systems

Publications (1)

Publication Number Publication Date
TW364976B true TW364976B (en) 1999-07-21

Family

ID=10800363

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085112296A TW364976B (en) 1996-09-23 1996-10-08 Input operand control in data processing systems

Country Status (7)

Country Link
EP (1) EP0927391A1 (en)
JP (1) JP3645574B2 (en)
KR (1) KR20000048531A (en)
CN (1) CN1226325A (en)
IL (1) IL127291A0 (en)
MY (1) MY133769A (en)
TW (1) TW364976B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7292586B2 (en) * 2001-03-30 2007-11-06 Nokia Inc. Micro-programmable protocol packet parser and encapsulator
JP3857614B2 (en) 2002-06-03 2006-12-13 松下電器産業株式会社 Processor
US7668897B2 (en) 2003-06-16 2010-02-23 Arm Limited Result partitioning within SIMD data processing systems
GB2409062C (en) * 2003-12-09 2007-12-11 Advanced Risc Mach Ltd Aliasing data processing registers
GB2409059B (en) * 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
GB2409066B (en) * 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
US7437541B2 (en) * 2004-07-08 2008-10-14 International Business Machiens Corporation Atomically updating 64 bit fields in the 32 bit AIX kernel
US8914619B2 (en) * 2010-06-22 2014-12-16 International Business Machines Corporation High-word facility for extending the number of general purpose registers available to instructions
CN107908427B (en) * 2011-12-23 2021-11-09 英特尔公司 Instruction for element offset calculation in multi-dimensional arrays
CN108304217B (en) * 2018-03-09 2020-11-03 中国科学院计算技术研究所 Method for converting long-bit-width operand instructions to short-bit-width operand instructions
CN111459546B (en) * 2020-03-30 2023-04-18 芯来智融半导体科技(上海)有限公司 Device and method for realizing variable bit width of operand

Also Published As

Publication number Publication date
KR20000048531A (en) 2000-07-25
CN1226325A (en) 1999-08-18
EP0927391A1 (en) 1999-07-07
JP3645574B2 (en) 2005-05-11
IL127291A0 (en) 1999-09-22
MY133769A (en) 2007-11-30
JP2001501001A (en) 2001-01-23

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