TW324799B - MOS termination for low power signaling - Google Patents
MOS termination for low power signalingInfo
- Publication number
- TW324799B TW324799B TW085108179A TW85108179A TW324799B TW 324799 B TW324799 B TW 324799B TW 085108179 A TW085108179 A TW 085108179A TW 85108179 A TW85108179 A TW 85108179A TW 324799 B TW324799 B TW 324799B
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- bias
- low power
- termination
- coupled
- Prior art date
Links
- 230000011664 signaling Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/497,919 US5546016A (en) | 1995-07-03 | 1995-07-03 | MOS termination for low power signaling |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW324799B true TW324799B (en) | 1998-01-11 |
Family
ID=23978871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085108179A TW324799B (en) | 1995-07-03 | 1996-07-06 | MOS termination for low power signaling |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5546016A (zh) |
| EP (1) | EP0836767A4 (zh) |
| KR (1) | KR100269012B1 (zh) |
| AU (1) | AU5679996A (zh) |
| BR (1) | BR9609554A (zh) |
| TW (1) | TW324799B (zh) |
| WO (1) | WO1997002658A1 (zh) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4445846A1 (de) * | 1994-12-22 | 1996-06-27 | Sel Alcatel Ag | Verfahren und Schaltungsanordnung für den Abschluß einer zu einer integrierten CMOS-Schaltung führenden Leitung |
| US6026456A (en) * | 1995-12-15 | 2000-02-15 | Intel Corporation | System utilizing distributed on-chip termination |
| US5719737A (en) * | 1996-03-21 | 1998-02-17 | Intel Corporation | Voltage-tolerant electrostatic discharge protection device for integrated circuit power supplies |
| AU7367698A (en) * | 1997-05-07 | 1998-11-27 | California Micro Devices Corporation | Active termination circuit and method therefor |
| US6870419B1 (en) | 1997-08-29 | 2005-03-22 | Rambus Inc. | Memory system including a memory device having a controlled output driver characteristic |
| US5994918A (en) * | 1997-08-29 | 1999-11-30 | Hewlett-Packard Co. | Zero delay regenerative circuit for noise suppression on a computer data bus |
| US5949825A (en) * | 1997-09-17 | 1999-09-07 | Hewlett-Packard Co. | Regenerative clamp for multi-drop busses |
| US6127840A (en) * | 1998-03-17 | 2000-10-03 | International Business Machines Corporation | Dynamic line termination clamping circuit |
| US6426854B1 (en) | 1998-06-10 | 2002-07-30 | Intel Corporation | Voltage clamp |
| US6351358B1 (en) * | 1998-06-11 | 2002-02-26 | Intel Corporation | Stress-follower circuit configuration |
| US6438636B2 (en) | 1998-12-23 | 2002-08-20 | Intel Corporation | Updating termination for a bus |
| US6646953B1 (en) | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
| US6388495B1 (en) * | 2001-02-23 | 2002-05-14 | Sun Microsystems, Inc. | Dynamic termination and clamping circuit |
| US6633178B2 (en) * | 2001-09-28 | 2003-10-14 | Intel Corporation | Apparatus and method for power efficient line driver |
| US6670836B1 (en) * | 2002-08-15 | 2003-12-30 | Micron Technology, Inc. | Differential buffer having bias current gated by associated signal |
| US6815980B2 (en) * | 2003-02-27 | 2004-11-09 | International Business Machines Corporation | Termination circuit for a differential transmission line |
| US6924660B2 (en) | 2003-09-08 | 2005-08-02 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
| GB2406924B (en) * | 2003-10-10 | 2006-05-24 | Advanced Risc Mach Ltd | Level shifting in a data processing apparatus |
| US6980020B2 (en) | 2003-12-19 | 2005-12-27 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
| US7009894B2 (en) * | 2004-02-19 | 2006-03-07 | Intel Corporation | Dynamically activated memory controller data termination |
| US7535279B2 (en) * | 2004-12-07 | 2009-05-19 | Analog Devices, Inc. | Versatile control pin electronics |
| US7196567B2 (en) | 2004-12-20 | 2007-03-27 | Rambus Inc. | Systems and methods for controlling termination resistance values for a plurality of communication channels |
| US7439760B2 (en) | 2005-12-19 | 2008-10-21 | Rambus Inc. | Configurable on-die termination |
| US7486104B2 (en) | 2006-06-02 | 2009-02-03 | Rambus Inc. | Integrated circuit with graduated on-die termination |
| WO2008079911A1 (en) | 2006-12-21 | 2008-07-03 | Rambus Inc. | Dynamic on-die termination of address and command signals |
| KR100795027B1 (ko) * | 2007-03-12 | 2008-01-16 | 주식회사 하이닉스반도체 | 반도체 집적 회로 및 이를 포함하는 반도체 패키지 모듈 |
| JP2013534100A (ja) | 2010-06-17 | 2013-08-29 | ラムバス・インコーポレーテッド | 平衡したオンダイターミネーション |
| US10164635B2 (en) * | 2011-12-16 | 2018-12-25 | Intel Corporation | Low voltage transmitter with variable output swing |
| US8729951B1 (en) | 2012-11-27 | 2014-05-20 | Freescale Semiconductor, Inc. | Voltage ramp-up protection |
| US9495002B2 (en) | 2014-05-05 | 2016-11-15 | Intel Corporation | Apparatuses, methods, and systems for providing a dynamic bias voltage to one or more transistors of a transceiver |
| US12205512B2 (en) * | 2022-10-31 | 2025-01-21 | LAPIS Technology Co., Ltd. | Output buffer circuit, display driver, data driver, and display device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4029971A (en) * | 1976-02-13 | 1977-06-14 | Rca Corporation | Tri-state logic circuit |
| US4958132A (en) * | 1989-05-09 | 1990-09-18 | Advanced Micro Devices, Inc. | Complementary metal-oxide-semiconductor translator |
| US5027008A (en) * | 1990-02-15 | 1991-06-25 | Advanced Micro Devices, Inc. | CMOS clamp circuits |
| GB9006088D0 (en) * | 1990-03-17 | 1990-05-16 | Digital Equipment Int | Interference suppression |
| US5023488A (en) * | 1990-03-30 | 1991-06-11 | Xerox Corporation | Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines |
| US5223751A (en) * | 1991-10-29 | 1993-06-29 | Vlsi Technology, Inc. | Logic level shifter for 3 volt cmos to 5 volt cmos or ttl |
| FR2694851B1 (fr) * | 1992-08-12 | 1994-12-23 | Sgs Thomson Microelectronics | Circuit de tirage vers un état déterminé d'une entrée de circuit intégré. |
| US5347177A (en) * | 1993-01-14 | 1994-09-13 | Lipp Robert J | System for interconnecting VLSI circuits with transmission line characteristics |
| EP1564947B1 (en) * | 1993-11-29 | 2006-12-27 | Fujitsu Limited | Electronic system for terminating bus lines |
-
1995
- 1995-07-03 US US08/497,919 patent/US5546016A/en not_active Expired - Lifetime
-
1996
- 1996-05-14 EP EP96914002A patent/EP0836767A4/en not_active Ceased
- 1996-05-14 BR BR9609554A patent/BR9609554A/pt not_active Application Discontinuation
- 1996-05-14 AU AU56799/96A patent/AU5679996A/en not_active Abandoned
- 1996-05-14 KR KR1019980700003A patent/KR100269012B1/ko not_active Expired - Fee Related
- 1996-05-14 WO PCT/US1996/006932 patent/WO1997002658A1/en not_active Ceased
- 1996-07-06 TW TW085108179A patent/TW324799B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100269012B1 (ko) | 2000-10-16 |
| WO1997002658A1 (en) | 1997-01-23 |
| BR9609554A (pt) | 1999-03-02 |
| US5546016A (en) | 1996-08-13 |
| EP0836767A4 (en) | 2001-05-09 |
| EP0836767A1 (en) | 1998-04-22 |
| KR19990028705A (ko) | 1999-04-15 |
| AU5679996A (en) | 1997-02-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |