A6 _________B6 五、發明説明（I ) 經濟部中央襻準局8工消費合作社印製 本發明之領域： 本發明係關於顯示記慷髏架構*更明確地説*本發明 係關於顯示記憶«架構，其解決在全色彩（True Color)琢 埴下，指棵色彩（index Color)像素處理過慢的問題，以 提高繪圖系統之整骽效率。 本發明之背景： 在圖1中，這種繪圖系統架構10,包括一個主電腦（ΙΙ-ost Computer)12， 以及一個繪固 副系統 （Graphics Sub-systen〇3〇，主電腦包括一個中央處理單元（CPU>14，一 套主系統記14 ft! (Main System Memory) 16，以及一個磁碟 記憶體（Disk Memory) 18，以上都是透過一個系統匯流排 (System Bus)20將彼此連接起來，繪圖副系統30包括一個 與系統匯流排互通的繪圔處理器（Graphics Processor) 40 ，以及一個與繪圈處理器40連接的區域匯流排（Local Bus )42，與區域匯流排42連接之圖框記憶體（Frame Memory} 50儲存著由繪圖處理器40產生之釤像資料，另有與區域匯 流排42連接之顬深記憶體（Z-Buffer)60儲存著用來顳示重 4視窗的領域深度，調色晶片（RAMDAC}62是一個數位/類 比轉換器（Digitel-to-Analog Converter)，將來自圈框 記慷體50的數位資料與螢幕控制信猇混合以產生和顯示器 (Display) 64相容的類比信猇。 傳統的圖框記憶體50之架構圖示於圖2。圔框記憶體 50是由許多視頻專用記憶體（Video RAM,以下簡稱爲VRAM) (請先閲讀背面之注意事項再埸寫本頁) 本紙張尺度適用中躅國家標準（CNS)甲4规格（210 X 297公釐） 82.3. 40,000 五、發明説明（2 ) A6 B6 經濟部中央標準局貝工消費合作社印製 所構成。這些VRAM被安排成數個區塊（Bank)(亦即區塊0, 區塊1,區塊2,區塊3>。每個區塊包括數個緩衝器（Buffer )，亦即緩衝器〇,緩衡器1,緩衝器2，圈框記憶體50是用許 多位兀面（Bit Plane)組截而成，也就是標不著0，1，··· / 23的24個位元面，每個緩衝器包含8個位元面。更明確地 説，顔示器64 (見圖1)中每條掃描線的第4n個像素是儲存 於區塊〇,每條掃描線的第4Π+1個像素是儲存在區塊1，第 4Π+2個像素是儲存在區塊2，以及第4n+3個像素是儲存在 區塊3。 —個全色彩像素包括24個位元，一個位元存於相對 應的位元面。進一步地説，針對圖2中圖框記憶體5〇的全 色彩像素，R(紅色）成分佔有第〇-7位元面，G(綠色）成分 佔有第8-15位元面，以及B(藍色）成份佔有第I6-23位元面 0 (全色彩像素可以二個色度（Chrominance)成分，加上一 個亮度（Luminance)成分來代表’用以替代RGB的表示方法 > 。更明確地説，因爲區域匯流排42的寛度爲32位元，所 以在每一個遇期中，圔框記憶體50只有一個全色彩像素可 被存取（亦即讀出或寫入 >。區域匯流排42以32位元的字元 (Word)傳输資料，且每一個位元的位置標示著〇,1.··,31 。區域匯流排42所使用的字元圖示於圖3。如圖4如示，當 一個全色彩像素在匯流排上傳輸時· R成分佔在位元〇_7的 位置，G成分佔在位元8-15的位置以及B成分佔在位元23-31 的位置。23-31的位臞則未被使用。因此，在圖2之圖框記 憶體50的24位元面舆區域匯流排上，資料字元的前24位元 (請先閲讀背面之注意事項再埙寫本頁) 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 82.3. 40,000 ^99406 A6 B6 五、發明説明（3 ) 經濟部中央標準局貝工消費合作社印製 位置之間，有著一對一的對應關係。繪圖處理器4〇是基於 圈4 R,G,B成分的次序來處理全色彩像素。 除了全色彩模式之外，亦可使用指標色彩模式來儲存 。在指標色彩模式下，每個像素都是以8位元來表示。傳 統上，連續四個像素匕，P2 ,P3 ,P4存於圖框記憶體5〇 的位置如圖5所示，其原則爲連績的像素分別存於連續的 區塊。然而，因爲在圖框記憶體的位元面與區域匯流排42 的位元位置之問，有著一對一的對應關係，只有一個位於 圖框記憶雔内的8位元指標模式的像素可以在一個週期之 内被存取。連續四個指標模式的像素無法在一個週期之内 被存取。在區域匯流排42上，單一個指標色彩模式的像素 (亦即像素P2)落於資料字元内的位置圖示於圖6。如圖6所 示，資料字元内尚有24個位元未使用到。因此，雖然在指 標色彩模式下每個像素只利用到少數位元，但是在處理速 度上並未得到任何好處；仍然只有一個像素在區域匯流排 42上的資料字元内，也就是説，每個週期一個像素。 圖7所示爲先前解決此問題良方。有一組附加的圖框 記憶體80追加至圈框記憶體50。此附加的圖框記憶體8〇包 括四個緩衝器（緩衝器〇,緩衝器1,鍰衝器2,緩衝器3>和總 數達32的位元面分別標示著0,1,.· .,31。連續的四個指標 像素Pi ,P2 ,Pa ,P4分別佔有8個位元面，0-7,8-15,16-23 ,24-31。因爲在位元面和匯流排42上資料字的位元位置之 間有著一對一的對應關係，所以可同時存取像素Pi ,P2 , P3 ,P4且皆位於匯流排42上同一資料字元内，就如圖8所 (請先閲讀背面之注意事項再填寫本頁) 4 i裝· 訂. 衣紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公货） 82.3. 40,000 五、發明説明（+) A6 B6 經濟部中央標準扃員工消費合作社印製 示。 如此即可在毎一遇期内處理四個指標色彩像素，因而 可達到速度上明顳的優勢，但是附加的記愴容董則導致成 本的增加。 本發明的目的是提供一套顯示記憶體架構*不但克服 了先前技術的問題，亦可更有效率地同時處理全色彩和指 標色彩像素。値得一提的是，這些都是在不使用附加圖框 記憶體的情況下達成的，這點也是本發明的目的之一，本 發明的另一目的是提出一套可處理全色彩和指標色彩像素 的顯示記憶《架構，用以改進繪圖系統的速度和效率。 本發明之簡諭： 本發明是一套可有效率地儲存和處理指摞色彩與全色 彩模式像素的顯示記憶雔架構。 根據本發明，全色彩模式像素的R,G,B成分在不同的 區塊内佔有不同組的位元面。此外*連續的指標色彩像素 是位於連續區塊内不同組的位元面，這些位元面組是非重 叠的且不一定是連續的。基於此種安排，全色彩和指標色 彩模式的像素可使用同一個記憶體緩衝器。當使用於指標 色彩模式時，在每一遇期内皆可存取四個指標色彩模式的 像素。 當一個全色彩像素需要自圖框記憶體誚出或寫入時， R,G,B成分的次序是決定存取自那一個區塊且異於繪圖處 理器處理R,G,B成分的特定次序。因此，介於根據像素所 (請先W讀背面之注意ί項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 82.3. 40,000 五、發明説明（ο A6 B6 經濟部中央標準局貝工消費合作社印製 處區塊而決定之R,G,B成分的次序與繪0處理器處理R,G,B 成分的次序之間，需要像素切換線路來加以轉換。此外， 在指摞色彩模式下，像素切換線路是用來進行介於記憶髖 位元面上像素的次序與繪圔處理器處理指摞色彩模式像素 的連續次序之間的切換工作。 圖式之簡要説明： 圖1所示爲具有繪圖能力的電腦系統。 圖2所示爲供圖1系統所用之圖框記憶體的傳統結構 ，其内所儲存的是全色彩像素。 圖3所示爲圖1系統内區域匯流排上資料字元的格式。 圖4所示爲在圖3資料字元内，一個全色彩像素R,G,B 成分的位置。 圖5所示爲供儲存指摞色彩模式像素的圖框記憶髋之 傳統結構。 圔6所示爲圖1系統内區域匯流排上資料字元所擁有 指標色彩模式像素之位罱。 圖7所示爲一套同時儲存全色彩和指摞色彩模式像素 之習知技術的B框記憶體架構。 圖8所示爲自圖7之圔框記憶體同時存取包含有四個 指樣色彩模式像素之資料字元。 圖9所示爲根據本發明可同時儲存全色彩和指標色彩 模式像素之圖框記憶體結構。 圔10(a) , 10(b) , 11(a) ,ll(b)所示爲當利用圖9之圖框 (請先閲讀背面之注意事項再堉寫本頁) •丨裝· 訂.A6 _________B6 V. Description of the invention (I) The Central Haptic Bureau of the Ministry of Economic Affairs, the 8th Industrial Consumer Cooperative, printed the field of the present invention: The present invention relates to the display of the generous skeleton structure * more specifically * the invention relates to the structure of display memory «, It solves the problem that under the full color (True Color), the processing of the index color pixels is too slow, so as to improve the overall efficiency of the drawing system. Background of the present invention: In FIG. 1, this drawing system architecture 10 includes a main computer (ΙΙ-ost Computer) 12, and a graphics solid-sub system (Graphics Sub-systen〇3〇, the main computer includes a central processing Unit (CPU> 14, a set of main system memory 14 ft! (Main System Memory) 16, and a disk memory (Disk Memory) 18, the above are connected to each other through a system bus (System Bus) 20 The drawing sub-system 30 includes a Graphics Processor 40 communicating with the system bus, and a Local Bus 42 connected to the drawing circle processor 40, and connected to the regional bus 42. The frame memory (Frame Memory) 50 stores the samarium image data generated by the graphics processor 40, and the Z-Buffer 60 connected to the regional bus 42 stores the 4 windows used for temporal weight display Depth of field, toning chip (RAMDAC) 62 is a digital / analog converter (Digitel-to-Analog Converter), which mixes digital data from the ring frame 50 with the screen control signal to generate and display (Display ) 64 compatible analog signals. The frame diagram of the traditional frame memory 50 is shown in Figure 2. The frame memory 50 is composed of many video-specific memories (Video RAM, hereinafter referred to as VRAM) (please read the back first (Notes to be written on this page) This paper scale is applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297 mm) 82.3. 40,000 V. Description of the invention (2) A6 B6 Ministry of Economic Affairs Central Standards Bureau shellfish consumption Printed by the cooperative. These VRAMs are arranged into several banks (that is, block 0, block 1, block 2, block 3>. Each block includes several buffers (Buffer), That is, the buffer 〇, the balancer 1, the buffer 2, the circle frame memory 50 is formed by using many bit planes (Bit Plane), which is not marked with 0, 1, ... 24 of 24 Bit plane, each buffer contains 8 bit planes. More specifically, the 4nth pixel of each scan line in the display 64 (see FIG. 1) is stored in block 0, each scan The 4Π + 1 pixel of the line is stored in block 1, the 4Π + 2 pixel is stored in block 2, and the 4n + 3 pixel is stored in block 3. A full-color image The pixel includes 24 bits, and one bit is stored in the corresponding bit plane. Further, for the full-color pixel of the frame memory 50 in FIG. 2, the R (red) component occupies bits 0-7 In the surface, the G (green) component occupies the 8-15th bit surface, and the B (blue) component occupies the I6-23 bit surface 0 (full-color pixels can have two chroma components, plus a brightness (Luminance) component to represent 'representation method to replace RGB>. More specifically, because the area bus 42 has a width of 32 bits, only one full-color pixel of the frame memory 50 can be accessed (that is, read or write>) in each encounter period. The regional bus 42 transmits data in 32-bit characters (Word), and the position of each bit is marked with 〇.1 .., 31. The character icons used by the regional bus 42 are shown in FIG. 3 As shown in Figure 4, when a full-color pixel is transmitted on the bus, the R component occupies the position of bit 0_7, the G component occupies the position of bit 8-15 and the B component occupies the bit 23 The position of -31. The positions of 23-31 are not used. Therefore, the first 24 bits of the data characters are on the 24-bit face and area bus of the frame memory 50 of FIG. 2 (please read first Note on the back and then write this page) This paper scale is applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297 mm) 82.3. 40,000 ^ 99406 A6 B6 V. Description of the invention (3) Ministry of Economic Affairs Central Standards Bureau There is a one-to-one correspondence between the printed positions of industrial and consumer cooperatives. The graphics processor 4 is based on the order of the R, G, and B components of the circle 4 Manage full-color pixels. In addition to the full-color mode, you can also use the index color mode to store. In the index color mode, each pixel is represented by 8 bits. Traditionally, four consecutive pixels, P2, The location where P3 and P4 are stored in the frame memory 50 is shown in Figure 5. The principle is that successive pixels are stored in consecutive blocks. However, because the bit plane and the area bus in the frame memory The position of 42 bits has a one-to-one correspondence. Only one 8-bit index mode pixel located in the memory frame of the frame can be accessed within one cycle. Four consecutive index mode pixels cannot It is accessed within one cycle. On the regional bus 42, the position of a single pixel of the index color mode (that is, pixel P2) within the data character is shown in Figure 6. As shown in Figure 6, the data There are still 24 bits unused in the character. Therefore, although only a few bits are used per pixel in the index color mode, there is no benefit in processing speed; there is still only one pixel in the regional bus Information on 42 Within the character, that is, one pixel per cycle. Figure 7 shows the previous solution to this problem. There is an additional set of frame memory 80 added to the circle frame memory 50. This additional frame memory 8〇 includes four buffers (buffer 〇, buffer 1, buffer 2, buffer 3 > and a total of 32 bit planes are marked with 0, 1, ..., 31. Four consecutive The index pixels Pi, P2, Pa, P4 occupy 8 bit planes, 0-7, 8-15, 16-23, 24-31. Because the bit position of the data word on the bit plane and the bus 42 There is a one-to-one correspondence between them, so pixels Pi, P2, P3, P4 can be accessed at the same time and all are located in the same data character on the bus 42, as shown in Figure 8 (please read the precautions on the back before filling in (This page) 4 i pack and order. The size of the clothing paper is in accordance with the Chinese National Standard (CNS) A 4 specifications (210 X 297 public goods) 82.3. 40,000 V. Description of the invention (+) A6 B6 Central Standard of the Ministry of Economy Printed by the Staff Consumer Cooperative Show. In this way, the four index color pixels can be processed in each encounter period, which can achieve the advantage of speed and speed, but the additional memory capacity increases the cost. The object of the present invention is to provide a display memory architecture * which not only overcomes the problems of the prior art, but also processes full-color and index-color pixels more efficiently at the same time. It is worth mentioning that these are achieved without the use of additional frame memory. This is also one of the objectives of the present invention. Another objective of the present invention is to propose a set that can handle full colors and indicators Color pixel display memory "architecture, used to improve the speed and efficiency of the drawing system. Brief description of the present invention: The present invention is a set of display memory architecture that can efficiently store and process finger stack color and full-color color mode pixels. According to the present invention, the R, G, and B components of a full-color mode pixel occupy different sets of bit planes in different blocks. In addition, * continuous index color pixels are bit planes located in different groups in consecutive blocks. These bit plane groups are non-overlapping and not necessarily continuous. Based on this arrangement, pixels in full color and index color mode can use the same memory buffer. When used in the index color mode, four pixels in the index color mode can be accessed during each encounter period. When a full-color pixel needs to be evicted or written from the frame memory, the order of the R, G, and B components is to determine which block is accessed from and is different from the specific processing of the R, G, and B components by the graphics processor. order. Therefore, according to the pixel (please read the notes on the back and then fill in this page), the paper size is applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297 mm) 82.3. 40,000 V. Description of invention ( ο A6 B6 The order of the R, G, B components determined by the printing division of the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs and the order of the R, G, B components processed by the graphics processor require pixel switching lines. In addition, in the finger stack color mode, the pixel switching circuit is used to switch between the order of memory pixels on the hip bit surface and the continuous order of the picture processor processing the finger stack color mode pixels. Brief description of the drawings: Figure 1 shows a computer system with drawing capabilities. Figure 2 shows the traditional structure of the frame memory used in the system of Figure 1, which stores full-color pixels. Figure 3 Shown is the format of data characters on the regional bus in the system of Figure 1. Figure 4 shows the location of a full-color pixel R, G, B component in the data characters of Figure 3. Figure 5 shows the storage index Stack of color pattern pixel picture frame memory hip tradition Structure 6. Figure 6 shows the position of the index color mode pixels possessed by the data characters on the regional bus in the system shown in Figure 1. Figure 7 shows a set of conventional technologies that simultaneously store full color and finger color mode pixels Frame B memory architecture. Figure 8 shows the simultaneous access of data characters containing four finger-like color mode pixels from the frame memory of Figure 7. Figure 9 shows that full color and The memory structure of the frame of the index color mode pixel. 10 (a), 10 (b), 11 (a), ll (b) shows the frame of Figure 9 (please read the precautions on the back first (Write this page) • Install and order.
V 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐） 82.3. 40,000 A6 B6 經濟部中央標準局A工消費合作社印製 五、發明説明（) 記憶體架構時*像素切換動作的需求。 圖12所示為依據本發明的繪圖處理器·包括像素輸入 切換和像素輸出切換線路。 圖13 (a)和13(b)綜合了圖12之像素輸入切換線路所執 行之切換動作。 圖14 (a)和14(b)綜合了圖12之像素輸出切換線路所執 行之切換動作。 圖15是像素輸入切換線路之線路圖。 圖16是像素輸出切換線路之線路圖。 本發明之詳细說明： 圖9所示為根據本發明所建立的圖框記憶體•圃9的 圖框記憶體50包括四個區塊（區塊〇,區塊1,區塊2,區塊3) •每個區塊包括四個緩衝器（媛衝器〇,媛衝器1,媛衝器2, 媛衝器3)，位元面共有32個，分別標示0,1.....31，在全 色彩模式下•每個像素的成分是儲存在每個區塊内 特定的位元面内，就如圖9所示。尤其•當像素從其中之 一的區塊移至下一個區塊時* R,G,B成分是K循環的方式 順時鐘地平移一個緩衝器，亦即8個位元面。 當一個全色彩像素為譆自圖9所示之記憶體500的區塊 0時，資料匯流排42(參考圖1)上的字元擁有如圖10(a)所 示格式。這正好是繪圖處理器40用來處理全色彩像素的次 序*所以不需任何切換的動作，然而*當一個全色彩像素 是謓自區塊1,區塊2,或區塊3時·像素切換是必須的·舉 ί-------裝------，訂-----rh (請先閲面之注意事项再塡寫本頁) 本紙張尺度適用中《國家揉準（CNS) 4规格（21Cf X 297公釐） 82.3. 40,000 、發明説明 (7) A6 B6 經濟部中央標準局员工消费合作社印製 例來說•如果一個像素是謓自區塊2 ·則資枓匯流排42上 字元的格式就如圖10 (b)所示•這不是繪圖處理器40使用 的格式•因此•繪圖處理器40包括一组像素輸入切換線路 用Μ切換圖10(b)字元内，以完成如圖l〇(a)所示之格式。 繪圖處理器亦包括一組像素輸出切換線路•繪圖處理 器所產生之資料字元包含一個全色彩像素，其格式如圖1〇 (a)所示•然而*根據此像素要寫入圖框記憶體中的那一 個區塊•資料字元R,G,B成分的次序必須重新安排•舉例 而言•如果要將像素寫入區塊2 ·圖10(a)之資料字元必須 透過像素輸出切換線路重新安排成圖10 (b)之格式•透過 圖 12.13(a), 13(b),14(a),14(b),15和 16 ·可進一步探討 像素輸入切換線路和像素輸出切換線路。 圖9的圖框記憶體500可同時使用於指標色彩像素•因 此，四個連續的指標色彩像素PI，P2，P3，P4可如圖9所 示的方式儲存至區塊和位元面•也就是對應於全色彩像素 R成分的位置•四個連續的指標色彩像素Ρ1·,Ρ2·,Ρ3·,Ρ4· 亦可如圖9所示的成式儲存至相對應於G成分位置的區塊 和位元面•四個連續的指標色彩像素Ρ1··,Ρ2，，，Ρ3**,Ρ4* 亦可如圖9所示的方式儲存至相對應於Β成分位置的區塊 和位元面，所以，當使用於指標色彩像素時•圖9的圃框 記憶體500可視為三個媛衝器，其中之一個鍰衝器對應於 R的位置•第二個媛衝器對應於G的位置•而第三個則對 應於Β的位置。 像素輸入切換線路和像素輸出切換線路亦可使用於指 (請先閲讀背面之注意事项再填寫本頁)V This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 82.3. 40,000 A6 B6 Printed by the Central Standards Bureau of the Ministry of Economic Affairs A Industrial and Consumer Cooperatives 5. Description of the invention () When the memory architecture * pixel switching Action needs. Fig. 12 shows a graphics processor according to the present invention, including pixel input switching and pixel output switching circuits. Figures 13 (a) and 13 (b) integrate the switching operations performed by the pixel input switching circuit of Figure 12. Figures 14 (a) and 14 (b) integrate the switching operations performed by the pixel output switching circuit of Figure 12. 15 is a circuit diagram of a pixel input switching circuit. 16 is a circuit diagram of a pixel output switching circuit. Detailed description of the present invention: FIG. 9 shows a frame memory created according to the present invention. The frame memory 50 of the garden 9 includes four blocks (block 0, block 1, block 2, and area Block 3) • Each block includes four buffers (Yuan Chongji, Yuan Chong 1, Yuan Chong 2, Yuan Chong 3), there are 32 bit planes, labeled 0, 1 ... ..31, in full color mode • The composition of each pixel is stored in a specific bit plane within each block, as shown in Figure 9. Especially • When the pixel moves from one of the blocks to the next block * The R, G, and B components are in a K-cycle manner. A buffer is shifted clockwise, that is, 8 bit planes. When a full-color pixel is from block 0 of the memory 500 shown in FIG. 9, the characters on the data bus 42 (refer to FIG. 1) have the format shown in FIG. 10 (a). This happens to be the order that the graphics processor 40 uses to process full-color pixels * so no switching is required, however * when a full-color pixel is from block 1, block 2, or block 3. Pixel switching It is a must · cite ------- install ------, order ----- rh (please read the notes before reading the page and write this page) Standard (CNS) 4 specifications (21Cf X 297 mm) 82.3. 40,000, invention description (7) A6 B6 Printed example of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs • If a pixel is from block 2 The format of the characters on the girdle bus 42 is shown in FIG. 10 (b). This is not the format used by the graphics processor 40. Therefore, the graphics processor 40 includes a set of pixel input switching circuits. Within the character, to complete the format shown in Figure 10 (a). The graphics processor also includes a set of pixel output switching circuits. • The data characters generated by the graphics processor include a full-color pixel, the format of which is shown in FIG. 10 (a). The block in the body • The order of the data characters R, G, and B must be rearranged • For example • If you want to write pixels to block 2 • The data characters in Figure 10 (a) must be output through the pixels Switching lines are rearranged into the format of Figure 10 (b) • Through Figures 12.13 (a), 13 (b), 14 (a), 14 (b), 15 and 16 · Pixel input switching lines and pixel output switching can be further explored line. The frame memory 500 of FIG. 9 can be used for index color pixels simultaneously. Therefore, four consecutive index color pixels PI, P2, P3, and P4 can be stored in the block and bit plane as shown in FIG. 9 It is the position corresponding to the R component of the full-color pixel. Four consecutive index color pixels Ρ1 ·, Ρ2 ·, Ρ3 ·, Ρ4 · can also be stored into the block corresponding to the location of the G component as shown in Figure 9 And bit plane • Four consecutive index color pixels Ρ1 ··, Ρ2 ,,, Ρ3 **, Ρ4 * can also be stored in the block and bit plane corresponding to the position of the component B as shown in Figure 9 Therefore, when used for index color pixels • The garden frame memory 500 of FIG. 9 can be regarded as three yuan punches, one of which corresponds to the position of R • The second punch corresponds to the position of G • The third one corresponds to the position of Β. Pixel input switching circuit and pixel output switching circuit can also be used to refer to (please read the notes on the back before filling this page)
J 丨裝_ 訂 本紙張尺度適用中國國家標準（CNS)甲4规格（210 X 297公釐） 82.3. 40,000 A6 B6 五、發明説明（公）J 丨 Installation _ Order This paper size is applicable to China National Standard (CNS) A 4 specifications (210 X 297 mm) 82.3. 40,000 A6 B6 V. Description of the invention (public)
標色彩像素Q 玆考慮用B緩衝器儲存指標色彩像素的狀況，四個像 素可在一個週期内自圖9之記憶體500讀出。因為在記憶體 5〇〇內的位元面和位元位置之間有著一對一的對應關係， 字元將可在一個週期之内自記憶體讀出，就如圖11 U)所 示，然而，像素？1’’，？2’’，？3’’，？4’’並非在連績的位置 ，而繪圖處理器40所處理的卻是四個連嫌的指標色彩像素 ，因此，在圖11 U)資料字元內的像素會透過像素輸入切 換線路重新安排圖11 (b)所示之次序，以符合繪圖處理器 處理的格式，同樣地，繪圖處理器將會産生包含四個連續 指標色彩模式像素的字元，其格式如圖11 (b)所示，然而 ，如果此字元會寫入B緩衝器，則像素輪出切換線路必須 重新安排此像素圖11 U)所示之格式〇 經濟部中央標準局Η工消費合作杜印製 (請先"讀背面之注意^項再f本頁) 圖12所示為繪圖處理器40,繪圖處理器40包含一個透 過系統匯流排20連接至主電腦12(參考圖1)的主介面4〇1， 繪圖處理器亦包括一個傳統的螢幕控制器4〇2，一個繪圖 記憶體控制器403，以及一個繪圖引擎4〇4，此繪圖引擎可 透過區域匯流排42接收來自圖框記憶體500的像素，且亦 包括一組像素輸入切換線路8〇，如上所示，針對全色彩像 素，像素輸入切換線路會將讀自圖框記憶體5〇〇(參考圖 9)的像素重新安排R,G,B成分的位置，所以資料字元内的 前三個位元組會以R,G，B的次序排列，針對指標色彩像素 ，像素輸入切換線路會將讀自圖框記憶體5〇〇資料字元 內的四個指標色彩像素重新安排，以便使指標色彩像素變 本纸張尺度適用中B國家標準（CN’S>甲4规格（210 X 297公釐） 82.3. 40,000 399406 A6 B6 五、發明説明（9 ) <請先聞讀背面之注$項再填寫本頁> 成連鑕。 繪圖記憶體控制器403透過匯流排42 ·將欲輸出之像 素傳至圖框記憶體500並寫入，繪圖記憶體控制器403包括 —组像素輸出切換線路90 *像素輸出切換線路90會收到全 色彩像素•其R，G,B成分位於四個位元姐字元內的前三個 位元姐•並將R,G,B成分重新安排•所以這些像素將會被 寫入記憶體500内特定的區塊。若是針對指標色彩像素而 言*像素輸出切換線路90會接收位於四個位元姐字元內的 連级四個的指標色彩像素*並加以重新排列*所以這些像 素將會被寫入記憶體500内三個（R,G,或B)指標色彩媛衝 器中的其中一個。 圖13(a)和圖13(b)綜合了像素輸入切換線路分別針對 全色彩和指標色彩像素而執行的動作。當控制信號CMS = 1 時為全色彩模式· CMS=0時則為指標色彩模式•在全色彩 模式時（CMS=1) ·控制信號ΑΙΑ0的是由像素X軸座標的最 低兩位元所組成•用來表示像素將自圃框記憶體500內的 那一個區塊讀出，圖13(a)中上層120的資料字元包含著謓 自圖框記憶體500中每個區塊0,1,2,3的資料字元。這些像 素是根據ΑΙΑ0所決定的特定模型來切換•進而產生R,G,B 成分都固定位於前三個位元組的資料字元•如圖13 (a)下 層140所示•俾利繪圖處理器的處理。 經濟部中央標準局R工消費合作社印製 在指標色彩模時（CMS=0) ·控制信號TBS=00,01,lx是 表示用到三個媛衝器（圖9中R,G,或B的位置）中的那一個· 圖13 (b)所示為每種狀況的切換230方式•上層220包含讀 本紙張尺度適用中國國家標準（CNS)甲4規格（210 X 297公釐) 82.3. 40,000 五、發明説明（丨〇) 自圃框記億超的資料字元·而下層240則表示繪圃處理器 所希望的格式。 圖14(a)和圖14(b)綜合了像素輸入切換線路分別針對 全色彩和指標色彩像素而執行的動作》像素輸出切換線路 輸入是由繪圖處理器所產生•如圖14 U)的上層320和圖 14(b)的上層370所示•圖14(a)和圔14(b)的下層340和390 表示出經過切換動作後的结果*所以這些像素就是要寫入 記憶體500的型式*在全色彩模式（CMS=1)的吠況下*控制 信號ΑΙΑ0是用來表示下層340的字元將被寫入那一個區塊 。在指標色彩模式（CMS=0)的狀況下•控制信號TBS表示出 將會寫入三個緩衝器（R,G或B)中的那一個。 圖15所示為像素輸入切換線路80 ·謓自記憶體500 32 位元寬的資料字元藉著匯流排801抵達•供繪圖處理器處 理之32位元寬的資料字元藉著匯流排802離開•經由四個 多工器803-1,803-2,803-3,803-4來執行切換的動作，每 個多工器803-1,803-2,803-3有四組8位元的輸入804供接 收來自匯流排801上32位元之資料字元中的8個位元•舉例 來說，多工器803-1的輸入A接收位元0-7，多工器803-1的 輸入B接收位元8-15 ·多工器803-1的輸入C接收位元16-23 •多工器803-1的輸入D接收位元24-31·多工器803-4有三 個輸入•換句話說，輸入A接收位元24-31，輸入B接收位 元0-7 ·輸入C接收位元8-15 *每個多工器803都有一個輸 出805 ·每個多工器803都會從輸入（A,B,C,D)中選擇一姐 8位元傳送至輸出805 *多工器803-1的輸出姐成匯流排802 五、發明説明（il) A6 B6 經濟部中央標準局WT工消费合作社印製 上輸出資料字元的位元0-7·多工器803-2的輸出姐成匯流 排802上字元的位元8-15 ·多工器803-1的輸出姐成匯流排 802上字元的位元23-31 〇 每個多工器803接收二個位元的控制信號SO * S1 ·用 以控制由那個輸入A,B,C或D傳送到輸出•控制信號SO，S1 是由控制理輯810產生•控制邏輯810包括6個NAND閘811 和一個反相器812。控制邏輯810的輸入是CMS, AIA0和TAB [0,1] · CMS是用來選擇全色彩或指標色彩模式，ΑΙΑ0是用 來在全色彩模式（參考圖13(a))下*選擇區塊TBS[0,1]則 是用來在指標色彩模式下選擇緩衝器（R,G,或B)。 圖16所示之像素輸出切換線路90有個類似的结構•來 自繪圖處理器的字元藉著32位元匯流排901抵達·適合寫 入圖框記憶體500 (參考圖9)格式的32位元字元會藉著匯流 排902輸出*像素輸出切換線路包括四個多工器903-1,903 -2,903-3,903-4。每個多工器903有四姐8位元輸入804用 來接收來自匯流排901上32位元之資料字元中的8涸位元· 舉例來說*多工器903-1的輸入A接收位元0-7 *多工器 903-1的輸入B接收位元8-15 ·輸入C接收位元16-23，輸 入D接收位元24-31，每個多工器903都有一個輸出905， 每個多工器903都會從輸入（A,B,C,D)中選擇一组8位元傳 送至輸出905 ·多工器903-1的輸出組成匯流排902上輸出 字元的位元0-7·多工器903-2的輸出組成匯流排902上字 元的位元8-15 ·多工器903-3的輸出姐成匯流排902上字元 的位元16-23 *多工器903-4的輸出組成匯流排9〇2上字元 (請先閲讀背面之注意事項再填寫本頁) 」 .裝· 訂· 本紙張尺度適用中國國家螵準（CNS)甲4規格（210 X 297公货） 82,3. 40,000 五、發明説明（丨2) A6 B6 的位元23-31。 每個多工器903接收二個位元的控制信號SO · S1 ·用 K控制由那個輸入A,B,C或D傳送到輸出•控制信號S0 · S1 是由控制邏輯910產生*控制埵輯910包括6個NAND閘911 和一個反相器912。控制邏輯910的輸入是CMS, ΑΙΑ0和TAB [0,1] · CMS是用來選擇全色彩或指標色彩棋式· ΑΙΑ0是用 來在全色彩模式（參考圖14(a))下•選擇區塊TBS[0,1]則 是用來在指標色彩模式下選擇鍰衝器（R,G,或B)。 簡而言之·本文揭露了可Μ在全色彩環境下以高速和 有效率地方式處理指標色彩像素的顯示記憶體架構。最後 •Κ上有關本發明的具體化描述僅供說明之用•許多可替 代的具體方案可以在不脫離下列申請專利範圍的精神和範 圍的情況下根據此技術做進一步的修正。 (請先閲讀背面之注意事项再？^本頁) • —裝· 訂 經濟部中央標準局貝工消费合作社印製The target color pixel Q considers the condition of using the B buffer to store the target color pixel. The four pixels can be read from the memory 500 of FIG. 9 in one cycle. Because there is a one-to-one correspondence between the bit planes and bit positions in the memory 500, the characters will be read from the memory within one cycle, as shown in Figure 11 U), However, pixels? 1'',? 2'',? 3 ’’ ,? 4 '' is not in a consecutive position, but the graphics processor 40 is dealing with four consecutive index color pixels. Therefore, in FIG. 11 U) the pixels in the data characters will be rearranged through the pixel input switching circuit The sequence shown in Fig. 11 (b) conforms to the format processed by the graphics processor. Similarly, the graphics processor will generate characters containing four consecutive index color mode pixels. The format is shown in Fig. 11 (b) However, if this character is written to the B buffer, the pixel round switch circuit must rearrange the format shown in this pixel (Figure 11 U). The Central Standardization Bureau of the Ministry of Economic Affairs and Industry Cooperative Printing (please first "; Read the note on the back ^ Item and f this page) Figure 12 shows the graphics processor 40, the graphics processor 40 includes a main interface 4〇1 connected to the host computer 12 (refer to FIG. 1) through the system bus 20, The graphics processor also includes a conventional screen controller 402, a graphics memory controller 403, and a graphics engine 404. The graphics engine can receive pixels from the frame memory 500 through the regional bus 42. And also includes a set of pixels Into the switching circuit 8〇, as shown above, for full-color pixels, the pixel input switching circuit will rearrange the pixels read from the frame memory 500 (refer to FIG. 9) to the position of the R, G, B components, so the data The first three bytes in the character will be arranged in the order of R, G, B. For the indicator color pixels, the pixel input switching circuit will read the four indicator colors in the 500 data characters from the frame memory Pixel rearrangement in order to make the index color pixels change to the paper standard applicable to the B national standard (CN'S > A 4 specifications (210 X 297 mm) 82.3. 40,000 399406 A6 B6 V. Invention description (9) < Please listen first Read the note $ item on the back and then fill in this page> into a serial link. The graphics memory controller 403 passes the bus 42. · Transfers the pixels to be output to the frame memory 500 and writes, the graphics memory controller 403 includes —Group of pixel output switching lines 90 * The pixel output switching line 90 will receive full-color pixels • Its R, G, and B components are located in the first three bit sisters of the four-bit sister characters • Put R, G, B component rearranged • So these pixels will be written to memory 5 The specific block in 00. For the target color pixels, the * pixel output switching circuit 90 will receive the four consecutive target color pixels in the four-bit sister characters * and rearrange them * so these pixels will be It will be written to one of the three (R, G, or B) indicator color filters in memory 500. Figure 13 (a) and Figure 13 (b) integrate the pixel input switching circuit for full color and The action performed by the index color pixel. When the control signal CMS = 1, it is the full color mode. When CMS = 0, it is the index color mode. • In the full color mode (CMS = 1). The control signal ΑΙΑ0 is determined by the pixel X axis. The coordinate is composed of the lowest two digits. • It is used to indicate that the pixel will be read out from the block in the garden frame memory 500. The data characters of the upper layer 120 in FIG. 13 (a) include the frame memory 500. The data characters of each block 0,1,2,3 in. These pixels are switched according to the specific model determined by ΑΙΑ0. • The data characters whose R, G, and B components are all fixed in the first three bytes are generated. As shown in FIG. 13 (a) the lower layer 140. Processor processing. When the R-Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy prints the indicator color mode (CMS = 0). The control signal TBS = 00, 01, lx means that three yuan punches are used (R, G, or B in FIG. 9 The position in the figure). Figure 13 (b) shows the way of switching 230 for each situation. • The upper layer 220 contains the reader. The paper size is applicable to the Chinese National Standard (CNS) A 4 specifications (210 X 297 mm) 82.3. 40,000 Fifth, the description of the invention (丨 〇) frame the data characters of Yi Chao from the garden, and the lower layer 240 represents the format desired by the painting garden processor. Figures 14 (a) and 14 (b) integrate the actions performed by the pixel input switching circuit for full-color and index-color pixels, respectively. The pixel output switching circuit input is generated by the graphics processor • Figure 14 U) upper layer 320 and the upper layer 370 of FIG. 14 (b) are shown. • The lower layers 340 and 390 of FIGS. 14 (a) and 14 (b) show the result after the switching action * so these pixels are the type to be written into the memory 500 * In the full color mode (CMS = 1), the control signal AIA0 is used to indicate to which block the characters of the lower layer 340 will be written. In the indicator color mode (CMS = 0) • The control signal TBS indicates which of the three buffers (R, G or B) will be written. Figure 15 shows the pixel input switching circuit 80. The 32-bit wide data characters from the memory 500 arrive via the bus 801. The 32-bit wide data characters for processing by the graphics processor via the bus 802 Leaving • Switching is performed via four multiplexers 803-1, 803-2, 803-3, 803-4. Each multiplexer 803-1, 803-2, 803-3 has four 8-bit inputs 804 for receiving from the bus 801 8 of the 32-bit data characters • For example, input A of multiplexer 803-1 receives bits 0-7, and input B of multiplexer 803-1 receives bits 8-15 • Input C of multiplexer 803-1 receives bits 16-23 • Input D of multiplexer 803-1 receives bits 24-31 • Multiplexer 803-4 has three inputs • In other words, input A receives Bits 24-31, input B receives bits 0-7 · input C receives bits 8-15 * Each multiplexer 803 has an output 805 · Each multiplexer 803 will receive input (A, B, C, D) choose a sister 8-bit to send to the output 805 * the output of the multiplexer 803-1 into the bus 802 5. Description of the invention (il) A6 B6 Printed by the WT Industrial and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Output data character bits Element 0-7 • The output of the multiplexer 803-2 is bit 8-15 of the characters on the bus 802. The output of the multiplexer 803-1 is bit 23-31 of the characters on the bus 802 〇 Each multiplexer 803 receives a two-bit control signal SO * S1 · used to control which input A, B, C or D is transmitted to the output • The control signal SO, S1 is generated by the control logic 810 • control The logic 810 includes six NAND gates 811 and an inverter 812. The input of control logic 810 is CMS, AIA0 and TAB [0,1] · CMS is used to select the full color or index color mode, ΑΙΑ0 is used to select the block in the full color mode (refer to Figure 13 (a)) * TBS [0,1] is used to select the buffer (R, G, or B) in the index color mode. The pixel output switching circuit 90 shown in FIG. 16 has a similar structure. • The characters from the graphics processor arrive via the 32-bit bus 901. • 32 bits suitable for writing into the frame memory 500 (refer to FIG. 9) format The metacharacters are output via the bus 902 * The pixel output switching circuit includes four multiplexers 903-1, 903-2, 903-3, 903-4. Each multiplexer 903 has four sisters 8-bit input 804 for receiving 8-bit data from the 32-bit data characters on the bus 901. For example * Multiplexer 903-1 input A receives Bits 0-7 * Input B of multiplexer 903-1 receives bits 8-15 · Input C receives bits 16-23, input D receives bits 24-31, and each multiplexer 903 has an output 905, each multiplexer 903 will select a set of 8 bits from the input (A, B, C, D) to transmit to the output 905. The output of the multiplexer 903-1 constitutes the bit of the output character on the bus 902 Element 0-7 · The output of multiplexer 903-2 makes up bits 8-15 of the character on bus 902 · The output of multiplexer 903-3 becomes bits 16-23 of the character on bus 902 * The output of the multiplexer 903-4 constitutes the upper character of the bus 9〇2 (please read the precautions on the back before filling out this page) ”. Packing · Ordering · This paper standard is applicable to China National Standard (CNS) A 4 specifications (210 X 297 public goods) 82,3. 40,000 V. Description of invention (丨 2) Bits 23-31 of A6 B6. Each multiplexer 903 receives a two-bit control signal SO · S1 · uses K to control which input A, B, C or D is transmitted to the output • The control signal S0 · S1 is generated by the control logic 910 910 includes 6 NAND gates 911 and an inverter 912. The input of the control logic 910 is CMS, ΑΙΑ0 and TAB [0,1] · CMS is used to select the full color or index color chess style · ΑΙΑ0 is used to select the area in the full color mode (refer to Figure 14 (a)) The block TBS [0,1] is used to select the chisel (R, G, or B) in the index color mode. In short, this article discloses a display memory architecture that can process index color pixels in a high-speed and efficient manner in a full-color environment. Finally • The specific description of the invention on K is for illustrative purposes only. Many alternative specific solutions can be further modified based on this technology without departing from the spirit and scope of the following patent application. (Please read the precautions on the back first? ^ This page) •-Binding · Order Printed by Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs