A7 296436 _ B7 五、發明説明（1 ) 〔發明之背景〕 本發明，係有關實裝在印刷電路板（PC板）上之集 體電路，特別關於內裝有用以檢知信號端子的斷開不良之 測試電路的集體電路。 引出線插入型之實裝有多數集體電路的P C板，係具 有各別對應於各集體電路之多數引出線（外部端子）的多 數通孔，和使之電連接在各通孔地形成圖型的多數印刷配 線。根據將各個集體電路之引出線插入對應通孔，且在所 有插入處實施焊錫，而達成各引出線和印刷配線之電連接 。可是，有時會在P C板上發生斷開不良，短路不良等焊 錫缺陷。斷開不良係由焊錫供給不足等發生缺陷，無意地 在引出線和印刷配線之間成爲斷開狀態者。短路不良係由 焊錫供給過多等而發生的缺陷，無意地多數之印刷配線互 相電性地短路者。如此的焊錫缺陷，在表面實裝技術等將 其他採用封裝技術之集體電路實裝在P C板上時也會發生 〇 已往，爲了檢出P C板上的集體電路之焊錫缺陷，係 使用電路中測試器（in-circurt-tester)。此時，電路 中測試器之多數探針將分別接觸在測試對象集體電路周圍 之配線。然後，將從一部份探針向集體電路的输入端子供 給測試資料信號，從該集體電路之輸出端子得到的信號將 從其他探針做爲測試結果信號取入至電路中測試器，而把 該取入之信號和期待値比較。從該比較的結果，判定有無 焊錫缺陷。可是，在1張PC板上有多數之集體電路高密 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I---------批衣------1T------^ (請先閱讀背面之注意事項再：AV本頁) 一 經濟部中央標準局貝工消費合作杜印裝 經濟部中央標準局員工消費合作社印策 A7 B7_五、發明説明（2 ) 度實裝時，和具有PC板多層化的配線時，有時實際上無 法使探針接觸在配線，因此逐漸無法利用電路中測試器。 因此，能夠考慮將美國專利第5 ，0 8 4 ，8 7 4號 等揭示之邊界掃描測試（B S T )的技術利用在檢出焊錫 缺陷。根據B ST技術時，將在PC板上經由多數之印刷 配線互相連接的2個集體電路各別中設置多數之邊界掃描 格（BSC)而成的測試電路。然後，內裝在一方之集體 電路的測試電路，將經由該集體電路之對應输出端子，分 別在印刷配線上供給測試信號。各印刷配線上的信號，將 經由他方之集體電路的對應輸入端子，做爲測試結果信號 取入至內裝在該集體電路之測試電路。所有的B S C，將 在某一模式互相連接爲串聯。因此，將由掃描動作達成測 試資料信號之供給，和觀測測試結果信號，根據比較測試 資料信號和測試結果信號而判定有無焊錫缺陷。 可是，上述已往之利用B S T技術的檢出焊錫缺陷， 係以在P C板上互相連接之2個集體電路各別內裝有多數 B S C而成的測試電路做爲前提者。因此，當一方之集體 電路未內裝有測試電路時，即使他方的集體電路內裝有測 試電路，也有無法達成檢出焊錫缺陷之問題。同時，在某 集體電路的信號端子連接有電晶體，二極體等分立之有源 元件，式變壓器，電容器等被動元件時，因此等元件不能 內裝測試電路，所以即使集體電路內裝有測試電路，也無 法檢出該集體電路之信號端子的焊錫缺陷。因此，已往無 法在P C板全體得到焊錫缺陷之高檢出率。 —訂 線 (請先閲讀背面之注意事項各.与本頁) ~ 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2丨Ο X 297公釐） 經濟部中央標準局員工消費合作社印裝 A7 B7 _ 五、發明説明（3 ) 〔發明之概要〕 本發明之目的，係只以內裝在集體電路之測試電路， 而和該集體電路在P C板上連接在何種元件無關地，使之 能夠檢知該集體電路的信號端子之斷開不良。 爲了達成該目的，本發明，係做爲在P C板上從集體 電路之信號端子在印刷配線正常地電連接時，和未電連接 時的負荷容量之差，檢知該信號端子的斷開不良者。 做爲表示電特性之量，有電阻，電感及浮動容量。其 中，以容易測定而選擇浮動容量爲理想。對配線具有之浮 動容量C進行充電時的充電電流I ( t )和充電電壓V ( t)之關係，將以下式表示。 I (t)=CXdV (t)/dt 在此，t爲時間。因此，浮動容量之差，能夠做爲充電時 g[之差，充電電流之差，或充電電壓之差而檢出。其中， 從測定的簡便以選擇充電時間之差爲理想。亦即，從浮動 容量的充電所需要時間之差，做爲檢知信號端子的斷開不 良0 具體上，將在集體電路中，在測試模式經由各對應之 信號端子，設置用以供給向P C板上的對應配線具有之浮 動容量供給充電電流的多數之測試狀態緩衝器。因在該多 數的測試狀態緩衝器之各信號延遲時間將反映浮動容量的 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐） ---------和衣------、訂------^ (請先閱讀背面-之注意事項再产本頁) ~ 經濟部中央標準局員工消費合作社印裝 206436 at B7 五、發明説明（4 ) 差，所以更在集體電路中，設置用以供給具有表示各個對 應之測試狀態緩衝器的輸入變遷時間和其輸出變遷時間之 時間間隔的脈寬之邏輯信號的互斥Ο R閘。根據該構成時 ，因和集體電路在PC板上連接在任何元件無關地能夠檢 知斷開不良，故能得到在P C板全體達成焊錫缺陷之高檢 出率的效果。 〔資施例〕 以下，關於有關本發明之內裝測試電路的集體電路之 具體例，參照圖面說明。 圖1，係顯示有關本發明之集體電路的構成例。圖1 之集體電路1 0，具有第1及第2輸入端子IN1， IN2 ，和1個輸出端子OUT，和5個測試端子TDI ，TD0，TCTL，TCK1 ，TCK2。該集體電路 1 0實裝在PC板上時，3個信號端子INI ，IN2 ， OUT將根據焊錫電連接在各個P C板上之對應的配線。 圖1中之C，表示各配線具有的浮動容量。1 1係使之實 現集體電路1 0的原來機能地內部連接在3個端子IN 1 ，IN2，〇UT之內部邏輯（應用邏輯）。在內部邏輯 11和输出端子OUT之間，當測試控制信號TCTL指 定測試模式時（TCTL二1 )係保持高阻抗輸出，且測 試控制信號TCTL指定非測試模式（TCTL=0)時 ，介在有用以將信號’從內部邏輯1 1傅達至输出端子 OUT之試驗狀態緩衝器1 2。再者，雖然在圖1之例係 本紙伕尺度適用中國國家標準（CNS ) A4規格（210ΧΜ7公釐） I.---------裝------訂------線 1''' (請先閱讀背面-之注意事項本頁) · A7 B7 經濟部中央標準局員工消費合作社印製 五、 發明説明 ( 5 ) 1 I 考 慮 說 明 的 方 便 而 將 信 號 端 子 數 做 爲 3 9 但 是 並 不 限 於 此 1 1 內 裝 在 1 bfl 圖 1 之 集 體 電 路 1 0 的 測 試 電 路 9 具 有 第 1 及 1 1 I 請 1 • j 第 2 之 正 反 器 2 1 9 2 6 9 和 第 1 5 第 2 及 第 3 試 驗 狀 態 先 閱 1 I 讀 1 緩 衝 器 2 2 a 9 2 2 b ， 2 2 C 9 和 第 1 9 第 2 及 第 3 互 背 Λ 1 之 1 斥 % 或 嬅 閘 2 3 a > 2 3 b 9 2. 3 C 9 和 1 個 及 • 閘 注 意 1 1 2 4 9 和 1 個 選 擇 器 2 5 〇 事 項 1 1 1 第 1 D 正 反 器 2 1 9 係 將 測 試 資 料 信 號 T D 1 和 第 1 本 裝 測 試 時 鐘 信 號 T C K 1 之 上 升 變 遷 同 步 地 閂 鎖 9 且 用 以 將 頁 1 1 該 閂 Azb 鎖 的 信 號 向 3 個 試 驗 狀 態 緩 衝 器 2 2 a 9 2 2 b 9 1 1 2 2 C 分 配 之 輸 入 正 反 器 〇 3 個 試 Β6Δ. 厥 狀 態 緩 衝 器 2 2 a 9 1 | 2 2 b 5 2 2 C 的 共 同 之 輸 入 信 號 做 爲 D I 0 訂 I 第 1 試 驗 狀 態 緩 衝 器 2 2 a 係 將 信 號 D 0 a 向 第 1 輸 1 1 I 入 端 子 I N 1 9 第 2 試 驗 狀 態 緩 衝 器 2 2 b 係 將 信 號 1 1 I D 0 b 向 第 2 輸 入 端 子 I N 2 ， 第 3 試 驗 狀 態 緩 衝 器 1 1 2 2 C 係 將 信 號 D 0 C 向 输 出 端 子 0 U T 分 別 輸 出 者 〇 當 線 1 測 試 控 制 信 號 T C T L 指 定 測 試 模 式 時 ( T C T L = 1 ) .1 J 第 1 試 驗 狀 態 緩 衝 器 2 2 a 將 經 由 第 1 輸 入 端 子 I N 1 1 I 9 第 2 試 驗 狀 態 緩 衝 器 2 2 b 將 經 由 第 2 輸 入 端 子 I N 2 1 I 9 第 3 試 驗 狀 態 緩 衝 器 2 2 c 將 經 由 輸 出 端 子 0 U T 分 別 1 1 I 向 P C 板 上 之 對 應 配 線 具 有 的 浮 動 容 量 C 供 給 微 小 之 充 電 * 1 1 電 流 0 當 測 試 控 制 信 號 T C τ L 指 定 非 測 試 模 式 ( 1 1 T C T L = 0 ) 時 9 3 個 試 願 狀 態 緩 衝 器 2 2 a 2 2 b 1 1 9 2 2 C 皆 將 保 持 高 阻 抗 m 出 〇 第 1 互 斥 或 • 閘 2 3 a 1 1 本紙悵尺度通用中國國家標準（CNS ) Λ4規格（2丨OX 297公釐） 經濟部中央橾準局員工消f合作社印裝 A7 B7 五、發明説明（6 ) ，將供給具有表示第1試驗狀態緩衝器2 2 a之輸入信號 D I的上升變遷時刻，和第1試驗狀態緩衝器2 2 a之輸 出信號D 0 a的上升變遷時刻之時間間隔的脈寬之邏輯信 號XORa。第2互斥、或^閘2 3 b，將供給具有表示 第2試驗狀態緩衝器2 2 b之輸入信號D I的上升變遷時 刻，和第2試驗緩衝器2 2 b之輸出信號DO b的上升變 遷時刻之時間間隔的脈寬之邏輯信號XOR b。第3互斥 *或―閘2 3 c，將供給具有表示第3試驗狀態緩衝器2 2 c之輸入信號D I的上升變遷時刻，和第3試驗狀態緩 衝器2 2 c之输出信號DOc的上升變遷時刻之時間間隔 的脈寬之邏輯信號XORc。 *及^閘2 4 ，係供給3個邏輯信號XORa， X〇Rb，XORc之邏輯積信號AND者。選擇器2 5 ，係測試控制信號TCTL指定測試模式（TCTL = 1 )時將邏輯積信號AND，當測試控制信號TCTL指定 非測試模式（TCTL=0 )時將第1 D正反器2 1之輸 出信號分別向第2D正反器2 6做爲資料信號供給者。第 2D正反器2 6 ，係將從選擇器2 5供給之資料信號和第 2測試時鐘信號TCK2的上升變遷同步地閂鎖，且把該 閂鎖之信號做爲測試結果信號T D 0輸出用的輸出正反器 〇 圖2 ，係顯示上述集體電路1 〇之測試動作（ TCTL=1)。在此，將做爲2個輸入端子IN1 ， I N 2沒有焊錫缺陷，而输出端子OUT具有斷開不良之 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） I H 裝 I 訂 線 . (請先閱讀背面之注意事項一4 .¾本頁) ' 經濟部中央標準局員工消費合作杜印製 A7 B7 ~ I - _ _ _ _ 五、發明説明（7 ) 焊錫缺陷。將測試資料輸入信號TD 1的邏輯値設定爲1 後，在時刻71把第1測試時鐘信號TCK1上升時，第 1 D正反器2 1之輸出信號將從邏輯値0變遷爲邏輯値1 。亦即，3個試驗狀態緩衝器2 2a，22b，22c之 共同的輸入信號DI將上升變遷。因2個輸入端子INI ’ IN2不具有焊錫缺陷，故第1及第2試驗狀態緩衝器 2 2 a，2 2 b將分別向浮動容量C供給微小之充電電流 。在第1試驗狀態緩衝器2 2 a的信號延遲時間，將成爲 緩衝器固有之閘延遲時間Tg，和依賴配線具有的浮動容 置C之配線延遲時間Tw的和。在第2試驗狀態緩衝器 2 2 b也相同。一方面，因輸出端子OUT具有斷開不良 之焊錫缺陷，故第3試驗狀態緩衝器2 2 c將不進行向浮 動容量C供給充電電流。因此，在第3試驗狀態緩衝器 2 2 c的信號延遲時間，將和緩衝器固有之閘延遲時間 Tg —致。亦即，如圖2所示，第3試驗狀態緩衝器. 2 2 c的输出信號DOc在時刻T2上升變遷後，第1及 第2試驗狀態緩衝器2 2 a，2 2 b之輸出信號D〇a， DOb將在時刻T3上升變遷。結果，從第1及第2互斥 "^或"閘2 3 a，2 3 b供給之邏輯信號XORa， XORb將具有脈寬Tg+Tw，從第3互斥、或"閘 2 3 c供給的邏輯信號XORc將具有脈寬Tg。亦即， 從及閘2 4供給之邏輯積信號，具有脈寬Tg。 配線延遲時間Tw，將以下式表示。 本紙悵尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） —. 裝 訂 線 (請先閱讀背面之注意事項死本頁) -10 - A7 B7 --· ----. 五、發明説明（8 ) T w = C X T c 裝 .訂 在此，T c爲每單位容量之延遲時間，例如將設定爲1 〇 n s/pF。此時，即使浮動容量C爲1 pF，信號 DOc的上升變遷時刻T2，和信號DOa，DOb之上 升變遷時刻T3間，將會有1 0 n s的時間差。然後，第 2測試時鐘信號TCK2，將在時刻Τ2和時刻Τ3之間 的時刻Tm上升。因在時刻Tm邏輯積信號AND之遨n 値已成爲0，故第2D正反器2 6閂鎖邏輯値0的結果， 測試結果信號TDO將成爲表示「有斷開不良」之邏輯値 0。該測試結果信號TD0，將在時刻T4觀測。當2f§ 輸入端子INI ，IN2和1個輸出端子OUT皆無焊錫 缺陷時，將如圖2中以想像線（二點鏈線）所示，在時刻 T4之測試結果信號TD 0將成爲表示「無斷開不良」的 邏輯値1。 線 經濟部中央標準局貝工消費合作社印裝 如以上所述，根據圖1之集體電路10時，只以內裝 在該集體電路10的測試電路，就能夠檢知3個信號端子 I N 1 ，I N 2 ，OUT中是否有斷開不良之信號端子存 在。亦即，能夠容易地實現PC板上的集體電路1 0之關 於焊錫缺陷的，所謂GO/NG測試。 圖3，係顯示實裝包含有關本發明之4個集體電路的 多數電路元件之PC板的例子。在圖3之PC板5，實裝 有內裝將圖1中的構成分別擴張之測試電路的第1 ，第2 ，第3及第4集體電路l〇a，l〇b，10c，10d 本紙悵尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） -11 - 206436 A7 B7 經濟部中央標準局員工消費合作社印製 五、 發明説明 ( 9 ) 1 9 和記憶器 1 5 9 和 變 壓 器 1 6 ， 和 電 晶 體 群 1 7 9 和 數 1 1 位 類比轉換 器 ( D A C ) 1 8 9 和 發 光 二 極 體 ( L E D ) 1 I 群 1 9 〇 4 個 集 體 電 路 1 0 a 9 1 0 b 1 0 C 9 1 0 d «V I 分 別具有6 個 信 Ofeb 端 子 9 和 5 個 測 試 端 子 T D 1 9 T D 0 請 先1 閲 I 9 T C T L ， T C K 1 9 T C K 2 0 P C 板 5 9 具 有 7 個 | -面 | 信 號端子， 和 5 個 測 試 uii 端 子 T D 1 T D 0 5 T C T L 9 之1 ί T C K 1， T C K 2 0 分 別 從 外 部 供 給 P C 板 5 之 測 試 控 事1 項 I 苒 制 信號T C T L ， 第 1 測 試 時 鐘 信 號 T C K 1 及 第 2 測 試 1 勿 裝 本千 時 鐘信號T C K 2 9 將 分 別 並 聯 地 供 給 4 個 集 體 電 路 ί 1 1 1 0 a，1 0 b ， 1 0 C 1 0 d 〇 測 試 控 制 信 號 1 1 T C T L指 定 非 測 試 模 式 ( T C T L — 0 ) 時 0 將 根 據 選 1 | 擇 器2 5 ( 參 閱 ΓΗΓΙ 圖 1 ) 之 作 用 如 圖 3 所 示 9 在 P C 板 5 訂 I 的 測試資料 輸 入 端 子 T D 1 和 測 試 結 果 輸 出 端 子 T D 0 之 1 1 I 間 ，內裝在 4 個 集 體 電 路 1 0 a 9 1 0 b 9 1 0 C 9 1 1 1 1 0 d的合 計 8 個 D 正 反 器 2 1 9 2 6 將 互 相 串 聯 連 接 0 1 記 憶器1 5 及 D A C 1 8 9 皆 係 未 內 裝 測 試 電 路 之 集 體 電 線 路 。變壓器 1 6 ， 電 晶 體 群 1 7 及 L E D 群 1 9 9 皆 係 不 1 1 能 內裝測試 電 路 的 元 件 0 1 根據圖 3 之 P C 板 時 向 4 個 集 體 電 路 1 0 a 9 1 I 1 0 b ，1 0 C 9 1 0 d 的 各 測 試 資 料 信 號 之 供 給 9 和 4 1 1 | 個 集體電路 1 0 a 9 1 0 b > 1 0 C 9 1 0 d 的 各 測 試 結 1 果 信號之觀 測 > 將 根 據 和 已 往 的 B S T 技 術 相 同 之 掃 描 動 1 1 作 (T C T L 0 ) 而 達 成 0 此 時 9 將 做 爲 第 1 測 試 時 鐘 1 1 信 號T C K 1 及 第 2 測 試 時 適 信 號 T C K 2 9 從 外 部 供 給 1 1 本紙張尺度適用中國國家標隼（CNS ) A4規格（2丨OX 2Q7公釐） -12 - A7 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（i〇) 同一時鐘信號。同時，指定測試模式之測試控制信號 TCTL (TCTL=1)從外部供給PC板5時，將實 行根據4個集體電路1 〇a，1 Ob，1 0c，1 0d的 各信號端子之浮動容量的斷開不良測試。具體而言，第1 集體電路1 0 a之2個信號端子，第2集體電路1 0 c的 2個信號端子及第4集體電路1 0 d之2個信號端子係經 由各印刷配線連接在記憶器1 5，記憶器1 5雖未內裝測 試電路，但是此等信號端子能分別撿知斷開不良。第1集 體電路1 0 a之其他2個信號端子，第2集體電路1 0 b 的1個信號端子及第4集體電路1 0 d之其他2個信號端 子，雖然分別經由印刷配線在P C板5的信號端子開放， 但是分別能檢知斷開不良。第2集體電路1 0 b之其他1 個信號端子係經由印刷配線在變壓器1 6，第2集體電路 1 0 b的其他4個信號端子係分別經由印刷配線在電晶體 群1 7之各基極，第3集體電路1 0 c的其他4個信號端 子係分別經由印刷配線連接在LED群19之各陽極，雖 然變壓器1 6，電晶體群1 7及LED群1 9皆係不能內 裝測試電路的元件，但是此等信號端子也分別能夠檢知斷 開不良。第1集體電路1 0 a之其他2個信號端子和第4 集體電路1 0 d的其他2個信號端子，雖然分別經由印刷 配線互相連接，但是分別能夠檢知斷開不良。因此，根據 圖3之構成時，在PC板5全體的焊錫缺陷之檢出率，將 比已往的B S T技術時大幅度地提高。 圖4 ，顯示有關本發明之集體電路的其他構成例。圖 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I I 訂 — 線 (請先閱讀背面之注意事項再 ~本頁) 經濟部中央標準局員工消費合作社印策 A7 B7 五、發明説明（11) 4之集體電路3 0，具有第1及第2输入端子IN1 ， IN2，和1個輸出端子OUT，和4個測試端子TDI ，TD0，TCTL，TCLK。該集體電路3 0實裝在 PC板上時，3個信號端子INI ，IN2 ，OUT將分 別根據焊錫電性連接在P C板上之對應的配線。圖4中之 C，表示各配線具有的浮動容置。3 1係使之實現集體電 路3 0的原來機能地內部連接在3個信號端子IN1 ， IN2 ，OUT之內部邏輯（應用邏輯）。在內部邏輯 3 1和輸出端子OUT之間，介在有測試控制信號 TCTL指定測試模式（TCTL=1 )時將保持高阻抗 輸出，且測試控制信號T C T L指定非測試模式（ TCTL=0)時將從內部邏輯31向輸出端子OUT傳 達信號用之試驗狀態緩衝器3 2。再者，雖然在圖4的例 係考慮方便說明而將信號端子數做爲3個，但是並不限於 此° 內裝在圖4之集體電路的測試電路，具有第1互斥 OR閘4 1 ，和延遲電路4 2，和第1選擇器4 2 ，和第 2 ，第3及第4選擇器44a，44b，44c，和第5 ，第6及第7選擇器4 5a，4 5b，4 5c，和第1 ， 第2及第3D正反器4 6a，4 6b，4 6c，和第1 ， 第2及第3試驗狀態緩衝器4 7a，4 7b，4 7 c，和 第2，第3及第4互斥％或，閘48a，48b，48c Ο 延遲電路4 2，係用以使從外部供給之測試時鐘信號 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2丨OX 297公釐） (請先閱讀背面.之注意事項' .寫本頁) 、ys -14 -A7 296436 _ B7 5. Description of the invention (1) [Background of the invention] The present invention relates to a collective circuit mounted on a printed circuit board (PC board), in particular, it is equipped with a built-in circuit for detecting defective disconnection of signal terminals. The collective circuit of the test circuit. The lead-out plug-in type is a PC board equipped with a plurality of collective circuits, and has a plurality of through holes corresponding to the plurality of lead wires (external terminals) of each collective circuit, and is electrically connected to each through hole to form patterns Most of the printed wiring. According to inserting the lead wires of each collective circuit into the corresponding through holes, and soldering at all the insertion points, the electrical connection between each lead wire and the printed wiring is achieved. However, solder defects such as poor disconnection and short circuit may occur on the PC board. Defective disconnection is caused by defects such as insufficient solder supply, and unintentionally becomes disconnected between the lead wire and the printed wiring. A short-circuit defect is a defect that occurs due to excessive solder supply, etc., and many of the unintentionally printed wiring are electrically short-circuited with each other. Such solder defects will also occur when surface mounting technology and other collective circuits using packaging technology are mounted on the PC board. In the past, in order to detect the solder defects of the collective circuit on the PC board, it is tested in the circuit. (In-circurt-tester). At this time, most of the probes of the tester in the circuit will respectively contact the wiring around the collective circuit of the test object. Then, the test data signal will be supplied from a part of the probes to the input terminal of the collective circuit, and the signal obtained from the output terminal of the collective circuit will be taken as the test result signal from other probes to the tester in the circuit, and the The incoming signal is compared with the expected value. From the result of this comparison, it is determined whether there is a solder defect. However, there are a large number of collective circuit high-density paper on one PC board. The standard of China National Standard (CNS) A4 (210X297mm) is applicable I --------- approved clothing ----- 1T ------ ^ (Please read the precautions on the back first: AV this page) 1. The Ministry of Economic Affairs, Central Standards Bureau, Beigong Consumer Cooperation Du Printing Equipment Ministry of Economics, Central Standards Bureau, Employee Consumer Cooperatives, A7, B7 Explanation (2) When it is mounted at a high degree and when wiring with multiple layers of PC boards, the probe may not actually be in contact with the wiring, so the in-circuit tester is gradually unavailable. Therefore, it can be considered to use the technology of the boundary scan test (B S T) disclosed in US Patent No. 5, 084, 874, etc. to detect solder defects. According to the B ST technology, a test circuit consisting of a plurality of boundary scan cells (BSCs) is provided on each of two collective circuits connected to each other on a PC board via a plurality of printed wirings. Then, the test circuit built into one collective circuit will supply the test signal to the printed wiring via the corresponding output terminal of the collective circuit. The signals on each printed wiring will be taken into the test circuit built into the collective circuit as the test result signal through the corresponding input terminal of the other collective circuit. All B S C will be connected to each other in series in a certain mode. Therefore, the supply of the test data signal will be achieved by the scanning action, and the test result signal will be observed, and the presence or absence of solder defects will be determined based on the comparison of the test data signal and the test result signal. However, the above-mentioned detection of solder defects using the B S T technology is based on the premise that a test circuit made up of a large number of B S Cs is installed in each of the two collective circuits connected to the PC board. Therefore, when the test circuit is not installed in the collective circuit of one party, even if the test circuit is installed in the collective circuit of the other party, there is a problem that the solder defect cannot be detected. At the same time, when discrete signal active components such as transistors, diodes, etc., transformers, capacitors and other passive components are connected to the signal terminals of a collective circuit, such components cannot be equipped with a test circuit, so even if the collective circuit is equipped with a test circuit The circuit cannot detect solder defects of the signal terminals of the collective circuit. Therefore, it has not been possible to obtain a high detection rate of solder defects on the entire PC board. —Threading (please read the precautions on the back side and this page first) ~ This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 Ο X 297mm) Printed by the Ministry of Economic Affairs Central Standards Bureau Staff Consumer Cooperative A7 B7 _ V. Description of the invention (3) [Summary of the invention] The purpose of the present invention is to only test the circuit built into the collective circuit, regardless of what kind of component the collective circuit is connected to on the PC board, to enable it Detected the disconnection of the signal terminals of the collective circuit. In order to achieve this object, the present invention is to detect the poor disconnection of the signal terminal when the signal terminals of the collective circuit are normally electrically connected to the printed wiring on the PC board when the printed wiring is normally connected to the non-electrical connection. By. As a quantity representing electrical characteristics, there are resistance, inductance and floating capacity. Among them, it is desirable to select the floating capacity for easy measurement. The relationship between the charging current I (t) and the charging voltage V (t) when charging the floating capacity C of the wiring is expressed by the following formula. I (t) = CXdV (t) / dt Here, t is time. Therefore, the difference in floating capacity can be detected as the difference in g [during charging, the difference in charging current, or the difference in charging voltage. Among them, it is desirable to select the difference in charging time from the convenience of measurement. That is, the difference in the time required for charging the floating capacity is used to detect the disconnection of the signal terminal. Specifically, it will be provided in the collective circuit in the test mode via the corresponding signal terminal for supply to the PC. The floating capacity of the corresponding wiring on the board provides most of the test status buffer for charging current. Because the signal delay time of each buffer in the majority of the test states will reflect the floating capacity of this paper standard, the Chinese National Standard (CNS) A4 specification (2 丨 Ο X 297mm) --------- and Clothing ------, order ------ ^ (please read the precautions on the back-first reproduce this page) ~ Printed 206436 at B7 by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of invention (4 ) Is poor, so in the collective circuit, a mutually exclusive Ο R gate is provided to supply a logic signal having a pulse width representing the time interval between the input transition time and output transition time of each corresponding test state buffer. According to this configuration, since it is possible to detect disconnection failure regardless of any component connected to the collective circuit on the PC board, the effect of achieving a high detection rate of solder defects in the entire PC board can be obtained. [References] Hereinafter, specific examples of the collective circuit incorporating the test circuit of the present invention will be explained with reference to the drawings. FIG. 1 shows an example of the configuration of the collective circuit of the present invention. The collective circuit 10 of FIG. 1 has the first and second input terminals IN1, IN2, and one output terminal OUT, and five test terminals TDI, TD0, TCTL, TCK1, TCK2. When the collective circuit 10 is mounted on the PC board, the three signal terminals INI, IN2, and OUT will be electrically connected to the corresponding wiring on each PC board according to the solder. C in Fig. 1 represents the floating capacity of each wiring. 1 1 is the internal logic (application logic) that enables the original circuit of collective circuit 10 to be internally connected to the three terminals IN 1, IN2, and UT. Between the internal logic 11 and the output terminal OUT, when the test control signal TCTL specifies the test mode (TCTL 2 1), it maintains a high impedance output, and the test control signal TCTL specifies the non-test mode (TCTL = 0). The signal 'from the internal logic 1 1 to the test state buffer 12 of the output terminal OUT. In addition, although the example in Figure 1 is applicable to the Chinese national standard (CNS) A4 specification (210ΧΜ7mm), the paper scale is I .--------- installed ------ order ---- --Line 1 '' '(please read the notes on the back-page first) A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (5) 1 I Consider the convenience of the description and change the number of signal terminals As 3 9 but not limited to this 1 1 built-in 1 bfl Figure 1 collective circuit 1 0 test circuit 9 with the first and 1 1 I please 1 • j second flip-flop 2 1 9 2 6 9 And 1st 5th 2nd and 3rd test status first read 1 I read 1 buffer 2 2 a 9 2 2 b, 2 2 C 9 and 1 9 2nd and 3rd mutually opposite Λ 1 of 1% or% Gate 2 3 a > 2 3 b 9 2. 3 C 9 and 1 and gate note 1 1 2 4 9 and 1 selector 2 5 〇 Matters 1 1 1 1st D flip-flop 2 1 9 series will Test Information Letter No. TD 1 and the first installed test clock signal TCK 1 rising latch synchronously 9 and used to latch the page 1 1 signal of the Azb lock to three test status buffers 2 2 a 9 2 2 b 9 1 1 2 2 C input input flip-flop 〇3 test B6Δ. Jue state buffer 2 2 a 9 1 | 2 2 b 5 2 2 C common input signal as DI 0 order I first test state buffer 2 2 a is to input the signal D 0 a to the first 1 1 1 I input terminal IN 1 9 2nd test state buffer 2 2 b is to send the signal 1 1 ID 0 b to the second input terminal IN 2 and the 3rd test state Buffer 1 1 2 2 C is to output signal D 0 C to output terminal 0 UT respectively. When line 1 test control signal TCTL specifies the test mode (TCTL = 1) .1 J 1st test state buffer 2 2 a Will pass the first input terminal IN 1 1 I 9 2nd test status buffer 2 2 b Will pass the second input terminal IN 2 1 I 9 3rd The status buffer 2 2 c will supply a small charge to the floating capacity C of the corresponding wiring on the PC board via the output terminal 0 UT 1 1 I 1 * Current 1 When the test control signal TC τ L specifies the non-test mode ( 1 1 TCTL = 0) when 9 3 wishing state buffers 2 2 a 2 2 b 1 1 9 2 2 C will all maintain a high impedance m out of the first mutual exclusion or gate 2 3 a 1 1 paper mediocre scale General Chinese National Standard (CNS) Λ4 specification (2 丨 OX 297mm) Printed A7 B7 by the Central Committee of the Ministry of Economic Affairs of the Ministry of Economic and Social Welfare Co., Ltd. Printed A7 B7 5. Description of invention (6), will be provided with a buffer 2 indicating the first test status The logic signal XORa of the pulse width of the time interval between the rising transition time of the input signal DI of 2 a and the rising transition time of the output signal D 0 a of the first test state buffer 2 2 a. The second mutually exclusive or OR gate 2 3 b will be supplied with the rising transition time of the input signal DI indicating the second test state buffer 2 2 b and the rising of the output signal DO b of the second test buffer 2 2 b The logic signal XOR b of the pulse width at the time interval of the transition time. The third mutually exclusive * or gate 2 3 c will be supplied with the rising transition time of the input signal DI indicating the third test state buffer 2 2 c and the rising of the output signal DOc of the third test state buffer 2 2 c The logic signal XORc of the pulse width at the time interval of the transition time. * And ^ gate 2 4 are the logical product signals AND that supply three logical signals XORa, XORb, and XORc. The selector 2 5 is the logical product signal AND when the test control signal TCTL specifies the test mode (TCTL = 1), and the first D flip-flop 2 1 when the test control signal TCTL specifies the non-test mode (TCTL = 0) The output signals are sent to the 2D flip-flop 26 as data signal providers. The second 2D flip-flop 2 6 latches the data signal supplied from the selector 25 and the rising transition of the second test clock signal TCK2 synchronously, and outputs the latched signal as the test result signal TD 0 The output flip-flop ○ Figure 2 shows the test action of the above collective circuit 1 TC (TCTL = 1). Here, it will be regarded as two input terminals IN1, IN 2 has no solder defects, and the output terminal OUT has a poor disconnection. This paper standard is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297 mm) IH binding I binding line (Please read the note 1 on the back of this page first. 4. This page) 'The A7 B7 ~ I _ _ _ _ _ printed by the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (7) Solder defects. After the logic value of the test data input signal TD 1 is set to 1, when the first test clock signal TCK1 rises at time 71, the output signal of the first D flip-flop 21 will change from the logic value 0 to the logic value 1. That is, the common input signal DI of the three test state buffers 22a, 22b, and 22c will rise and change. Since the two input terminals INI 'IN2 do not have solder defects, the first and second test state buffers 2 2 a, 2 2 b will supply a small charging current to the floating capacity C, respectively. The signal delay time of the buffer 2 2 a in the first test state is the sum of the gate delay time Tg inherent to the buffer and the wiring delay time Tw of the floating capacitor C depending on the wiring. The buffer 2 2 b is the same in the second test state. On the one hand, since the output terminal OUT has a defective solder defect, the third test state buffer 2 2 c will not supply the charging current to the floating capacity C. Therefore, the signal delay time of the buffer 2 2 c in the third test state will be consistent with the buffer's inherent gate delay time Tg. That is, as shown in FIG. 2, the third test state buffer. The output signal DOc of 2 2 c rises and changes at time T2, and the output signals D of the first and second test state buffers 2 2 a, 2 2 b 〇a, DOb will rise and change at time T3. As a result, the logical signals XORa supplied from the first and second mutually exclusive "^ or" gates 2 3 a, 2 3 b, XORb will have a pulse width Tg + Tw, from the third mutually exclusive, or "gate 2 The logic signal XORc supplied by 3c will have a pulse width Tg. That is, the logical product signal supplied from the AND gate 24 has a pulse width Tg. The wiring delay time Tw is expressed by the following formula. The standard of this paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) —. Gutter (please read the notes on the back page first) -10-A7 B7-· ----. V. Description of the invention (8) T w = CXT c Binding. Here, T c is the delay time per unit capacity, for example, it will be set to 10 ns / pF. At this time, even if the floating capacity C is 1 pF, there will be a time difference of 10 n s between the rising transition time T2 of the signal DOc and the rising transition time T3 above the signals DOa and DOb. Then, the second test clock signal TCK2 rises at time Tm between time T2 and time T3. Since the value n of the logical product signal AND at the time Tm has become 0, the 2D flip-flop 26 latches the logical value 0, and the test result signal TDO will become the logical value 0 indicating “there is a disconnection failure”. The test result signal TD0 will be observed at time T4. When the 2f§ input terminals INI, IN2 and one output terminal OUT are free of solder defects, as shown in the imaginary line (two-point chain line) in Figure 2, the test result signal TD 0 at time T4 will become "no The logic value of "disconnection failure" is 1. Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs As mentioned above, according to the collective circuit 10 of FIG. 1, only the test circuit built in the collective circuit 10 can detect three signal terminals IN 1 2. Is there any signal terminal with bad disconnection in OUT? That is, the collective circuit 10 on the PC board related to solder defects can be easily realized, so-called GO / NG test. Fig. 3 shows an example of mounting a PC board containing a plurality of circuit elements related to the four collective circuits of the present invention. On the PC board 5 of FIG. 3, the first, second, third, and fourth collective circuits 10a, 10b, 10c, and 10d of the built-in test circuits of FIG. 1 are installed. The scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) -11-206436 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (9) 1 9 and memory 1 5 9 and transformer 1 6, and transistor group 1 7 9 and number 1 1 bit analog converter (DAC) 1 8 9 and light emitting diode (LED) 1 I group 1 9 〇4 collective circuit 1 0 a 9 1 0 b 1 0 C 9 1 0 d «VI has 6 letters Ofeb terminal 9 and 5 test terminals TD 1 9 TD 0 Please read 1 9 I TCTL first, TCK 1 9 TCK 2 0 PC board 5 9 has 7 |-face | Signal terminals, and 5 test UIi terminals TD 1 TD 0 5 TCTL 9 of 1 ί TCK 1, TCK 2 0 are externally supplied to the PC board 5 test controller 1 item I control signal TCTL, the first test clock signal TCK 1 and 2nd test 1 do not install Thousand clock signal TCK 2 9 will be supplied to 4 collective circuits in parallel 1 1 1 1 0 a, 1 0 b, 1 0 C 1 0 d 〇 Test control signal 1 1 When TCTL specifies the non-test mode (TCTL — 0) 0 According to the function of the selector 1 | selector 2 5 (see ΓΗΓΙ Figure 1) as shown in Figure 3 9 on the PC board 5 order I between the test data input terminal TD 1 and the test result output terminal TD 0 1 1 I, within Installed in 4 collective circuits 1 0 a 9 1 0 b 9 1 0 C 9 1 1 1 1 0 d Total 8 D flip-flops 2 1 9 2 6 Will be connected in series with each other 0 1 Memory 1 5 and DAC 1 8 9 are collective electrical circuits without built-in test circuits. Transformer 1 6, transistor group 1 7 and LED group 1 9 9 are all different. 1 1 Components that can contain a test circuit 0 1 According to the PC board of Figure 3, 4 collective circuits 1 0 a 9 1 I 1 0 b , 1 0 C 9 1 0 d of each test data signal supply 9 and 4 1 1 | a collective circuit 1 0 a 9 1 0 b > 1 0 C 9 1 0 d of each test result 1 observation of the signal> ; Will be based on the same scanning action as the previous BST technology 1 1 (TCTL 0) to achieve 0. At this time 9 will be used as the first test clock 1 1 signal TCK 1 and the second test time signal TCK 2 9 externally supplied 1 1 This paper scale is applicable to China National Standard Falcon (CNS) A4 specification (2 丨 OX 2Q7mm) -12-A7 A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (i〇) Same clock signal . At the same time, when the test control signal TCTL (TCTL = 1) of the designated test mode is supplied to the PC board 5 from the outside, the floating capacity of each signal terminal according to the four collective circuits 1 〇a, 1 Ob, 1 0c, 1 0d will be implemented. Disconnect the bad test. Specifically, two signal terminals of the first collective circuit 10 a, two signal terminals of the second collective circuit 10 c, and two signal terminals of the fourth collective circuit 10 d are connected to the memory via each printed wiring Although there is no built-in test circuit in the device 15 and the memory 15, these signal terminals can detect the disconnection failure. The other two signal terminals of the first collective circuit 1 0 a, one signal terminal of the second collective circuit 1 0 b and the other two signal terminals of the fourth collective circuit 10 d, although they are printed on the PC board 5 via printed wiring Of the signal terminals are open, but each can detect a defective disconnection. The other one signal terminal of the second collective circuit 1 0 b is connected to the transformer 16 via printed wiring, and the other four signal terminals of the second collective circuit 1 0 b are respectively connected to the base electrodes of the transistor group 17 via printed wiring The other four signal terminals of the third collective circuit 10 c are connected to the anodes of the LED group 19 via printed wiring, although the transformer 16, the transistor group 17 and the LED group 19 cannot be built-in test circuits. Components, but these signal terminals can also detect poor disconnection. Although the other two signal terminals of the first collective circuit 10 a and the other two signal terminals of the fourth collective circuit 10 d are connected to each other via printed wiring, respectively, they can detect a disconnection failure. Therefore, according to the configuration of FIG. 3, the detection rate of solder defects in the entire PC board 5 is greatly improved compared with the conventional BST technology. Fig. 4 shows another configuration example of the collective circuit of the present invention. The scale of the paper and paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) III. Set-line (please read the precautions on the back first ~ this page) A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Inventions Description (11) The collective circuit 30 of 4 has the first and second input terminals IN1, IN2, and one output terminal OUT, and four test terminals TDI, TD0, TCTL, TCLK. When the collective circuit 30 is mounted on the PC board, the three signal terminals INI, IN2, OUT will be electrically connected to the corresponding wiring on the PC board according to the solder. C in Figure 4 represents the floating accommodation of each wiring. 3 1 is the internal logic (application logic) that enables the original function of the collective circuit 30 to be internally connected to the three signal terminals IN1, IN2, and OUT. Between the internal logic 31 and the output terminal OUT, the high impedance output will be maintained when the test control signal TCTL specifies the test mode (TCTL = 1), and the test control signal TCTL specifies the non-test mode (TCTL = 0) from The internal logic 31 transmits the test state buffer 32 for outputting a signal to the output terminal OUT. In addition, although the example of FIG. 4 considers the convenience of description and the number of signal terminals is three, it is not limited to this. The test circuit built in the collective circuit of FIG. 4 has the first mutually exclusive OR gate 4 1 , And the delay circuit 4 2, and the first selector 4 2, and the second, third and fourth selectors 44a, 44b, 44c, and the fifth, sixth and seventh selectors 4 5a, 4 5b, 4 5c, and 1st, 2nd and 3D flip-flops 4 6a, 4 6b, 4 6c, and 1st, 2nd and 3rd test status buffers 4 7a, 4 7b, 4 7 c, and 2nd, The third and fourth mutually exclusive% or gates 48a, 48b, 48c Ο Delay circuit 42 is used to make the test clock signal supplied from the outside of the paper standard of China National Standards (CNS) Λ4 specifications (2 丨 OX 297 Mm) (please read the notes on the back. 'Write this page), ys -14-
經濟部中央標準局員工消費合作社印$L A7 B7 五、發明説明（l2) TCLK延遲一定時間ΛΤ的電路。第1互斥|或#閘 4 1 ，係將測試時鐘信號TCLK和延遲電路4 2之輸出 信號的排斥性邏輯和信號做爲內部時鐘信號X 0 R供給者 。第1選擇器4 3，係測試控制信號TCTL指定測試模 式（TCTL=1 )時把從第1互斥*或#閘4 1供給之 內部時鐘信號XOR，而測試控制信號TCTL指定非測 試模式（TCTL=0 )時把從外部供給之測試時鐘信號 TCLK分別供給3個D正反器4 6 a，4 6b，4 6 c 者。 第2選擇器4 4 a，係測試時鐘信號TCLK之邏輯 値爲0時，把第1 D正反器4 6 a的反轉輸出信號做爲自 生成之測試資料信號選擇，而測試時鐘信號TC LK的邏 輯値爲1時，將選擇從第2互斥*或〃閘4 8 a供給之邏 輯信號XORa者。第5選擇器4 5 a，係測試控制信號 TCTL指定測試模式（TCTL = 1 )時把根據第2選 擇器4 4 a選擇之信號，而測試控制信號TCTL指定非 測試模式（TCTL=0 )時把第2正反器4 6 b的非反 轉輸出信號分別向第1 D正反器4 6 a做爲資料信號供給 者。第1 D正反器4 6 a，係將從第5選擇器4 5 a供給 之資料信號同步地閂鎖在從第1選擇器4 3供給的時鐘信 號之上升變遷，且把該閂鎖的信號供給第1試驗狀態緩衝 器4 7 a者。第1 D正反器4 6 a之非反轉輸出，係連接 在測試結果輸出端子TD0。 第3選擇器4 4 b，係測試時鐘信號TCLK之邏輯 本紙浪尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） __I ^ I I I I 裝 I —訂 I I I ! I i 線 (請先閱讀背面之注意事項再厂:^本頁) 一 -15 - 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（13) 値爲0時把第2 D正反器4 6 b的反轉輸出信號做爲自生 成之測試資料信號選擇，而測試時鐘信號TC LK的邏輯 値爲1時，將選擇從第3互斥a或'閘4 8 b供給之邏輯 信號XORb者。第6選擇器4 5 b，係測試控制信號 TCTL指定測試模式（TCTL=1 )時，把根據第3 選擇器4 4 b選擇之信號，而測試控制信號TCTL指定 非測試模式（TCTL=0 )時，把第3D正反器4 6 c 之非反轉輸出信號分別向第2 D正反器4 6 b做爲資料信 號供給者。第2D正反器4 6 b，把從第6選擇器4 5 b 供給之資料信號和從第1選擇器4 3供給的時鐘信號之上 升變遷同步地閂鎖，且把該閂鎖的信號向第2試驗狀態緩 衝器4 7 b供給者。 第4選擇器4 4 c，係測試時鐘信號TCLK之邏輯 値爲0時，將第3D正反器4 6 c的反轉输出信號做爲自 生成之測試資料信號選擇，而測試時鐘信號TC LK的邏 輯値爲1時，將選擇從第4互斥^或〃閘4 8C供給之邏 輯信號XORc者。第7選擇器4 5 c，係測試控制信號 TCTL指定測試模式（TCTL=1 )時把根據第4選 擇器4 4 c選擇之信號，而測試控制信號TCTL指定非 測試模式（TCTL = 0 )時，把經由測試資料輸入端子 TD1供給的信號，分別向第3D正反器4 6 c做爲資料 信號供給者。第3D正反器4 6 c，把從第7選擇器 4 5 c供給之資料信號和從第1選擇器4 3供給的時鐘信 號之上升變遷同步地閂鎖，且把該閂鎖的信號向第3試驗 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐) —^ 裝 I I I訂I I 線 (請先閱讀背面之注意事項> 冩本頁) -16 - 經濟部中央標準局員工消費合作社印製 A7 _______B7____ 五、發明説明（Η) 狀態緩衝器4 7 C供給者。 第1試驗狀態緩衝器4 7 a係把信號DOa向第1輸 入端子IN1 ，第2試驗狀態緩衝器4 7 b係把信號 DOb向第2输入端子IN2 ，第3試驗狀態緩衝器4 7 c係把信號DO c向输出端子OUT分別輸出者。測試控 制信號TCTL指定測試模式（TCTL=1 )時，第1 試驗狀態緩衝器4 7 a將經由第1输入端子IN1 ，第2 試驗狀態緩衝器4 7b將經由第2输入端子IN2，第3 試驗狀態緩衝器4 7 c將經由输出端子OUT分別向PC 板上之對應配線具有的浮動容量C供給微小之充電電流。 測試控制信號TCTL指定非測試模式（TCTL=0 ) 時，3個試驗狀態緩衝器4 7 a，4 7 b，4 7 c皆將保 持高阻抗輸出。第2互斥^或^閘4 8 a，將供給具有表 示第1試驗狀態緩衝器4 7 a之輸入信號D I a的上升變 遷時刻，和第1試驗狀態緩衝器4 7 a之輸出信號D〇a 的上升變遷時刻之時間間隔的脈寬之邏輯信號XOR a。 第3互斥^或"閘4 8 b，將供給具有表示第2試驗狀態 緩衝器4 7 b的輸入信號D I b之上升變遷時刻，和第2 試驗狀態緩衝器4 7 b的輸出信號D〇b之上升變遷時刻 的時間間隔之脈寬的邏輯信號XORb。第4互斥、或， 閘4 8 c，將供給具有表示第3試驗狀態緩衝器4 7 c的 輸入信號D I c之上升變遷時刻，和第3試驗狀態緩衝器 4 7 c的输出信號DO c之上升變遷時刻的時間間隔之脈 寬的邏輯信號X〇Rc。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210 X 297公釐）' " ~~ —^ — 裝 訂 線 (請先閲讀背面之注意事項再 ~本頁) 經濟部中央標準局負工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 x 297公釐） A7 ______B7_______ 五、發明説明（is ) 根據圖4之集體電路3 0時，對3個D正反器4 6 a ’ 4 6 b，4 6 c的各測試資料信號之供給，和閂鎖在該 3個D正反器4 6 a，4 6 b，4 6 c的各測試結果信號 之觀測，將根據和已往的B S T技術相同之掃描動作（ TCTL = 0 )而達成。譯言之，當測試控制信號 TCTL指定非測試模式（TCTL=0 )時，將形成從 測試資料輸入端子TD1 ，經由第7選擇器4 5 c，第 3D正反器4 6 c，第6選擇器4 5 b，第2D正反器 4 6 b，第5選擇器4 5 a及第1D正反器4 6 a至測試 結果输出端子TD 0之掃描路線。同時，向3個D正反器 4 6 a，4 6 b，4 6 c將分別有從外部供給的測試時鐘 信號TC LK，做爲資料轉移用之時鐘信號供給。 圖5，顯示上述集體電路3 0之測試動作（TCTL =1〉。在此，係做爲2個輸入端子INI， IN2不具 有焊錫缺陷，而輸出端子OUT具有斷開不良之焊錫缺陷 。同時，做爲3個D正反器4 6a，4 6b，4 6 c的各 非久轉输出信號，係根據掃描動作（TCTL=0)，皆 事先設定爲邏輯値0。因此，在測試時鐘信號TC LK的 邏輯値爲0之間，3個D正反器4 6a，4 6b，4 6c 的各反轉輸出信號，將分別做爲遍輯値1之自生成的測試 資料信號，而分別供給該3個D正反器4 6 a，4 6 b， 4 6 c ° 第1互斥、或^閘4 1和延遲電路4 2，將從測試時 鐘信號TCLK生成內部時鐘信號X〇R °生成之內部時 -18 - .I裝 訂 線 (請先閲讀背面之注意事¾.. V寫本頁) * A7 B7 經濟部中央標準局員工消费合作社印製 五、 發明説明 ( 16; 1 I 鐘 信 疏 X 0 R > 係 如 圖 5 所 示 具 有 從 測 試 時 適 信 號 1 1 T C L K 的 上 升 變 遷 時 刻 開 始 之 寬 △ T 的 脈 波 P 1 9 和 從 1 1 測 試 時 鐘 信 號 T C L K 之 下 降 變 遷 時 刻 開 始 的 寬 △ T 之 脈 /-—V 1 請 I 波 P 2 者 0 先 閱 1 | 讀 I 在 時 刻 T 1 把 測 試 時 鐘 信 號 T C L K 上 升 時 9 3 個 D 背 面 1 I 正 反 器 4 6 a ， 4 6 b 4 6 C 之 各 非 反 轉 輸 出 信 號 9 將 之 注 » 1 和 升 步 思 事 1 內 部 時 鐘 信 號 X 0 R 的 脈 波 P 1 之 上 變 遷 同 9 皆 從 項 , 1 邏 輯 値 0 向 邏 輯 値 1 變 遷 〇 亦 即 ， 3 個 試 驗 狀 態 緩 衝 器 本 1 裝 4 7 a 9 4 7 b ， 4 7 C 的 各 輸 入 信 號 D I a 9 D I b 9 頁 1 1 D I C 皆 將 上 升 變 遷 0 因 2 個 輸 入 端 子 I N 1 9 I N 2 皆 1 1 不 具 有 焊 錫 缺 陷 9 故 第 1 及 第 2 試 驗 狀 態 緩 衝 器 4 7 a 9 1 | 4 7 b 將 分 別 向 各 浮 動 容 量 C 供 給 微 小 之 充 電 電 流 0 在 第 訂 1 1 試 驗 狀 態 緩 衝 器 4 7 a 的 信 號 延 遲 時 間 9 將 成 爲 緩 衝 器 1 1 1 固 有 之 閘 延 遲 時 間 T S 9 和 依 賴 配 線 具 有 的 浮 動 容 量 C 之 1 1 I 配 線 延 遲 時 間 T W 的 和 〇 在 第 2 試 驗 狀 態 緩 衝 器 4 7 b 亦 ..... 1 1 相 同 〇 一 方 面 y 輸 出 端 子 0 U T 因 具 有 斷 開 不 良 之 焊 錫 缺 線 1 陷 9 故 第 3 試 驗 狀 態 緩 衝 器 4 7 C 將 不 進 行 向 浮 動 容 量 C 1 1 供 給 充 電 電 流 〇 因 此 9 在 第 3 試 驗 狀 態 緩 衝 器 4 7 C 的 信 1 號 延 遲 時 間 9 將 和 緩 衝 器 固 有 之 閘 延 遲 時 間 T g — 致 〇 亦 1 1 I 即 9 如 圖 5 所 示 > 第 3 試 驗 狀 態 緩 衝 器 4 7 C 的 输 出 信 號 1 1 D 0 C 上 升 變 遷 後 9 第 1 及 第 2 試 驗 狀 態 緩 衝 器 4 7 a 9 - 1 1 4 7 b 之 输 出 信 號 D 0 a ， D 0 b 將 上 升 變 遷 〇 結 果 9 從 1 1 第 1 及 第 2 互 斥 % 或 閘 4 8 a 9 4 8 b 供 給 的 遍 辑 信 號 1 1 X 0 R a 9 X 0 R b 將 具 有 脈 寬 T g + T W y 而 從 第 3 互 1 1 本紙張尺度通用中國國家標隼（CNS ) A4規格（2丨0X2^7公釐） -19 - A 7 B7 經濟部中央標準局貝工消費合作社印製 五、 發明説明 ( 17) 1 斥 或 • 閘 4 8 C 供 給 之 邏 輯 信 號 X 0 R C 將 具 有 脈 寬 1 1 T g 〇 1 I 在 從 時 刻 T 1 經 過 時 間 △ T 1 之 時 把 測 試 時 鐘 信 號 1 | T C L K 下 降 時 y 和 內 部 時 鐘 信 疏 X 0 R 的 脈 波 P 2 之 上 請 先 閲 1 I 升 變 遷 同 步 9 3 個 邏 輯 信 號 X 0 R a 5 X 0 R b 讀 背 1 ' 1 1 X 0 R C 將 分 別 閂 鎖 在 D 正 反 器 4 6 a 4 6 b ， 4 6 C 之 注 1 I 意 I 〇 此 時 j 係 T S < △ T 1 < T 8 + T W 0 因 此 5 信 號 事 1 1 D I a 將 成 爲 表 示 厂 無 斷 開 不 良 J 之 涵 7m 輯 値 1 9 信 號 寫 本 1 裝 D I b 將 成 爲 表 示 厂 無 斷 開 不 良 J 的 邏 輯 値 1 9 信 號 頁 1 1 D I c 將 成 爲 表 示 厂 有 斷 開 不 良 J 之 邏 輯 値 0 Ο 此 等 信 號 1 1 D I a 9 D I b 9 D I C 將 根 據 掃 描 動 作 ( T C T L = 0 1 I ) 5 經 由 測 試 結 果 输 出 端 子 T D 0 觀 測 〇 再 者 9 如 圖 5 所 1 訂 I 示 9 在 時 刻 T 2 將 測 試 時 鐘 信 號 T C L K 再 度 上 升 9 更 在 I 1 I 經 過 時 間 Δ T 2 時 把 測 試 時 鐘 信 號 T C L K 下 降 時 9 信 號 1 1 1 D I a 9 D I b 9 D I C 之 各 邏 輯 値 將 全 部 回 復 爲 0 〇 在 1 1 線 1 此 9 爲 T g + T W < △ T 2 0 如 以 上 所 述 > 根 據 圖 4 之 集 體 電 路 3 0 時 > 能 夠 只 以 1 1 內 裝 在 該 集 體 電 路 3 0 的 測 試 電 路 J 將 3 個 信 號 端 子 1 I N 1 ί I N 2 9 〇 U T 之 中 具 有 mi m 開 不 良 的 信 號 端 子 特 1 I 定 〇 因 此 9 有 能 夠 將 斷 開 不 良 處 容 易 修 理 之 優 點 0 而 且 9 1 1 I 因 3 個 D 正 反 器 4 6 a 9 4 6 b 9 4 6 C 分 別 兼 有 用 以 測 1 1 試 資 料 信 號 的 輸 入 之 輸 入 正 反 器 的 機 能 ， 和 輸 出 測 試 結 果 1 1 信 號 之 输 出 正 反 器 機 能 9 故 測 試 電 路 的 規 模 變 小 〇 同 時 > 1 1 因 把 具 有 用 以 閂 鎖 測 試 信 號 之 脈 波 P 1 9 和 閂 鎖 測 試 結 果 1 1 本紙悵尺度適用中國國家標準（CNS ) A4規格（2丨OX 297公釐） A7 B7 五、發明説明（18) 信號的脈波P 2之內部時鐘信號XOR，以第1互斥、或 ^閘4 1和延遲電路4 2生成，故能得到只從外部供給j 個測試時鐘信號TC LK即可的優點。 再者，雖然在圖1及圖4之例，係把供給測試資料信 號和觀測測試結果信號，做爲根據和已往的B S T技術相 同之掃描動作達成，但是並不限於此。同時，本發明不限 於數位集體電路，也能夠適用於類比集體電路。 四.圚面之簡單說明 圖1 ，爲顯示有關本發明之集體電路的構成例之電路 圖。 圖2，爲顯示圖1之集體電路的測試動作之時序圖。 圖3，爲顯示實裝包含將圖1中各構成擴張的測試電 路內裝之4個集體電路的多數電路元件之P C板的例之方 塊圖。 J--.------^------.訂------^ (請先閲讀背面之注意事現¾寫本頁) 經濟部中央標準局員工消费合作社印製 圖圖圖 路 Imml ιρτ 4 5 的 例 成 構 他 其 之 路 S 體 舅 的 明 發 本 關 有 示 顯 爲 圖 序 時 之 作 mn 試 測 的 路 電 體 集 之 4 圖 示 顯 爲 本紙悵尺度通用中國國家標準（CNS ) A4規格（210 X 297公釐） -21 -$ L A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention Description (l2) A circuit with TCLK delayed by a certain time ΛΤ. The first mutual exclusion | or # gate 4 1 is the exclusive logical sum signal of the test clock signal TCLK and the output signal of the delay circuit 42 as the internal clock signal X 0 R supplier. The first selector 4 3 is the test control signal TCTL designating the test mode (TCTL = 1) when the internal clock signal supplied from the first mutually exclusive * or # gate 4 1 is XOR, and the test control signal TCTL designates the non-test mode ( TCTL = 0), the test clock signal TCLK supplied from the outside is supplied to three D flip-flops 4 6 a, 4 6 b, 4 6 c respectively. The second selector 4 4 a is when the logic value of the test clock signal TCLK is 0, the inverted output signal of the first D flip-flop 4 6 a is selected as the self-generated test data signal, and the test clock signal TC When the logic value of LK is 1, the logic signal XORa supplied from the second mutually exclusive * or gate 4 8 a will be selected. The fifth selector 4 5 a is the signal selected according to the second selector 4 4 a when the test control signal TCTL specifies the test mode (TCTL = 1), and the test control signal TCTL specifies the non-test mode (TCTL = 0) The non-inverted output signals of the second flip-flop 4 6 b are respectively supplied to the first D flip-flop 4 6 a as data signal suppliers. The first D flip-flop 4 6 a latches the data signal supplied from the fifth selector 4 5 a synchronously at the rising transition of the clock signal supplied from the first selector 43, and the latched The signal is supplied to the first test state buffer 47a. The non-inverted output of the first 1D flip-flop 4 6 a is connected to the test result output terminal TD0. The third selector 4 4 b is the logical clock of the test clock signal TCLK. The paper standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) __I ^ IIII Pack I — order III! I i line (please read the back first Matters needing attention to re-factory: ^ this page) 1-15-A7 B7 printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (13) When the value is 0, the second D flip-flop 4 6 b is reversed The output signal is selected as the self-generated test data signal, and when the logic value of the test clock signal TC LK is 1, the logic signal XORb supplied from the third mutually exclusive a or gate 4 8 b will be selected. 6th selector 4 5 b, when the test control signal TCTL specifies the test mode (TCTL = 1), the signal selected according to the 3rd selector 4 4 b, and the test control signal TCTL specifies the non-test mode (TCTL = 0) At this time, the non-inverted output signals of the 3D flip-flop 4 6 c are sent to the second D flip-flop 4 6 b as data signal providers. The 2D flip-flop 4 6 b latches the data signal supplied from the sixth selector 4 5 b and the rising transition of the clock signal supplied from the first selector 4 3 synchronously, and latches the latched signal to The second test state buffer 4 7 b supplier. The fourth selector 4 4 c is when the logic value of the test clock signal TCLK is 0, the inverted output signal of the 3D flip-flop 4 6 c is used as the self-generated test data signal selection, and the test clock signal TC LK When the logic value of is 1, the logic signal XORc supplied from the fourth mutex or gate 48C will be selected. The seventh selector 4 5 c is the signal selected according to the fourth selector 4 4 c when the test control signal TCTL specifies the test mode (TCTL = 1), and the test control signal TCTL specifies the non-test mode (TCTL = 0) The signals supplied through the test data input terminal TD1 are respectively supplied to the 3D flip-flop 46 c as data signal suppliers. The 3D flip-flop 4 6 c latches the data signal supplied from the seventh selector 4 5 c and the rising transition of the clock signal supplied from the first selector 4 3 synchronously, and latches the latched signal to The paper size of the third test is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm) — ^ Binding III line II (please read the precautions on the back first> page of this page) -16-Staff of Central Bureau of Standards, Ministry of Economic Affairs Printed by the consumer cooperative A7 _______B7____ V. Description of invention (H) Status buffer 4 7 C supplier. The first test state buffer 4 7 a is to send the signal DOa to the first input terminal IN1, the second test state buffer is 4 7 b is to send the signal DOb to the second input terminal IN2, and the third test state buffer is 4 7 c The signal DO c is separately output to the output terminal OUT. When the test control signal TCTL specifies the test mode (TCTL = 1), the first test state buffer 4 7 a will pass the first input terminal IN1, the second test state buffer 4 7 b will pass the second input terminal IN2, the third test The state buffer 47c will supply a small charging current to the floating capacity C of the corresponding wiring on the PC board via the output terminal OUT, respectively. When the test control signal TCTL specifies the non-test mode (TCTL = 0), the three test status buffers 4 7 a, 4 7 b, and 4 7 c will all maintain high impedance output. The second mutex ^ or ^ gate 4 8 a will supply the rising transition time with the input signal DI a indicating the first test state buffer 4 7 a and the output signal D of the first test state buffer 4 7 a. The logic signal XOR a of the pulse width of the time interval of the rising transition time of a. The third mutually exclusive ^ or "gate 4 8 b" will supply the rising transition time with the input signal DI b indicating the second test state buffer 4 7 b and the output signal D of the second test state buffer 4 7 b The logic signal XORb of the pulse width of the time interval at the rising transition time of 〇b. The fourth mutual exclusion, or gate 4 8 c, will supply the rising transition time with the input signal DI c indicating the third test state buffer 4 7 c and the output signal DO c of the third test state buffer 4 7 c The logic signal XORC of the pulse width at the time interval of the rising transition time. This paper scale is applicable to the Chinese National Standard (CNS) Λ4 specification (210 X 297 mm) '" ~~ — ^ — binding line (please read the precautions on the back before this page) The Ministry of Economic Affairs Central Standards Bureau negative labor consumption The paper size of the paper printed in cooperation with China is applicable to the Chinese National Standard (CNS) A4 (2 丨 0 x 297mm) A7 ______B7_______ 5. Invention Description (is) According to the collective circuit 30 in Figure 4, the three Ds are positive and negative 4 6 a '4 6 b, 4 6 c of the test data signal supply, and latch the 3 D flip-flop 4 6 a, 4 6 b, 4 6 c of the test result signal observation, It will be achieved based on the same scanning action (TCTL = 0) as the previous BST technology. In other words, when the test control signal TCTL specifies the non-test mode (TCTL = 0), the test data input terminal TD1 will be formed via the seventh selector 4 5 c, the third 3D flip-flop 4 6 c, and the sixth selection 4 5 b, 2D flip-flop 4 6 b, 5th selector 4 5 a and 1D flip-flop 4 6 a to the test result output terminal TD 0 scanning route. At the same time, the three D flip-flops 4 6 a, 4 6 b, and 4 6 c will have test clock signals TC LK supplied from the outside as clock signals for data transfer. Figure 5 shows the test operation of the above collective circuit 30 (TCTL = 1>. Here, it is used as two input terminals INI, IN2 does not have solder defects, and the output terminal OUT has solder defects that are poorly disconnected. At the same time, As the three D flip-flops 4 6a, 4 6b, 4 6 c, the non-long-duration output signals are set to logic 0 in advance according to the scanning action (TCTL = 0). Therefore, the test clock signal TC The logic value of LK is between 0, and each of the inverted output signals of the three D flip-flops 4 6a, 4 6b, 4 6c will be used as the self-generated test data signal of the compiling value 1, and supplied to the respective Three D flip-flops 4 6 a, 4 6 b, 4 6 c ° The first mutually exclusive, OR ^ gate 4 1 and delay circuit 4 2 will generate an internal clock signal X〇R ° from the test clock signal TCLK Internal time -18-.I binding line (please read the notes on the back ¾ .. V to write this page first) * A7 B7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (16; 1 I Zhong Xinshu X 0 R > as shown in Figure 5 when there is a transition from the test signal 1 1 TCLK rising Pulse width P 1 9 of the starting width △ T and the pulse width △ T starting from the moment of the falling transition of the 1 1 test clock signal TCLK / -— V 1 I wave P 2 0 0 Read 1 | Read I at time T 1 When the test clock signal TCLK rises 9 3 D backside 1 I flip-flop 4 6 a, 4 6 b 4 6 C each non-inverted output signal 9 Note it »1 and step by step 1 internal clock The transition on the pulse wave P 1 of the signal X 0 R is the same as 9 from the term, 1 logical value 0 to logical value 1 transition. That is, 3 test state buffers 1 installed 4 7 a 9 4 7 b, 4 7 Each input signal of C DI a 9 DI b 9 Page 1 1 DIC will rise and change 0 Because 2 input terminals IN 1 9 IN 2 are both 1 1 No solder defects 9 So the first and second test status buffer 4 7 a 9 1 | 4 7 b will provide a small charge to each floating capacity C Flow 0 in order 1 1 The signal delay time 9 of the buffer state 4 7 a of the test state will be 1 of the gate delay time TS 9 of the buffer 1 1 1 and the floating capacity C depending on the wiring 1 1 I of the wiring delay time TW Same as 〇 in the second test state buffer 4 7 b ..... 1 1 same. On the one hand y output terminal 0 UT due to defective solder disconnection of the solder wire 1 sink 9 so the third test state buffer 4 7 C will not supply the charging current to the floating capacity C 1 1. So 9 in the third test state the buffer 4 7 C signal 1 delay time 9 will be the same as the buffer's inherent gate delay time T g-the same 1 1 I is 9 as shown in Figure 5> The output signal of the third test state buffer 4 7 C 1 1 D 0 C After the rising transition 9 The first and second test state buffers 4 7 a 9-1 1 4 7 b The output signal D 0 a, D 0 b will rise and change. The result 9 changes from 1 1 to the first and second. Reject% or gate 4 8 a 9 4 8 b Supplied traverse signal 1 1 X 0 R a 9 X 0 R b will have a pulse width T g + TW y and from the 3rd mutual 1 1 This paper scale is universal Chinese national standard Falcon (CNS) A4 specification (2 丨 0X2 ^ 7mm) -19-A 7 B7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention description (17) 1 Exclusion or • Gate 4 8 C Supply logic The signal X 0 RC will have a pulse width of 1 1 T g 〇1 I when the time T 1 passes the time △ T 1 when the test clock signal 1 | TCLK falls y and the internal clock signal X 0 R pulse P 2 Please read above 1 I Synchronization of up transition 9 3 logic signals X 0 R a 5 X 0 R b Read back 1 '1 1 X 0 RC will latch on D flip-flop 4 6 a 4 6 b, 4 respectively 6 Note for C 1 I meaning I 〇 At this time j is TS < △ T 1 < T 8 + TW 0 Therefore 5 signal events 1 1 DI a will become the meaning of the factory without disconnection fault J 7m series 1 9 Signal write This 1 installed DI b will become the logical value indicating that the factory has no disconnection fault J 1 9 Signal Page 1 1 DI c will become the logical value indicating that the factory has disconnection fault J 0 Ο These signals 1 1 DI a 9 DI b 9 DIC will observe the scan action (TCTL = 0 1 I) 5 through the test result output terminal TD 0 to observe ○ Furthermore 9 as shown in Figure 5 1 set I indicated 9 at time T 2 will increase the test clock signal TCLK again 9 more in I 1 I The test clock signal TCLK falls when the time ΔT 2 falls. 9 The signal 1 1 1 DI a 9 DI b 9 The logic values of the DIC will all return to 0. On the 1 1 line 1 this 9 is T g + TW < △ T 2 0 as described above> When the collective circuit 3 0 according to FIG. 4 is able to test the three signal terminals 1 IN 1 ί IN 2 9 with only 1 1 built in the test circuit J of the collective circuit 30 ○ The signal terminals of the UT that have a poorly open mi m are set to 1 I. Therefore, 9 can disconnect The advantage of easy repair of defective parts is 0 and 9 1 1 I because of 3 D flip-flops 4 6 a 9 4 6 b 9 4 6 C are both useful for testing the function of input flip-flops of 1 1 test data signal input, And output test result 1 1 signal output flip-flop function 9 so the scale of the test circuit becomes smaller. At the same time > 1 1 because of having a pulse wave P 1 9 for latching the test signal and the latch test result 1 1 paper The scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 OX 297 mm) A7 B7 5. Invention description (18) The internal clock signal XOR of the pulse wave P 2 of the signal, with the first mutual exclusion, or ^ gate 4 Since 1 and the delay circuit 42 are generated, the advantage that only j test clock signals TC LK are supplied from the outside can be obtained. In addition, although in the examples of FIGS. 1 and 4, the supply of test data signals and observation test result signals are based on the same scanning operation as the previous BST technology, it is not limited to this. At the same time, the invention is not limited to digital collective circuits, but can also be applied to analog collective circuits. Four. Simple description of the surface Figure 1 is a circuit diagram showing a configuration example of the collective circuit of the present invention. FIG. 2 is a timing diagram showing the test operation of the collective circuit of FIG. 1. FIG. Fig. 3 is a block diagram showing an example of mounting a PC board including a plurality of circuit elements of four collective circuits built into the expanded test circuits of Fig. 1; J --.------ ^ ------. Subscribe ------ ^ (Please read the notes on the back first ¾ write this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs The example of Imtu ιρτ 4 5 in Tututu Road constitutes the other way. The Mingfa of the uncle of the body is shown as the preface of the picture. The 4th set of the electrical test set for the mn test is shown in the paper. Common Chinese National Standard (CNS) A4 specification (210 X 297 mm) -21-