TW202537411A - Transistor device with insertion layer and manufacturing method thereof - Google Patents

Abstract

A method of forming the insertion layers for different regions of parts of transistor devices and its structural demonstrations are provided. The method includes forming a device substrate region, forming the trench region, forming the trench filling layer, and forming trench region could further include forming the trench oxide layer, forming the patternable segmental dielectric layer, and forming the patternable segmental upper dielectric layer. Upon device substrate region, one or more embodiments demonstrates that parts of transistor device structure could further include the device channel region, the multilaminate pad region, and other pad layers to protect device channel region from process manipulation. The method further includes forming the first mask layer and forming the second mask layer to avoid current leakage and to achieve better device performance. One or more embodiments demonstrates that some parts of transistor device structure further includes parts of transistor source/drain region, which often includes source/drain epitaxial layer and source/drain metallic layer. The method further includes forming middle metal layer and forming insertion layer to suitably connect different parts of transistor device regions in highly densified integrated circuits.

Description

Transistor device with intercalation layer and its manufacturing method

This invention primarily relates to embedded component structures for electronic devices, particularly for fin-type and fully enclosed gate transistors, including nanowire FETs, nanosheet FETs, forksheet FETs, and complementary FETs. These embedded component structures can be applied to various sectors of the electronics industry, including upstream, midstream, and downstream processes, media, components, and even products related to conductor materials in integrated circuits.

U.S. Patent No. 20200411436, published on December 31, 2020, discloses a method for forming embedded power lines 212 between transistor components. See the original text of U.S. Patent No. 20200411436 and its figure 1 for details. This method includes forming a pair of adjacent transistor elements (including, from bottom to top, a device bottom pillar 110, a tunnel bottom dielectric layer 230, a nanosheet sacrifice layer 140, and a nanosheet tunnel layer 150) on a substrate 110, wherein the pair of adjacent transistor elements are separated by a trench, and the trench is filled with a trench filling layer 170 (see the original text of U.S. Patent No. 20200411436). Clearly, for the structural portion of advanced components, an effective mechanism for constructing intercalation layers can simplify the complexity of the metal wire connections above the MOSFETs, reduce the overall area of the components, and effectively provide the ability to connect different areas of the transistor components. This will help achieve denser logical circuits with higher computational efficiency per unit area.

A transistor element partial structure having an intercalation layer and a method for forming the intercalation layer on the formed transistor element partial structure. The method includes forming a transistor element substrate region, forming a trench, and forming a trench region filling layer. Forming a trench may further include forming a trench region oxide layer, forming a patternable segmented nano-dielectric layer, and forming a patternable segmented upper nano-dielectric layer. On the basis of the transistor element substrate region, a transistor partial element structure is further formed, wherein forming the transistor partial element structure includes forming a transistor element channel region, a multi-structure padding region, and other padding layers.

The transistor component structure further includes, based on a patterned fabrication concept, partially etching a first mask dielectric layer and partially etching a second mask dielectric layer to prevent leakage current generated during component operation and to optimize component characteristics.

The transistor component structure further includes the source/drain region structure of the transistor component, including the source/drain epitaxial layer and the source/drain metal layer.

The process of forming the transistor component structure further includes forming an intermediate metal layer and an insertion layer to connect different transistor component regions, thereby providing flexibility in dense circuit design.

These features and advantages can be better explained through the detailed textual descriptions and illustrations in the following examples.

100: Transistor Component Substrate Area

110:Substrate

120: Trench area filling layer

130: First epitaxial layer

140: Insulation layer of the first trench area

150: Insulation layer of the second trench area

160: Second epitaxial layer

200: Transistor element first channel region

210: First nanosheet dielectric layer

220: First Nanosheet Semiconductor Layer

250: Second channel region of transistor device

260: Second nanosheet dielectric layer

270: Second nanosheet semiconductor layer

300: Multi-structure paving area

310: First bottom paving layer

320: First intermediate paving layer

330: First Top Paving Layer

340: Second Top Pavement

350: Oxide layer in the trench area

360°: Patternable Fragmented Nanodielectric Layers

365: Patternable, fragmented top nano-dielectric layer

370: Component Cover Layer

380: Polycrystalline silicon layer

390: First masking dielectric layer

400: Fill layer

410: Etching Fill Layer

421: Bottom Etching Fill Layer

422: Sidewall Etching Filler Layer

430: First Pad Filling Layer

440: Second Pad Filling Layer

510: Second masking dielectric layer

520: Padding Mask

530: Gate-type resistance insulation layer

610: First Inner Insulation Layer

620: First Source/Extreme Geometric Layer

630: Second Inner Insulation Layer

640: Second Source/Dig-based Epitaxial Layer

650: Source/Drain Metal Layer

660: Insertion layer

710: Intermediate Metal Layer

720: First etched intermediate metal layer

730: Second etched intermediate metal layer

740: Etched Intermediate Padding Layer

Figure 1 illustrates, according to some embodiments, the gate structure and tunnel structure of the transistor component in the transistor component structure, with the direction of the parallel patterned transistor component channel region, and shows the position of the insertion layer 660 relative to the transistor component structure.

Figure 2-40 illustrates the fabrication process of the transistor component structure and the insertion layer 660, using a parallelogram-patterned transistor component channel region, according to some embodiments.

The following description and examples of embodiments of this invention are for reference only and are not the only possible embodiments.

In one or more embodiments, substrate 110 (shown in FIG. 2) typically comprises a plurality of materials, such as single-element semiconductors Si and Ge (e.g., single-crystal Si, single-crystal Ge, polycrystalline Si, polycrystalline Ge, amorphous Si, amorphous Ge, etc.), group III-V compound semiconductor materials (e.g., GaAs, GaP, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP, etc.), group IV-IV compound semiconductors (e.g., SiC, SiGe, etc.), or different substrate structures (e.g., silicon-on-insulator substrate, silicon-on-insulator) and/or combinations thereof. Different regions of substrate 110 may be doped with n-type, p-type, neutral impurities, or combinations thereof to improve the conductivity of substrate 110.

According to one or more embodiments, a component structure (shown in FIG. 1) can be disposed on a substrate 110 (shown in FIG. 1-2), wherein the component structure includes a portion of the transistor component structure. These transistor component structures can be of various types, including horizontal fin type, horizontal nanosheet type, nanowire type, forked nanosheet type, or others. The fin-like, nanowire, nanosheet, or forked nanosheet transistor component channel structures can be separated and covered by an insulating layer to optimize component characteristics and provide appropriate physical protection.

In several embodiments (shown in Figures 3-8), multiple etching and crystal growth processes effectively increase the aspect ratio of the trench region. A second epitaxial layer 160 covers the trench, effectively improving the stability of crystal growth in the upper device structure. The substrate 110, the first epitaxial layer 130, and the second epitaxial layer 160 can be made of different materials. For example, the substrate 110 can be made of monocrystalline silicon, while the first epitaxial layer 130 and the second epitaxial layer 160 can be made of silicon-germanium alloy to ensure that different lattice sizes do not cause defects in the upper device formation during matching.

Regarding the definition of the groove area, the techniques for transferring patterns during component manufacturing can be used, but are not limited to, the two main different methods. One is direct writing, including extreme ultraviolet lithography , electron beam lithography, and/or combinations thereof. The other is self-aligned single patterning, self-aligned double patterning, self-aligned quadruple patterning, other self-aligned patterning processes, and/or combinations thereof. Recent research shows that extreme ultraviolet (EUV) light is commonly used as a primary technology for transistor transfer in advanced manufacturing processes. The value of EUV transfer technology, including the value of machine tools, the use of photoresist materials, and the frequency of its application in advanced processes, may be a key consideration for future process value. The material composition of the trench filling layer 120 is mostly, but not limited to, dielectric materials.

According to one or more embodiments, the first trench area insulating layer 140 and the second trench area insulating layer 150 (shown in FIG. 6 ) may be, but are not limited to, the same or different dielectric layer materials. For example, phosphosilicate glass (PSG), SiON, SiCN, SiOCN, SiC, etc. Typically, the dielectric layer material used for the metal interconnects of the front-end of line can be similar or different from the dielectric layer material used for the backend interconnect layers, depending on device design considerations. In other words, low k-value materials may be used. Low-dielectric materials include, but are not limited to, fluorinated silicon oxide (SiO₂F), carbon-doped silicon oxide (SiO₂C), silane trioxide (HSQ), methylsiloxane (MSQ), tetraethyl orthosilicate (TEOS), or other types of low-dielectric materials and/or combinations thereof. The doped compounds are represented herein as doped:doped, for example, fluorinated silicon oxide (SiO₂F).

According to one or more embodiments (shown in FIG. 9), a first channel region 200 and a second channel region 250 of a transistor element are grown on a transistor element substrate region 100. The first channel region 200 of the transistor element includes a first nanosheet dielectric layer 210 and a first nanosheet semiconductor layer 220, while the second channel region 250 of the transistor element includes a second nanosheet dielectric layer 260 and a second nanosheet semiconductor layer 270. Typically, the transistor element channel region may have single-layer or multi-layer padding regions 300, including, but not limited to, a first bottom padding layer 310, a first intermediate padding layer 320, and a first top padding layer 330. A second top padding layer 340 may be provided above the transistor element channel region, and the second top padding layer 340 may be a single-layer or multi-layer padding structure. The addition of padding regions and padding layers helps to improve the electrical and physical isolation and protection within and between the element channel region.

According to one or more embodiments (shown in Figure 9), the transistor device channel region may include staggered nanosheet dielectric layers and nanosheet semiconductor layers. In many embodiments, the nanosheet dielectric layer may be a semiconductor material, including but not limited to Si, Ge, GeSn, SiGe, SiC, Si:C, other semiconductor materials and/or combinations thereof, wherein the material of the nanosheet dielectric layer is generally similar to that of the nanosheet semiconductor layer. Recent studies have indicated that the use of certain metal/non-metal compound materials can effectively reduce the space ratio of the transistor device channel region relative to other transistor device-related regions, such as WSx, WCx, other carbon-based materials, low-dimensional materials, etc., which can effectively enhance the flexibility of transistor device structures in advanced process design. The tireless efforts of our predecessors and experts in this field have made a small but significant contribution to the advancement of human technology.

In various embodiments, the nanosheet semiconductor layer may be a semiconductor material, including, but not limited to, Si, Ge, GeSn, SiGe, SiC, Si:C and/or combinations thereof, wherein the material of the nanosheet semiconductor layer may differ from that of the nanosheet dielectric layer.

Taking silicon-germanium alloy as the channel region of a transistor element as an example, the nanosheet dielectric layer can be SiGe with a [Ge] concentration of approximately 20 atomic percentages (at.%) to approximately 40 atomic percentages (at%), but not limited to it. By referencing the SiGe of the nanosheet dielectric layer, the [Ge] concentration of the nanosheet semiconductor layer is typically equal to or greater than that of the SiGe of the nanosheet dielectric layer.

According to one or more embodiments (shown in Figures 10 and 11), the transistor channel layer covered by the padding layer and the nanosheet dielectric layer can be further enhanced by redefining the trench region to create a trench region with a higher aspect ratio. Furthermore, by depositing an oxide layer 350 in the trench region and a patternable segmented nano-dielectric layer 360, the effects of distinguishing multiple device channel layers and protecting the transistor channel layer can be achieved.

According to one or more embodiments (shown in Figure 12), overgrowth can be planarized through a planarization process and chemical mechanical polishing (CMP), and the correct polishing dimensions can be achieved through precise control. Figure 12 is only schematic to illustrate that CMP can polish down to the transistor portion of the device channel layer. At this point, the oxide layer 350 in the trench area is typically exposed on the substrate surface.

According to one or more embodiments (shown in Figures 13 and 14), by defining the source/drain regions of the transistor element using photoresist, a portion of the transistor element channel region, trench region oxide layer 350, and patternable segmented nano-dielectric layer 360 are etched away to achieve an ideal height/width ratio. The post-etching geometric scaling here primarily stems from the pre-lithography dimensional proportions.

Furthermore, if over-etching occurs after lithography is defined, it can be corrected by repeating part of the process (shown in Figure 3-8), ensuring a return to the desired state.

Considering that the standards for each process may not be the same, lithography and etching can be performed separately, in combination, continuously, in stages, and/or multiple times to ensure that the overall condition remains normal after etching.

Figure 14 is similar to Figure 13, except that the widths of the trench oxide layer 350 and the patternable segmented nano-dielectric layer 360 differ.

According to one or more embodiments (shown in Figures 14 and 15), a device cover layer 370 and a defined polycrystalline silicon layer 380 are deposited on top of the transistor device channel layer. The former protects the partially exposed transistor device channel layer, while the polycrystalline silicon layer 380 is used here only to mark the location of the transistor device gate.

According to one or more embodiments (shown in FIG. 16), a first masking dielectric layer 390 is further deposited on the device.

According to one or more embodiments (shown in Figure 17), the filler layer 400 is further deposited on the component, covering the entire component.

In several embodiments, the filler layer 400 may include various deposition methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), fluid chemical vapor deposition (FCVD), plasma-assisted chemical vapor deposition (PECVD), atmospheric chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), and combinations thereof. In one or more embodiments, the CVD precursors include silicates, siloxanes, MSQ, HSQ, MSQ/HSQ, perhydrosiloxanes (TCPS), perhydropolysiloxanes (PSZ), tetraethyl orthosilicates (TEOS), or silylamines such as trisilaneamine (TSA). After CVD film deposition, silicon oxide is typically formed by heating and removing excess elements. As the excess elements leave the film, the film density increases and the volume decreases.

In some embodiments, multiple annealing processes are used. The CVD thin film may also be doped with boron (B) or phosphorus (P). In some embodiments, the filler layer 400 may consist of one or more layers of different materials, such as spin-on glass (SOG), SiO, SiON, SiOCN, and/or fluorodoped silicate glass (FSG). After the filler layer 400 is filled, an annealing process is usually performed to achieve the best quality insulation layer.

According to one or more embodiments (shown in FIG. 18), the heights of the first mask dielectric layer 390 and the fill layer 400 after etching can be effectively defined by etching the first mask dielectric layer 390 and the fill layer 400 in stages.

According to one or more embodiments (shown in FIG. 19), a second masking dielectric layer 510 is deposited on the entire device. The material of the second masking dielectric layer 510 may be different from that of the first masking dielectric layer 390.

According to one or more embodiments (shown in FIG. 20), the second masking dielectric layer 510 is etched to partially suspend it above the sidewall of the transistor channel layer, and together with the underlying first masking dielectric layer 390, covers the sidewall of the transistor channel layer. The fill layer 400 may be consumed during the etching process, reducing its height and exposing a portion of the first masking dielectric layer 390 to the surface.

According to one or more embodiments (shown in FIG. 21), etching the first masking dielectric layer 390 exposed on the surface can expose a portion of the component cover layer 370 covered by the first masking dielectric layer 390.

According to one or more embodiments (shown in FIG. 22), selective etching can effectively remove a portion of the device cover layer 370, exposing a portion of the transistor device channel layer. The extent of this exposure depends on the geometry of the first masking dielectric layer 390, the device cover layer 370, the fill layer 400, and the second masking dielectric layer 510, as well as their relative positions to the channel device layer.

According to one or more embodiments (shown in Figures 23 and 24), the first nanosheet dielectric layer 210 is selectively etched, and a first internal insulating layer 610 and a first source/drain epitaxial layer 620 can be formed through appropriate processing. The design of the first source/drain epitaxial layer 620 can be performed by adjusting the geometry of the first mask dielectric layer 390, the device cover layer 370, the fill layer 400, and the second mask dielectric layer 510, as well as their relative positions to the channel device layer.

According to one or more embodiments (shown in Figures 25 and 26), an etched filling layer 410 can be formed by deposition and etching to adjust the geometry of the material within the trench region. Photolithography/etching can effectively obtain a better geometry of the material within the trench region, as shown in Figure 26.

According to one or more embodiments (shown in FIG. 27), the source/drain metal layer 650 may be further deposited outside the source/drain metal layer as a subsequent metal wire connection point. Here, the source/drain metal layer 650 can be adjusted by modifying the geometry of the first masking dielectric layer 390, the device cover layer 370, the fill layer 400, the bottom etch fill layer 421, the sidewall etch fill layer 422, and the second masking dielectric layer 510, as well as their relative positions to the channel device layer.

According to one or more embodiments (shown in Figures 28 and 29), a first padding fill layer 430 is deposited over the device. Parts of the first masking dielectric layer 390, the device cover layer 370, the fill layer 400, the bottom etched fill layer 421, the sidewall etched fill layer 422, and/or the second masking dielectric layer 510 can be removed by selective etching, chemical mechanical polishing (CMP), and lithography. A padding mask layer 520 is then deposited over these layers.

The padding mask layer 520 can be similar to the filler layer 400.

The component manufacturing process shown in Figures 28-29 can be widely applied to different stages of the manufacturing process.

The polycrystalline silicon layer shown in Figure 29 is for reference only. Actual component manufacturing should be based on component characteristics and the designer's requirements.

According to one or more embodiments (shown in Figures 30 and 31), a portion of the padding mask 520 is removed by selective etching, chemical mechanical polishing (CMP), and/or lithography. The height of the padding mask 520 at this point determines the proportion of the second channel region 250 of the transistor device that is exposed. The height of the padding mask 520 is determined by the proportion of the second channel region 250 of the transistor device that is exposed.

The second nanosheet dielectric layer 260, located above the padding mask 520, can form a second inner insulating layer 630 through a similar fabrication process to the first nanosheet dielectric layer 210 (shown in Figures 23 and 24). The material of the second inner insulating layer 630 can be the same as that of the first inner insulating layer 610. Depositing the gate resistor insulating layer 530 on the device effectively defines the proportion of the second channel region 250 used in the transistor device.

In some embodiments (shown in FIG. 32), a self-aligning gate barrier 530 can be formed on the sidewalls of the polycrystalline silicon layer 380, the second channel region 250 of the transistor device, and the multi-structure pad region 300 by partially etching the pad mask 520 and the gate barrier 530.

In some embodiments (shown in FIG. 32), selective etching of the padding mask 520 can expose portions of the multi-structure padding region 300, the second channel region 250 of the transistor element, and/or the first channel region 200 of the transistor element.

In some embodiments (shown in Figure 32), a self-aligned partial etching mechanism can be used to form a single-layer or multi-layer transistor element partial structure and/or a transistor element partial insulation structure with contact surfaces in a specific area, consisting of characteristic materials such as insulation, semiconductor, or conductor materials.

In some embodiments (shown in FIG. 33), the selective etching portions are the first padding fill layer 430 and the first intermediate padding layer 320. In non-selective etching, the first padding fill layer 430, the multi-structure padding region 300, the patternable segmented nano-dielectric layer 360, the second masking dielectric layer 510, the transistor element second channel region 250, the transistor element first channel region 200, and/or other adjacent regions can all be used to define the geometry of the etching.

In some embodiments (shown in Figures 34, 35, and 36), the partial etching size adjustment of the first padding fill layer 430 is of considerable importance to the subsequent metal layer formed on top.

The etching process for the first padding fill layer 430 places high demands on dimensional adjustments for different transistor component structures and different locations within the same transistor component structure. In this case, the first padding fill layer 430 and the subsequently deposited second padding fill layer 440 can be deposited as single or multiple layers using the same and/or different deposition methods in partially patterned and/or partially unpatterned environments. This ensures optimal results for the deposition, dimensional adjustments, coverage, and adhesion of the intermediate metal layer 710.

The degree of protection between metal layers, between component channel areas, and between different transistor component structures relies heavily on the first padding fill layer 430, the second padding fill layer 440, the patternable segmented insulation structure, and the geometry and material fit of the surrounding materials.

In some embodiments (shown in Figure 37), the second channel region 250 of the transistor element is exposed by etching the self-aligned gate insulating layer 530. A second source/drain epitaxial layer 640 is then formed. At this time, the intermediate metal layer 710 simultaneously connects multiple transistor elements. By increasing the gate patterning process, adjusting the first padding fill layer 430, and using multiple structured padding regions 300, different regions of the multiple transistor elements can be effectively connected, potentially achieving the simplest current transmission path.

Component designers should use the second padding fill layer 440 as a reference for forming the source/drain epitaxial layer, rather than the sole environmental condition for epitaxial layer growth. Furthermore, the second padding fill layer 440 can be a single or multiple layers of conductive or semiconductor materials serving as the internal layering basis for insulating properties, to accommodate different component design considerations, such as surrounding metal, semiconductor, or insulating materials.

In some embodiments (shown in Figure 38), photolithography defines the intermediate metal layer 710, and subsequently, the height of the second padding fill layer 440 is defined by formation and etching. The geometry of the intermediate metal layer 710, including the first etched intermediate metal layer 720 and the second etched intermediate metal layer 730, can be defined not only by the surrounding material, including the patternable segmented transistor portion insulation structure, but also by photolithography.

In some embodiments (shown in Figures 38-39), a patternable, segmented top nano-dielectric layer 365 can be formed by repeating the process (shown in Figures 3-8), creating and adjusting barrier layers for different device regions. The geometry of the second etched intermediate metal layer 730, the etched intermediate padding layer 740, and the first padding fill layer 430 can be precisely adjusted using lithography and lateral etching.

In some embodiments (shown in Figure 40), an insertion layer 660 is formed outside the source/drain metal layer 650. Part of the insertion layer 660 is blocked by a patternable fragmented upper nano-dielectric layer 365, and this portion of the insertion layer 660 can connect the source/drain region of one transistor device to the gate region of another transistor device. By using gate patterning processes and similar methods, interconnections between different regions of multiple transistor devices can be effectively achieved. The design of the insertion layer 660, combined with a patternable fragmented insulation structure, effectively achieves better design flexibility.

The 660 intercalation layer can be deposited using atomic layer deposition (ALD) or plasma-assisted atomic layer deposition (PEALD) for uniform deposition, chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), organometallic chemical vapor deposition (MOCVD), bulk deposition, and/or combinations thereof.

In one or more embodiments, the intercalation layer 660 may include, but is not limited to, different conductive materials, such as semiconductor materials (doped with single-crystal Si, doped with polycrystalline Si, doped with amorphous Si, Ge, SiGe, other semiconductor materials and/or combinations thereof), metallic materials (e.g., W, Ti, Ta, Ru, Hf, Zr, Co, Ni, Cu, Al, Pt, Sn, Ag, Au, etc.), metallic compounds (e.g., GeSn, TaN, TiN, WN, RuO2, etc.), silicon-based alloys (e.g., CoSi, NiSi, ZrSi, RuSi, WSi, etc.), transition metal-aluminum alloys (e.g., Ti3Al, ZrAl), conductive carbon materials (e.g., TaC, TiC, TiAlC, TaMgC, etc.), carbon nanotubes, graphene, or any material that meets the conditions and/or combinations thereof. The doping process may be further incorporated into or after the deposition of conductive materials.

In some embodiments, the gate layer may include a gate dielectric layer, a work function adjustment layer, and a gate electrode, but for simplicity, these are not shown in the figures. The gate layer can become complex depending on the intended use. In this invention, the polycrystalline silicon layer 380, the gate insulating layer 530, the padding mask 520, and the inner insulating layer are shown to separate the device channel layer, the gate region, and the source/drain region; therefore, detailed information about the gate layer is not included here. Although all the aforementioned component regions provide physical protection against leakage current, these regions are manufactured in different processes, resulting in variations in material composition, shape, and construction mechanism. Typically, to minimize electrical losses between the gate region and the source/drain regions, the gate resistive insulation layer 530 uses low-k-value materials such as SiO:F, SiO:C, HSQ, MSQ, TEOS, SiON, SiCN, SiOCN, SiC, etc., and/or combinations thereof.

Typically, the insulation structure of the source/drain regions is used in materials that, depending on the complexity of the manufacturing process, can be a dielectric material based on one or more semiconductor materials, such as SiO:F, SiO:C, HSQ, MSQ, TEOS, SiON, SiCN, SiOCN, SiC, SiGe:O, Ge:O, SiO2, SiGeON, GeON, and/or combinations thereof.

For the sake of simplicity, the same pattern is used for the source/drain metal layers 650 in the illustrations of this invention. However, as mentioned above, different conductive materials can be used with different manufacturing processes, materials and shapes. The source/drain metal layer 650 can be one or more layers of conductive material, such as semiconductor materials (e.g., doped single-crystal Si, doped polycrystalline Si, doped amorphous Si, Ge, SiGe and/or combinations thereof), metal materials (e.g., W, Ti, Ta, Ru, Hf, Zr, Co, Ni, Cu, Al, Pt, Sn, Ag, Au, etc.), metal compounds (e.g., GeSn, TaN, TiN, WN, RuO2, etc.), silicon-based alloys (e.g., CoSi, NiSi, ZrSi, RuSi, WSi, etc.), transition metal-aluminum alloys (e.g., Ti3Al, ZrAl), conductive carbides (e.g., TaC, TiC, TiAlC, TaMgC, CNT, graphene, or any suitable conductive material and/or combinations thereof). The doping process may be further incorporated into or after the deposition process of conductive materials.

The source/drain epitaxial layer material includes, but is not limited to, semiconductor materials (e.g., doped single-crystal Si, doped polycrystalline Si, doped amorphous Si, Ge, SiGe and/or combinations thereof) and/or conductive carbon-based materials (e.g., TaC, TiC, TiAlC, TaMgC, carbon nanotubes (CNTs), graphene, etc.) or any suitable material and/or combination thereof. The doping process may be further incorporated into or after the deposition of the conductive material.

Figure 2-40 illustrates the fabrication process of a nanochip transistor device, depicted in parallel patterned transistor channel layers according to some embodiments. While Figure 2-40 shows some examples of the fabrication process, more fabrication processes can be inserted before, during, or after the processes shown in Figure 2-40, and the fabrication processes shown in Figure 2-40 can be replaced, deleted, or their order interchanged.

In some embodiments, the mask can be a multi-layered structure used to protect and define active regions within the semiconductor. However, multi-layered structures can be used to provide better definition capabilities for semiconductor active regions. The mask can be deposited using, but is not limited to, ALD, CVD, PECVD, APCVD, LPCVD, HDPCVD, and/or other suitable processes.

The illustrations only show how the transistor structure completes the relationship between the intercalation layer and the transistor element; the dimensions and shapes are conceptual and do not fully represent the actual situation.

The methods described above can be used in integrated circuit chip manufacturing. Manufacturers can package and distribute manufactured integrated circuit chips in wafer form, bare die form, or packaged die form. Packaged die forms are further divided into single-chip packages and multi-chip packages. Chips can be integrated into different types of chips, such as discrete circuit components, signal processing components, or even integrated into motherboards or client products. Client products can be any product that uses integrated circuit chips, ranging from low-end applications such as traditional refrigerators to advanced computer products.

The elemental concentrations in the compound are expressed as SixGe(1-x), where x is less than or equal to 1. Different concentration ratios are all included in the simplest chemical formula, SiGe. If the compound contains other elements, it can also be referred to as an alloy.

"In one embodiment" does not necessarily refer to the same embodiment, but rather to a single characteristic. "In some embodiments" does not necessarily refer to the same set of embodiments, but rather to a few specific characteristics.

When the description includes "including A, B, C, or combinations thereof," it means the text includes individual items A, B, and C, or A and B, A and C, B and C, or A and B and C. This concept can be extended, as the list may only represent a portion of the possible ways.

As used herein, spatial adjectives such as below, above, bottom, top, vertical, horizontal, etc., are used for convenience when referring to the structure of a field-effect transistor (FET). These references are intended to be used only in accordance with the accompanying drawings for educational purposes and are not intended to be absolute references to FETs. For example, FETs can be spatially oriented in any manner different from those shown in the accompanying drawings. When referring to the accompanying drawings, "vertical" is used to refer to a direction perpendicular to the semiconductor layer surface, while "horizontal" is used to refer to a direction horizontal only to the semiconductor layer surface. "Above" is used to refer to a vertical direction away from the semiconductor layer. A component located "above" ("below") another component is farther (closer) to the semiconductor layer surface than that other component.

Since this invention can be readily modified and implemented by those skilled in the art with the aid of the teachings herein, the specific embodiments disclosed above are merely exemplary. For example, the above process steps may be performed in different orders. Furthermore, this invention is not intended to be limited to the details of the structure or design shown in the text, but rather as described in the claims above. Therefore, it is evident that modifications or alterations can be made to the specific embodiments disclosed above, and such modifications fall within the scope and spirit of this invention. It should be noted that the use of terms such as "first," "second," "third," or "fourth," used to describe the various processes or structures in this specification and the appended claims, can be used as a quick reference to such structures/steps and does not necessarily imply an order in which such steps/structures are arranged. Of course, depending on the precise language of the patent application, the order of these processes, semantic extensions, semantic omissions, and combinations thereof may be adjusted or not adjusted to achieve a complete interpretation of the patent scope. Therefore, the scope of protection sought by this invention is as described in the patent application.

100: Transistor Component Substrate Area

110:Substrate

120: Trench area filling layer

130: First epitaxial layer

140: Insulation layer of the first trench area

150: Insulation layer of the second trench area

160: Second epitaxial layer

200: Transistor element first channel region

210: First nanosheet dielectric layer

220: First Nanosheet Semiconductor Layer

250: Second channel region of transistor device

260: Second nanosheet dielectric layer

270: Second nanosheet semiconductor layer

300: Multi-structure paving area

310: First bottom paving layer

320: First intermediate paving layer

330: First Top Paving Layer

340: Second Top Pavement

350: Oxide layer in the trench area

360°: Patternable Fragmented Nanodielectric Layers

365: Patternable, fragmented top nano-dielectric layer

370: Component Cover Layer

380: Polycrystalline silicon layer

390: First masking dielectric layer

400: Fill layer

410: Etching Fill Layer

421: Bottom Etching Fill Layer

422: Sidewall Etching Filler Layer

430: First Pad Filling Layer

440: Second Pad Filling Layer

510: Second masking dielectric layer

520: Padding Mask

530: Gate-type resistance insulation layer

610: First Inner Insulation Layer

620: First Source/Extreme Geometric Layer

630: Second Inner Insulation Layer

640: Second Source/Dig-based Epitaxial Layer

650: Source/Drain Metal Layer

660: Insertion layer

710: Intermediate Metal Layer

720: First etched intermediate metal layer

730: Second etched intermediate metal layer

740: Etched Intermediate Padding Layer

Claims (12)

A method for forming a region portion of a transistor device includes: Forming a transistor element substrate region; forming a partial transistor element structure, wherein forming the partial transistor element structure includes forming a transistor element channel region and forming a multi-structure padding region; forming a patterned transistor gate, wherein forming the patterned transistor gate includes forming a partially etched element channel region, forming a transistor gate metal layer, and forming a transistor gate metal capping layer on the basis of the transistor gate metal layer; forming a trench, wherein forming the trench includes forming a patterned trench region partial transistor insulation structure and, based on the patterned trench region partial transistor insulation structure, self-aligning to form a patternable trench region segmental nano-dielectric layer. According to the method of claim 1, forming a transistor element substrate region includes partially etching one or more layers of material of the transistor element substrate region, forming one or more layers of transistor element partial insulation structure in the partially etched transistor element substrate region, and forming one or more layers of material of the transistor element substrate region. According to the method in claim 2, the method further includes repeatedly performing "partial etching of one or more layers of material in the transistor element substrate region, forming one or more layers of transistor element partial insulation structure in the partially etched transistor element substrate region, and forming one or more layers of material in the transistor element substrate region," and may be combined with unidirectional or uniform partial etching to form one or more layers of transistor element partial insulation structure. According to the method of claim 1, forming the trench includes partially etching one or more layers of transistor channel regions, partially etching one or more layers of transistor insulation structures, and partially etching the material of one or more layers of transistor substrate regions, based on the formation of a transistor element substrate region. The method according to claim 4 further includes forming a trench oxide layer and a patternable segmented nano-dielectric layer on the basis of one or more layers of transistor element partial insulation structure, wherein the patternable segmented nano-dielectric layer has no contact surface with the one or more layers of transistor element partial insulation structure. According to the method in claim 1, the transistor insulation structure in the patterned trench region includes, on the basis of the patterned transistor element channel region, uniformly forming one or more mask dielectric layers, with the height of the filling layer serving as a design reference, and partially etching the height of the one or more mask dielectric layers. The method according to claim 6 further includes, on the basis of the patterned trench region portion of the transistor element insulation structure, forming a second mask dielectric layer, partially etching the second mask dielectric layer, partially etching the fill layer, and laterally etching one or more mask dielectric layers. The method according to claim 1 further includes forming a source/drain epitaxial layer and forming a source/drain metal layer. According to the method of claim 1, forming the trench includes partially etching one or more layers of padding mask and self-aligning etching to form one or more gate resistive layers based on the conductive structure of a portion of the transistor element in the patterned trench region, wherein the width of the padding mask is defined with reference to the definition of the width of the gate resistive layer formed by self-aligning etching. According to the method of claim 1, forming the trench includes, on the basis of a patterned trench region portion of the transistor element insulation structure, laterally etching a masking dielectric layer of one or more transistor element channel regions to form a metal layer, wherein the metal layer may have a contact surface with the one or more transistor element channel regions. The method according to claim 10 further includes forming an etched intermediate pad layer on top of forming an intermediate metal layer, wherein the method of forming the etched intermediate pad layer includes isotropic, lateral, or self-aligned partial etching. According to the method of claim 1, forming the trench includes further forming one or more patternable segmented upper nano-dielectric layers on the basis of a patterned transistor element conductor structure in the trench region, wherein a portion of the structure of the one or more patternable segmented upper nano-dielectric layers can isolate the transistor element conductor structure in the trench region.