TW202536226A - Semiconductor structure and method of forming the same - Google Patents

Abstract

An interfacial layer, between nanostructure channels and gate structures, is formed using a fresh silicon cap process. For example, by using diisopropylaminosilane as a precursor, amorphous silicon may be formed on spacers and crystalline silicon may be formed on channels. The amorphous silicon and crystalline silicon may be oxidized to form the interfacial layer, which has a relatively uniform thickness in a range from approximately 0.5 nanometers (nm) to approximately 1.0 nm. As a result, miniaturization and gate efficiency are improved while reducing current leakage out of the channels.

Description

Semiconductor structure and its formation method

This invention relates to semiconductor structures, and more particularly to semiconductor structures having interface layers of uniform thickness on channels and spacers.

As semiconductor device manufacturing methods advance and process node sizes shrink, short-channel effects such as hot carrier degradation, energy barrier reduction, quantum confinement, and other effects can impact transistors. Furthermore, as transistor gate sizes shrink for smaller process nodes, source/drain electron tunneling increases, leading to increased transistor turn-off current (the current flowing through the transistor channel when the transistor is set to off). Silicon/silicon-germanium nanostructure transistors (such as nanowires, nanosheets, nanoribbons, multi-bridge channels, and fully wound gate devices) are strong candidates for overcoming short-channel effects at smaller process nodes. Compared with other types of transistors, nanostructured transistors can effectively reduce short-channel effects and increase carrier mobility.

Some embodiments described herein provide methods for forming semiconductor structures. The methods include growing a seed layer on a spacer. The methods include depositing silicon on the seed layer to form amorphous silicon and depositing silicon on the channel to form crystalline silicon. The methods include oxidizing amorphous silicon and crystalline silicon to form an interface layer. The methods include forming a high-dielectric-constant layer on the interface layer.

Some embodiments described herein provide methods for forming semiconductor structures. The methods include growing a seed layer on a spacer. The methods include depositing silicon on the seed layer to form amorphous silicon and depositing silicon on channels to form crystalline silicon. The methods include performing multiple cycles to achieve thicknesses of approximately 4.0 Å to approximately 6.0 Å for both the crystalline and amorphous silicon, wherein each cycle includes an oxidation process and a trimming process. The methods include oxidizing the amorphous and crystalline silicon to form an interface layer.

Some embodiments described herein provide semiconductor structures. The semiconductor structure includes nanostructure channels formed between multiple source/drain regions. The semiconductor structure includes gate structures formed around the nanostructure channels. The semiconductor structure includes spacers located between an interlayer dielectric layer and the gate structures. The semiconductor structure includes an interface layer contacting the nanostructure channels and the spacers, the interface layer comprising silicon oxide, and the thickness of the interface layer being approximately 0.5 nm to approximately 1.0 nm.

The following detailed description, accompanied by illustrations, will aid in understanding all aspects of this invention. It is important to note that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of the various structures may be increased or decreased as needed for clarity.

The following disclosure provides numerous different embodiments or examples to implement the various features of this invention. The following disclosure illustrates specific examples of the components and their arrangements for simplification. These specific examples are not intended to limit the embodiments of the invention. For example, if an embodiment of the invention illustrates that a first structure is formed on top of a second structure, it means that the first structure may be in direct contact with the second structure, or that additional structures may be formed between the first and second structures, so that the first and second structures are not in direct contact. Furthermore, the repetition of reference numerals in various embodiments of the invention for simplification or clarity does not imply that structures with the same reference numerals in various embodiments and/or arrangements have the same relative relationship.

In addition, spatial relative terms such as "below," "lower," "above," "higher," or similar terms are used to describe the relationship between some elements or structures in a diagram and another element or structure. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is rotated to a different orientation (rotated 90 degrees or otherwise), the spatial relative adjectives used will also be interpreted according to the orientation after the rotation.

Nanostructured transistors (such as nanowire transistors, nanosheet transistors, fully wound gate transistors, multi-bridge channel transistors, nanocharged transistors, and/or other types of nanostructured transistors) can overcome one or more of the drawbacks of the aforementioned fin field-effect transistors. However, nanostructured transistors face fabrication challenges that can cause performance issues and/or device failures. For example, the thickness of the interface layer between the channels and gates in nanostructured transistors needs to be reduced to approximately 1 nm to further improve structure miniaturization. One of the processes used to grow such thin interface layers is atomic layer deposition. However, atomic layer deposition is difficult to control and often results in some parts of the interface layer being too thick, reducing the gate efficiency, and other parts of the interface layer being too thin, causing leakage current outside the channel.

Some embodiments described herein provide nanostructured transistors and methods for their formation. In some embodiments, the interface layer is formed using a fresh silicon capping process. For example, using diethylpropylaminosilane as a precursor, amorphous silicon can be formed on the spacers and crystalline silicon on the channels. The amorphous and crystalline silicon can be oxidized to form the interface layer, which can have a relatively uniform thickness, such as approximately 0.5 nm to approximately 1.0 nm. This improves structure miniaturization and gate efficiency, and reduces leakage current outside the channels.

Figure 1 is a diagram of an environment 100 in which the systems and/or methods described herein may be implemented, as exemplified in Figure 1. As shown in Figure 1, an example of environment 100 may include multiple semiconductor process tools such as deposition tools 102 to plating tools 112 and wafer and/or die transport tools 114. The multiple semiconductor process tools such as deposition tools 102 to plating tools 112 may include deposition tool 102, exposure tool 104, development tool 106, etching tool 108, planarization tool 110, plating tool 112, and/or another type of semiconductor process tool. The tools included in the example of environment 100 may be located in a semiconductor cleanroom, semiconductor foundry, semiconductor fabrication plant, manufacturing plant, and/or other facilities.

The deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices for depositing various materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool for depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition tool, such as a plasma-assisted chemical vapor deposition tool, a high-density plasma chemical vapor deposition tool, a secondary-pressure chemical vapor deposition tool, a low-pressure chemical vapor deposition tool, an atomic layer deposition tool, a plasma-assisted atomic layer deposition tool, or another type of chemical vapor deposition tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition tool, such as a sputtering tool or another physical vapor deposition tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to epitaxially grow layers and/or regions of the apparatus. In some embodiments, examples of environment 100 include multiple deposition tools 102.

Exposure tool 104 is a semiconductor manufacturing tool that can irradiate a photoresist layer with a radiation source such as an ultraviolet light source (e.g., deep ultraviolet light source, extreme ultraviolet light source, and/or similar light source), an X-ray source, an electron beam source, and/or similar light source. Exposure tool 104 can irradiate the photoresist layer with a radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns used to form one or more semiconductor devices, patterns used to form one or more structures of a semiconductor device, patterns used to etch various parts of a semiconductor device, and/or similar patterns. In some embodiments, exposure tool 104 includes a scanner, a stepper, and/or similar types of exposure tools.

The developing tool 106 is a semiconductor manufacturing tool that can develop a photoresist layer exposed to a radiation source to reveal a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 can remove unexposed portions of the photoresist layer to reveal the pattern. In some embodiments, the developing tool 106 can remove exposed portions of the photoresist layer to reveal the pattern. In some embodiments, the developing tool 106 can use a chemical developer to dissolve either exposed or unexposed portions of the photoresist layer to reveal the pattern.

The etching tool 108 is a semiconductor manufacturing tool capable of etching various materials, including substrates, wafers, or semiconductor devices. For example, the etching tool 108 may include wet etching tools, dry etching tools, and/or similar tools. In some embodiments, the etching tool 108 includes a chamber for filling with an etching agent, and the substrate can be placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may employ plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may employ ionized gas to etch one or more portions isotropically or directionally. In some embodiments, the etching tool 108 includes a plasma-based ashing machine to remove photoresist material and/or another material.

Planarization tool 110 is a semiconductor manufacturing tool that can grind or planarize various layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical polishing tool and/or another planarization tool that can grind or planarize layers or surfaces with deposited or plated materials. Planarization tool 110 can grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (such as chemical etching and free abrasive polishing). Planarization tool 110 may employ abrasives and corrosive chemical polishing slurries, along with a polishing pad and a retaining ring (whose diameter is typically larger than that of the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic grinding head can rotate along different axes of rotation to remove material and smooth any irregularities in the semiconductor device, making the semiconductor device smooth or flat.

The plating tool 112 is a semiconductor manufacturing tool that can plate one or more metals onto a substrate (such as a wafer, semiconductor device, and/or the like) or portions thereof. For example, the plating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, an electroplating device for compound materials or alloys (such as silver tin, lead tin, and/or the like), and/or an electroplating device for one or more other types of conductive materials, metals, and/or similar materials.

The wafer and/or die transport tool 114 includes mobile robots, robotic arms, light rails or railcars, overhead cranes, automated material handling systems, and/or other devices used for transporting substrates and/or semiconductor devices between semiconductor process tools such as deposition tools 102 to plating tools 112, between process chambers of the same semiconductor tool, and/or from other locations (such as wafer racks, storage chambers, or other locations) or to other locations. In some embodiments, the wafer and/or die transport tool 114 is a programmable tool configured to transport along a specific path and/or operate automatically or semi-automatically. In some embodiments, environment 100 includes multiple wafers and/or die transport tools 114.

For example, the wafer and/or die transport tool 114 may be included in a clustering tool or another tool having multiple process chambers, and may be configured to transport substrates and/or semiconductor devices between multiple process chambers, between process chambers and buffer areas, between process chambers and interface tools (such as equipment front-end modules), between process chambers and transport carriers (such as front-opening wafer transport boxes), and/or similar arrangements. In some embodiments, the wafer and/or die transport tool 114 may be included in a multi-chamber (or clustered) deposition tool 102, which may include multiple pre-cleaning process chambers (for cleaning or removing oxides, oxides, and/or other types of contaminants or byproducts from the substrate and/or semiconductor device) and multiple deposition process chambers (e.g., process chambers for depositing different types of materials, or process chambers for performing different types of deposition steps). In these embodiments, the wafer and/or die transport tool 114 is configured to transport the substrate and/or semiconductor device between the process chambers of the deposition tool 102 without breaking or removing vacuum (or at least partial vacuum) between the process chambers and/or between deposition steps in the deposition tool 102, as described herein.

As described herein, semiconductor process tools such as deposition tools 102 to plating tools 112 can be used to perform combinations of steps to form one or more portions of a nanostructured transistor. In some embodiments, the combination of steps includes growing a seed layer on a spacer, depositing silicon on the seed layer to form amorphous silicon and depositing silicon on a channel to form crystalline silicon, oxidizing the amorphous silicon and crystalline silicon to form an interface layer, forming a high dielectric constant layer on the interface layer, and/or other steps.

The number and configuration of devices shown in Figure 1 are only for providing one or more examples. In practice, there may be additional devices, fewer devices, different devices, or devices with different configurations (compared to the devices described with reference to Figure 1). Furthermore, the two or more devices shown in Figure 1 may be implemented in a single device, or the single device shown in Figure 1 may be implemented in multiple distributed devices. One set of devices in environment 100 (such as one or more devices) may additionally or alternatively perform one or more functions performed by another set of devices in environment 100.

Figure 2 is a schematic diagram of an example of the semiconductor device 200 described herein. The semiconductor device 200 includes one or more transistors. The one or more transistors may include nanostructured transistors such as nanowire transistors, nanosheet transistors, fully wound gate transistors, multi-bridge channel transistors, nanocharged transistors, and/or other types of nanostructured transistors. The semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in Figure 2. For example, the semiconductor device 200 may include additional layers and/or grains formed on and/or beneath a portion of the semiconductor device 200 shown in Figure 2. One or more additional semiconductor structures and/or semiconductor devices may be additionally or alternatively formed in the same layer of an electronic device or integrated circuit (which includes semiconductor devices such as semiconductor device 200 shown in FIG. 2). FIG. 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, 7A and 7B, 8A to 8D, 9, 10A to 10H, and 11 are cross-sectional views of various portions of semiconductor device 200 shown in FIG. 2 and correspond to various process stages in forming the nanostructure transistors of semiconductor device 200.

Semiconductor device 200 includes a semiconductor substrate 205. The semiconductor substrate 205 includes a silicon substrate, a substrate formed of a silicon-containing material, a substrate of a III-V group semiconductor compound material (such as gallium arsenide), a silicon substrate on an insulating layer, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or another type of semiconductor substrate. The semiconductor substrate 205 may include various layers (such as conductive or insulating layers) formed on the semiconductor substrate. The semiconductor substrate 205 may include semiconductor compounds and/or semiconductor alloys. The semiconductor substrate 205 may include various doping arrangements to conform to one or more design parameters. For example, different doping profiles (such as n-type wells or p-type wells) can be formed on the semiconductor substrate 205 in the region, and the region is designed for different device types (such as p-type metal-oxide-semiconductor transistors and n-type metal-oxide-semiconductor transistors). Suitable doping methods may include ion implantation dopants and/or diffusion processes. Furthermore, the semiconductor substrate 205 may include an epitaxial layer, may be stressed to improve performance, and/or may have other suitable enhancement structures. The semiconductor substrate 205 may include a portion of a semiconductor wafer on which other semiconductor devices can be formed.

Mesa regions 210 may be included on and/or extend above semiconductor substrate 205. Nanostructures of semiconductor device 200 may be formed on the structure provided by mesa regions 210, such as nanostructure channels, nanostructure gate portions covering each nanostructure channel, sacrifice nanostructures, and/or other structures. In some embodiments, one or more mesa regions 210 are formed within and/or from fin structures (such as silicon fin structures), and the fin structures are formed in semiconductor substrate 205. Mesa regions 210 and semiconductor substrate 205 may include the same material and may be formed from semiconductor substrate 205. In some embodiments, the mesa region 210 is doped to form different types of nanostructured transistors, such as p-type and/or n-type nanostructured transistors. In some embodiments, the mesa region 210 comprises silicon or another semiconductor element material such as germanium. In some embodiments, the mesa region 210 comprises semiconductor alloy materials such as silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or combinations thereof.

The mesa region 210 can be fabricated using suitable semiconductor manufacturing techniques, such as masking, photolithography, etching, and/or other processes. For example, the fin structure can be formed by etching a portion of the semiconductor substrate 205 to form a recess in the semiconductor substrate 205. An isolation material can then be filled into the recess, and the isolation material can be recessed or etched back to form a shallow trench isolation region 215 on the semiconductor substrate 205 between the fin structure and the mesa region. Source/drain recesses can be formed in the fin structure, resulting in the mesa region 210 formed between the source/drain recesses. However, other manufacturing techniques can also be used to form the shallow trench isolation region 215 and/or the mesa region 210.

The shallow trench isolation region 215 can electrically isolate adjacent fin-like structures and can provide other layers and/or layers on which the semiconductor device 200 is formed. The shallow trench isolation region 215 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, low dielectric constant dielectric materials, and/or another suitable insulating material. The shallow trench isolation region 215 may include a multilayer structure, such as having one or more padding layers.

Semiconductor device 200 includes multiple nanostructure channels 220 that extend between and are electrically coupled to source/drain regions 225. The source/drain region may refer to a single source or drain, or a source and drain, depending on the context. The nanostructure channels 220 are arranged approximately perpendicular to the semiconductor substrate 205. In other words, the nanostructure channels 220 are vertically arranged or stacked on the semiconductor substrate 205.

The nanostructure channel 220 includes a silicon-based nanostructure (such as nanosheets, nanowires, or other examples) that can serve as a semiconductor channel for the nanostructure transistor of the semiconductor device 200. In some embodiments, the nanostructure channel 220 may include silicon-germanium or another silicon-based material. The source/drain region 225 includes silicon and one or more dopants such as p-type materials (such as boron, gallium, or other materials), n-type materials (such as phosphorus, arsenic, or other materials), and/or another type of dopant. In summary, the semiconductor device 200 may include a p-type metal-oxide-semiconductor nanostructure transistor (which includes a p-type source/drain region 225), an n-type metal-oxide-semiconductor nanostructure transistor (which includes an n-type source/drain region 225), and/or other types of nanostructure transistors.

In some embodiments, the buffer region 230 is located between and below the source/drain region 225 and the fin-like structure on the semiconductor substrate 205. The buffer region 230 can provide isolation between the source/drain region 225 and the adjacent mesa region 210. The buffer region 230 can reduce, minimize, and/or prevent electrons from passing through the mesa region 210 (instead passing through the nanostructure channel 220 to reduce leakage current), and/or reduce, minimize, and/or prevent doping from entering the mesa region 210 from the source/drain region 225 (which can reduce short-channel effects).

Capping layer 235 may be located above and/or below source/drain region 225. Capping layer 235 may include silicon, silicon-germium, doped silicon, doped silicon-germium, and/or another material. Capping layer 235 may reduce dopant diffusion and protect source/drain region 225 during semiconductor fabrication steps used in semiconductor device 200 prior to contact formation. Furthermore, capping layer 235 facilitates the formation of metal-semiconductor alloys (such as silicates).

At least one set of nanostructure channels 220 extends through one or more gate structures 240. The gate structure 240 may be composed of one or more metallic materials, one or more high dielectric constant materials, and/or one or more other types of materials. In some embodiments, a dummy gate structure (such as a polysilicon gate structure or another type of gate structure) is formed at the location of the gate structure 240 (before the formation of the gate structure 240), so one or more other layers and/or structures of the semiconductor device 200 may be formed before the formation of the gate structure 240. This reduces and/or avoids damage to the gate structure 240, which could otherwise be damaged by steps that form one or more layers and/or structures. A gate replacement process is then performed to remove the dummy gate structure and replace it with the gate structure 240 (e.g., a gate replacement structure).

As shown in Figure 2, portions of the gate structure 240 are formed between pairs of nanostructure channels 220 in a staggered vertical arrangement. In other words, the semiconductor device 200 includes one or more vertically stacked portions of the staggered nanostructure channels 220 and the gate structure 240, as shown in Figure 2. In this manner, the gate structure 240 covers multiple sides of the associated nanostructure channels 220 to increase control of the nanostructure channels 220, increase the driving current used by the nanostructure transistors of the semiconductor device 200, and reduce short-channel effects of the nanostructure transistors of the semiconductor device 200.

As detailed in Figures 10A to 10H, an interface layer can be formed between the gate structure 240 and the nanostructure channel 220. For example, the interface layer can be composed of a dielectric material such as an oxide (e.g., silicon oxide) to suppress electron tunneling out of the nanostructure channel 220. Furthermore, the thickness of the interface layer is approximately 0.5 nm to approximately 1.0 nm. Choosing a thickness not exceeding 1.0 nm allows for significant miniaturization of the gate structure 240 and the nanostructure channel 220, as a thicker interface layer would reduce the efficiency of the gate structure 240. Choosing a thickness of at least 0.5 nm helps to avoid leakage current in the nanostructure channel 220, because a thinner interface layer may allow electrons to tunnel out of the nanostructure channel 220 (e.g., tunneling to the inner spacer 245, as described below).

Two or more nanostructured transistors of semiconductor device 200 may share some source/drain regions 225 and gate structures 240. In these embodiments, one or more source/drain regions 225 and gate structures 240 may be connected or coupled to multiple nanostructure channels 220, as in the example shown in Figure 2. This can allow multiple nanostructure channels 220 to be controlled by a single gate structure 240 and a pair of source/drain regions 225.

The inner spacer 245 may be located between the source/drain region 225 and the adjacent gate structure 240. Specifically, the inner spacer 245 may be located between the source/drain region 225 and the portion of the gate structure 240 that covers multiple nanostructure channels 220. The inner spacer 245 is located at the end of the portion of the gate structure 240 that covers multiple nanostructure channels 220. The cavity contains the inner spacer 245, and the cavity is formed between the end portions of adjacent nanostructure channels 220. The inner spacer 245 reduces parasitic capacitance and protects the source/drain regions 225 from etching during the nanosheet release step, in which the sacrificial nanosheets between the nanostructure channels 220 are removed. The inner spacer 245 includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, and/or another dielectric material.

In some embodiments, semiconductor device 200 includes a hybrid fin structure (not shown). The hybrid fin structure can also be considered as a dummy fin, a hybrid of fins, a non-active fin, or similar. The hybrid fin structure may be located between adjacent source/drain regions 225, between portions of gate structure 240, between stacks of adjacent nanostructure channels 220, and/or between other structures. The hybrid fin extends approximately perpendicular to the gate structure 240.

The hybrid fin structure is configured to provide electrical isolation between two or more structures and/or components in the semiconductor device 200. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between stacks of two or more nanostructure channels 220. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between two or more source/drain regions 225. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between portions of two or more gate structures. In some embodiments, the hybrid fin structure is configured to provide electrical isolation between the source/drain regions 225 and the gate structure 240.

Hybrid fin structures may include a variety of dielectric materials. Hybrid fin structures may include a combination of one or more dielectric materials with low dielectric constants (such as silicon oxide, silicon nitride, and/or other materials) and one or more dielectric materials with high dielectric constants (such as iron oxide and/or other dielectric materials with high dielectric constants).

Semiconductor device 200 may also include an interlayer dielectric layer, such as dielectric layer 250, on shallow trench isolation region 215. Dielectric layer 250 can be considered as a zeroth interlayer dielectric layer. Dielectric layer 250 surrounds gate structure 240 to provide electrical isolation and/or insulation between gate structure 240, source/drain region 225, and/or other structures. Conductive structures such as contacts and/or interconnects may pass through dielectric layer 250 to source/drain region 225 and gate structure 240 to control source/drain region 225 and gate structure 240.

As mentioned above, Figure 2 is provided as an example. Other examples may differ from the example illustrated with Figure 2.

Figures 3A and 3B are examples of embodiment 300 of the fin formation process described herein. Examples of embodiment 400 include forming a fin structure for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in Figures 3A and 3B. The semiconductor device 200 may include additional layers and/or dies formed above and/or below portions of the semiconductor device 200 shown in Figures 3A and 3B. One or more additional semiconductor structures and/or semiconductor devices may be formed additionally or alternatively in the same layer of an electronic device containing the semiconductor device 200.

Figure 3A shows a perspective view of the semiconductor device 200 and a cross-sectional view along section A-A in the perspective view. As shown in Figure 3A, the semiconductor device 200 can be fabricated on a semiconductor substrate 205. A layered stack 305 is formed on the semiconductor substrate 205. The layered stack 305 can be considered as a superlattice. In some embodiments, one or more steps related to the semiconductor substrate 205 can be performed before forming the layered stack 305. For example, a breakdown-resistant implantation step can be performed. The breakdown-resistant implantation step can be performed in one or more regions of the semiconductor substrate, on which nanostructure channels 220 can be formed. For example, a breakdown-resistant implantation step can be performed to reduce and/or avoid breakdown or unwanted diffusion into the semiconductor substrate 205.

The layered stack 305 includes multiple staggered layers arranged approximately perpendicular to the semiconductor substrate 205. For example, the layered stack 305 includes a first layer 310 and a second layer 315 arranged perpendicularly on the semiconductor substrate 205. The number of first layers 310 and second layers 315 shown in FIG. 3A is merely illustrative, and other numbers of first layers 310 and second layers 315 are also within the scope of embodiments of the present invention. In some embodiments, the thicknesses of the first layer 310 and the second layer 315 are different. For example, the thickness of the second layer 315 may be greater than the thickness of the first layer 310. In some embodiments, the thickness of the first layer 310 (or a group of first layers 310) may be approximately 4 nm to approximately 7 nm. In some embodiments, the thickness of the second layer 315 (or a group of second layers 315) may be approximately 8 nm to approximately 12 nm. However, other values used for the thickness of the first layer 310 and the second layer 315 are also within the scope of the embodiments of the present invention.

The first layer 310 comprises a first material composition, and the second layer 315 comprises a second material composition. In some embodiments, the first material composition and the second material composition are the same. In some embodiments, the first material composition and the second material composition are different. For example, the first layer 310 may comprise silicon-germium, and the second layer 315 may comprise silicon. In some embodiments, the first material composition and the second material composition have different oxidation rates and/or etching selectivity.

As described herein, the second layer 315 can be processed to form nanostructure channels 220 for subsequent formation of the nanostructure transistor in the semiconductor device 200. The first layer 310 is a sacrifice nanostructure and will ultimately be removed to define the vertical distance between adjacent nanostructure channels 220 for the subsequent formation of the gate structure 240 in the semiconductor device 200. In summary, the first layer 310 can be considered a sacrifice layer, and the second layer 315 can be considered a channel layer.

A deposition tool 102 deposits and/or grows interlaced layers of stacked layers 305 to form nanostructures (such as nanosheets) on a semiconductor substrate 205. For example, the deposition tool 102 may epitaxially grow interlaced layers. However, other processes may be used to form interlaced layers of stacked layers 305. The method of epitaxially growing interlaced layers of stacked layers 305 may be a molecular beam epitaxy process, an organometallic chemical vapor deposition process, and/or another suitable epitaxial growth process. In some embodiments, the epitaxially grown layers, such as the second layer 315, may comprise the same material as the semiconductor substrate 205. In some embodiments, the first layer 310 and/or the second layer 315 comprises materials different from the material of the semiconductor substrate 205. As described above, in some embodiments, the first layer 310 comprises an epitaxially grown silicon-germium layer, while the second layer 315 comprises an epitaxially grown silicon layer. The first layer 310 and/or the second layer 315 may be modified to include other materials such as germanium, semiconductor compound materials (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide), semiconductor alloys (such as silicon-germium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or gallium indium arsenide phosphide), and/or combinations thereof. The choice of materials for the first layer 310 and/or the second layer 315 can provide different oxidation characteristics, different etching selectivity, and/or other different properties.

As shown in Figure 3A, the deposition tool 102 may form one or more additional layers on the layered stack 305. For example, a hard mask layer 320 may be formed on the layered stack 305, such as on the topmost second layer 315 of the layered stack 305. In another example, a capping layer 325 may be formed on the hard mask layer 320. In yet another example, another hard mask layer containing an oxide layer 330 and a nitride layer 335 may be formed on the capping layer 325. One or more hard mask layers 320, capping layers 325, and oxide layers 330 may be used to form one or more structures of the semiconductor device 200. The oxide layer 330 can serve as an adhesion layer between the layered stack 305 and the nitride layer 335, and can also serve as an etch stop layer for etching the nitride layer 335. One or more hard mask layers 320, capping layers 325, and the oxide layer 330 may include silicon-germium, silicon nitride, silicon oxide, and/or another material. The capping layer 325 may include silicon and/or another material. In some embodiments, the capping layer 325 and the semiconductor substrate 205 may be made of the same material. In some embodiments, thermal growth or deposition (such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, and/or another deposition technique) can form one or more additional layers.

Figure 3B shows a perspective view of the semiconductor device 200 and a cross-sectional view along section A-A. As shown in Figure 3B, the layered stack 305 and the semiconductor substrate 205 can be etched to remove portions of the layered stack 305 and the semiconductor substrate 205. The portions 340 of the layered stack 305 and the mesa regions 210 (which can also be considered as silicon mesa or mesa portions) remaining after the etching step can be considered as fin structures 345 on the semiconductor substrate 205 of the semiconductor device 200. The fin structure 345 includes portions 340 of the layered stack 305 located on the mesa regions 210 within and/or above the semiconductor substrate 205. The fin structure 345 can be formed using any suitable semiconductor manufacturing process technology. For example, the deposition tool 102, exposure tool 104, development tool 106, and/or etching tool 108 can form the fin-like structure 345 using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, resulting in a pattern spacing smaller than that obtained using a single direct photolithography process. For example, a sacrifice layer can be formed on a substrate, and the sacrifice layer can be patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrifice layer. The sacrifice layer is then removed, and the remaining spacers can then be used to pattern the fin-like structure.

In some embodiments, a deposition tool 102 forms a photoresist layer on a hard mask layer containing an oxide layer 330 and a nitride layer 335. An exposure tool 104 exposes the photoresist layer with radiation (such as deep ultraviolet or extreme ultraviolet), performs a post-exposure baking process (to remove residual solvent from the photoresist layer), and a developing tool 106 develops the photoresist layer to form mask units (or patterns) within the photoresist layer. In some embodiments, the method of patterning the photoresist layer to form mask units can employ electron beam lithography. Next, a masking unit can be used to protect portions of the semiconductor substrate 205 and the layered stack 305 during the etching step, keeping these portions of the semiconductor substrate 205 and the layered stack 305 unetched to form a finned structure 345. The unprotected portions of the substrate and the unprotected portions of the layered stack 305 can be etched (e.g., by etching tool 108) to form trenches in the semiconductor substrate 205. The etching tool can employ dry etching techniques (such as reactive ionic etching), wet etching techniques, and/or combinations thereof to etch the unprotected portions of the substrate and the unprotected portions of the layered stack 305.

In some embodiments, another fin-forming technique may be used to form the fin structure 345. For example, a fin region may be defined (e.g., defined by a mask or isolation region), and the portion 340 may be epitaxially grown in the form of the fin structure 345. In some embodiments, the method of forming the fin structure 345 includes a trimming process to reduce the width of the fin structure 345. The trimming process may include a wet etching process, a dry etching process, and/or other processes.

As shown in Figure 3B, fin structures 345 can be formed for use in different types of nanostructure transistors used in the semiconductor device 200. Specifically, a first set of fin structures 345a can be formed for p-type nanostructure transistors (such as p-type metal-oxide-semiconductor nanostructure transistors), and a second set of fin structures 345b can be formed for n-type nanostructure transistors (such as n-type metal-oxide-semiconductor nanostructure transistors). The second set of fin structures 345b can be doped with p-type dopants (such as boron, germanium, and/or other dopants), while the first set of fin structures 345a can be doped with n-type dopants (such as phosphorus, arsenic, and/or other dopants). Subsequently, p-type source/drain regions may be additionally or alternatively formed for use in p-type nanostructure transistors containing the first set of fin structures 345a, and n-type source/drain regions may be formed for use in n-type nanostructure transistors containing the second set of fin structures 345b.

The first set of finned structures 345a (such as a p-type metal-oxide-semiconductor semi-finned structure) and the second set of finned structures 345b (such as an n-type metal-oxide-semiconductor semi-finned structure) may have similar and/or different properties. For example, the first set of finned structures 345a may have a first height, while the second set of finned structures 345b may have a second height, wherein the first height and the second height are different. In another example, the first set of finned structures 345a may have a first width, while the second set of finned structures 345b may have a second width, wherein the first width and the second width are different. In the example shown in Figure 3B, the second width of the second set of fin structures 345b (e.g., for n-type metal-oxide-semiconductor transistors) is greater than the first width of the first set of fin structures 345a (e.g., for p-type metal-oxide-semiconductor transistors). However, other examples also fall within the scope of embodiments of the present invention.

As described above, Figures 3A and 3B are provided as examples. Other examples may differ from those described with reference to Figures 3A and 3B. Examples of embodiment 300 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described with reference to Figures 3A and 3B).

Figures 4A and 4B illustrate an example of embodiment 400 of the shallow trench isolation formation process described herein. Embodiment 400 includes forming shallow trench isolation regions 215 between fin-like structures 345 for use with a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in Figures 4A and 4B. The semiconductor device 200 may include additional layers and/or dies formed above and/or below portions of the semiconductor device 200 shown in Figures 4A and 4B. One or more additional semiconductor structures and/or semiconductor devices may be formed additionally or alternatively in the same layer of an electronic device containing the semiconductor device 200. In some embodiments, the steps described in conjunction with Figures 3A and 3B may be followed by the steps described in the example of embodiment 400.

Figure 4A shows a perspective view and a cross-sectional view along section A-A of the semiconductor device 200. As shown in Figure 4A, a pad 405 and a dielectric layer 410 are formed on the semiconductor substrate 205 and inserted into fin-like structures 345 (e.g., formed between fin-like structures 345). A deposition tool 102 can deposit the pad 405 and the dielectric layer 410 on the semiconductor substrate 205 and in the trenches between the fin-like structures 345. The deposition tool 102 can form the dielectric layer 410 such that the height of the upper surface of the dielectric layer 410 is approximately the same as the height of the upper surface of the nitride layer 335.

The deposition tool 102 can be modified to form a dielectric layer 410 with a height greater than the height of the upper surface of the nitride layer 335, as shown in Figure 4A. In this manner, the dielectric layer 410 can be overfilled into the trenches between the fin-like structures 345 to ensure that the trenches are completely filled with the dielectric layer 410. A planarization or polishing step (such as a chemical mechanical polishing step) can be performed after the planarization tool 110 to planarize the dielectric layer 410. In this step, the nitride layer 335 of the hard mask layer can serve as a stop layer for chemical mechanical polishing. In other words, the planarization tool 110 can planarize the dielectric layer 410 until the nitride layer 335 of the hard mask layer is exposed. In summary, the height of the upper surface of the dielectric layer 410 after this step can be approximately the same as the height of the upper surface of the nitride layer 335.

The deposition tool 102 may employ compliant deposition techniques to deposit the pad 405. The deposition tool 102 may employ chemical vapor deposition techniques (such as flowable chemical vapor deposition or another chemical vapor deposition technique), physical vapor deposition techniques, atomic layer deposition techniques, and/or another deposition technique to deposit the dielectric layer. In some embodiments, the semiconductor device 200 may be annealed after the pad 405 is deposited to improve the quality of the pad 405.

The pad 405 and the dielectric layer 410 may each include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric material, and/or another suitable insulating material. In some embodiments, the dielectric layer 410 may include a multilayer structure, such as having one or more pad layers.

Figure 4B shows a perspective view and a cross-sectional view along section A-A of the semiconductor device 200. As shown in Figure 4B, a back etch step can be performed to remove portions of the pad 405 and the dielectric layer 410 to form a shallow trench isolation region 215. The etching tool 108 can etch the pad 405 and the dielectric layer 410 in the back etch step to form the shallow trench isolation region 215. The etching tool 108 can etch the pad 405 and the dielectric layer 410 according to a hard mask layer (such as a hard mask layer containing an oxide layer 330 and a nitride layer 335). The etching tool 108 etches the pad 405 and the dielectric layer 410 such that the height of the shallow groove isolation region 215 is less than or approximately equal to the bottom height of the portion 340 of the layered stack 305. In summary, the portion 340 of the layered stack 305 extends above the shallow groove isolation region 215. In some embodiments, the pad 405 and the dielectric layer 410 are etched such that the height of the shallow groove isolation region 215 is less than the height of the upper surface of the mesa region 210.

In some embodiments, the etching tool 108 employs dry etching technology to etch the pad 405 and the dielectric layer 410. Ammonia, hydrofluoric acid, and/or another etching agent may be used. Plasma-based dry etching technology can cause reactions between the etching agent and the materials of the pad 405 and the dielectric layer 410, including: _SiO₂ + 4HF → _SiF₄ + _2H₂O . The silicon oxide of the pad 405 and the dielectric layer 410 reacts with hydrofluoric acid to form a byproduct containing silicon tetrafluoride and water. Hydrofluoric acid and ammonia further decompose the silicon tetrafluoride to form an ammonium fluorosilicate byproduct. _{SiF₄ +} 2HF + _2NH₃ → ( _NH₄ ) _₂SiF₆ The ammonium fluorosilicate byproduct can be removed from the process chamber of the self-etching tool 108. After removing the ammonium fluorosilicate, the ammonium fluorosilicate can be sublimated into silicon tetrafluoride, ammonia, and hydrofluoric acid at a post-processing temperature of approximately 100°C to approximately 250°C.

In some embodiments, the etching tool 108 etches the pad 405 and the dielectric layer 410, such that the height of the shallow groove isolation region 215 between the first set of fin structures 345a (e.g., for p-type metal-oxide-semiconductor transistors) is greater than the height of the shallow groove isolation region 215 between the second set of fin structures 345b (e.g., for n-type metal-oxide-semiconductor transistors). This is primarily because the width of the second set of fin structures 345b is greater than the width of the first set of fin structures 345a. Furthermore, this causes the upper surface of the shallow groove isolation region 215 between the first set of fin structures 345a and the second set of fin structures 345b to tilt (e.g., tilting downwards from the first set of fin structures 345a to the second set of fin structures 345b, as shown in the example in Figure 4A). The van der Waals forces between the etchant and the surfaces of the pad 405 and the dielectric layer 410 can physically attract the etchant used to etch the pad 405 and the dielectric layer 410, for example, physically bonding the etchant to the pad 405 and the dielectric layer 410. Dipole moment forces can trap the etchant. The etchant then adheres to the suspension bonds between the pad 405 and the dielectric layer 410 and begins chemical adsorption. The chemical adsorption of the etchant on the surfaces of the pad 405 and the dielectric layer 410 causes etching of the pad 405 and the dielectric layer 410. The wider grooves between the second set of finned structures 345a allow for a larger surface area for chemical adsorption, resulting in a higher etching rate between the second set of finned structures 345b. The higher etching rate results in a shallow groove isolation region 215 between the second set of fin structures 345b being smaller than the shallow groove isolation region 215 between the first set of fin structures 345a.

As described above, Figures 4A and 4B are provided as examples. Other examples may differ from those described with reference to Figures 4A and 4B. Examples of embodiment 400 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described with reference to Figures 4A and 4B).

Figures 5A to 5C are examples of embodiments 500 of the covered sidewall fabrication process described herein. Examples of embodiments 500 include forming covered sidewalls on the sides of a portion 340 of a layered stack 305 for use with a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in Figures 5A to 5C. The semiconductor device 200 may include additional layers and/or dies formed above and/or below the portions of the semiconductor device 200 shown in Figures 5A to 5C. One or more additional semiconductor structures and/or semiconductor devices may be formed additionally or alternatively in the same layer of an electronic device containing the semiconductor device 200. In some embodiments, the steps described in conjunction with Figures 3A and 3B and 4A and 4B may be followed by the steps described in conjunction with the example of embodiment 500.

Figure 5A shows a perspective view and a cross-sectional view along section A-A of the semiconductor device 200. As shown in Figure 5A, a cladding 505 is formed over the fin-like structures 345 (such as over the upper surface and sidewalls of the fin-like structures 345) and over the shallow groove isolation regions 215 between the fin-like structures 345. The cladding 505 includes silicon-germanium or another material. The cladding layer 505 can be made of the same material as the first layer 310, allowing the same etching steps (such as nanostructure release processes) to remove the cladding sidewall (which will be formed by the cladding layer 505) and the first layer 310, while a replacement gate (such as gate structure 240) can be formed in the area originally occupied by the cladding sidewall and the first layer 310. This allows the replacement gate to completely surround the nanostructure channels of the nanostructure transistor of the semiconductor device 200.

The deposition tool 102 can deposit a coating 505. In some embodiments, the deposition tool 102 deposits a seed layer (such as a silicon seed layer or another type of seed layer) on the fin structure 345 (such as on the upper surface and sidewalls of the fin structure 345) and on the shallow groove isolation regions 215 between the fin structures 345. The deposition tool 102 can then deposit silicon-germanium on the seed layer to form the coating 505. The seed layer can promote the growth and adhesion of the coating 505.

The seed layer deposition process may include supplying a silicon precursor to the process chamber of the deposition tool 102 using a carrier gas such as nitrogen, hydrogen, or other gases. Some embodiments include a pre-cleaning step before seed layer deposition to reduce germanium oxide formation. The silicon precursor may include ethylene silane or another silicon precursor. Using ethylene silane is advantageous for forming a seed layer with a thickness of approximately 0.5 nm to approximately 1.5 nm to provide sufficient cover sidewall thickness and achieve a controllable and consistent thickness for the capping 505. However, other ranges and values for the seed layer thickness are also within the scope of this invention.

The temperature for depositing the seed layer can be approximately 450˚C to approximately 500˚C (or another range of temperatures), the pressure can be approximately 30 Torr to approximately 100 Torr (or another range of pressures), the time can be approximately 100 seconds to approximately 300 seconds (or another range of times), and/or other parameters.

The step of depositing silicon-germanium coating 505 may include forming a coating 505 with an amorphous configuration to promote compliant deposition of coating 505. The germanium content of silicon-germanium may be approximately 15% to approximately 25%. However, other values for germanium content are also within the scope of embodiments of the invention. The step of depositing coating 505 may include using a carrier gas such as nitrogen, hydrogen, or other gas to provide a silicon precursor (such as ethylene silane, silane, or other silicon precursor) and a germanium precursor (such as germane or another germanium precursor) to the deposition chamber of deposition tool 102. The temperature of the deposition coating 505 may be approximately 500˚C to approximately 550˚C (or another range of temperatures) and/or the pressure may be approximately 5 Torr to approximately 20 Torr (or another range of pressures).

Figure 5B shows a perspective view and a cross-sectional view along section A-A. As shown in Figure 5B, a back-etching step is performed to etch the coating 505 to form the coating sidewall 510. The etching tool 108 can employ a plasma-based dry etching technique or another etching technique to etch the coating 505. The etching tool 108 can perform a back-etching step to remove a portion of the coating 505 from the top of the fin-like structure 345 and the top of the shallow groove isolation area 215. Removing the top cover 505 from the shallow groove isolation area 215 between the fin structures 345 ensures that the cover sidewall 510, without feet, is located on the shallow groove isolation area 215 between the fin structures 345. This ensures that the cover sidewall 510, without feet, is located under the mixed fin structure, which will be formed on the shallow groove isolation area 215 between the fin structures 345.

In some embodiments, the etching tool 108 uses a fluorine-based etching agent to etch the coating 505. The fluorine-based etching agent may include sulfur hexafluoride, fluorinated methane, and/or another fluorine-based etching agent. Other reactants and/or carrier gases such as methane, hydrogen, argon, and/or helium may also be used in the back-etching step. In some embodiments, the plasma bias voltage used in the back-etching step may be approximately 500 volts to approximately 2000 volts. However, other values for the plasma bias voltage are also within the scope of the embodiments of the present invention. In some embodiments, the step of removing a portion of the coating 505 from the top of the shallow groove isolation region 215 includes performing highly directional (e.g., isotropic) etching to selectively remove (e.g., selectively etch) the coating 505 on the top of the shallow groove isolation region 215 between the fin structures 345.

In some embodiments, the cover sidewall 510 includes asymmetrical features (e.g., different lengths, depths, and/or angles). These asymmetrical features can increase the depth of the gate structure 240 used by different types of nanotransistors (e.g., p-type or n-type nanotransistors) and reduce and/or minimize the footprint of the cover sidewall 510 on the shallow trench isolation region 215 beneath the mixed fin structure of the nanotransistor of the semiconductor device 200 (thus reducing and/or minimizing the footprint of the gate structure 240 formed in the area originally occupied by the cover sidewall 510 after its removal). Reducing and/or minimizing pins can further reduce the problems of electrical short circuits and/or leakage current.

Figure 5C shows a perspective view and a cross-sectional view along section A-A of the semiconductor device 200. As shown in Figure 5C, the hard mask layer containing oxide layer 330 and nitride layer 335, as well as the capping layer 325, are removed to expose the hard mask layer 320. In some embodiments, the removal of the capping layer 325, oxide layer 330, and nitride layer 335 may employ an etching step (performed by etching tool 108), a planarization technique (performed by planarization tool 110), and/or another semiconductor fabrication technique.

As described above, Figures 5A to 5C are provided as examples. Other examples may differ from those described with reference to Figures 5A to 5C. Examples of embodiment 500 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described with reference to Figures 5A to 5C).

Figures 6A to 6C are examples of embodiments 600 of the hybrid fin structure formation process described herein. Examples of embodiment 600 include forming a hybrid fin structure between fin structures 345 for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in Figures 6A to 6C. The semiconductor device 200 may include additional layers and/or dies formed above and/or below portions of the semiconductor device 200 shown in Figures 6A to 6C. One or more additional semiconductor structures and/or semiconductor devices may be formed additionally or alternatively in the same layer of an electronic device containing the semiconductor device 200. In some embodiments, the steps described in conjunction with Figures 3A and 3B, 4A and 4B, and 5A to 5C may be followed by the steps illustrated in the example of embodiment 600.

Figure 6A shows a perspective view of the semiconductor device 200 and a cross-sectional view along section A-A. As shown in Figure 6A, a pad 605 and a dielectric layer 610 are formed on a shallow trench isolation region 215 sandwiched between fin structures 345 and on the fin structure 345. A deposition tool 102 can deposit the pad 605 and the dielectric layer 610. The deposition tool 102 can employ a compliant deposition technique to deposit the pad 605. The deposition tool 102 may be used to deposit the dielectric layer 610 using chemical vapor deposition (CPV) techniques (such as flowable CPV or another CPV technique), physical vapor deposition (PVD), atomic layer deposition (ALD), and/or another deposition technique. In some embodiments, the semiconductor device 200 may be annealed after the dielectric layer 610 is deposited to improve the quality of the dielectric layer 610.

The deposition tool 102 can be used to make the height of the upper surface of the formed dielectric layer 610 approximately the same as the height of the upper surface of the hard mask layer 320. Alternatively, the deposition tool 102 can be used to make the height of the upper surface of the formed dielectric layer 610 greater than the height of the upper surface of the hard mask layer 320, as shown in the example of FIG. 6A. In this manner, the dielectric layer 610 overfills the trenches between the fin-like structures 345 to ensure that the trenches completely fill the dielectric layer 610. A planarization or polishing step (such as a chemical mechanical polishing step) can be performed after the planarization tool 110 to planarize the dielectric layer 610.

The pad 605 and the dielectric layer 610 may each include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, fluorosilicate glass, a low dielectric constant dielectric material, and/or another suitable insulating material. In some embodiments, the dielectric layer 610 may include a multilayer structure, such as having one or more pad layers.

Figure 6B shows a perspective view of the semiconductor device 200 and a cross-sectional view along section A-A. As shown in Figure 6B, an etch-back step is performed to remove a portion of the dielectric layer 610. The etch tool 108 can etch the dielectric layer 610 in the etch-back step to reduce the height of the upper surface of the dielectric layer 610. Specifically, the etch tool 108 etches the dielectric layer 610 such that the height of the portion of the dielectric layer 610 between the fin structures 345 is less than the height of the upper surface of the hard mask layer 320. In some embodiments, the etching tool 108 etches the dielectric layer 610 such that the height of a portion of the dielectric layer 610 between the fin structures 345 is approximately equal to the height of the upper surface of the second layer 315 at the very top of the portion 340.

Figure 6C shows a perspective view and a cross-sectional view along section A-A of the semiconductor device 200. As shown in Figure 6C, a high dielectric constant layer 615 is deposited on a portion of the dielectric layer 610 between the finned structures 345. The deposition tool 102 can deposit a high dielectric constant material such as iron oxide and/or another high dielectric constant material to form the high dielectric constant layer 615, and the formation method can employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, and/or another deposition technique. The combination of portions of the dielectric layer 610 between the fin structures 345 and portions of the high-dielectric-constant layer 615 between the fin structures 345 can be considered as a hybrid fin structure 620 (or a dummy fin structure). In some embodiments, the planarization tool 110 may perform a planarization step to planarize the high-dielectric-constant layer 615 so that the height of the upper surface of the high-dielectric-constant layer 615 is approximately the same as the height of the hard mask layer 320.

Then, as shown in Figure 6C, the hard mask layer 320 is removed. The method of removing the hard mask layer 320 may include using an etching technique (such as plasma etching, wet chemical etching, and/or another etching technique) or another removal technique.

As described above, Figures 6A to 6C are provided as examples. Other examples may differ from those described in conjunction with Figures 6A to 6C. Examples of embodiment 600 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described in conjunction with Figures 6A to 6C).

Figures 7A and 7B are examples of an embodiment 700 of the dummy gate formation process described herein. Examples of embodiment 700 include forming a dummy gate structure for use in a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include one or more additional devices, structures, and/or layers not shown in Figures 7A and 7B. The semiconductor device 200 may include additional layers and/or dies formed above and/or below portions of the semiconductor device 200 shown in Figures 7A and 7B. One or more additional semiconductor structures and/or semiconductor devices may be formed additionally or alternatively in the same layer of the electronic device containing the semiconductor device 200. In some embodiments, the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, and 6A to 6C may be followed by the steps described in conjunction with the example of embodiment 700.

Figure 7A shows a perspective view of semiconductor device 200. As shown in Figure 7A, a dummy gate structure 705 (which can also be viewed as a dummy gate stack or a temporary gate structure) is formed on the fin structure 345 and the hybrid fin structure 620. The dummy gate structure 705 is a sacrifice structure that will be replaced by a replacement gate structure or a replacement gate stack (such as gate structure 240) in subsequent process stages used in semiconductor device 200. The portion of the fin structure 345 below the dummy gate structure 705 can be considered as a channel region. The virtual gate structure 705 can also define the source/drain regions of the fin structure 345, such as the regions of the fin structure 345 on both sides of the channel region and adjacent to both sides of the channel region.

The dummy gate structure 705 may include a gate layer 710, a hard mask layer 715 located on the gate layer 710, and spacer layers 720 located on both sides of the gate layer 710 and the hard mask layer 715. The dummy gate structure 705 may be formed on the gate dielectric layer 725 between the topmost second layer 315 and the dummy gate structure 705, and between the mixed fin structure 620 and the dummy gate structure 705. The gate layer 710 includes polycrystalline silicon or another material. The hard mask layer 715 includes one or more layers such as oxide layers (e.g., a silicon dioxide or other material-containing oxide pad layer) and nitride layers formed on the oxide layers (e.g., silicon nitride such as trisilicon tetranitride or other material-containing oxide pad layer). The spacer layer 720 includes silicon carbide, nitrogen-free silicon carbide, or another suitable material. The gate dielectric layer 725 may include silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., trisilicon tetranitride), a high dielectric constant dielectric material, and/or another suitable material.

The formation of the layered structure 705 of the virtual gate structure can employ various semiconductor manufacturing techniques such as deposition (e.g., by deposition tool 102), patterning (e.g., by exposure tool 104 and development tool 106), etching (e.g., by etching tool 108), and/or other techniques. Examples may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, photolithography, photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying (e.g., spin drying and/or hard baking), dry etching (e.g., reactive ion etching), wet etching, and/or other techniques.

In some embodiments, a gate dielectric layer 725 is compliantly deposited on the semiconductor device 200, and then the gate dielectric layer 725 is selectively removed from portions of the semiconductor device 200 (such as source/drain regions). A gate layer 710 is then deposited on the retained portion of the gate dielectric layer 725. A hard mask layer 715 is then deposited on the gate layer 710. A spacer layer 720 can be compliantly deposited in a manner similar to that of the gate dielectric layer 725, and the spacer layer 720 can be etched back, leaving the spacer layer 720 on the sidewall of the dummy gate structure 705. In some embodiments, the spacer layer 720 includes multiple spacer layers. For example, the spacer layer 720 may include a sealing spacer layer formed on the sidewall of the virtual gate structure 705, and a substrate spacer layer formed on the sealing spacer layer. The sealing spacer layer and the substrate spacer layer may be composed of similar or different materials. In some embodiments, the substrate spacer layer is formed without the plasma surface treatment used for the sealing spacer layer. In some embodiments, the thickness of the substrate spacer layer is greater than the thickness of the sealing spacer layer. In some embodiments, the gate dielectric layer 725 can be omitted in the self-dummy gate structure forming process, and instead formed in the gate replacement process.

Figure 7A further shows the reference cross-sections used in subsequent diagrams. Cross-section A-A in the x-z plane (which can be considered a y-section) crosses the fin structure 345 and the mixed fin structure 620 in the source/drain region of the semiconductor device 200. Cross-section B-B in the y-z plane (which can be considered an x-section) is perpendicular to cross-section A-A and crosses the dummy gate structure 705 in the source/drain region of the semiconductor device 200. Cross-section C-C in the x-z plane is parallel to cross-section A-A and perpendicular to cross-section B-B, and runs along the dummy gate structure 705. Subsequent diagrams will be based on the reference cross-sections for clarity. In some diagrams, the same labels for the shown components or structures may be omitted to avoid obscuring other components or structures, which helps to make the diagram clearer.

Figure 7B includes a cross-sectional view along sections A-A, B-B, and C-C of Figure 7A. As shown in sections B-B and C-C of Figure 7B, a dummy gate structure 705 is formed on the fin structure 345. As shown in section C-C of Figure 7B, portions of the gate dielectric layer 725 and the gate layer 710 are formed in recesses on the fin structure 345, and the recesses are formed by removing the hard mask layer 320.

As described above, Figures 7A and 7B are provided as examples. Other examples may differ from those described with reference to Figures 7A and 7B. Examples of embodiment 700 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described with reference to Figures 7A and 7B).

Figures 8A to 8D are examples of embodiment 800 of the source/drain recess formation process and the internal spacer formation process described herein. Examples of embodiment 800 include forming a source/drain recess and an internal spacer 245 for use in a semiconductor device 200. Figures 8A to 8D are shown as perspective views of Figure 7A, including cross-sectional views along section A-A, section B-B, and section C-C in Figure 7A. In some embodiments, the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, and 7A and 7B may be performed after the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, and 7A and 7B.

As shown in cross sections A-A and B-B of Figure 8A, source/drain recesses 805 are formed in portion 340 of the fin structure 345 during the etching step. The source/drain recesses 805 are formed to provide space on both sides of the dummy gate structure 705 after the source/drain regions 225 are formed. The etching tool 108 can perform the etching step, which can be considered a strain source/drain etching step. In some embodiments, the etching step includes plasma etching, wet chemical etching, and/or another etching technique.

The source/drain recess 805 also extends into a portion of the mesa region 210 of the fin structure 345. This can form multiple mesa regions 210 in each fin structure 345, with the sidewalls of the portion of the source/drain recess 805 below the portion 340 corresponding to the sidewalls of the mesa region 210. The source/drain recess 805 can penetrate wells (such as p-type or n-type wells) in the fin structure 345. In an embodiment where the semiconductor substrate 205 includes a (100) oriented silicon material, a (111) crystal plane can be formed at the bottom of the source/drain recess 805, resulting in a V-shaped or triangular bottom profile of the source/drain recess 805. In some embodiments, wet etching with tetramethylammonium hydroxide and/or chemical dry etching with hydrogen chloride can be used to form a V-shaped profile. However, the bottom profile of the source/drain recess 805 may include other shapes, such as circular, semi-circular, or other shapes.

As shown in cross sections B-B and C-C of Figure 8A, after the etching step that forms the source/drain recess 805, portions of the first layer 310 and the second layer 315 of the layered stack 305 can be retained beneath the dummy gate structure 705. The portion of the second layer 315 beneath the dummy gate structure 705 can form the nanostructure channel 220 of the nanostructure transistor of the semiconductor device 200. The nanostructure channel 220 extends between adjacent source/drain recesses 805 and adjacent mixed fin structures 620.

As shown in cross section B-B of Figure 8B, the first layer 310 can be etched laterally during the etching step (e.g., in a direction approximately parallel to the length of the first layer 310), thereby forming voids 810 between portions of the nanostructure channels 220. Specifically, the etching tool 108 can laterally etch the end of the first layer 310 beneath the dummy gate structure 705 via the source/drain recess 805 to form voids 810 between the ends of the nanostructure channels 220. In embodiments where the first layer 310 is silicon-germanium and the second layer 315 is silicon, the etching tool 108 may use a wet etching agent, such as a mixture containing hydrogen peroxide, acetic acid, and/or hydrofluoric acid, to selectively etch the first layer 310, followed by cleaning with water. The mixture and water may be provided to the source/drain recess 805 to etch the first layer 310 from the source/drain recess 805. In some embodiments, the steps of etching with the mixture and cleaning with water may be repeated approximately 10 to approximately 20 times. In some embodiments, the etching time with the mixture may be approximately 1 minute to approximately 2 minutes. The operating temperature of the mixture may be approximately 60°C to approximately 90°C. However, other values used for the parameters in the etching step also fall within the scope of embodiments of this invention.

The cavity 810 may be formed in an approximately arcuate, approximately concave, approximately triangular, approximately square, or other shape. In some embodiments, the depth of one or more cavities 810 (e.g., the dimension of the cavity extending from the source/drain recess 805 into the first layer 310) may be approximately 0.5 nm to approximately 5 nm. In some embodiments, the depth of one or more cavities 810 may be approximately 1 nm to approximately 3 nm. However, other values used for the depth of the cavity 810 are also within the scope of the embodiments of the present invention. In some embodiments, the length of the cavity 810 formed by the etching tool 108 (e.g., the dimension of the cavity extending from the nanostructure channel 220 under the first layer 310 to another nanostructure channel 220 on the first layer 310) allows the cavity 810 to partially extend into the side of the nanostructure channel 220 (e.g., the width or length of the cavity 810 is greater than the thickness of the first layer 310). In this manner, the inner spacers subsequently formed in the cavity 810 can extend into the end portion of the nanostructure channel 220. In some embodiments, forming the cavity 810 causes thinning of the covering sidewall 510 in the source/drain recess 805.

As shown in cross sections A-A and B-B of Figure 8C, an insulating layer 815 can be compliantly deposited along the sidewalls and bottom of the source/drain recess 805. The insulating layer 815 may further extend along the spacer layer 720. The deposition tool 102 may employ chemical vapor deposition, physical vapor deposition, atomic layer deposition, and/or another deposition technique to deposit the insulating layer 815. The insulating layer 815 includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxide carbon, silicon carbonitride, silicon carbonitride, and/or another dielectric material. The insulating layer 815 may be made of a different material than the spacer layer 720.

The thickness of the insulating layer 815 formed by the deposition tool 102 is sufficient to fill the voids 810 between the nanostructure channels 220. For example, the thickness of the insulating layer 815 can be approximately 1 nm to approximately 10 nm. In another example, the thickness of the insulating layer 815 can be approximately 2 nm to approximately 5 nm. However, other values used for the thickness of the insulating layer 815 are also within the scope of embodiments of the present invention.

As shown in cross sections A-A and B-B of Figure 8D, the insulation layer 815 can be partially removed, so that the remaining portion of the insulation layer 815 corresponds to the inner spacer 245 in the cavity 810. An etching tool 108 can perform an etching step to partially remove the insulation layer 815. As shown in cross section A-A of Figure 8D, the etching step can also remove the covering sidewall 510 from the source/drain recess 805 to partially remove the insulation layer 815.

In some embodiments, the etching process may create an arcuate or recessed surface on the inner spacer 245 facing the source/drain recess 805. The recess depth in the inner spacer 245 may be approximately 0.2 nm to approximately 3 nm. In another example, the recess depth in the inner spacer 245 may be approximately 0.5 nm to approximately 2 nm. In yet another example, the recess depth in the inner spacer 245 may be less than approximately 0.5 nm. In some embodiments, the surface of the inner spacer 245 facing the source/drain recess 805 is approximately flat, such that the surface of the inner spacer 245 is approximately flush with the end surface of the nanostructure channel 220.

As described above, Figures 8A to 8D are provided as examples. Other examples may differ from those described with reference to Figures 8A to 8D. Examples of embodiment 800 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described with reference to Figures 8A to 8D).

Figure 9 is an example of embodiment 900 of the source/drain region formation process described herein. The example of embodiment 900 includes forming source/drain regions 225 in source/drain recesses 805 for use in a semiconductor device 200. Figure 9 is shown as a perspective view of Figure 7A, including cross-sectional views along section A-A, B-B, and C-C of Figure 7A. In some embodiments, the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, 7A and 7B, and 8A to 8D may be performed after the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, 7A and 7B, and 8A to 8D.

As shown in cross sections A-A and B-B of Figure 9, one or more layers are filled into the source/drain recess 805 to form a source/drain region 225 within the source/drain recess 805. For example, a deposition tool 102 may deposit a buffer region 230 at the bottom of the source/drain recess 805, deposit the source/drain region 225 on the buffer region 230, and deposit a capping layer 235 on the source/drain region 225. The buffer region 230 may include silicon, boron-doped silicon, or another doped silicon, and/or another material. The buffer region 230 can reduce, minimize, and/or prevent the migration of dopants and/or leakage current from the source/drain region 225 to the adjacent mesa region 210, which could otherwise cause short-channel effects in the semiconductor device 200. In summary, the buffer region 230 can increase the performance and/or yield of the semiconductor device 200.

The source/drain region 225 may include one or more layers of epitaxial growth material. For example, the deposition tool 102 may epitaxially grow a first layer (referred to as L1) of the source/drain region 225 on the buffer region 230, and may epitaxially grow a second layer (referred to as L2, L2-1, and/or L2-2) of the source/drain region 225 on the first layer. The first layer may include lightly doped (e.g., doped with boron, phosphorus, and/or other dopants) silicon, and may serve as a masking layer to reduce short-channel effects in the semiconductor device 200 and reduce dopant crowding or migration into the nanostructure channels 220. The second layer may include heavily doped silicon or highly doped silicon-germanium. The second layer may provide compressive stress to the source/drain region 225 to reduce boron loss.

As described above, Figure 9 is provided as an example. Other examples may differ from the examples described with reference to Figure 9. Examples of embodiment 900 may include additional steps, fewer steps, different steps, and/or steps in a different order (compared to the steps described with reference to Figure 9).

Figures 10A to 10H are examples of embodiment 1000 of the interface layer formation process described herein. Examples of embodiment 1000 include examples of the formation process of the interface layer 1010a and the high dielectric constant layer 1010b of the semiconductor device 200. Figures 10A to 10H are shown as perspective views of Figure 7A, including cross-sectional views along section A-A, section B-B, and section C-C in Figure 7A. In some embodiments, the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, 7A and 7B, 8A to 8D, and 9 can be performed afterward.

As shown in cross sections A-A and B-B of Figure 10A, a dielectric layer 250 is formed on the source/drain region 225. The dielectric layer 250 fills the areas between the dummy gate structures 705, between the mixed fin structures 620, and above the source/drain region 225. The dielectric layer 250 can reduce and/or avoid damage to the source/drain region 225 during the interface layer formation process. The dielectric layer 250 can be considered as a zeroth interlayer dielectric layer or another interlayer dielectric layer.

In some embodiments, a contact etch stop layer may be compliantly deposited (e.g., using deposition tool 102) on the source/drain region 225, the dummy gate structure 705, and the spacer layer 720 before the dielectric layer 250 is formed. The dielectric layer 250 is then formed on the contact etch stop layer. The contact etch stop layer provides a mechanism to stop the etch process when forming the contacts or vias used in the source/drain region 225. The contact etch stop layer may be composed of a dielectric material with etch selectivity different from that of adjacent layers or components. The contact etch stop layer may include or may be a nitrogen-containing material, a silicon-containing material, and/or a carbon-containing material. Furthermore, the contact etch stop layer may include or may be silicon nitride, silicon carbonitride, carbon nitride, silicon oxynitride, silicon oxycarbide, combinations thereof, or other materials. The deposition method for the contact etch stop layer may employ deposition techniques such as atomic layer deposition, chemical vapor deposition, or another deposition technique.

As shown in cross sections B-B and C-C of Figure 10B, the dummy gate structure 705 is removed from the semiconductor device 200 by one or more semiconductor process tools, such as deposition tool 102 to plating tool 112. Removing the dummy gate structure 705 will leave an opening 1005 (or a recess) between the dielectric layer 250 on the source/drain regions 225 and between the mixed fin structure 620. The dummy gate structure 705 can be removed by one or more etching steps. This etching step may include plasma etching, wet chemical etching, and/or another etching technique.

As shown in cross sections B-B and C-C of Figure 10C, a nanostructure release step (such as a silicon-germanium release step) is performed to remove the first layer 310 (such as a silicon-germanium layer). This will form an opening 1005 between the nanostructure channels 220 (such as the region surrounding the nanostructure channels 220). The nanostructure release step may include an etching step with an etching tool 108, which removes the first layer 310 based on the etching selectivity difference between the material of the first layer 310 and the material of the nanostructure channels 220 (and the etching selectivity difference between the material of the first layer 310 and the material of the inner spacer 245). The inner spacer 245 can serve as an etch stop layer during the etching process to protect the source/drain regions 225 from etching. As shown in Figure 10C, the nanostructure release step removes the cover sidewall 510. This exposes the area surrounding the nanostructure channel 220, allowing the interface layer 1010a and the high-dielectric-constant layer 1010b to be formed around the entire periphery of the nanostructure channel 220.

As shown in cross section B-B of Figure 10D, interface layer 1010a is formed on nanostructure channel 220, inner spacer 245, and spacer layer 720. Furthermore, interface layer 1010a may be additionally deposited on dielectric layer 250. In an embodiment where capping layer 235 extends around the sidewalls of dielectric layer 250, interface layer 1010a may be additionally deposited on capping layer 235. In other words, because the method of forming interface layer 1010a employs anti-selective deposition, interface layer 1010a can be formed on all exposed surfaces of semiconductor device 200 after removal of dummy gate structure 705 and first layer 310. The method for forming interface layer 1010a is explained below with reference to Figures 10E to 10G.

As shown in Figure 10E, the initial fabrication process for forming amorphous silicon 1015a and crystalline silicon 1015b is similar to that used for forming interface layer 1010a. Figure 10E shows regions 200A, 200B, and 200C in cross-section B-B. Specifically, amorphous silicon 1015a can be formed on spacer layer 720 and inner spacer 245, while crystalline silicon 1015b can be formed on nanostructure channel 220. Different chemical reactions, as illustrated in conjunction with Figure 10F, can result in amorphous silicon 1015a forming on spacer layer 720 and inner spacer 245, and crystalline silicon 1015b forming on nanostructure channel 220. The thickness of amorphous silicon 1015a can be approximately 4.0 Å to approximately 6.0 Å. Choosing a thickness of at least 4.0 Å results in an interface layer 1010a with a thickness of at least 0.5 nm, while a thinner interface layer of amorphous silicon could cause leakage current in the nanostructure channel 220 (to the inner spacer 245). Choosing a thickness of no more than 6.0 Å results in an interface layer 1010a with a thickness of no more than 1.0 nm, while a thicker layer of amorphous silicon could reduce the volume of the gate structure 240, thus reducing its efficiency. The thickness of the crystalline silicon 1015b can be similarly approximately 4.0 Å to approximately 6.0 Å. In this way, the interface layer 1010a has a more uniform thickness (e.g., within an error range of less than or equal to 5.0 Å).

The chemical reactions for forming amorphous silicon 1015a and crystalline silicon 1015b are shown in Figure 10F. First, prior to forming amorphous silicon 1015a and crystalline silicon 1015b, the nanostructure channels 220 can be cleaned using a chemical oxide removal step (e.g., by cleaning with one or more semiconductor process tools such as deposition tool 102 to plating tool 112). The chemical oxide removal step removes silicon oxide from the exposed surface of the nanostructure channels 220. In one example, hydrogen fluoride and ammonia can react with silicon oxide to form water and salts such as ammonium fluorosilicate, as shown in the following chemical reaction: _SiO₂ + 4HF _SiF₄ + _2H₂O , and _SiF₄ + 2HF + _2NH₃ ( _NH4 ) _{2SiF6 .}

Evaporable salts (e.g. _, annealed by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) react as shown in the following chemical reaction: ( _NH4 ) _{2SiF6 SiF₄} + 2HF + _2NH₃

In this way, silicon oxide can be removed from the exposed surface of the nanostructure channel 220. However, the hydroxyl group can remain on the surface of the inner spacer 245 and the spacer layer 720. A precursor can be delivered (e.g., by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) to initiate the growth of silicon on the nanostructure channel 220, the inner spacer 245, and the spacer layer 720. The precursor may have the following structure: Silicon alkylates (nitrogen bonded to the precursor) can be deposited on the exposed surfaces of the nanostructure channel 220 and can be replaced by free hydrogen retained on the exposed surfaces (or by otherwise transporting the carrier gas and the precursor). Similarly, silicon alkylates can be deposited on the exposed surfaces of the inner spacer 245 and the spacer layer 720 and can be replaced by hydroxyl hydrogen retained on the exposed surfaces. Thus, silicon alkylates can be formed on the nanostructure channel 220, while seed layers 1015a' (e.g., containing silanol groups) are formed on the inner spacer 245 and the spacer layer 720.

In the precursor structure, the groups _R1 , _R2 , _R3 , or _R4 do not react with the silicon of the nanostructure channel 220 or the hydroxyl groups of the inner spacer 245 and spacer layer 720. For example, at least one _R1 , _R2 , _R3 , or _R4 may comprise a methyl group. In fact, two or more _R1 , _R2 , _R3 , or _R4 may comprise methyl groups. In one example, the precursor may comprise diisopropylaminosilane.

The temperature at which the precursor is introduced can be approximately 200°C to approximately 300°C. Choosing a temperature of at least 200°C allows the precursor to react with the nanostructure channel 220, the inner spacer 245, and the spacer layer 720. However, temperatures that are too low may inhibit the formation of silanes on the nanostructure channel 220 and inhibit the formation of the seed layer 1015a' on the inner spacer 245 and the spacer layer 720. Choosing a temperature no higher than 300°C is beneficial for the reaction between the precursor and the hydroxyl groups of the inner spacer 245 and the spacer layer 720, thereby improving the adhesion of the seed layer 1015a'.

As shown in Figure 10F, methane and/or ethane (e.g., conveyed by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) can be delivered to form amorphous silicon 1015a on the inner spacer 245 and spacer layer 720 to replace the seed layer 1015a'. Additionally, methane and/or ethane can be delivered to grow crystalline silicon 1015b on the nanostructure channel 220.

Semiconductor device 200 can be located in a chamber with a pressure less than 3 Torr to deposit silicon. Choosing a pressure less than 3 Torr reduces impurities in amorphous silicon 1015a and crystalline silicon 1015b, while too high a pressure may increase contamination in the chamber and inhibit the formation of amorphous silicon 1015a and crystalline silicon 1015b. The temperature at which methane and/or ethylene is transported can be approximately 300°C to approximately 500°C. Choosing a temperature of at least 300°C allows methane and/or ethylene to react with the nanostructure channels 220, the inner spacers 245, and the spacer layer 720, while too low a temperature may inhibit silicon deposition. Choosing a temperature no higher than 500°C can improve the thickness control of deposited silicon, while too high a temperature may result in an excessively thick interface layer, which may reduce the volume of the gate structure 240 and thus reduce the efficiency of the gate structure 240.

In some embodiments, the deposition time for forming amorphous silicon 1015a and crystalline silicon 1015b is proportional to the temperature of methane and/or ethylene silane. For example, the deposition time using methane at a temperature close to 500°C is approximately 15 minutes compared to using methane at a temperature close to 400°C. In another example, the deposition time using ethylene silane at a temperature close to 400°C is approximately 20 minutes compared to using ethylene silane at a temperature close to 300°C. The selection of deposition time and/or temperature can be achieved using machine learning models. Machine learning models may include and/or may be related to one or more of the following: regression models, random forest models, cluster models, neural networks, and/or other models. In some embodiments, the machine learning model accepts candidate temperatures and/or deposition times as input, and the machine learning model can determine the likelihood, probability, or confidence of the specific output (such as the target thickness of amorphous silicon 1015a and crystalline silicon 1015b) achievable by using the candidate parameters. In some embodiments, the machine learning model accepts a target thickness as input, and the machine learning model can identify or recognize the specific combination of temperature and/or deposition time to achieve the target thickness.

Machine learning models can be trained, updated, and/or optimized to increase the accuracy of the results and/or parameters validated by the machine learning model. For example, machine learning models can be trained, updated, and/or optimized based on feedback and/or results from subsequent silicon deposition steps and historical or related silicon deposition steps (e.g., from hundreds, thousands, or more historical or related silicon deposition steps).

Therefore, the thickness of each of the amorphous silicon 1015a and crystalline silicon 1015b can be approximately 4.0 Å to approximately 6.0 Å, as described above. The thickness of the amorphous silicon 1015a and/or crystalline silicon 1015b can be increased (e.g., up to approximately 9.0 Å). Thus, a cycle of oxidation and finishing can be performed on the semiconductor device 200. In other words, a portion of the amorphous silicon 1015a and/or crystalline silicon 1015b can be oxidized (e.g., by applying oxygen and/or another oxygen-dominant molecule), followed by partial etching of the oxidized portion (e.g., using dry etching and/or wet etching). Since the thicker layers of amorphous silicon 1015a and crystalline silicon 1015b can undergo more oxidation, the same thicker layers can be etched. In this way, amorphous silicon 1015a and crystalline silicon 1015b will eventually have a more consistent thickness (for example, within an error range of less than or equal to 3.0 Å).

As shown in Figure 10G, an interface layer 1010a is formed from amorphous silicon 1015a and crystalline silicon 1015b. Figure 10G shows regions 200A, 200B, and 200C in cross-section B-B. Specifically, amorphous silicon 1015a and crystalline silicon 1015b are oxidized (e.g., by one or more semiconductor process tools such as deposition tool 102 to plating tool 112) to form the interface layer 1010a. The thickness of the interface layer 1010a can be approximately 0.5 nm to approximately 1.0 nm, as described above. Furthermore, the ratio of the thickness of the inner spacer 245 to the thickness of the interface layer 1010a can be approximately 4.0 to approximately 8.0. Choosing a thickness ratio of at least 4.0 ensures that the thickness of the inner spacer 245 is sufficient to isolate the gate structure 240 from the source/drain region 225, while a thickness ratio that is too small may increase the leakage current of the gate structure 240. Choosing a thickness ratio of no more than 8.0 ensures that the thickness of the interface layer 1010a is sufficient to isolate the gate structure 240 from the nanostructure channel 220, while a thickness ratio that is too large may increase the leakage current of the nanostructure channel 220. In one example, the thickness of the inner spacer 245 is approximately 3.5 nm to approximately 4.5 nm. Similarly, the ratio of the thickness of the spacer layer 720 to the thickness of the interface layer 1010a is approximately 4.0 to approximately 8.0. In one example, the thickness of the spacer layer 720 is approximately 3.5 nm to approximately 4.5 nm.

As shown in Figure 10H, the interface layer 1010a is located at the interface between the inner spacer 245 and the nanostructure channel 220. As shown in Figure 10H, the barrier layer 1020 can suppress electron tunneling from the nanostructure channel 220 to the inner spacer 245. For example, the barrier layer 1020 can be formed before the formation of the inner spacer 245, as illustrated in Figures 8C and 8D. Specifically, the barrier layer 1020 can be an oxygen-rich layer. Here, "oxygen-rich" can refer to a chemical composition in which oxygen atoms outnumber nitrogen atoms (e.g., unlike nitrogen-rich layers such as the inner spacer 245). As shown in Figure 10H, due to the non-selective formation of the interface layer 1010a, the interface layer 1010a contacts the inner spacer 245, the nanostructure channel 220, and the interface between the inner spacer 245 and the nanostructure channel 220 (as shown in the corner of Figure 10H). In this way, the interface layer 1010a reduces the leakage current from the nanostructure channel 220 to the inner spacer 245 at the corner. For example, the interface layer 1010a can increase the critical voltage associated with the leakage current between the nanostructure channel 220 and the inner spacer 245. Thus, compared to a semiconductor device without an interface layer formed from the fresh silicon cap fabrication process, the semiconductor device 200 can operate at high voltages.

The above steps (such as chemical oxide removal, formation of seed layer 1015a', formation of amorphous silicon 1015a and crystalline silicon 1015b, and oxidation) can be performed in situ. Furthermore, a high dielectric constant layer 1010b is formed on the interface layer 1010a. The high dielectric constant layer 1010b can also be formed in situ (or separately).

As described above, the number and configuration of the devices and steps shown in Figures 10A to 10H are provided as one or more examples. In practice, additional steps and devices, fewer steps and devices, different steps and devices, or steps and devices with different configurations may be used (compared to the steps and devices described in conjunction with Figures 10A to 10H).

Figure 11 is a diagram illustrating an embodiment 1100 of a gate replacement process. Examples of embodiment 1100 include examples of a gate replacement process used to form a gate structure 240 (such as a gate replacement structure) of a semiconductor device 200. Figure 11 is shown as a perspective view of Figure 7A, including a cross-sectional view along section A-A, a cross-sectional view along section B-B, and a cross-sectional view along section C-C in Figure 7A. In some embodiments, the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, 7A and 7B, 8A to 8D, 9, and 10A to 10H may be performed after the steps described in conjunction with Figures 3A and 3B, 4A and 4B, 5A to 5C, 6A to 6C, 7A and 7B, 8A to 8D, 9, and 10A to 10H.

As shown in cross sections B-B and C-C of Figure 11, a continuous gate replacement step is performed, wherein the deposition tool 102 and/or plating tool 112 can form a gate structure 240 (such as a replacement gate structure) between the opening 1005 between the source/drain regions 225 and the mixed fin structure 620. Specifically, the gate structure 240 fills the area between and around the nanostructure channels 220 (previously occupied by the first layer 310 and the covering sidewalls 510), thus completely enclosing and surrounding the nanostructure channels 220. The gate structure 240 may include a metallic gate structure. A barrier layer 1010, comprising an interface layer 1010a and a high dielectric constant layer 1010b as illustrated in Figures 10D to 10H, may be formed between the nanostructure channel 220 and the gate structure 240. The gate structure 240 may include additional layers such as a work function adjustment layer, a metal electrode structure, and/or other layers.

As described above, the number and configuration of the structure and steps shown in Figure 11 are provided as one or more examples. In practice, additional steps and structures, fewer steps and structures, different steps and structures, or different configurations of steps and structures (compared to the steps and structures described with reference to Figure 11) may be used.

Figure 12 is a schematic diagram of the components of the device 1200 described herein in one example. In some embodiments, one or more semiconductor process tools, such as deposition tools 102 to plating tools 112 and/or wafer/die transport tools 114, may include one or more devices 1200 and/or one or more components of device 1200. As shown in Figure 12, device 1200 may include bus 1210, processor 1220, memory 1230, input components 1240, output components 1250, and/or communication components 1260.

Bus 1210 includes one or more components that enable wired and/or wireless communication of components of device 1200. Bus 1210 can couple two or more components of FIG. 12 together, for example via operative coupling, communication coupling, electronic coupling, and/or electrical coupling. Processor 1220 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, special-purpose integrated circuit, and/or other processing components. Processor 1220 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1220 may include one or more processors that are programmable to perform one or more steps or processes described elsewhere.

Memory 1230 may include volatile and/or non-volatile memory. For example, memory 1230 may include random access memory, read-only memory, a hard disk, and/or another type of memory (such as flash memory, magnetic memory, and/or optical memory). Memory 1230 may include internal memory (such as dynamic random access memory, read-only memory, or a hard disk) and/or removable memory (such as memory moved via a Universal Serial Bus connection). Memory 1230 may be a non-transitory computer-readable medium. Memory 1230 may store data, instructions, and/or software (such as one or more software applications) related to the operation of device 1200. In some embodiments, memory 1230 includes one or more memory units coupled to one or more processors (such as processor 1220) via bus 1210.

Input component 1240 enables device 1200 to receive input, such as user input and/or sensed input. For example, input component 1240 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, accelerometer, gyroscope, and/or actuator. Output component 1250 enables device 1200 to provide output, such as via a screen, speaker, and/or light-emitting diode. Communication component 1260 enables device 1200 to communicate with other devices via wired and/or wireless connections. For example, communication component 1260 may include a receiver, transmitter, transceiver, modem, network interface card, and/or antenna.

Device 1200 may perform one or more steps or processes described herein. For example, a non-transient computer-readable medium (such as memory 1230) may store a set of instructions (such as one or more instructions or codes) executed by processor 1220. Processor 1220 may execute a set of instructions to perform one or more steps or processes described herein. In some embodiments, one or more processors 1220 execute a set of instructions, causing one or more processors 1220 and/or device 1200 to perform one or more steps or processes described herein. In some embodiments, hardware circuitry may replace or be combined with instructions to perform one or more steps or processes described herein. The processor 1220 may be additionally or alternatively configured to perform one or more steps or processes described herein. Therefore, the implementation methods described herein are not limited to any particular combination of hardware and software.

The number and configuration of components shown in Figure 12 are merely illustrative. Device 1200 may include additional components, fewer components, different components, or different configurations of components (compared to the components illustrated in Figure 12). One or more functions performed by another set of components of device 1200 may be performed additionally or alternatively by one set of components of device 1200 (e.g., one or more components).

Figure 13 is a flowchart of the relevant process 1300 for forming the interface layer in one example. In some embodiments, one or more process steps of Figure 13 may be performed by one or more semiconductor process tools (such as one or more semiconductor process tools such as deposition tools 102 to plating tools 112). One or more process steps of Figure 13 may additionally or alternatively be performed by one or more components of device 1200 (such as processor 1220, memory 1230, input components 1240, output components 1250, and/or communication components 1260).

As shown in Figure 13, process 1300 may include growing a seed layer on the spacer (step 1310). For example, one or more semiconductor process tools, such as deposition tools 102 to plating tools 112, may be used to grow a seed layer 1015a' on the inner spacer 245 or the spacer layer 720, as described herein.

As shown in Figure 13, process 1300 may include depositing silicon on a seed layer to form amorphous silicon and depositing silicon on channels to form crystalline silicon (step 1320). For example, one or more semiconductor process tools such as deposition tools 102 to plating tools 112 may be used to deposit silicon on seed layer 1015a' to form amorphous silicon layer 1015a and deposit silicon on nanostructure channel 220 to form crystalline silicon 1015b, as described herein.

As shown in Figure 13, process 1300 may include oxidizing amorphous silicon and crystalline silicon to form an interface layer (step 1330). For example, one or more semiconductor process tools, such as deposition tools 102 to plating tools 112, may be used to oxidize amorphous silicon 1015a and crystalline silicon 1015b to form interface layer 1010a, as described herein.

As shown in Figure 13, process 1300 may include forming a high dielectric constant layer on the interface layer (step 1340). For example, one or more semiconductor process tools, such as deposition tool 102 to plating tool 112, may be used to form a high dielectric constant layer 1010b on the interface layer 1010a, as described herein.

Process 1300 may include additional embodiments, such as any single embodiment described below, or any combination of the embodiments described below and/or other processes described elsewhere.

In the first embodiment, the step of growing the seed layer 1015a' includes using a precursor to form the seed layer, and the seed layer includes diisopropylaminosilane.

In the second embodiment (which can be carried out alone or in combination with the first embodiment), the temperature for growing the seed layer 1015a' can be approximately 200°C to approximately 300°C.

In the third embodiment (which may be carried out alone or in combination with one or more of the first and second embodiments), silicon deposition includes using methane or ethane to deposit silicon.

In the fourth embodiment (which may be carried out alone or in combination with one or more of the first to third embodiments), the temperature for silicon deposition may be approximately 300°C to approximately 500°C.

In the fifth embodiment (which can be carried out alone or in combination with one or more of the first to fourth embodiments), the process pressure for silicon deposition can be less than 3.0 Torr.

In the sixth embodiment (which may be performed alone or in combination with one or more of the first to fifth embodiments), process 1300 includes a chemical oxide removal step to clean the nanostructure channel 220 before depositing silicon onto the nanostructure channel 220.

In the seventh embodiment (which may be carried out alone or in combination with one or more of the first to sixth embodiments), the thickness of the crystalline silicon 1015b is approximately 4.0 Å to approximately 6.0 Å.

In the eighth embodiment (which may be carried out alone or in combination with one or more of the first to seventh embodiments), the thickness of the amorphous silicon 1015a is approximately 4.0 Å to approximately 6.0 Å.

Although Figure 13 shows an example of the steps of process 1300, process 1300 in some embodiments may include additional steps, fewer steps, different steps, or configured steps (compared to the steps illustrated with reference to Figure 13). Two or more steps of process 1300 may be performed in parallel, either additionally or alternatively.

In this approach, a fresh silicon capping process is used to form the interface layer. For example, using diisopropylaminosilane as a precursor, amorphous silicon can be formed on the spacers and crystalline silicon on the channels. The amorphous and crystalline silicon can be oxidized to form the interface layer, which has a more uniform thickness, ranging from approximately 0.5 nm to approximately 1.0 nm. This improves miniaturization and gate efficiency, and reduces leakage current outside the channels.

As detailed above, some embodiments described herein provide methods for forming semiconductor structures. The methods include growing a seed layer on a spacer. The methods include depositing silicon on the seed layer to form amorphous silicon and depositing silicon on the channel to form crystalline silicon. The methods include oxidizing amorphous silicon and crystalline silicon to form an interface layer. The methods include forming a high-dielectric-constant layer on the interface layer.

In some embodiments, the step of growing a seed layer includes forming a seed layer using a precursor, wherein the precursor includes diisopropylaminosilane.

In some embodiments, the temperature at which the seed layer grows is approximately 200°C to approximately 300°C.

In some embodiments, the silicon deposition step includes using at least one of methane and ethane to deposit silicon.

In some embodiments, the temperature at which silicon is deposited is approximately 300°C to approximately 500°C.

In some embodiments, the pressure of deposited silicon is less than 3.0 Torr.

In some embodiments, the above method further includes a chemical oxide removal step to clean the channel before silicon is deposited on it.

In some embodiments, the thickness of the crystalline silicon is approximately 4.0 Å to approximately 6.0 Å.

In some embodiments, the thickness of the amorphous silicon is approximately 4.0 Å to approximately 6.0 Å.

As detailed above, some embodiments described herein provide methods for forming semiconductor structures. The methods include growing a seed layer on a spacer. The methods include depositing silicon on the seed layer to form amorphous silicon and depositing silicon on the channel to form crystalline silicon. The methods include performing multiple cycles to achieve thicknesses of approximately 4.0 Å to approximately 6.0 Å for both the crystalline and amorphous silicon, wherein each cycle includes an oxidation process and a trimming process. The methods include oxidizing the amorphous and crystalline silicon to form an interface layer.

In some embodiments, the step of growing a seed layer includes using a precursor to form a seed layer, wherein the precursor includes diisopropylaminosilane.

In some embodiments, the silicon deposition process includes using at least one of methane and ethane to deposit silicon.

In some embodiments, the finishing process includes a selective etching process for silicon oxide.

As detailed above, some embodiments described herein provide semiconductor structures. The semiconductor structure includes nanostructure channels formed between multiple source/drain regions. The semiconductor structure includes gate structures formed around the nanostructure channels. The semiconductor structure includes spacers located between an interlayer dielectric layer and the gate structures. The semiconductor structure includes an interface layer contacting the nanostructure channels and the spacers, the interface layer comprising silicon oxide, and the thickness of the interface layer being approximately 0.5 nm to approximately 1.0 nm.

In some embodiments, the semiconductor structure further includes an inner spacer located between the source/drain region and the gate structure, wherein the interface layer further contacts the inner spacer.

In some embodiments, the interface layer increases the critical voltage associated with the leakage current between the nanostructure channels and the inner spacers.

In some embodiments, the semiconductor structure further includes an oxygen-rich layer located at the interface between the nanostructure channels and the internal spacers.

In some embodiments, the ratio of the thickness of the inner spacer to the thickness of the interface layer is approximately 4.0 to approximately 8.0.

In some embodiments, the interface layer is in contact with the interface between the nanostructure channel and the spacer.

In some embodiments, the ratio of the thickness of the spacer to the thickness of the interface layer is approximately 4.0 nm to approximately 8.0 nm.

The term "meets critical value" as used here may, depending on the context, mean greater than, greater than or equal to, less than, less than or equal to, equal to, not equal to, or similar definition.

The features of the above embodiments are conducive to the understanding of the invention by those skilled in the art. Those skilled in the art should understand that the invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and/or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the invention, and can be modified, substituted, or altered without departing from the spirit and scope of the invention.

A-A, B-B, C-C: Cross-section 100: Environment 102: Deposition tool 104: Exposure tool 106: Development tool 108: Etching tool 110: Planarization tool 112: Plating tool 114: Wafer and/or die transport tool 200: Semiconductor device 200A, 200B, 200C: Area 205: Semiconductor substrate 210: Mesa area 215: Shallow trench isolation area 220: Nanostructure channel 225: Source/drain area 230: Buffer area 235, 325: Cap layer 240: Gate structure 245: Inner spacer 250, 410, 610: Dielectric layer 300, 400, 500, 600, 700, 800, 900, 1000, 1100: Embodiment 305: Layered stacking 310: First layer 315: Second layer 320, 715: Hard masking layer 330: Oxide layer 335: Nitride layer 340: Partial 345: Fin-like structure 345a: First group of fin-like structures 345b: Second group of fin-like structures 405, 605: Padding 505: Coating 510: Covering sidewalls 615, 1010b: High dielectric constant layer 620: Mixed fin structure 705: Virtual gate structure 710: Gate layer 720: Spacer layer 725: Gate dielectric layer 805: Source/drain recess 810: Void 815: Insulation layer 1005: Opening 1010, 1020: Barrier layer 1010a: Interface layer 1015a: Amorphous silicon 1015a': Seed layer 1015b: Crystalline silicon 1200: Device 1210: Bus 1220: Processor 1230: Memory 1240: Input Components 1250: Output Components 1260: Communication Components 1300: Manufacturing Process 1310, 1320, 1330, 1340: Steps

Figure 1 is a diagram illustrating an environment in which the systems and/or methods described herein may be implemented. Figure 2 is a diagram illustrating a semiconductor device described herein. Figures 3A and 3B are diagrams illustrating a fin formation process described herein. Figures 4A and 4B are diagrams illustrating a shallow trench isolation process described herein. Figures 5A to 5C are diagrams illustrating a sidewall covering formation process described herein. Figures 6A to 6C are diagrams illustrating a mixed fin structure formation process described herein. Figures 7A and 7B are diagrams illustrating a dummy gate structure formation process described herein. Figures 8A to 8D are diagrams illustrating, in one example, the source/drain recess formation process and the internal spacer formation process described herein. Figure 9 is a diagram illustrating, in one example, the source/drain region formation process described herein. Figures 10A to 10H are diagrams illustrating, in one example, the interface layer formation process described herein. Figure 11 is a diagram illustrating, in one example, the gate replacement process described herein. Figure 12 is a diagram illustrating, in one example, the components of one or more devices described herein. Figure 13 is a flowchart illustrating, in one example, the related processes for forming the semiconductor device described herein.

B-B: Section

200A, 200B, 200C: Areas

220: Nanostructured Channels

225: Source/Drawing Area

235: Cover Layer

245: Inner partition

720: Spacer layer

1000: Implementation Methods

1010a: Interface Layer

Claims (20)

A method for forming a semiconductor structure includes: growing a seed layer on a spacer; depositing silicon on the seed layer to form amorphous silicon, and depositing silicon on a channel to form crystalline silicon; oxidizing the amorphous silicon and the crystalline silicon to form an interface layer; and forming a high-dielectric-constant layer on the interface layer. The method for forming a semiconductor structure as described in claim 1, wherein the step of growing the seed layer includes forming the seed layer using a precursor, wherein the precursor includes diisopropylaminosilane. The method for forming a semiconductor structure as described in claim 1, wherein the temperature at which the seed layer is grown is approximately 200°C to approximately 300°C. The method for forming a semiconductor structure as described in claim 1, wherein the silicon deposition step comprises: depositing silicon using at least one of methane and ethane. The method for forming a semiconductor structure as described in claim 1, wherein the temperature for silicon deposition is approximately 300°C to approximately 500°C. A method for forming a semiconductor structure as described in claim 1, wherein the pressure for depositing silicon is less than 3.0 Torr. The method for forming a semiconductor structure as described in claim 1 further includes: performing a chemical oxide removal step to clean the channel before depositing silicon on it. The method for forming a semiconductor structure as described in claim 1, wherein the thickness of the crystalline silicon is approximately 4.0 Å to approximately 6.0 Å. The method for forming a semiconductor structure as described in claim 1, wherein the thickness of the amorphous silicon is approximately 4.0 Å to approximately 6.0 Å. A method for forming a semiconductor structure includes: growing a seed layer on a spacer; depositing silicon on the seed layer to form amorphous silicon, and depositing silicon on a channel to form crystalline silicon; performing multiple cycles such that the thickness of the crystalline silicon and the amorphous silicon are each approximately 4.0 Å to approximately 6.0 Å, wherein each of the cycles includes an oxidation process and a trimming process; and oxidizing the amorphous silicon and the crystalline silicon to form an interface layer. The method for forming a semiconductor structure as described in claim 10, wherein the step of growing the seed layer includes: using a precursor to form the seed layer, wherein the precursor comprises diisopropylaminosilane. The method for forming a semiconductor structure as described in claim 10, wherein the silicon deposition step comprises: depositing silicon using at least one of methane and ethane. A method for forming a semiconductor structure as described in claim 10, wherein the finishing process includes a selective etching process for silicon oxide. A semiconductor structure comprising: a nanostructure channel formed between multiple source/drain regions; a gate structure formed around the nanostructure channel; a spacer located between an interlayer dielectric layer and the gate structure; and an interface layer contacting the nanostructure channel and the spacer, the interface layer comprising silicon oxide and having a thickness of approximately 0.5 nm to approximately 1.0 nm. The semiconductor structure as described in claim 14 further includes: an inner spacer located between the source/drain regions and the gate structure, wherein the interface layer further contacts the inner spacer. The semiconductor structure as described in claim 15, wherein the interface layer increases the critical voltage associated with leakage current between the nanostructure channel and the inner spacer. The semiconductor structure as described in claim 15 further includes: an oxygen-rich layer located at the interface between the nanostructure channel and the inner spacer. The semiconductor structure as described in claim 15, wherein the ratio of the thickness of the inner spacer to the thickness of the interface layer is approximately 4.0 to approximately 8.0. The semiconductor structure as described in claim 14, wherein the interface layer further contacts the interface between the nanostructure channel and the spacer. The semiconductor structure as described in claim 14, wherein the ratio of the thickness of the spacer to the thickness of the interface layer is approximately 4.0 nm to approximately 8.0 nm.