TW202526608A - Data reading method for chip, chip, computer equipment and computer-readable storage medium - Google Patents

Abstract

The embodiment of the disclosure discloses a data reading method for a chip, a chip, computer equipment and a computer-readable storage medium, wherein the method comprises: acquiring a data reading instruction; the data reading instruction is used to instruct data reading according to the reading information and data prefetching according to the prefetching information; acquiring a first data reading request according to a data reading instruction; the first data reading request includes reading information and prefetching information; sending a first data reading request to a cache module, so that the cache module responds to the first data reading request, reads and returns the first target data according to the reading information, and prefetches and caches the second target data according to the prefetching information; receiving the first target data returned by the cache module. According to the embodiment of the present disclosure, the data request pressure between the request source and the cache module can be reduced, the request bandwidth can be compressed, the processor performance can be improved, and the prefetch mode can be flexibly controlled task by task to better meet the data reading requirements of each task.

Description

Data reading method for chip, chip, computer device and computer-readable storage medium

[Related Application]

This invention is based on and claims priority from Chinese patent application No. 202311809260.9, filed on December 26, 2023, and entitled “Data reading method for chip, chip, computer device, and storage medium,” the entire contents of which are incorporated herein by reference.

The present invention relates to, but is not limited to, the field of computer technology, and more particularly to a data reading method for a chip, a chip, a computer device, and a computer-readable storage medium.

Processors typically include a cache module to adapt data read and write speeds to the computational speed of the processor's compute modules, improving system performance. In related technologies, processors often employ data prefetching techniques. This predicts future memory accesses and issues access requests for corresponding memory blocks before explicit accesses occur. This allows data from the memory blocks to be pre-fetched into the cache module, thereby improving cache hit rates. However, these data prefetching schemes increase the data request pressure between the request source and the cache module, impacting other normal memory access requests. Furthermore, some data prefetching schemes in related technologies make it difficult to flexibly control prefetching.

In view of this, embodiments of the present invention at least provide a data reading method for a chip, a chip, a computer device, and a computer-readable storage medium.

The technical solution of an embodiment of the present invention is implemented as follows: This embodiment of the present invention provides a data reading method for a chip, comprising: obtaining a read instruction; the read instruction is used to instruct data reading according to read information and data prefetching according to prefetch information; obtaining a first read request based on the read instruction; the first read request includes the read information and the prefetch information; sending the first read request to a cache module, so that the cache module responds to the first read request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; receiving the first target data returned by the cache module.

An embodiment of the present invention provides a data reading method for a chip, comprising: Receiving a first read data request sent by a request source, the first read data request being used to request data reading according to read information and data prefetching according to prefetch information; According to the first read data request, obtaining the read information and prefetch information; Based on the read information, reading first target data from storage space and/or memory of a cache module and returning the first target data to the request source; Based on the prefetch information, prefetching second target data from the memory and caching the second target data into at least one cache unit of the cache module.

An embodiment of the present invention provides a chip comprising: a computing module configured to: obtain a read instruction; the read instruction is configured to instruct data reading according to read information and data prefetching according to prefetch information; obtain a first read request based on the read instruction; the first read request includes the read information and the prefetch information; send the first read request to a cache module, causing the cache module to respond to the first read request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; and receive the first target data returned by the cache module; The cache module is configured to: receive a first read data request sent by the computing module, the first read data request being used to request data reading according to read information and data prefetching according to prefetch information; obtain the read information and prefetch information based on the first read data request; read first target data from the storage space and/or memory of the cache module based on the read information, and return the first target data to the computing module; and prefetch second target data from the memory based on the prefetch information, and cache the second target data into at least one cache unit of the cache module.

An embodiment of the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, it implements part or all of the steps in the above method, or the processor includes the above chip.

An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, some or all of the steps in the above method are implemented.

In an embodiment of the present invention, a read data instruction is obtained, the read data instruction being used to instruct data reading according to read information and data prefetching according to prefetch information; a first read data request is obtained according to the read data instruction, the first read data request including the read information and the prefetch information; the first read data request is sent to a cache module, so that the cache module responds to the first read data request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; and the first target data returned by the cache module is received. In this way, the request source of a read request can send prefetch information along with the read request to the cache module. Therefore, data can be read and prefetched through a single read request. This can reduce the data request pressure between the request source and the cache module, compress the request bandwidth, and improve processor performance. On the other hand, the prefetch information contained in the read request can be used to control data prefetching, thereby facilitating flexible control of the prefetching method on a task-by-task basis to better meet the data reading needs of each task.

It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the technical solutions of the present invention.

In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present invention. All other embodiments obtained by ordinary technical personnel in this field without making creative efforts are within the scope of protection of the present invention.

In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first/second/third" are used solely to distinguish similar items and do not represent a specific ordering of the items. It is understood that the specific order or precedence of "first/second/third" may be interchanged where permitted, so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein are for the purpose of describing the present invention only and are not intended to limit the present invention.

Embodiments of the present invention provide a data reading method that can be applied to a chip, for example, and can be executed by a cache module in the chip. The chip can be, for example, at least one of a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, and a data processing unit (DPU) chip. The chip can be used in any suitable computer device, such as a server, laptop, tablet, desktop, smart TV, set-top box, mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device), and other devices with data processing capabilities.

Figure 1 is a schematic diagram illustrating a data reading method according to an embodiment of the present invention. As shown in Figure 1 , the method includes the following steps S101 to S104: Step S101: Receive a first data read request from a request source. The first data read request is used to request data reading according to read information and to prefetch data according to prefetch information.

Step S102: Obtain the read information and the pre-fetch information according to the first read data request.

Here, the request source may include but is not limited to at least one of a computing module in a chip, an upstream cache module of a cache module currently to read data, and the like.

In some embodiments, a first read data request may be received by a cache module in a chip (referred to as the current cache module), and the request source may send at least one first read data request to the current cache module as needed. For example, if the request source is a computing module, the computing module may generate a first read data request after parsing the read data instruction in the task and send the first read data request to the cache module. For another example, if the request source is an upstream cache module of the current cache module, the upstream cache module may send at least one first read data request to the current cache module based on the upstream read data request if the cache unit corresponding to the received upstream read data request is missing.

In some embodiments, the first read data request may include read information and prefetch information. After receiving the first read data request sent by the request source, the first read data request may be parsed to obtain the read information and prefetch information corresponding to the first read data request. The read information may include any appropriate information indicating data reading. For example, the read information may include, but is not limited to, at least one of a first read request address and a first read data length. The first read request address is the starting address of the data to be read corresponding to the first read data request. The first read data length refers to the length of the data to be read. The prefetch information may include any appropriate information indicating data prefetching. For example, the prefetch information may include but is not limited to at least one of whether to perform data prefetching, the length of prefetched data, etc.

During implementation, the first read data request can be parsed in any appropriate parsing method according to the actual situation, and the embodiment of the present invention is not limited to this.

In some embodiments, the first read data request may include a read request address signal, a read data length signal, and a prefetch control signal. Parsing the read request address signal yields the first read request address, parsing the read data length signal yields the first read data length, and parsing the prefetch control signal yields prefetch information. During implementation, a plurality of correspondences between prefetch control signals and prefetch information may be pre-set, and based on these correspondences, the prefetch information corresponding to the prefetch control signal in the first read data request may be determined. Those skilled in the art may determine an appropriate correspondence between prefetch control signals and prefetch information based on actual circumstances, and the present invention is not limited thereto.

In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is to be performed. The prefetch switch state can be indicated by the value of a prefetch control signal. For example, when the prefetch control signal is 0'b0, the prefetch switch state can be determined to be a closed state indicating that data prefetching is not to be performed. When the prefetch control signal is 0'b1, the prefetch switch state can be determined to be an open state indicating that data prefetching is to be performed. When the prefetch switch state is an open state indicating that data prefetching is to be performed, the prefetch data length can be a default or controlled by other signals, which is not limited here.

In some embodiments, the prefetch information includes the prefetch data length, and the prefetch data length can be indicated by the value of the prefetch control signal. For example, when the prefetch control signal is 0’b0, the prefetch data length can be determined to be 0, and when the prefetch control signal is 0’b1, the prefetch data length can be determined to be 1 cache unit. For another example, when the prefetch control signal is 0’b00, the prefetch data length can be determined to be 0, when the prefetch control signal is 0’b01, the prefetch data length can be determined to be 1 cache unit, when the prefetch control signal is 0’b10, the prefetch data length can be determined to be 2 cache units, and when the prefetch control signal is 0’b11, the prefetch data length can be determined to be 3 cache units.

In some implementations, the first read data request may include a request type signal, a read request address signal, and a read data length signal. Parsing the read request address signal may yield the first read request address, parsing the read data length signal may yield the first read data length, and parsing the request type signal may yield prefetch information. In implementations, multiple request type signals may be predefined, and different request type signals may indicate different prefetch information. Thus, corresponding prefetch information may be determined based on the request type signal in the first read data request. Those skilled in the art can define appropriate request type signals and the corresponding relationship between the request type indicated by each request type signal and the prefetch information according to actual circumstances, and the embodiments of the present invention are not limited thereto.

In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is performed. The request type can be indicated by the value of a request type signal, and the prefetch switch state is determined based on the request type. For example, if the request type signal is 0'b101, the request type can be determined to be a read-only type, i.e., only data reading is performed without data prefetching, and the prefetch switch state is set to a closed state, indicating that data prefetching is not performed. If the request type signal is 0'b110, the request type can be determined to be a read-with-prefetch type, i.e., both data reading and data prefetching are performed, and the prefetch switch state is set to an open state, indicating that data prefetching is performed.

In some embodiments, the prefetch information includes the prefetch data length. The request type can be indicated by the value of the request type signal, and the prefetch data length can be determined based on the request type. For example, if the request type signal is 0'b101, the request type can be determined to be read-only, thereby determining the prefetch data length to be 0. If the request type signal is 0'b110, the request type can be determined to be read with a prefetch of 1 cache unit, thereby determining the prefetch data length to be 1 cache unit. If the request type signal is 0'b111, the request type can be determined to be read with a prefetch of 4 cache units, thereby determining the prefetch data length to be 4 cache units.

Step S103: Based on the read information, read the first target data from the storage space and/or memory of the cache module, and return the first target data to the request source.

Here, a cache unit hit detection can be performed in the storage space of the cache module based on the read information. If the cache unit corresponding to the read information hits, the first target data is obtained from the cache unit; if the cache unit corresponding to the read information is missing, the first target data is obtained from the memory based on the read information.

In some embodiments, when the read information includes a first read request address and a first read data length, a cache unit hit detection can be performed in the storage space of the cache module based on the first read request address and the first read data length. If the cache unit corresponding to the first read request address and the first read data length hits, the first target data is obtained from the cache unit; if the cache unit corresponding to the first read request address and the first read data length misses, the first target data is obtained from the memory based on the first read request address and the first read data length.

In step S104, based on the prefetch information, second target data is prefetched from the memory, and the second target data is cached into at least one cache unit of the cache module.

Here, a prefetch start address and a prefetch data length can be determined based on the prefetch information, and then the second target data can be prefetched from the memory based on the prefetch start address and the prefetch data length, and the second target data can be cached into at least one cache unit of the cache module. The cache unit may include but is not limited to a cache block, a cache sector, etc.

In some embodiments, a prefetch start address and a prefetch data length can be determined based on the prefetch information, and a cache unit hit detection can be performed in the storage space of the cache module based on the prefetch start address and the prefetch data length. If the cache unit corresponding to the prefetch start address and the prefetch data length is missing, the second target data is prefetched from the memory and cached into at least one cache unit of the cache module; if the cache unit corresponding to the prefetch start address and the prefetch data length is hit, the second target data does not need to be prefetched from the memory.

It can be understood that the first target data is the data requested to be read by the first read data request, and the second target data is the data requested to be pre-fetched by the first read data request. During the current request process, the first target data will be returned to the request source, and the second target data will be cached in at least one cache unit of the cache module. In subsequent read data requests, if the second target data is requested to be read, the cached second target data can be directly read from the cache module. In this way, the cache hit rate can be improved, thereby improving the efficiency of data reading.

In an embodiment of the present invention, a first read data request sent by a request source is received, where the first read data request is used to request data reading according to read information and data prefetching according to prefetch information. Based on the first read data request, read information and prefetch information are obtained. Based on the read information, first target data is read from the storage space and/or memory of the cache module and the first target data is returned to the request source. Based on the prefetch information, second target data is prefetched from the memory and the second target data is cached into at least one cache unit of the cache module. In this way, the request source can send prefetch information to the cache module along with the read data request, so data can be read and prefetched through a single read data request. This can, on the one hand, reduce the data request pressure between the request source and the cache module, compress the request bandwidth, and improve processor performance. On the other hand, the prefetch information obtained from the read data request can be used to control data prefetching, thereby facilitating flexible control of the prefetching method on a task-by-task basis to better meet the data reading needs of each task.

In some embodiments, the above steps S101 to S104 may be executed by a cache module in a chip; the first target data includes at least one first sub-target data, and the cache module includes a first cache sub-module and a second cache sub-module.

Step S101 may include the following step S111: In step S111, the first cache sub-module receives a first data read request sent by a request source.

Step S102 may include the following step S112: In step S112, the first cache sub-module obtains the read information and the prefetch information based on the first read request; the read information includes the first read request address and the first read data length.

Step S103 may include the following steps S113 to S114: In step S113, the first cache sub-module determines at least one read data sub-request based on the first read request address and the first read data length. The data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache sub-module.

Here, the first read request address and first read data length can correspond to one read data sub-request or multiple read data sub-requests. The data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache sub-module. In other words, the request data volume corresponding to each read data sub-request is aligned according to the cache unit length of the first cache sub-module.

In some embodiments, the first read data length is less than the cache unit length of the first cache sub-module, indicating that the data amount of the first read data request is less than one cache unit. The first read request address and the first read data length can be aligned according to the cache unit length to obtain a read data sub-request whose data request length is equal to the cache unit length of the first cache sub-module.

In some embodiments, the first read data length is equal to the cache unit length of the first cache submodule, indicating that the data amount of the first read data request corresponds to one cache unit, and a read data sub-request can be directly obtained based on the first read data request address and the first read data length.

In some embodiments, the first read data length is greater than the cache unit length of the first cache sub-module, indicating that the data size of the first read data request exceeds one cache unit. The first read request address and the first read data length can be split and aligned according to the cache unit length to obtain multiple read data sub-requests, and the data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache sub-module.

In step S114, the first cache sub-module obtains the first sub-target data corresponding to each of the read data sub-requests from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and/or the memory, and returns each of the first sub-target data to the request source.

Step S104 may include the following step S115: In step S115, the second cache sub-module pre-fetches second target data from the memory based on the pre-fetch information and caches the second target data into at least one cache unit of the second cache sub-module.

In the above embodiment, the cache module includes a first cache sub-module and a second cache sub-module. The first cache sub-module responds to receiving a first read data request sent by a request source, parses the first read data request, and obtains the first read request address, the first read data length, and prefetch information. The first cache sub-module determines at least one read data sub-request based on the first read request address and the first read data length. The data request length corresponding to each read data sub-request is the same as the first cache sub-module. The cache units of the two sub-modules have equal lengths. The first cache sub-module retrieves the first sub-target data corresponding to each read data sub-request from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and/or memory, and returns each first sub-target data to the request source. The second cache sub-module, based on prefetch information, prefetches the second target data from memory and caches the second target data into at least one cache unit of the second cache sub-module. In this way, in a cache module including multiple cache levels, data reading and prefetching can be simply and quickly achieved through a single read data request from the request source.

In some embodiments, the first cache sub-module in step S114 retrieves the first sub-target data corresponding to each read data sub-request from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and/or memory, which may include the following steps S121 and S122: In step S121, the first cache sub-module performs a cache unit hit check in the storage space of the first cache sub-module based on each read data sub-request, and obtains a second check result corresponding to each read data sub-request.

In step S122, for each of the read data sub-requests, if the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is hit, the first cache sub-module reads the first sub-target data corresponding to the read data sub-request from the hit cache unit; and if the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is missing, the first cache sub-module sends a second read data request to the second cache sub-module based on the second read request address and second read data length corresponding to the read data sub-request, as well as the prefetch information, and receives the first sub-target data corresponding to the read data sub-request returned by the second cache sub-module.

Here, the second read request address corresponding to the read data sub-request refers to the starting address of the data requested by the read data sub-request, and the second read data length corresponding to the read data sub-request refers to the length of the data requested by the read data sub-request.

If the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is missing, a second read data request can be generated based on the second read request address and second read data length corresponding to the read data sub-request, as well as prefetch information, and sent to the second cache sub-module. In implementation, those skilled in the art can use any suitable method to generate the second read data request based on the second read request address and second read data length corresponding to the read data sub-request, as well as prefetch information, according to actual circumstances. The embodiments of the present invention are not limited to this.

In some embodiments, a read request address signal, a read data length signal, and a request type signal may be determined based on the second read request address, the second read data length, and the prefetch information, and a second read data request may be generated based on the read request address signal, the read data length signal, and the request type signal. For example, the second read request address may be encoded as the read request address signal in the second read data request, and the second read data length may be encoded as the read data length signal in the second read data request. Based on a correspondence between a request type indicated by a preset request type signal and the prefetch information, a request type signal corresponding to the prefetch information may be determined and used as the request type signal for the second read data request.

In some embodiments, a read request address signal, a read data length signal, and a prefetch control signal may be determined based on the second read request address, the second read data length, and the prefetch information, and a second read data request may be generated based on the read request address signal, the read data length signal, and the prefetch control signal. For example, the prefetch control signal corresponding to the prefetch information may be determined based on a preset correspondence between the prefetch control signal and the prefetch information.

The second cache sub-module described in step S115 prefetches the second target data from the memory based on the prefetch information, which may include the following steps S123 to S125: In step S123, the second cache sub-module, in response to receiving the second read data request sent by the first cache sub-module, parses the second read data request to obtain the second read request address, the second read data length, and the prefetch information.

In step S124, the second cache submodule obtains the first subtarget data from the storage space and/or memory of the second cache submodule based on the second read request address and the second read data length, and returns the first subtarget data to the first cache submodule.

In step S125, the second cache submodule prefetches second target data from the memory based on the prefetch information, and caches the second target data into at least one cache unit of the second cache submodule.

Here, steps S123 to S125 correspond to steps S101 to S104 in the aforementioned embodiment, and the implementation of the aforementioned steps S101 to S104 may be referred to.

In the above embodiment, for each read data sub-request, if the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is hit, the first cache sub-module reads the first sub-target data corresponding to the read data sub-request from the hit cache unit. If the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is missed, the first cache sub-module sends a second read data request to the second cache sub-module based on the second read request address and second read data length corresponding to the read data sub-request, as well as the prefetch information. In response to receiving the second read data request sent by the first cache submodule, the second cache submodule parses the second read data request to obtain the second read request address, the second read data length, and the prefetch information. In this way, if a partial read data subrequest corresponding to the first read data request misses a cache unit in the first cache submodule, the prefetch information can be carried to the second cache submodule via the second read data request corresponding to the partial read data subrequest. This can reduce the data request pressure between the request source and the first cache submodule in a cache module including a multi-level cache, reduce request bandwidth usage, and improve processor performance.

In some embodiments, if all cache units corresponding to read data sub-requests are hit, the pre-fetch information can be discarded, that is, the pre-fetch information is not sent to the second cache sub-module. In this way, since all cache units corresponding to read data sub-requests are hit, the data request pressure between the first cache sub-module and the second cache sub-module can be reduced, thereby reducing the request bandwidth between the first cache sub-module and the second cache sub-module from becoming an access bottleneck. Generally, the request bandwidth between the request source and the first cache sub-module is not less than the request bandwidth between the first cache sub-module and the second cache sub-module. The request bandwidth between modules can be reduced, thereby also reducing the situation where the request bandwidth between the first and second cache sub-modules becomes an access bottleneck. In this way, the request source can prefetch the data corresponding to the discarded prefetch information by sending a separate prefetch request to the first cache sub-module, thereby reducing the processing resources occupied by the second cache sub-module to process the prefetch information carried by the read request. Furthermore, when prefetching is used in a loop-based calculation scenario, the data requested in each loop calculation process typically does not overlap, and the data corresponding to the prefetch information is typically missing in the first request. Therefore, the prefetch information carried in the first read request for the data, used to prefetch the next piece of data to be prefetched, is typically carried to the second cache submodule.

An embodiment of the present invention provides a data reading method that can be applied in a chip, for example, by a cache module within the chip. Figure 2 is a schematic diagram illustrating the implementation flow of the data reading method provided by an embodiment of the present invention. As shown in Figure 2, the method includes the following steps S201 to S205: Step S201: Receive a first data read request from a request source. The first data read request is used to request data reading according to read information and to prefetch data according to prefetch information.

Step S202: Obtain the read information and the pre-fetch information according to the first read data request; wherein the pre-fetch information includes the pre-fetch data length.

Step S203: Based on the read information, read the first target data from the storage space and/or memory of the cache module, and return the first target data to the request source.

Here, steps S201 to S203 may respectively correspond to steps S101 to S103 in the aforementioned embodiment, and the implementation of the aforementioned steps S101 to S103 may be referred to.

Step S204: When the pre-fetch data length is greater than 0, a pre-fetch start address is determined based on the first read request address and the first read data length.

Here, the prefetch start address is the starting address for data prefetching.

In some implementations, the first read request address may be added to the first read data length to obtain a prefetch start address.

In some implementations, the first read request address and the first read data length may be aligned according to the cache unit length in the cache module to obtain the aligned first read request address and the first read data length, and the aligned first read request address may be added to the aligned first read data length to obtain the prefetch start address.

In step S205, based on the prefetch start address and the prefetch data length, second target data is prefetched from the memory, and the second target data is cached into at least one cache unit of the cache module.

In this embodiment of the present invention, if the prefetch data length is greater than 0, a prefetch start address is determined based on the first read request address and the first read data length. Based on the prefetch start address and the prefetch data length, second target data is prefetched from memory and cached into at least one cache unit of the cache module. This allows for simple and convenient control of whether data prefetching is performed based on whether the prefetch data length is greater than 0. Furthermore, if the prefetch data length is greater than 0, the prefetched second target data is controlled based on the prefetch data length, thereby flexibly meeting the data reading requirements of various tasks.

In some embodiments, the read information includes a first read request address and a first read data length. Step S202 may include the following steps S211 and S212: Step S211: Parse the request type signal, read request address signal, and read data length signal in the first read data request to obtain the first request type, the first read request address, and the first read data length.

Here, the first read data request sent by the request source to the cache module may include a request type signal, a read request address signal, and a read data length signal. The request type signal is used to indicate the request type of the first read data request, the read request address signal is used to indicate the starting address of the data to be read corresponding to the first read data request, and the read data length signal is used to indicate the length of the data to be read. Therefore, by parsing the request type signal, the read request address signal, and the read data length signal in the first read data request, the first request type, the first read request address, and the first read data length of the first read data request can be obtained.

Step S212: Determine the pre-fetched data length based on the first request type.

Here, multiple request types can be predefined, and different request types can correspond to different prefetched data lengths. Thus, the corresponding prefetched data length can be determined based on the first request type. In practice, those skilled in the art can define the correspondence between each request type and prefetched data length based on actual circumstances, and the present invention is not limited thereto.

For example, when the request type signal is 0’b101, the first request type is determined to be a read-only type, thereby determining the prefetch data length to be 0; when the request type signal is 0’b110, the first request type is determined to be a read and prefetch type of 1 cache unit, thereby determining the prefetch data length to be 1 cache unit; when the request type signal is 0’b111, the first request type is determined to be a read and prefetch type of 4 cache units, thereby determining the prefetch data length to be 4 cache units.

In the above embodiment, the request type signal, read request address signal, and read data length signal in the first read data request are analyzed separately to obtain the first request type, first read request address, and first read data length of the first read data request. The prefetch data length is then determined based on the first request type. This allows for a simple and quick way to determine the prefetch data length based on the request type.

In some embodiments, the read information includes a first read request address and a first read data length. Step S202 may include the following step S221: Step S221: Parse the read request address signal, the read data length signal, and the prefetch control signal in the first read data request to obtain the first read request address, the first read data length, and the prefetch data length.

Here, the first read data request may include a read request address signal, a read data length signal, and a prefetch control signal. Parsing the read request address signal yields the first read request address, parsing the read data length signal yields the first read data length, and parsing the prefetch control signal yields the prefetch data length. In practice, a correspondence between multiple prefetch control signals and prefetch data lengths may be pre-set, and based on this correspondence, the prefetch data length corresponding to the prefetch control signal in the first read data request may be determined. Those skilled in the art may determine an appropriate correspondence between prefetch control signals and prefetch data lengths based on actual circumstances, and the present invention is not limited thereto. For example, when the prefetch control signal is 0'b0, the prefetch data length is determined to be 0, and when the prefetch control signal is 0'b1, the prefetch data length is determined to be 1 cache unit.

In the above embodiment, the read request address signal, read data length signal, and prefetch control signal in the first read data request are analyzed separately to obtain the first read request address, first read data length, and prefetch data length of the first read data request. In this way, the prefetch data length can be determined simply and quickly using the prefetch control signal.

In some embodiments, step S205 may include the following steps S231 and S232: Step S231: Based on the prefetch start address and the prefetch data length, determine at least one prefetch sub-request, where the data request length corresponding to each prefetch sub-request is equal to the cache unit length of the cache module.

Here, the prefetch start address and prefetch data length can correspond to one prefetch sub-request or multiple prefetch sub-requests. The data request length corresponding to each prefetch sub-request is equal to the cache unit length of the first cache sub-module. In other words, the request data volume corresponding to each prefetch sub-request is aligned with the cache unit length of the first cache sub-module.

In some embodiments, the prefetch data length is less than the cache unit length of the first cache sub-module, indicating that the amount of data requested for prefetching by the first read data request is less than one cache unit. The prefetch start address and the prefetch data length can be aligned according to the cache unit length to obtain a prefetch sub-request whose data request length is equal to the cache unit length of the first cache sub-module.

In some embodiments, the first read data length is equal to the cache unit length of the first cache submodule, indicating that the amount of data requested for prefetching by the first read data request corresponds to one cache unit. A prefetch sub-request can be directly obtained based on the prefetch start address and the prefetch data length.

In some embodiments, the first read data length is greater than the cache unit length of the first cache sub-module, indicating that the amount of data requested for prefetching by the first read data request exceeds one cache unit. The prefetch start address and prefetch data length can be split and aligned according to the cache unit length to obtain multiple prefetch sub-requests, and the data request length corresponding to each prefetch sub-request is equal to the cache unit length of the first cache sub-module.

In step S232, for each of the prefetch sub-requests, a cache unit hit detection is performed in the storage space of the cache module based on the prefetch sub-request to obtain a first detection result. If the first detection result indicates that the cache unit corresponding to the prefetch sub-request is missing, second target data is prefetched from the memory based on the prefetch sub-request and the second target data is cached into at least one cache unit of the cache module.

In the above embodiment, cache unit hit detection can be performed for each prefetch sub-request. If the cache unit corresponding to the prefetch sub-request is missing, the second target data is prefetched from the memory based on the prefetch sub-request. In this way, data prefetching is performed at a granular level based on the prefetch sub-request, which can improve the flexibility of controlling data prefetching.

In some embodiments, the pre-fetched data length is an integer multiple of the cache unit length, and the cache unit includes a cache block or a cache sector. This can better adapt the cache module to the specific details of the cache unit.

An embodiment of the present invention provides a data reading method that can be applied to a chip, for example, by a cache module in the chip. FIG3 is a schematic diagram of the implementation process of a data reading method provided by an embodiment of the present invention. As shown in FIG3 , the method includes the following steps S301 to S306:

In step S301, a plurality of first data read requests sent by a request source are received, wherein the first data read requests are used to request data reading according to read information corresponding to the first data read requests and data prefetching according to prefetch information corresponding to the first data read requests.

In step S302, according to each first read data request, read information corresponding to the first read data request and prefetch information corresponding to the first read data request are obtained respectively; wherein the read information includes a first read request address and a first read data length.

Here, steps S301 to S302 correspond to steps S101 to S102 in the aforementioned embodiment, and the implementation of the aforementioned steps S101 to S102 may be referred to.

In step S303, for each first read data request, a cache unit corresponding to the first read data request is determined based on the first read request address and the first read data length corresponding to the first read data request.

Here, the cache unit corresponding to the first read data request may be obtained by mapping based on the first read request address and the first read data length corresponding to the first read data request.

In step S304, when the cache units corresponding to the multiple first read data requests overlap, the first read request addresses and first read data lengths corresponding to the multiple first read data requests are merged to obtain a merged first read request address and first read data length, and the prefetch information corresponding to the multiple first read data requests is merged to obtain a merged prefetch information.

Here, the first read request address and first read data length corresponding to each first read data request can each determine an address range.

In some implementations, the union of the address intervals corresponding to the first read data requests may be determined as the target address interval, the starting address of the target address interval may be determined as the merged first read request address, and the length of the target address interval may be determined as the merged first read data length.

In some implementations, the address intervals corresponding to the first read data requests may be aligned according to the length of the cache unit in the cache module, and the union of the aligned address intervals may be determined as the target address interval. The starting address of the target address interval may then be determined as the merged first read request address, and the length of the target address interval may be determined as the merged first read data length.

In step S305, based on the combined first read request address and the first read data length, first target data is obtained from the storage space and/or memory of the cache module, and the first target data is returned to the request source.

In step S306, based on the merged prefetch information, second target data is prefetched from the memory, and the second target data is cached into at least one cache unit of the cache module.

Here, steps S305 to S306 correspond to steps S103 to S104 in the aforementioned embodiment, and the implementation of the aforementioned steps S103 to S104 may be referred to.

In an embodiment of the present invention, when multiple first read data requests are received and the cache units corresponding to the multiple first read data requests overlap, the first read request addresses and first read data lengths corresponding to the multiple first read data requests can be merged to obtain a merged first read request address and first read data length. Furthermore, the prefetch information corresponding to the multiple first read data requests can be merged to obtain a merged prefetch information. In this way, the second target data can be prefetched from the memory based on the merged prefetch information, thereby reducing the number of data prefetches from the memory and, in turn, reducing the number of data requests between the cache module and the memory, further improving processor performance.

In some embodiments, merging the prefetch information corresponding to the multiple first read data requests to obtain the merged prefetch information in step S304 includes the following step S311: Step S311: Determine the prefetch information corresponding to the first read data request with the latest first read request address among the multiple first read data requests as the merged prefetch information.

Here, because the cache units corresponding to multiple first read data requests overlap, the data to be prefetched indicated by the prefetch information corresponding to a first read data request may overlap with the data requested by other first read data requests whose first read request addresses follow the first read request address corresponding to the first read data request. Therefore, the prefetch information corresponding to the first read data request with the latest first read request address among the multiple first read data requests can be determined as the merged prefetch information. This can reduce unnecessary data duplication and further improve processor performance.

An embodiment of the present invention provides a data reading method that can be applied to a chip. Figure 4 is a schematic diagram illustrating the implementation flow of the data reading method provided by the embodiment of the present invention. As shown in Figure 4, the method includes the following steps S401 to S404: Step S401: Obtain a data read instruction; the data read instruction is used to instruct data reading according to read information and data prefetching according to prefetch information.

Here, the read data instruction can be an instruction for reading data in the task currently executed by the computing module in the chip. During implementation, those skilled in the art can set an appropriate read data instruction based on the task actually executed.

In some embodiments, a read instruction may be generated by application software and sent to a computing module in the chip, instructing the computing module to read data according to read information and prefetch data according to prefetch information. The read information and prefetch information may be determined by the application software based on actual data read requirements.

In some embodiments, a data read instruction may be generated by a computing module within a chip and sent to another computing module, instructing the other computing module to read data according to the read instruction and prefetch data according to prefetch information. The read information and prefetch information may be determined by the computing module based on actual data read requirements.

In step S402, a first read data request is obtained according to the read data instruction; the first read data request includes the read information and the pre-fetch information.

Here, the read instruction can be parsed to obtain read information and prefetch information corresponding to the read instruction, and a first read request can be generated based on the read information and prefetch information. During implementation, any appropriate parsing method can be used to parse the read instruction according to actual circumstances, and the embodiments of the present invention are not limited to this.

In some implementations, the data read instruction may include a read control code and a prefetch control code. Parsing the read control code may obtain read information, and parsing the prefetch control code may obtain prefetch information.

In some embodiments, a read instruction may include a read request address code, a read data length code, and a prefetch control code. Parsing the read request address code may yield a first read request address, parsing the read data length code may yield a first read data length, and parsing the prefetch control code may yield prefetch information. During implementation, a correspondence between multiple prefetch control codes and prefetch information may be pre-set, and based on this correspondence, the prefetch information corresponding to the prefetch control code in the read instruction may be determined. Those skilled in the art may determine an appropriate correspondence between prefetch control codes and prefetch information based on actual circumstances, and the embodiments of the present invention are not limited thereto.

In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is to be performed. The prefetch switch state can be indicated by a prefetch control code. For example, when the prefetch control code is 0'b0, the prefetch switch state can be determined to be a closed state indicating that data prefetching is not to be performed. When the prefetch control code is 0'b1, the prefetch switch state can be determined to be an open state indicating that data prefetching is to be performed. When the prefetch switch state is an open state indicating that data prefetching is to be performed, the prefetch data length can be a default or controlled by other bit fields in the read data instruction, which is not limited here.

In some embodiments, the prefetch information includes the prefetch data length, and the prefetch data length can be indicated by a prefetch control code. For example, when the prefetch control code is 0’b0, the prefetch data length can be determined to be 0, and when the prefetch control code is 0’b1, the prefetch data length can be determined to be 1 cache unit. For another example, when the prefetch control code is 0’b00, the prefetch data length can be determined to be 0, when the prefetch control code is 0’b01, the prefetch data length can be determined to be 1 cache unit, when the prefetch control code is 0’b10, the prefetch data length can be determined to be 2 cache units, and when the prefetch control code is 0’b11, the prefetch data length can be determined to be 3 cache units.

In some implementations, a read data instruction may include an instruction type code, a read request address code, and a read data length code. Parsing the read request address code may yield a first read request address, parsing the read data length code may yield a first read data length, and parsing the instruction type code may yield prefetch information. During implementation, multiple instruction type codes may be predefined, and the instruction type codes may indicate a request type. Request types indicated by different instruction type codes may correspond to different prefetch information, thereby determining corresponding prefetch information based on the instruction type code in the read data instruction. Those skilled in the art can define appropriate instruction type codes and the correspondence between the request type indicated by each instruction type code and the prefetch information according to actual circumstances, and the embodiments of the present invention are not limited thereto.

In some embodiments, the prefetch information includes a prefetch switch state indicating whether data prefetching is performed. The request type may be indicated by the instruction type encoding, and the prefetch switch state may be determined based on the request type. For example, if the instruction type encoding is 0'b101, the request type may be determined to be a read-only type, i.e., only data reading is performed without data prefetching, and the prefetch switch state is set to a closed state, indicating that data prefetching is not performed. If the instruction type encoding is 0'b110, the request type may be determined to be a read-with-prefetch type, i.e., both data reading and data prefetching are performed, and the prefetch switch state is set to an open state, indicating that data prefetching is performed.

In some embodiments, the prefetch information includes a prefetch data length. The request type may be indicated by the instruction type encoding, and the prefetch data length may be determined based on the request type. For example, if the instruction type encoding is 0'b101, the request type may be determined to be read-only, thereby determining the prefetch data length to be 0. If the instruction type encoding is 0'b110, the request type may be determined to be read with a prefetch of 1 cache unit, thereby determining the prefetch data length to be 1 cache unit. If the instruction type encoding is 0'b111, the request type may be determined to be read with a prefetch of 4 cache units, thereby determining the prefetch data length to be 4 cache units.

In some implementations, the read information may be included in a read control signal in the first read request, and the prefetch information may be included in a request type signal in the first read request. The read control signal and the request type signal may be determined based on the read information and the prefetch information, respectively, and the first read request may be generated based on the read control signal and the request type signal.

In some implementations, the read information may be included in a read control signal in the first read request, and the prefetch information may be included in a prefetch control signal in the first read request. A read control signal and a prefetch control signal may be determined based on the read information and the prefetch information, respectively, and the first read request may be generated based on the read control signal and the prefetch control signal.

In step S403, the first read data request is sent to the cache module, so that the cache module responds to the first read data request by reading and returning the first target data according to the read information, and prefetching and caching the second target data according to the prefetch information.

Step S404: receiving the first target data returned by the cache module.

In an embodiment of the present invention, a read data instruction is obtained, the read data instruction being used to instruct data reading according to read information and data prefetching according to prefetch information; a first read data request is obtained according to the read data instruction, the first read data request including the read information and the prefetch information; the first read data request is sent to a cache module, so that the cache module responds to the first read data request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; and the first target data returned by the cache module is received. In this way, the request source of a read request can send prefetch information along with the read request to the cache module, allowing data to be read and prefetched with a single read request. This, on the one hand, reduces the data request pressure between the compute module and the cache module, compresses the request bandwidth, and improves processor performance. On the other hand, data prefetching can be controlled by parsing the prefetch information from the read instruction, achieving instruction-level prefetch control, thereby better meeting the data reading needs of each task.

In some embodiments, the read information includes a first read request address and a first read data length. Step S401 may include the following step S411: Step S411: Encode the command based on the first read request address, the first read data length, and the prefetch information to obtain the read data command.

Here, by encoding the first read request address, the first read data length, and the prefetch information into the read data instruction, the read data instruction can be obtained simply and quickly.

In some implementations, the read data instruction includes an instruction type code, a read request address code, and a read data length code. Step S411 may include the following steps S421 through S423: Step S421: Determine the instruction type code corresponding to the prefetch information from a preset set of instruction type codes.

In step S422, the first read request address is encoded to obtain the read request address code.

Step S423: Encode the first read data length to obtain the read data length code.

Here, the instruction type code set may include at least one pre-defined instruction type code, and different instruction type codes may represent different request types. During implementation, those skilled in the art may pre-define an appropriate instruction type code set based on actual application scenarios, and the present invention is not limited to this.

In the above embodiment, by encoding prefetch information into the instruction type code, the bit field occupancy in the data read instruction can be reduced, thereby simplifying the design of the instruction set.

In some embodiments, step S402 may include the following steps S431 and S432: Step S431: Parsing the instruction type code, the read request address code, and the read data length code to obtain the prefetch information, the first read request address, and the first read data length; Step S432: Generating the first read data request based on the prefetch information, the first read request address, and the first read data length.

Here, the read data instruction may include an instruction type code, a read request address code, and a read data length code. Parsing the read request address code may yield a first read request address, parsing the read data length code may yield a first read data length, and parsing the instruction type code may yield prefetch information. In some embodiments, the prefetch information includes the prefetch data length. During implementation, multiple instruction type codes may be predefined, and request types indicated by different instruction type codes may correspond to different prefetch data lengths. Thus, the corresponding prefetch data length may be determined based on the instruction type code in the read data instruction.

In the above embodiment, the instruction type code, read request address code, and read data length code in the read data instruction are parsed separately to obtain prefetch information, the first read request address, and the first read data length. This allows the prefetch information to be quickly and easily determined based on the request type, and the first read data request can be quickly generated based on the prefetch information, the first read request address, and the first read data length.

In some embodiments, the read data instruction includes a read request address code, a read data length code, and a prefetch control code. Step S411 may include the following steps S441 to S443: Step S441: Encode the first read request address to obtain the read request address code; Step S442: Encode the first read data length to obtain the read data length code; Step S443: Encode the prefetch information to obtain the prefetch control code.

It is understandable that the encoding method for the first read request address, the first read data length, and the pre-fetch information can be any appropriate encoding method determined according to the actual situation, and the embodiment of the present invention is not limited to this.

Thus, by encoding the prefetch information separately into the prefetch control code, there is no need to expand the existing instruction type code, thereby simplifying the encoding and decoding complexity of the instruction type code.

In some implementations, the prefetch information may include the prefetch data length, and the prefetch control code may be obtained by encoding the prefetch data length.

In some embodiments, step S402 may include the following steps S451 to S452: Step S451: Parse the read request address code, the read data length code, and the prefetch control code to obtain the first read request address, the first read data length, and the prefetch information.

Step S452: Generate the first read data request based on the prefetch information, the first read request address, and the first read data length.

Here, the read data instruction may include a read request address code, a read data length code, and a prefetch control code. Parsing the read request address code can obtain a first read request address, parsing the read data length code can obtain a first read data length, and parsing the prefetch control code can obtain prefetch information. In some embodiments, the prefetch information includes the prefetch data length. During implementation, a correspondence between multiple prefetch control codes and prefetch data lengths can be pre-set. Based on this correspondence, the prefetch data length corresponding to the prefetch control code in the read data instruction can be determined. For example, when the prefetch control code is 0'b0, the prefetch data length is determined to be 0, and when the prefetch control code is 0'b1, the prefetch data length is determined to be 1 cache unit.

In the above embodiment, the read request address code, read data length code, and prefetch control code in the read data instruction are parsed separately to obtain the first read request address, first read data length, and prefetch data length. This allows the prefetch control code to simply and quickly indicate prefetch information, thereby quickly generating the first read data request based on the prefetch information, the first read request address, and the first read data length.

In some embodiments, step S432 and/or step S452 may include the following step S461 or step S462: Step S461: Determine a read request address signal, a read data length signal, and a request type signal based on the first read request address, the first read data length, and the prefetch information, and generate the first read data request based on the read request address signal, the read data length signal, and the request type signal.

In some implementations, the first read request address can be encoded as a read request address signal in the first read data request; the first read data length can be encoded as a read data length signal in the first read data request; and based on the correspondence between the request type indicated by a preset request type signal and the prefetch information, a request type signal corresponding to the prefetch information is determined, and the request type signal is used as the request type signal of the first read data request.

In some embodiments, the prefetch information includes the prefetch data length. Based on the correspondence between the request type indicated by a preset request type signal and the prefetch data length, a request type signal corresponding to the prefetch data length can be determined, and the request type signal can be used as the request type signal of the first read data request.

In step S462, a read request address signal, a read data length signal, and a prefetch control signal are respectively determined based on the first read request address, the first read data length, and the prefetch information, and the first read data request is generated based on the read request address signal, the read data length signal, and the prefetch control signal.

In some implementations, the prefetch control signal corresponding to the prefetch information may be determined based on a preset correspondence between the prefetch control signal and the prefetch information.

In some embodiments, the prefetch information includes the prefetch data length, and the prefetch control signal corresponding to the prefetch data length can be determined based on a preset correspondence between the prefetch control signal and the prefetch data length.

In some embodiments, step S401 may include the following steps S471 to S473: Step S471: Obtain the read data volume and estimated calculation duration for the current task.

Here, the calculation time of the current task can be estimated to obtain the estimated calculation time. During implementation, any suitable estimation method can be used to estimate the calculation time of the current task, and the embodiment of the present invention is not limited to this.

In some implementations, the computational complexity of the current task may be determined, and the computational duration of the current task may be estimated based on the computational complexity to obtain an estimated computational duration.

The data read amount of the current task refers to the amount of data required to execute the current task. In some implementations, the data read amount can be included in the task information of the current task. In other implementations, the data read amount can be obtained by analyzing the data read requirements of the current task.

Step S472: Determine the pre-fetch information based on the read data volume and the estimated calculation time.

In some implementations, the time required to read data equal to the read data amount from the cache module is estimated to obtain an estimated read time; and prefetch information is determined based on the relationship between the estimated read time and the estimated calculation time.

Step S473: Determine the data read instruction based on the prefetch information.

It's understandable that, since the current task's data read volume and estimated computation time can respectively reflect the data access and computation time during the current task's execution, data prefetching can, to a certain extent, improve the efficiency of the data read process and reduce the time consumed during data reads. Therefore, based on the data read volume and estimated computation time, it's possible to determine whether data reads accompanied by data prefetching are necessary for the current task's execution scenario. Consequently, appropriate prefetch information and, consequently, data read instructions can be determined for the current task's execution scenario based on the data read volume and estimated computation time, thereby better balancing computation time and data access time during task execution.

In some embodiments, step S472 may include the following steps S481 to S482: Step S481: Determining a first estimated reading time corresponding to the amount of data to be read when the data prefetching function is enabled, and a second estimated reading time corresponding to the amount of data to be read when the data prefetching function is disabled; Step S482: Determining the prefetch information based on a relationship between the estimated calculation time and the first estimated reading time and/or the second estimated reading time.

Here, enabling data prefetching refers to reading data while prefetching it, i.e., the prefetch information carried in the read instruction instructs data prefetching. Disabling data prefetching refers to reading data without prefetching it, i.e., the prefetch information carried in the read instruction instructs data prefetching not to be performed.

It's understood that the first estimated read time can reflect the data access time required to execute the current task when data prefetching is enabled, while the second estimated read time can reflect the data access time required to execute the current task when data prefetching is disabled. Therefore, based on the relationship between the estimated computation time and the first and/or second estimated read times, it can be determined whether data prefetching is more suitable for the current task's execution scenario. This allows for the determination of appropriate prefetch information to balance computation time and data access time during task execution.

In some embodiments, the above-mentioned step S482 may include: when the estimated calculation time is greater than the first estimated reading time and less than the second estimated reading time, determining that the prefetch information is the first prefetch information indicating that the data prefetch function is enabled.

Therefore, since the estimated calculation time is greater than the first estimated read time and less than the second estimated read time, this indicates that when data prefetching is enabled, the data access time required to execute the current task is less than the estimated calculation time of the current task, and when data prefetching is disabled, the data access time required to execute the current task is greater than the estimated calculation time of the current task. Therefore, in this scenario, enabling data prefetching can reduce the impact of data read time on computing efficiency. Therefore, in this scenario, the prefetch information can be determined as the first prefetch information indicating that the data prefetch function is enabled, thereby reducing the impact of data reading time on computing efficiency, thereby better balancing computing time and data access time during task execution.

In some embodiments, the above-mentioned step S482 may include: when the estimated calculation time is less than or equal to the first estimated reading time, determining that the prefetch information is the first prefetch information indicating that the data prefetch function is turned on, or determining that the prefetch information is the second prefetch information indicating that the data prefetch function is turned off.

Therefore, since the estimated calculation time is less than or equal to the first estimated read time, it indicates that the data access time required to execute the current task with data prefetching enabled is at least as long as the estimated calculation time of the current task. Therefore, in this scenario, enabling data prefetching can reduce the impact of data read time on calculation efficiency to a certain extent. However, the impact of longer data read time on the overall task execution time will still exist. Therefore, in this scenario, the prefetch information can be determined as the first prefetch information indicating that the data prefetch function is enabled, thereby reducing the impact of data read time on computing efficiency, thereby better balancing computing time and data access time during task execution. The prefetch information can also be determined as the second prefetch information indicating that the data prefetch function is disabled, thereby simplifying the data read process.

In some embodiments, the above-mentioned step S482 may include: when the estimated calculation duration is greater than or equal to the second estimated reading duration, determining that the prefetch information is second prefetch information indicating that the data prefetch function is disabled.

In this case, since the estimated computation time is greater than or equal to the second estimated read time, this indicates that the data access time required to execute the current task with data prefetching disabled does not exceed the estimated computation time of the current task. Therefore, disabling data prefetching in this scenario does not affect computational efficiency due to data read time. Therefore, in this scenario, the prefetch information can be determined as the second prefetch information indicating that data prefetching is disabled, thereby simplifying the data read process.

In some implementations, the prefetch information includes a prefetch switch state. The first prefetch information may be an on state indicating that data prefetching is performed, and the second prefetch information may be an off state indicating that data prefetching is not performed.

In some implementations, the prefetch information includes the prefetch data length, the first prefetch information may be an integer greater than 0, or the first prefetch information may be 0.

It can be understood that when the prefetch information is the first prefetch information, the instruction type code or prefetch control code in the read data instruction indicates that data prefetching is turned on; when the prefetch information is the second prefetch information, the instruction type code or prefetch control code in the read data instruction indicates that data prefetching is turned off.

In some embodiments, step S481 may include the following steps S491 to S493: Step S491: Estimate the latency of sending a single request to the cache module, the latency of the cache module returning a single piece of data, the latency of the cache module sending a single request to the memory, and the latency of the memory returning a single piece of data to the cache module, respectively obtaining a first estimated latency, a second estimated latency, a third estimated latency, and a fourth estimated latency.

Here, any appropriate method can be used to estimate the delay in sending a request to the cache module and the delay in the cache module returning data, and the embodiments of the present invention are not limited to this.

In some embodiments, the request source of the first data read request may be a computing module in a chip. By collecting statistics on the historical latency of the computing module sending a single request to the cache module, the historical latency of the cache module returning a single data to the computing module, the historical latency of the cache module sending a single request to the memory, and the historical latency of the memory returning a single data to the cache module, a first estimated latency, a second estimated latency, a third estimated latency, and a fourth estimated latency may be obtained.

In some embodiments, the latency of a single request from the computing module to the cache module can be estimated based on the amount of data sent by the computing module to the cache module and the data bandwidth between the computing module and the cache module, thereby obtaining a first estimated latency. The latency of a single request from the cache module to the computing module can be estimated based on the amount of data returned by the cache module to the computing module and the data bandwidth between the computing module and the cache module, thereby obtaining a second estimated latency. The second estimated latency can be obtained by estimating the latency for the cache module to send a single request to the memory based on the amount of data sent by the cache module to the memory in a single request and the data bandwidth between the cache module and the memory. The fourth estimated latency can be obtained by estimating the latency for the memory to return a single data entry to the cache module based on the amount of data returned by the memory to the cache module and the data bandwidth between the cache module and the memory.

In step S492, the first estimated read duration is determined as the sum of a first ratio between the read data volume of the current task and a target bandwidth, the first estimated latency, and the second estimated latency; the target bandwidth is the data bandwidth between the request source of the first read data request and the cache module.

In step S493, the sum of the first ratio, the first estimated delay, the second estimated delay, the third estimated delay, and the fourth estimated delay is determined as a second estimated reading duration.

In the above embodiment, the first estimated reading duration is obtained based on the first ratio between the read data volume of the current task and the target bandwidth, the first estimated delay, and the sum of the second estimated delay; the second estimated reading duration is obtained based on the sum of the first ratio, the first estimated delay, the second estimated delay, the third estimated delay, and the fourth estimated delay; when the estimated calculation duration is greater than the first estimated reading duration and less than the second estimated reading duration, the prefetch information is determined to be the first prefetch information indicating that the data prefetch function is enabled. In this way, on the one hand, the first estimated reading time is the sum of the first ratio between the amount of data to be read in the current task and the target bandwidth, the first estimated delay for the computing module to send a single request to the cache module, and the second estimated delay for the cache module to return a single data to the computing module. Therefore, the first estimated reading time can represent the lower limit of the estimated time consumption for data reading in the current task; on the other hand, the second estimated reading time is the sum of the first ratio between the amount of data to be read in the current task and the target bandwidth, the first estimated delay for the computing module to send a single request to the cache module, and the second estimated delay for the cache module to return a single data to the computing module. The first estimated read duration is the sum of the first ratio between the data volume and the target bandwidth, the first estimated latency for the compute module to send a single request to the cache module, the second estimated latency for the cache module to return a single piece of data to the compute module, the third estimated latency for the cache module to send a single request to the memory, and the fourth estimated latency for the memory to return a single piece of data to the cache module. Therefore, the first estimated read duration can represent the estimated upper limit of the data reading time in the current task. In this way, when the estimated calculation time of the current task is greater than the first estimated reading time and less than the second estimated reading time, the prefetch information can be determined as the first prefetch information indicating that the data prefetch function is enabled, so that data reading and prefetching can be achieved through a single data request, thereby reducing the data request pressure between the request source and the cache module, improving system performance, and improving the cache hit rate, thereby reducing the data reading time in the current task, so that the data reading time is more covered by the calculation time, that is, reducing the impact of the data reading time on the computing efficiency, thereby better balancing the computing time and data access time during task execution.

The following describes the application of the data reading method provided by the embodiment of the present invention in a practical scenario, using an example of a data prefetch process accompanied by instruction-controlled read requests based on a combination of software and hardware.

Optimizing processor memory access performance is a hot topic in computer architecture. To address the delay problem caused by the mismatch between the access rate of memory (such as memory, etc.) and the computing rate of the computing module in the processor, a cache module can be designed in the processor to make the data read and write rate adapt to the computing rate of the computing module, thereby improving system performance. Figure 5A is a schematic diagram of a data cache implementation architecture provided by an embodiment of the present invention. As shown in Figure 5A, the architecture includes: computing module 511, register 512, cache module 513 and memory 514. Data can be input and/or output between the computing module 511, cache module 513 and memory 514. The computing module 511 can read data from the cache module 513 , the register 512 , and/or the memory 514 , perform operations, and store the operation results in the cache module 513 , the register 512 , and/or the memory 514 .

Among related technologies, most processors use data prefetching technology. By predicting future memory accesses and issuing access requests for corresponding memory blocks before explicit access, the data in the memory blocks can be fetched into the cache module in advance, thereby improving the cache hit rate.

In some related technologies, data prefetching can be implemented using software prefetching. In this software prefetching method, the processor supports prefetch instructions. The application software running in the processor can send the address of the data to be prefetched to the processor hardware in the form of a prefetch instruction, instructing the cache module to prefetch data based on the address. For example, in a loop-based computing scenario, application software can allocate 1, 2, or even 4 times the amount of register space per loop based on the processor's hardware resources to store prefetched data. Before starting the loop, multiple read requests following the current loop can be issued in advance to prefetch data, and the prefetched data can be stored in the additional allocated register space. In this way, although this software prefetching method only requires ordinary read requests and does not require additional hardware architecture support, the required on-chip register space is 1 to 4 times the original amount. Furthermore, on parallel processors, this will reduce task concurrency by increasing the amount of registers consumed by a single task. This problem is particularly pronounced in graphics memory architectures with limited on-chip register resources. Furthermore, downstream request paths and data return paths cannot accurately distinguish between prefetch requests and requests from the current loop. In a multi-processor parallel architecture, prefetch requests from some processors may block normal memory access requests from other processors, reducing the number of tasks that can be run in parallel.

In some related technologies, hardware prefetching can be used to automatically prefetch data. This hardware prefetching approach involves extending the cache module's hardware functionality. When a data request is sent to the cache module for a cache block address hit query, the cache module automatically determines the address to be prefetched based on a pre-set prefetch strategy and prefetches data based on that address. For example, the cache module can automatically perform a hit query on the next cache unit or units (referred to as prefetch blocks) immediately following the cache unit corresponding to the read request address. If the prefetch block is missing, the request is forwarded to a lower-level cache or memory. This approach eliminates the need for the request source to send separate read and prefetch requests, simplifying user programming complexity. However, prefetching cannot be controlled on a per-task basis. In some scenarios, prefetched data may replace in-use data in the cache, resulting in worse performance than if this approach were not used.

Based on this, an embodiment of the present invention provides a data reading method that uses a combination of hardware and software. By prefetching data used in subsequent loops and caching it in the cache module's storage space, there is no additional register usage overhead, which does not affect the number of parallel tasks allocated. Moreover, by carrying the prefetch data length with the read data request to the cache module for parsing and decomposition, no additional request path pressure is introduced, thereby compressing the request bandwidth. The prefetch data length can be configured by instruction on a task-by-task basis, allowing for flexible and convenient prefetch control of detailed instructions to better meet the prefetch requirements of tasks. In addition, the data reading method is also compatible with multiple cache modes, such as multi-level cache mode and sector mode.

In some embodiments, the data reading method provided by the present invention may be implemented with the following six aspects in mind: First, designing the instruction set.

Here, a read data instruction that supports prefetch control can be extended in the instruction set. In an embodiment of the present invention, the extended read data instruction reuses the read request address and read data length of the ordinary read instruction in the related art, and extends the modification of the prefetch data length. In this way, the prefetch data length can be used to describe the data length of the data to be prefetched with the read request address plus the read data length as the prefetch start address, without the need for a separate prefetch instruction or adding the transmission of the prefetch start address to the instruction set. In addition, when using the extended read data instruction, there is no need for additional prefetch start address calculation overhead and prefetch start address transmission overhead.

In some implementations, the modification method for extending the prefetch data length in read data instructions can be selected from the following two methods: 1) Type code expansion: If the current architecture has sufficient reserved code for instruction types, the instruction type can be distinguished as a read instruction (i.e., read-only type) or a read-with-prefetch instruction; 2) Adding a bit field: An additional bit field (corresponding to the prefetch control code) is added to indicate the prefetch data length, and a code of 0 can be reserved to indicate that prefetching is disabled (i.e., no data prefetching is performed). For example, these two methods for extending the prefetch data length can be shown in Table 1 below.

Table 1 Schematic diagram of two methods for extending the prefetch data length Encoding support method Encoding example before expansion Example of coding for extending the prefetch data length Type encoding extension 0'b101: Read 0'b110: Reserved 0'b111: Reserved 0'b101: Read 0'b110: Read and prefetch the next cache block 0'b111: Read and prefetch the next two cache blocks New bit fields without Prefetch control code: 0'b0: disable prefetch 0'b1: prefetch next memory block

In some implementations, to be forward compatible with the instruction set, the default value of the prefetch control encoding bit field is configured to indicate that prefetch is disabled.

Second, design the interface signals of the cache module.

The cache module interface signal design is similar to instruction set design. In implementation, the cache module interface signal can retain the existing read request address and read data length, while extending the prefetch data length modification. The request source simply sends the prefetch data length along with the read data request to the downstream cache module, which then passes the prefetch data length to the cache module for parsing and splitting.

The extended prefetch data length modification in the cache module interface signals is similar to the instruction set design, supporting two categories: 1) Type signal encoding extension: If the current architecture has sufficient reserved encoding for the request type, the request type signal can be used to directly distinguish between read-only requests and read requests with prefetch; 2) New prefetch control signal: The prefetch data length can be indicated by adding an additional prefetch control signal. The prefetch control signal can reserve the encoding of 0 to indicate that prefetch is disabled (i.e., no data prefetch is performed).

In some implementations, the design of interface signals may also consider compression of control information to increase information entropy.

Third, the amount of data requested in a single read request affects the data.

In some implementations, read requests sent to the cache module are processed in the following order: request splitting, cache block alignment, and hit detection. The module ultimately requests data from memory and returns the read data to the upstream request source and/or caches pre-fetched data into the cache block of the cache module.

Request Splitting: At the entry point of the cache module, read requests whose data length exceeds one cache block length are split and aligned according to the cache block length. The address range corresponding to the read request address and the read data length is split and aligned to obtain multiple read sub-requests. The address range corresponding to the prefetch start address (obtained by adding the read data length to the read request address) and the prefetch data length is split and aligned to obtain multiple prefetch sub-requests. Each read sub-request and prefetch sub-request can be independently checked for cache block hits.

Cache block alignment: A cache block is the basic unit of data allocation and management in the cache module. If the amount of data to be read from a single read request sent by the request source does not fit within a cache block, the cache module will align the address range corresponding to the read request address and the read data length according to the cache block length. If the amount of data to be prefetched from a single read request sent by the request source does not fit within a cache block, the cache module will align the address range corresponding to the prefetch start address and the prefetch data length according to the cache block length.

Cache block hit detection: The split read sub-request and prefetch sub-request are both sent to the cache block hit detection unit for cache block hit detection. If a cache block miss occurs in a read sub-request or prefetch sub-request, the cache module allocates cache space for the missed read sub-request or prefetch sub-request, records and updates the read sub-request or prefetch sub-request, transmits the missed read sub-request or prefetch sub-request to a downstream cache module or memory, and obtains the read data (corresponding to the first target data) or prefetched data (corresponding to the second target data) from the downstream cache module or memory. The read data is returned to the request source, and the prefetched data is cached in at least one cache block of the cache module.

Fourth, it must be compatible with the cache module's sector-supported mode.

In some implementations, where the current architecture supports more granular control over cache, a single request is permitted to be a subset of a cache block. For example, a cache block is 128 bytes and has four cache sectors. This allows the request source to issue read requests to the cache module in multiples of 32 bytes (i.e., the length of a cache sector), while cache blocks are still allocated based on the cache block length (e.g., 128 bytes). In this case, the corresponding prefetched data length in the read request can be a multiple of the cache sector length.

Fifth, it is compatible with multi-level cache mode.

In a multi-level cache scenario, you can consider request merging and situations where the upstream cache module has a full or partial hit.

Request merging: The data reading method provided by the embodiments of the present invention supports request merging. For example, in a multi-level cache, each read request sent by a request source or upstream cache module carries a prefetched data length. The downstream cache module can merge multiple read requests for overlapping cache blocks/sectors, with the merged request carrying only a single prefetched data length. Because the prefetch start address is the read request address plus the read data length, the prefetch data corresponding to the merged read request will fall within the address range between the read request address of the first read request, the read request address of the last read request plus the read data length, and the address following the prefetch data length.

Situation of full or partial hit in the upstream cache module: In the data reading method provided by the embodiment of the present invention, if multiple read sub-requests corresponding to the read data request sent by the request source partially hit in the upstream cache module, the read sub-requests that missed can carry the pre-fetched data length to the downstream cache module; if multiple read sub-requests corresponding to the read data request sent by the request source all hit in the upstream cache module, the first sub-target data cached in the upstream cache module for the multiple read sub-requests are merged to obtain the first target data corresponding to the read data request, and the first target data is returned to the request source, and the pre-fetched data length is discarded.

Sixth, scene selection.

Based on the characteristics of computation and memory access, tasks are typically categorized as either compute-intensive or memory-intensive. The quotient of computational scale and computational parallelism (i.e., throughput) is used as computation time, while the quotient of the amount of data required for computation and memory access bandwidth is defined as memory access time. For example, if a task's computation time is greater than its memory access time, it can be classified as compute-intensive; if its computation time is less than its memory access time, it can be classified as memory-intensive.

Figure 5B is a schematic diagram illustrating the interaction between the various modules in a data reading method provided by an embodiment of the present invention. As shown in Figure 5B , a request source 521 sends a read request, representing a read request with prefetching, to a cache module 522. In response to receiving the read request, cache module 522 can send a read request and a prefetch request to memory 523, and receive the read data and prefetched data returned by memory 523. Cache module 522 returns the received read data to request source 521 and caches the prefetched data into cache module 522's storage space. The time from request source 521 requesting data to the return of the read data can be divided into four phases: delays 0 to 3. Delay 0 represents the estimated latency for request source 521 to send a single request to cache module 522. Delay 1 represents the estimated latency for cache module 522 to send a single request to memory 523. Delay 2 represents the estimated latency for memory 523 to return a single piece of data to cache module 522. Delay 3 represents the estimated latency for cache module 522 to return a single piece of data to request source 521.

Without prefetching, the data reading time = the amount of data requested by the current task / target bandwidth + delay 0 + delay 1 + delay 2 + delay 3; where target bandwidth is the data bandwidth between the request source 521 and the cache module 522.

When prefetching, the required data is pre-fetched into the cache. When the data is requested again, it will be found in the cache module and returned directly. Therefore, there is no request delay to memory due to cache misses, and Delay 1 and Delay 2 do not need to be considered. Therefore, when prefetching, the time to read data = the amount of data requested by the current task / the target bandwidth + Delay 0 + Delay 3.

In some implementations, if the estimated computation time of the current task meets the following conditions, an instruction type code or prefetch control code can be used to indicate that data prefetching (i.e., the prefetch data length is greater than 0) is enabled for a read instruction. This reduces the impact of data read time on computation efficiency, thereby better balancing computation time and data access time during task execution: Current task requested data amount/target bandwidth + Delay 0 + Delay 3 < Current task estimated computation time < Current task requested data amount/target bandwidth + Delay 0 + Delay 1 + Delay 2 + Delay 3.

If the estimated calculation duration of the current task exceeds the current task's requested data volume/target bandwidth + Delay 0 + Delay 1 + Delay 2 + Delay 3, a read instruction can be used to disable data prefetching (i.e., the prefetch data length is equal to 0) using either the instruction type code or the prefetch control code.

The following describes the application of the data reading method provided by the embodiment of the present invention by taking a scenario of continuously accessing data from the memory in a loop with 128 bytes requested per loop as an example.

The request data address is defined as 128-byte aligned. Each read request can request 128 bytes of data (i.e., the read data length is 128 bytes), and the prefetch data length is 128 bytes. Figure 5C is a schematic diagram of an implementation of a read data request with prefetch data length provided by an embodiment of the present invention. As shown in Figure 5C, assuming the prefetched data has already been returned to the cache before the next loop, the processing in different loops is as follows: The first loop is loop 0. In loop 0, the request source requests the 128-byte starting address (cache block 0) and the prefetched 128-byte data (cache block 1). In loop 1, the request source requests cache block 1. Cache block 1 can hit the cache module and is returned to the request source with a shorter latency. A request to prefetch cache block 2 is then sent to the downstream cache module or memory. In loop 2, the request source requests cache block 2. Cache block 2 can be hit in the cache module, returned to the request source with a shorter latency, and a request to prefetch cache block 3 is sent to the downstream cache module or memory.

In loop 3, the request source requests cache block 3. Cache block 3 can be hit in the cache module and returned to the request source with a shorter delay, and the loop ends.

As can be seen, in the scenario of continuously accessing data from memory in a loop, when the pipeline is fully loaded, after adding support for the prefetch function, the data requested by each read request will be hit in the cache and returned to the request source with shorter latency.

FIG6 is a schematic diagram showing the structure of a chip according to an embodiment of the present invention. As shown in Figure 6, chip 600 includes a computing module 610 and a cache module 620, wherein: Computing module 610 is configured to: obtain a read instruction; the read instruction is configured to instruct data reading according to read information and data prefetching according to prefetch information; obtain a first read request based on the read instruction; the first read request includes the read information and the prefetch information; send the first read request to the cache module, so that the cache module responds to the first read request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; and receive the first target data returned by the cache module; The cache module 620 is configured to: receive a first read request sent by the computing module, the first read request being used to request data reading according to read information and data prefetching according to prefetch information; obtain the read information and prefetch information based on the first read request; read first target data from the cache module's storage space and/or memory based on the read information, and return the first target data to the computing module; and prefetch second target data from the memory based on the prefetch information, and cache the second target data into at least one cache unit of the cache module.

The description of the processor embodiment described above is similar to the description of the method embodiment described above, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the processor provided by the embodiments of the present invention can be used to execute the methods described in the method embodiments described above. For technical details not disclosed in the processor embodiment of the present invention, please refer to the description of the method embodiment of the present invention for understanding.

An embodiment of the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, some or all of the steps in the above method are implemented, or the processor comprises the chip described in the above embodiment.

An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above method. The computer-readable storage medium may be transient or non-transient.

An embodiment of the present invention provides a computer program, comprising computer-readable codes. When the computer-readable codes are executed in a computer device, a processor in the computer device executes the program to implement part or all of the steps in the above method.

Embodiments of the present invention provide a computer program product comprising a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, some or all of the steps of the above-described method are implemented. The computer program product can be implemented in hardware, software, or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium. In other embodiments, the computer program product is embodied as a software product, such as a software development kit (SDK).

It should be noted that the above descriptions of the various embodiments tend to emphasize the differences between them, and reference can be made to the similarities and similarities between them. The descriptions of the above embodiments of the apparatus, storage medium, computer program, and computer program product are similar to the descriptions of the above-mentioned method embodiments and have similar beneficial effects as the method embodiments. For technical details not disclosed in the apparatus, storage medium, computer program, and computer program product embodiments of the present invention, please refer to the descriptions of the method embodiments of the present invention for an understanding.

FIG7 is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. As shown in FIG7 , the hardware structure of the computer device 700 includes a processor 701 and a memory 702. The memory 702 stores a computer program that can be executed on the processor 701. When the processor 701 executes the program, the steps of the method according to any of the above embodiments are implemented.

Memory 702 stores computer programs that can be run on the processor. Memory 702 is configured to store instructions and applications that can be executed by processor 701. It can also cache data to be processed or processed by processor 701 and various modules in computer device 700 (for example, image data, audio data, voice communication data, and video communication data). This can be achieved through flash memory (FLASH) or random access memory (RAM).

When the processor 701 executes a program, it implements the steps of any of the above-mentioned data reading methods. The processor 701 generally controls the overall operation of the computer device 700.

An embodiment of the present invention provides a computer storage medium storing one or more programs. The one or more programs can be executed by one or more processors to implement the steps of the data reading method of any of the above embodiments.

It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present invention, please refer to the description of the method embodiments of the present invention for understanding.

The processor can be at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic device implementing the functions of the processor can also be other types, and the embodiments of the present invention are not specifically limited thereto.

The computer storage medium/memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface area memory, an optical disc, or a compact disc read-only disc (CDR). Memory, CD-ROM) and other memories; it can also be various terminals that include one or any combination of the above memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present invention, the size of the serial numbers of the above-mentioned steps/processes does not mean the order of execution. The execution order of each step/process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention. The above-mentioned serial numbers of the embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprise," "include," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

In addition, the various functional units in the various embodiments of the present invention may all be integrated into a single processing unit, each unit may be a separate unit, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or a combination of hardware and software functional units. A person skilled in the art will appreciate that all or part of the steps of the aforementioned method embodiments may be performed by hardware associated with program instructions. The aforementioned program may be stored in a computer-readable storage medium. When executed, the program performs the steps of the aforementioned method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as a mobile storage device, a read-only memory (ROM), a magnetic disk, or an optical disk.

Alternatively, if the integrated unit of the present invention is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the relevant technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

The above is only an embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technical personnel familiar with this technical field within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention.

S101, S102, S103, S104, S111, S112, S113, S114, S115, S121, S122, S123, S125, S201, S202, S203, S204, S205, S211, S212, S213, S214, S221, S231, S232, S301, S302, S303, S 304, S305, S306, S311, S401, S402, S403, S404, S411, S421, S423, S431, S432, S441, S442, S443, S451, S452, S461, S462, S471, S472, S473, S481, S482, S491, S492, S493: Steps 511, 610: Computing module 512: Register 513, 522, 620: Cache module 514, 523, 702: Memory 521: Request source 600: Chip 700: Computer device 701: Processor

The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present invention and, together with the specification, are used to illustrate the technical solutions of the present invention.

FIG1 is a schematic diagram of an implementation process of a data reading method provided by an embodiment of the present invention.

FIG2 is a schematic diagram of an implementation process of a data reading method provided by an embodiment of the present invention.

FIG3 is a schematic diagram of an implementation process of a data reading method provided by an embodiment of the present invention.

FIG4 is a schematic diagram of an implementation process of a data reading method provided by an embodiment of the present invention.

FIG5A is a schematic diagram of an implementation architecture of a data cache provided by an embodiment of the present invention.

FIG5B is a schematic diagram illustrating the interaction between modules in a data reading method provided by an embodiment of the present invention.

FIG5C is a schematic diagram illustrating an implementation of a read data request carrying pre-fetched data length provided by an embodiment of the present invention.

FIG6 is a schematic diagram of the composition structure of a chip provided by an embodiment of the present invention.

FIG7 is a schematic diagram of a hardware structure of a computer device provided in an embodiment of the present invention.

S401, S402, S403, S404: Steps

Claims (23)

A data reading method for a chip comprises the following steps: Obtaining a read instruction; the read instruction instructing data reading according to read information and data prefetching according to prefetch information; Obtaining a first read request based on the read instruction; the first read request including the read information and the prefetch information; Sending the first read request to a cache module, causing the cache module to respond to the first read request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; Receiving the first target data returned by the cache module. The data reading method of claim 1, wherein the read information includes a first read request address and a first read data length; and obtaining the read data instruction comprises the following steps: Encoding the instruction based on the first read request address, the first read data length, and the prefetch information to obtain the read data instruction. The data reading method of claim 2, wherein the read data instruction includes an instruction type code, a read request address code, and a read data length code; Encoding the instruction based on the first read request address, the first read data length, and the prefetch information to obtain the read data instruction comprises the following steps: Determining the instruction type code corresponding to the prefetch information from a preset set of instruction type codes; Encoding the first read request address to obtain the read request address code; Encoding the first read data length to obtain the read data length code. The data reading method of claim 3, wherein obtaining a first read data request based on the read data instruction comprises the following steps: Parsing the instruction type code, the read request address code, and the read data length code to obtain prefetch information, the first read request address, and the first read data length; Generating the first read data request based on the prefetch information, the first read request address, and the first read data length. The data reading method of claim 2, wherein the read data instruction includes a read request address code, a read data length code, and a prefetch control code; Encoding the instruction based on the first read request address, the first read data length, and the prefetch information to obtain the read data instruction comprises the following steps: Encoding the first read request address to obtain the read request address code; Encoding the first read data length to obtain the read data length code; Encoding the prefetch information to obtain the prefetch control code. The data reading method of claim 5, wherein obtaining a first read data request based on the read data instruction comprises the following steps: Parsing the read request address code, the read data length code, and the prefetch control code to obtain the first read request address, the first read data length, and the prefetch information; Generating the first read data request based on the prefetch information, the first read request address, and the first read data length. The data reading method of claim 4 or 6, wherein generating the first read data request based on the prefetch information, the first read request address, and the first read data length comprises one of the following steps: Determining a read request address signal, a read data length signal, and a request type signal based on the first read request address, the first read data length, and the prefetch information, respectively, and generating the first read data request based on the read request address signal, the read data length signal, and the request type signal; The read request address signal, the read data length signal, and the prefetch control signal are determined based on the first read request address, the first read data length, and the prefetch information, and the first read data request is generated based on the read request address signal, the read data length signal, and the prefetch control signal. The data reading method of any one of claims 1 to 6, wherein obtaining the data reading instruction comprises the following steps: Obtaining the amount of data to be read and the estimated computation time of the current task; Determining the prefetch information based on the amount of data to be read and the estimated computation time; Determining the data reading instruction based on the prefetch information. The data reading method of claim 8, wherein determining the prefetch information based on the read data amount and the estimated calculation time comprises the following steps: Determining a first estimated reading time corresponding to the read data amount when the data prefetch function is enabled, and a second estimated reading time corresponding to the read data amount when the data prefetch function is disabled; Determining the prefetch information based on a relationship between the estimated calculation time and the first estimated reading time and/or the second estimated reading time. The data reading method of claim 9, wherein determining the prefetch information based on the relationship between the estimated calculation time and the first estimated reading time and/or the second estimated reading time comprises the following steps: If the estimated calculation time is greater than the first estimated reading time and less than the second estimated reading time, determining the prefetch information as first prefetch information indicating activation of the data prefetch function. The data reading method of claim 8, wherein determining a first estimated reading duration corresponding to the amount of data to be read when a data prefetch function is enabled, and a second estimated reading duration corresponding to the amount of data to be read when the data prefetch function is disabled, comprises the following steps: Estimating a latency for sending a single request to the cache module, a latency for the cache module to return a single piece of data, a latency for the cache module to send the single request to a memory, and a latency for the memory to return the single piece of data to the cache module, to obtain a first estimated latency, a second estimated latency, a third estimated latency, and a fourth estimated latency, respectively; The first estimated read duration is determined as the sum of a first ratio between the read data volume of the current task and the target bandwidth, the first estimated latency, and the second estimated latency; the target bandwidth is the data bandwidth between the request source of the first read request and the cache module; The second estimated read duration is determined as the sum of the first ratio, the first estimated latency, the second estimated latency, the third estimated latency, and the fourth estimated latency. A data reading method for a chip comprises the following steps: Receiving a first read data request sent by a request source, the first read data request being used to request data reading according to read information and data prefetching according to prefetch information; According to the first read data request, obtaining the read information and prefetch information; Based on the read information, reading first target data from storage space and/or memory of a cache module and returning the first target data to the request source; Based on the prefetch information, prefetching second target data from the memory and caching the second target data into at least one cache unit of the cache module. The data reading method of claim 12, wherein the prefetch information includes a prefetch data length; Prefetching the second target data from the memory based on the prefetch information and caching the second target data into at least one cache unit of the cache module comprises the following steps: If the prefetch data length is greater than 0, determining a prefetch start address based on the first read request address and the first read data length; Prefetching the second target data from the memory based on the prefetch start address and the prefetch data length, and caching the second target data into at least one cache unit of the cache module. The data reading method of claim 13, wherein the read information includes the first read request address and the first read data length; Acquiring the read information and the prefetch information based on the first read data request comprises one of the following steps: Separately parsing the request type signal, the read request address signal, and the read data length signal in the first read data request to obtain the first request type, the first read request address, and the first read data length, and determining the prefetch data length based on the first request type; Separately parsing the read request address signal, the read data length signal, and the prefetch control signal in the first read data request to obtain the first read request address, the first read data length, and the prefetch data length. The data reading method of claim 13, wherein prefetching the second target data from the memory based on the prefetch start address and the prefetch data length and caching the second target data into at least one cache unit of the cache module comprises the following steps: Determining at least one prefetch sub-request based on the prefetch start address and the prefetch data length, wherein the data request length corresponding to each prefetch sub-request is equal to the cache unit length of the cache module; For each prefetch sub-request, a cache unit hit test is performed in the storage space of the cache module based on the prefetch sub-request to obtain a first test result. If the first test result indicates that the cache unit corresponding to the prefetch sub-request is missed, the second target data is prefetched from the memory based on the prefetch sub-request and cached into at least one cache unit of the cache module. The data reading method as described in claim 13, wherein the length of the pre-fetched data is an integer multiple of the length of the cache unit, and the cache unit includes a cache block or a cache sector. The data reading method of claim 12, wherein the number of the first read data requests is multiple; the read information includes a first read request address and a first read data length; Reading the first target data from the storage space and/or memory of the cache module based on the read information comprises the following steps: For each first read data request, determining the cache unit corresponding to the first read data request based on the first read request address and the first read data length corresponding to the first read data request; If the cache units corresponding to the multiple first read data requests overlap, merging the first read request addresses and first read data lengths corresponding to the multiple first read data requests to obtain a merged first read request address and first read data length, and merging the prefetch information corresponding to the multiple first read data requests to obtain a merged prefetch information; Based on the merged first read request address and first read data length, retrieving the first target data from the storage space and/or memory of the cache module; Prefetching the second target data from the memory based on the prefetch information and caching the second target data into at least one cache unit of the cache module comprises the following steps: Prefetching the second target data from the memory based on the merged prefetch information and caching the second target data into at least one cache unit of the cache module. The data reading method of claim 17, wherein merging the prefetch information corresponding to the multiple first read data requests to obtain the merged prefetch information comprises the following steps: Determining the prefetch information corresponding to the first read data request with the latest first read request address among the multiple first read data requests as the merged prefetch information. The data reading method of any one of claim items 12 to 18, wherein the first target data includes at least one first sub-target data, and the cache module includes a first cache sub-module and a second cache sub-module; Receiving a first read data request sent by a request source comprises the following steps: The first cache sub-module receives the first read data request sent by the request source; Acquiring the read information and the prefetch information based on the first read data request comprises the following steps: The first cache sub-module acquires the read information and the prefetch information based on the first read data request; the read information includes the first read request address and the first read data length; Reading first target data from the storage space and/or memory of the cache module based on the read information and returning the first target data to the request source comprises the following steps: The first cache submodule determines at least one read data sub-request based on the first read request address and the first read data length, wherein the data request length corresponding to each read data sub-request is equal to the cache unit length of the first cache submodule; the first cache submodule obtains first sub-target data corresponding to each read data sub-request from the storage space of the first cache submodule, the storage space of the second cache submodule, and/or the memory, and returns each first sub-target data to the request source; Prefetching the second target data from the memory based on the prefetch information and caching the second target data into at least one cache unit of the cache module comprises the following steps: The second cache submodule prefetches the second target data from the memory based on the prefetch information and caches the second target data into at least one cache unit of the second cache submodule. The data reading method of claim 19, wherein the first cache sub-module obtains first sub-target data corresponding to each read data sub-request from the storage space of the first cache sub-module, the storage space of the second cache sub-module, and/or the memory, comprising the following steps: Based on each read data sub-request, the first cache sub-module performs a cache unit hit check in the storage space of the first cache sub-module to obtain a second check result corresponding to each read data sub-request; For each read data sub-request, if the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is a hit, the first cache sub-module reads the first sub-target data corresponding to the read data sub-request from the hit cache unit. If the second detection result corresponding to the read data sub-request indicates that the cache unit corresponding to the read data sub-request is a miss, the first cache sub-module sends a second read data request to the second cache sub-module based on the second read request address and second read data length corresponding to the read data sub-request, as well as the prefetch information, and receives the first sub-target data corresponding to the read data sub-request returned by the second cache sub-module. The second cache submodule prefetches the second target data from the memory based on the prefetch information, comprising the following steps: In response to receiving a second read data request sent by the first cache submodule, the second cache submodule parses the second read data request to obtain a second read request address, a second read data length, and the prefetch information; Based on the second read request address and the second read data length, the second cache submodule obtains the first subtarget data from the storage space and/or the memory of the second cache submodule, and returns the first subtarget data to the first cache submodule; Based on the prefetch information, the second cache submodule prefetches the second target data from the memory, and caches the second target data into at least one cache unit of the second cache submodule. A chip comprises: A computing module configured to: obtain a read instruction; the read instruction is configured to instruct data reading according to read information and data prefetching according to prefetch information; obtain a first read request based on the read instruction; the first read request includes the read information and the prefetch information; send the first read request to a cache module, causing the cache module to respond to the first read request by reading and returning first target data according to the read information and prefetching and caching second target data according to the prefetch information; and receive the first target data returned by the cache module; The cache module is configured to: receive the first read data request sent by the computing module, the first read data request being used to request data reading according to the read information and data prefetching according to the prefetch information; obtain the read information and the prefetch information based on the first read data request; read the first target data from the storage space and/or memory of the cache module based on the read information, and return the first target data to the computing module; and prefetch the second target data from the memory based on the prefetch information, and cache the second target data into at least one cache unit of the cache module. A computer device includes a memory and a processor, wherein the memory stores a computer program that can be executed on the processor, wherein when the processor executes the computer program, the steps in the data reading method described in any one of claims 1 to 20 are implemented, or the processor includes the chip described in claim 21. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the data reading method as described in any one of claims 1 to 20 are implemented.