TW202517812A - Gapfill process using pulsed high-frequency radio-frequency (hfrf) plasma - Google Patents
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Abstract
Description
相關申請的交叉引用Cross-references to related applications
本案是於2021年1月25日提出申請的美國專利申請第17/157,307號的部分繼續申請,所述專利申請的全部公開內容藉由引用併入本文。This case is a continuation-in-part of U.S. patent application No. 17/157,307 filed on January 25, 2021, the entire disclosure of which is incorporated herein by reference.
本案整體上涉及用於間隙填充的方法。具體地,本案涉及使用脈衝高頻射頻(HFRF)電漿來填充間隙的製程。The present invention relates generally to methods for gap filling and more particularly to processes for gap filling using pulsed high frequency radio frequency (HFRF) plasma.
在微電子裝置製造中,對於許多應用,需要填充具有大於10:1的深寬比(AR)的窄溝槽而沒有空隙。一種應用是用於淺溝槽隔離(STI)。對於這種應用,膜需要在整個溝槽中具有高品質(例如,具有小於2的濕蝕刻速率比)並且具有非常低的洩漏。過去取得成功的一種方法是可流動CVD。在這種方法中,在氣相中小心地形成低聚物,所述低聚物冷凝在表面上,然後「流動」到溝槽中。沉積態的膜品質非常差,並且需要處理步驟,諸如蒸汽退火和UV固化。In microelectronic device fabrication, for many applications, narrow trenches with aspect ratios (AR) greater than 10:1 need to be filled without voids. One application is for shallow trench isolation (STI). For this application, the film needs to be of high quality throughout the trench (e.g., have a wet etch rate ratio of less than 2) and have very low leakage. One approach that has been successful in the past is flowable CVD. In this approach, oligomers are carefully formed in the gas phase, condense on the surface, and then "flow" into the trench. The as-deposited film quality is very poor and requires processing steps such as steam annealing and UV curing.
隨著結構尺寸的減小和深寬比的增加,沉積態的可流動膜的後固化方法變得困難。導致在整個所填充溝槽中具有不同組成的膜。As feature sizes decrease and aspect ratios increase, post-curing of as-deposited flowable films becomes difficult, resulting in films with varying compositions throughout the filled trenches.
非晶矽已被廣泛用於半導體製造製程中作為犧牲層,因為非晶矽可以提供相對於其他膜(例如,氧化矽、非晶碳等)的良好蝕刻選擇性。隨著半導體製造中臨界尺寸(CD)的減小,對於先進晶片製造,填充高深寬比間隙變得越來越敏感。當前的金屬替代閘極製程涉及熔爐多晶矽或非晶矽虛擬閘極。由於製程的性質,在Si虛擬閘極的中間形成接縫。這種接縫可能在後處理期間打開並導致結構失效。Amorphous silicon has been widely used as a sacrificial layer in semiconductor manufacturing processes because it can provide good etch selectivity relative to other films (e.g., silicon oxide, amorphous carbon, etc.). With the reduction of critical dimensions (CD) in semiconductor manufacturing, filling high aspect ratio gaps has become increasingly sensitive for advanced wafer manufacturing. The current metal replacement gate process involves either melt polysilicon or amorphous silicon virtual gate. Due to the nature of the process, a seam is formed in the middle of the Si virtual gate. This seam may open during post processing and cause structural failure.
非晶矽(a-Si)的一般電漿增強化學氣相沉積(PECVD)在窄溝槽的頂部形成「蘑菇形狀」的膜。這是由於電漿不能穿透到深溝槽中。結果是狹窄的溝槽從頂部被夾斷;在溝槽的底部形成空隙或接縫。Conventional plasma enhanced chemical vapor deposition (PECVD) of amorphous silicon (a-Si) forms a "mushroom-shaped" film at the top of narrow trenches. This is due to the inability of the plasma to penetrate into deep trenches. The result is that the narrow trench is pinched off from the top; a void or seam is formed at the bottom of the trench.
一般的熱CVD/爐製程可以經由矽前驅物(例如,矽烷、二矽烷)的熱分解來生長a-Si。然而,由於前驅物供應不足或分解副產物的存在,與溝槽底部的沉積速率相比,溝槽頂部的沉積速率更高。在溝槽中可以觀察到狹窄的接縫或空隙。Conventional thermal CVD/furnace processes can grow a-Si via thermal decomposition of silicon precursors (e.g., silane, disilane). However, due to insufficient precursor supply or the presence of decomposition byproducts, the deposition rate at the top of the trench is higher than the deposition rate at the bottom of the trench. Narrow seams or voids can be observed in the trench.
另外,許多半導體裝置應用包括保形襯墊。隨著裝置尺寸的縮小,金屬碳化物(例如碳化鎢)的一般電漿增強化學氣相沉積在窄溝槽的頂部上形成蘑菇形膜,其中在側壁處膜非常薄。由於電漿不能穿透到深溝槽中,因此這種形狀的膜不能用作保形襯墊。Additionally, many semiconductor device applications include conformal pads. As device sizes shrink, conventional plasma enhanced chemical vapor deposition of metal carbides (e.g., tungsten carbide) forms a mushroom-shaped film on top of narrow trenches, where the film is very thin at the sidewalls. Since plasma cannot penetrate into deep trenches, films of this shape cannot be used as conformal pads.
因此,需要用於在半導體裝置中形成金屬碳化物保形襯墊的方法。Therefore, there is a need for methods for forming metal carbide conformal pads in semiconductor devices.
本案的一或多個實施例涉及間隙填充的方法。將基板的基板表面暴露於沉積製程,所述沉積製程包括具有複數個HFRF脈衝的脈衝高頻射頻(HFRF)電漿以沉積襯墊。基板表面具有形成在基板表面中的複數個特徵。複數個特徵中的每一個從基板表面延伸到基板中一定距離並且具有底部和至少一個側壁。襯墊包括金屬碳化物。One or more embodiments of the present invention relate to a method of gap filling. A substrate surface of a substrate is exposed to a deposition process, the deposition process including a pulsed high frequency radio frequency (HFRF) plasma having a plurality of HFRF pulses to deposit a liner. The substrate surface has a plurality of features formed in the substrate surface. Each of the plurality of features extends a distance from the substrate surface into the substrate and has a bottom and at least one sidewall. The liner includes a metal carbide.
本案的另外的實施例涉及使用HFRF形成襯墊的方法。金屬碳化物襯墊形成在基板表面中形成的複數個特徵的側壁上。每個特徵從基板表面延伸到基板中一定距離並且具有至少一個側壁。形成襯墊包括將基板暴露於具有複數個襯墊HFRF脈衝的化學氣相沉積製程。Another embodiment of the present invention relates to a method of forming a liner using HFRF. A metal carbide liner is formed on the sidewalls of a plurality of features formed in a substrate surface. Each feature extends a distance from the substrate surface into the substrate and has at least one sidewall. Forming the liner includes exposing the substrate to a chemical vapor deposition process having a plurality of liner HFRF pulses.
本案的進一步實施例涉及在半導體裝置中形成襯墊的方法。金屬碳化物襯墊形成在基板表面中形成的複數個特徵的側壁上。每個特徵從基板表面延伸到基板中一定距離並且具有至少一個側壁。形成金屬碳化物襯墊包括使用含鎢前驅物、含鉬前驅物或含鎳前驅物中的一者或多者以及複數個襯墊HFRF脈衝將基板暴露於化學氣相沉積製程,以形成具有拉伸應力的金屬碳化物襯墊。Further embodiments of the present invention relate to methods of forming a pad in a semiconductor device. A metal carbide pad is formed on the sidewalls of a plurality of features formed in a substrate surface. Each feature extends a distance from the substrate surface into the substrate and has at least one sidewall. Forming the metal carbide pad includes exposing the substrate to a chemical vapor deposition process using one or more of a tungsten-containing precursor, a molybdenum-containing precursor, or a nickel-containing precursor and a plurality of pad HFRF pulses to form a metal carbide pad having a tensile stress.
在描述本案的幾個示例性實施例之前,應理解,本案不限於以下描述中所闡述的構造或者製程步驟的細節。本案能夠具有其他實施例,並且能夠以各種方式實踐或執行。Before describing several exemplary embodiments of the present invention, it should be understood that the present invention is not limited to the details of the construction or process steps described in the following description. The present invention is capable of other embodiments and can be practiced or implemented in various ways.
如本文所用,「基板」是指在製造製程期間在其上執行膜處理的任何基板或形成在基板上的材料表面。例如,取決於應用,可以在其上執行處理的基板表面包括材料,諸如矽、氧化矽、應變矽、絕緣體上矽(SOI)、碳摻雜的氧化矽、非晶矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石以及任何其他材料,諸如金屬、金屬氮化物、金屬合金和其他導電材料。基板包括但不限於半導體晶片。基板可以暴露於預處理製程以拋光、蝕刻、還原、氧化、羥基化、退火、UV固化、電子束固化及/或烘烤基板表面。除了直接在基板本身的表面上的膜處理之外,在本案中,所揭示的膜處理步驟中的任一者也可以在如下文更詳細地公開的形成在基板上的底層上進行,並且術語「基板表面」旨在包括如上下文所指示的此類底層。因此,例如,在膜/層或部分膜/層已經沉積到基板表面上的情況下,新沉積的膜/層的暴露表面變成基板表面。As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pre-treatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present case, any of the disclosed film processing steps can also be performed on an underlying layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, where a film/layer or portion of a film/layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.
本案的一或多個實施例提供低溫矽間隙填充製程。藉由首先沉積然後蝕刻一些溝槽結構周圍的矽膜,與溝槽的側壁或頂部相比,在溝槽的底部產生了相當程度的更厚的非晶矽(a-Si)膜量。一些實施例提供了循環沉積和蝕刻以形成無瑕疵矽間隙填充的方法。One or more embodiments of the present invention provide a low temperature silicon gapfill process. By first depositing and then etching some of the silicon film around the trench structure, a substantially thicker amorphous silicon (a-Si) film volume is produced at the bottom of the trench compared to the sidewalls or top of the trench. Some embodiments provide a method for cyclic deposition and etching to form a defect-free silicon gapfill.
本案的實施例提供了在具有小尺寸的高深寬比(AR)結構中沉積膜(例如,非晶矽)的方法。一些實施例有利地提供了涉及可在集群工具環境中執行的循環沉積-蝕刻-處理製程的方法。一些實施例有利地提供無瑕疵摻雜或合金化的高品質非晶矽膜以填充具有小尺寸的高AR溝槽。Embodiments of the present invention provide methods for depositing films (e.g., amorphous silicon) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide methods involving cyclic deposition-etch-treat processes that can be performed in a cluster tool environment. Some embodiments advantageously provide high-quality amorphous silicon films without defective doping or alloying to fill high AR trenches with small dimensions.
圖1圖示具有特徵110的基板100的局部橫截面視圖。為了說明的目的,附圖圖示具有單個特徵的基板;然而,本領域技藝人士將理解,可以存在多於一個特徵。特徵110的形狀可以是任何合適的形狀,包括但不限於溝槽和圓柱形通孔。如在這方面所使用的,術語「特徵」意指任何有意的表面不規則性。特徵的合適示例包括但不限於具有頂部、兩個側壁和底部的溝槽,具有頂部和兩個側壁的峰。特徵可以具有任何合適的深寬比(特徵的深度與特徵的寬度的比率)。在一些實施例中,深寬比大於或等於約5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。FIG. 1 illustrates a partial cross-sectional view of a
基板100具有基板表面120。至少一個特徵110在基板表面120中形成開口。特徵110從基板表面120延伸深度D到底表面112。特徵110具有限定特徵110的寬度W的第一側壁114和第二側壁116。由側壁和底部形成的開放區域也稱為間隙。
在間隙填充製程中,通常在填充材料中形成接縫。接縫的尺寸和寬度可能影響間隙填充部件的整體可操作性。接縫的尺寸和寬度也會受到製程條件和所沉積的材料的影響。因此,一或多個實施例有利地提供了用於無接縫(或無空隙)間隙填充的方法。所述方法的一些實施例有利地揭示用於間隙填充的循環沉積-處理-蝕刻製程。在一些實施例中,間隙填充是無瑕疵的。During a gap filling process, a seam is often formed in the fill material. The size and width of the seam may affect the overall operability of the gap filling component. The size and width of the seam may also be affected by process conditions and the deposited material. Thus, one or more embodiments advantageously provide a method for seamless (or void-free) gap filling. Some embodiments of the method advantageously disclose a cyclic deposition-treatment-etch process for gap filling. In some embodiments, the gap filling is flawless.
圖2和圖3A至圖3D圖示根據本案的一或多個實施例的示例性間隙填充方法200。在圖2所示的實施例中,在具有至少一個特徵110的基板100上執行方法200。在一些實施例中,特徵110具有大於或等於5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1的深寬比。在一些實施例中,方法200包括沉積膜220和蝕刻膜240。在一些實施例中,膜沉積220及/或膜蝕刻240在集群工具環境中的一或多個處理腔室中執行。在一些實施例中,膜沉積220及/或膜蝕刻240包括複數個高頻射頻(HFRF)脈衝。在一或多個實施例中,電漿包括脈衝HFRF電漿。在一些實施例中,脈衝HFRF電漿包括複數個HFRF脈衝。在一些實施例中,脈衝HFRF電漿沉積非保形膜。FIG. 2 and FIG. 3A-3D illustrate an
一些實施例有利地提供了使用電漿在特徵的側壁上比在特徵的底部更快地蝕刻材料(例如,Si)的方法。一些實施例有利地在不同表面和不同位置上使用不同的蝕刻速率,以藉由循環沉積-蝕刻製程來產生自下而上的生長。Some embodiments advantageously provide methods for using plasma to etch material (e.g., Si) faster on the sidewalls of a feature than at the bottom of the feature. Some embodiments advantageously use different etching rates on different surfaces and at different locations to produce bottom-up growth by a cyclic deposition-etching process.
在圖3A所示的實施例中,基板100具有形成在基板100上的特徵110和兩個不同的表面:第一表面350和第二表面360。第一表面350和第二表面360可以是不同的材料。例如,表面中的一個可以是金屬,而另一個可以是介電質。在一些實施例中,第一表面350和第二表面360具有相同的化學組成但不同的物理性質(例如,結晶度)。在描述下面的方法時,對基板100的引用意指第一表面350和第二表面360或其中形成特徵110的單個表面。In the embodiment shown in FIG. 3A ,
在圖3A所示的實施例中,特徵110由第一表面350和第二表面360形成。所示的特徵110是溝槽,其中第一表面350形成特徵的底部,並且第二表面360形成側壁和頂部。3A, feature 110 is formed by a first surface 350 and a second surface 360. The
一些實施例的方法200包括可選的基板預處理210。在一些實施例中,將基板暴露於一或多個製程條件以預處理或製備用於沉積的基板表面。例如,在一些實施例中,預處理使基板表面緻密化或改變表面封端。在一些實施例中,可選的預處理210包括拋光、蝕刻、還原、氧化、羥基化、退火、UV固化、電子束固化、電漿處理及/或烘烤基板表面中的一者或多者。在一些實施例中,電漿處理包括NH
3電漿處理。
Some embodiments of the
在一些實施例中,在襯墊形成製程215中在特徵110中形成襯墊。襯墊形成製程215是可被包括在方法200中或可以是單獨方法的一部分的可選製程。In some embodiments, a pad is formed in the
在沉積製程220處,在基板100上沉積膜370。在一或多個實施例中,沉積膜370包括電漿增強化學氣相沉積(PECVD)製程或電漿增強原子層沉積(PEALD)製程。在一些實施例中,沉積製程220包括PECVD製程。在一些實施例中,沉積製程220包括PEALD製程。在一些實施例中,PECVD包括間隙填充脈衝高頻射頻(HFRF)電漿。在一些實施例中,間隙填充脈衝HFRF電漿包括複數個間隙填充HFRF脈衝。間隙填充脈衝HFRF電漿也可以被稱為「第一」HFRF電漿。諸如「第一」、「第二」等序數的使用用於標識不同的製程或部件,並且不旨在暗示操作或使用的特定順序。At
如本文所用,高頻射頻電漿包括功率的高頻開/關脈衝。開啟時,功率以射頻傳輸。脈衝頻率和射頻是指用於產生電漿的功率的不同態樣,這些態樣可以被獨立地控制。As used herein, high frequency RF plasma includes high frequency on/off pulses of power. When on, the power is delivered at RF. Pulse frequency and RF refer to different aspects of the power used to generate plasma, which aspects can be controlled independently.
膜370可以是可以相對於第二表面360選擇性地沉積在第一表面350上的任何合適的膜。在一些實施例中,膜370包括矽。在一些實施例中,膜370基本上由矽組成。如以這種方式使用的,術語「基本上由……組成」意指膜以原子計大於或等於約90%、93%、95%、98%或99%的矽(或所闡明的物質)。在一些實施例中,膜370包括非晶矽。在一些實施例中,膜370基本上僅包括非晶矽。以這種方式使用的術語「基本上僅非晶矽」意指膜370大於或等於約90%、93%、95%、98%或99%的非晶矽。The film 370 can be any suitable film that can be selectively deposited on the first surface 350 relative to the second surface 360. In some embodiments, the film 370 includes silicon. In some embodiments, the film 370 consists essentially of silicon. As used in this manner, the term "consisting essentially of..." means that the film is greater than or equal to about 90%, 93%, 95%, 98%, or 99% silicon (or a specified substance) in terms of atoms. In some embodiments, the film 370 includes amorphous silicon. In some embodiments, the film 370 consists essentially only of amorphous silicon. The term "essentially only amorphous silicon" used in this manner means that the film 370 is greater than or equal to about 90%, 93%, 95%, 98%, or 99% amorphous silicon.
圖3A圖示形成在特徵110的基板表面(頂部374)、側壁376和底部372上的膜370。沉積在基板上的膜370將在特徵的側壁上具有膜厚度T
s,在特徵的頂部(即,在基板的表面上)具有膜厚度T
t,並且在特徵110的底部具有膜厚度T
b。
3A illustrates film 370 formed on the substrate surface (top 374), sidewalls 376, and bottom 372 of
在一些實施例中,膜370非保形地形成在至少一個特徵上。如本文所用,術語「非保形」或「非保形地」是指黏附到並且非均勻地覆蓋暴露表面的層,其中厚度變化相對於膜的平均厚度大於10%。例如,平均厚度為100Å的膜將具有大於10Å的厚度變化。這種厚度變化包括邊緣、拐角、側面和凹槽的底部。在一些實施例中,所述變化大於或等於10%、15%、20%、25%、30%、35%、40%、45%、50%、55%、60%、65%、70%、75%、80%、85%或90%。在一些實施例中,沉積在溝槽的側壁上的膜比沉積在溝槽底部或其中形成溝槽的表面上的膜的厚度更薄。在一些實施例中,側壁上的沉積膜的平均厚度小於或等於溝槽的底部及/或頂部上的平均厚度的90%、80%、70%、60%、50%、40%、30%或20%。In some embodiments, the film 370 is formed non-conformally on at least one feature. As used herein, the term "non-conformal" or "non-conformally" refers to a layer that adheres to and covers an exposed surface non-uniformly, wherein the thickness variation is greater than 10% relative to the average thickness of the film. For example, a film with an average thickness of 100Å will have a thickness variation greater than 10Å. Such thickness variations include edges, corners, sides, and the bottom of grooves. In some embodiments, the variation is greater than or equal to 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, or 90%. In some embodiments, the film deposited on the sidewalls of the trench is thinner than the film deposited at the bottom of the trench or on the surface in which the trench is formed. In some embodiments, the average thickness of the deposited film on the sidewalls is less than or equal to 90%, 80%, 70%, 60%, 50%, 40%, 30% or 20% of the average thickness on the bottom and/or top of the trench.
在一些實施例中,在停止沉積之前,將膜370沉積至1nm至100nm、1nm至80nm、1nm至50nm、10nm至100nm、10nm至80nm、10nm至50nm、20nm至100nm、20nm至80nm或20nm至50nm範圍內的平均厚度。在一些實施例中,膜370被沉積至在5nm至100nm、5nm至80nm、5nm至40nm、5nm至30nm或10nm至30nm範圍內的平均厚度。In some embodiments, before stopping the deposition, the film 370 is deposited to an average thickness in the range of 1 nm to 100 nm, 1 nm to 80 nm, 1 nm to 50 nm, 10 nm to 100 nm, 10 nm to 80 nm, 10 nm to 50 nm, 20 nm to 100 nm, 20 nm to 80 nm, or 20 nm to 50 nm. In some embodiments, the film 370 is deposited to an average thickness in the range of 5 nm to 100 nm, 5 nm to 80 nm, 5 nm to 40 nm, 5 nm to 30 nm, or 10 nm to 30 nm.
用於沉積膜370的製程參數可影響特徵的側壁、特徵的頂部及/或特徵的底部處的膜厚度。例如,特定前驅物及/或反應性物質、電漿條件、溫度等。在一些實施例中,特徵的頂部處的厚度T t大於特徵的側壁處的厚度T s。在一些實施例中,特徵的底部處的厚度T b大於特徵的側壁處的厚度T s。在一些實施例中,特徵的頂部處的厚度T t大於特徵的底部處的厚度T b。在一些實施例中,特徵的底部處的厚度T b大於特徵的頂部處的厚度T t。 The process parameters used to deposit film 370 can affect the film thickness at the sidewalls of the feature, the top of the feature, and/or the bottom of the feature. For example, specific precursors and/or reactive species, plasma conditions, temperature, etc. In some embodiments, the thickness Tt at the top of the feature is greater than the thickness Ts at the sidewalls of the feature. In some embodiments, the thickness Tb at the bottom of the feature is greater than the thickness Ts at the sidewalls of the feature. In some embodiments, the thickness Tt at the top of the feature is greater than the thickness Tb at the bottom of the feature. In some embodiments, the thickness Tb at the bottom of the feature is greater than the thickness Tt at the top of the feature.
在膜沉積220製程期間,將基板暴露於形成膜370的一或多個製程氣體及/或條件。在一些實施例中,處理氣體流入處理腔室的處理區域,並且由處理氣體形成脈衝HFRF電漿以沉積膜370。一些實施例的製程氣體包括矽前驅物和載氣,並且載氣藉由HFRF功率點燃成電漿。During the
在一或多個實施例中,間隙填充脈衝HFRF電漿是導電耦合電漿(CCP)或電感耦合電漿(ICP)。在一些實施例中,間隙填充脈衝HFRF電漿是直接電漿或遠程電漿。在一些實施例中,複數個間隙填充HFRF脈衝中的每一個是在0 W至500 W、50 W至500 W、50 W至400 W、50 W至300 W、50 W至200 W、50 W至100 W、100 W至500 W、100 W至400 W、100 W至300 W、100 W至200 W、200 W至500 W、200 W至400 W或200 W至300 W範圍內的間隙填充功率下獨立地產生的。在一些實施例中,最小間隙填充電漿功率大於0W。在一些實施例中,所有間隙填充脈衝具有相同的功率。在一些實施例中,間隙填充HFRF電漿中的各個脈衝功率變化。In one or more embodiments, the gap-filling pulsed HFRF plasma is a conductively coupled plasma (CCP) or an inductively coupled plasma (ICP). In some embodiments, the gap-filling pulsed HFRF plasma is a direct plasma or a remote plasma. In some embodiments, each of the plurality of gap-filling HFRF pulses is independently generated at a gap-filling power in the range of 0 W to 500 W, 50 W to 500 W, 50 W to 400 W, 50 W to 300 W, 50 W to 200 W, 50 W to 100 W, 100 W to 500 W, 100 W to 400 W, 100 W to 300 W, 100 W to 200 W, 200 W to 500 W, 200 W to 400 W, or 200 W to 300 W. In some embodiments, the minimum gap-filling plasma power is greater than 0 W. In some embodiments, all gap-filling pulses have the same power. In some embodiments, the power of each pulse in the gap-filling HFRF plasma varies.
在一或多個實施例中,複數個間隙填充HFRF電漿脈衝具有在1%至50%、1%至45%、1%至40%、1%至35%、1%至30%、1%至25%、1%至20%、1%至15%、1%至10%、5%至50%、5%至45%、5%至40%、5%至35%、5%至30%、5%至25%、5%至20%、5%至15%、5%至10%、10%至50%、10%至45%、10%至40%、10%至35%、10%至30%、10%至25%、10%至20%或10%至15%範圍內的間隙填充工作週期。在一些實施例中,間隙填充沉積製程期間的電漿脈衝中的每一者具有相同的工作週期。在一些實施例中,工作週期在間隙填充沉積製程期間改變。In one or more embodiments, a plurality of gap-filling HFRF plasma pulses have a gap-filling duty cycle in a range of 1% to 50%, 1% to 45%, 1% to 40%, 1% to 35%, 1% to 30%, 1% to 25%, 1% to 20%, 1% to 15%, 1% to 10%, 5% to 50%, 5% to 45%, 5% to 40%, 5% to 35%, 5% to 30%, 5% to 25%, 5% to 20%, 5% to 15%, 5% to 10%, 10% to 50%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In some embodiments, each of the plasma pulses during the gapfill deposition process has the same duty cycle. In some embodiments, the duty cycle varies during the gapfill deposition process.
在一或多個實施例中,複數個間隙填充HFRF電漿脈衝中的每一個獨立地具有在以下範圍內的脈衝寬度:5毫秒至50微秒、4毫秒至50微秒、3毫秒至50微秒、2毫秒至50微秒、1毫秒至50微秒、800微秒至50微秒、500微秒至50微秒、200微秒至50微秒、5毫秒至100微秒、4毫秒至100微秒、3毫秒至100微秒、2毫秒至100微秒、1毫秒至100微秒、800微秒至100微秒、500微秒至100微秒和200微秒至100微秒。在一些實施例中,脈衝寬度中的每一者在沉積製程期間是相同的。在一些實施例中,脈衝寬度在沉積製程期間變化。In one or more embodiments, each of the plurality of gap-fill HFRF plasma pulses independently has a pulse width in the range of 5 milliseconds to 50 microseconds, 4 milliseconds to 50 microseconds, 3 milliseconds to 50 microseconds, 2 milliseconds to 50 microseconds, 1 millisecond to 50 microseconds, 800 microseconds to 50 microseconds, 500 microseconds to 50 microseconds, 200 microseconds to 50 microseconds, 5 milliseconds to 100 microseconds, 4 milliseconds to 100 microseconds, 3 milliseconds to 100 microseconds, 2 milliseconds to 100 microseconds, 1 millisecond to 100 microseconds, 800 microseconds to 100 microseconds, 500 microseconds to 100 microseconds, and 200 microseconds to 100 microseconds. In some embodiments, each of the pulse widths is the same during the deposition process. In some embodiments, the pulse width is varied during the deposition process.
在一或多個實施例中,複數個間隙填充HFRF電漿脈衝中的每一個獨立地具有在0.1 kHz至20 kHz、0.1 kHz至15 kHz、0.1 kHz至10 kHz、0.1 kHz至5 kHz、0.5 kHz至20 kHz、0.5 kHz至15 kHz、0.5 kHz至10 kHz、0.5 kHz至5 kHz、1 kHz至20 kHz、1 kHz至15 kHz、1 kHz至10 kHz、1 kHz至5 kHz、2 kHz至20 kHz、2 kHz至15 kHz、2 kHz至10 kHz或2 kHz至5 kHz範圍內的間隙填充脈衝頻率。在一些實施例中,脈衝頻率在沉積製程期間保持相同。在一些實施例中,脈衝頻率在沉積製程期間變化。In one or more embodiments, each of the plurality of gap-fill HFRF plasma pulses independently has a gap-fill pulse frequency in the range of 0.1 kHz to 20 kHz, 0.1 kHz to 15 kHz, 0.1 kHz to 10 kHz, 0.1 kHz to 5 kHz, 0.5 kHz to 20 kHz, 0.5 kHz to 15 kHz, 0.5 kHz to 10 kHz, 0.5 kHz to 5 kHz, 1 kHz to 20 kHz, 1 kHz to 15 kHz, 1 kHz to 10 kHz, 1 kHz to 5 kHz, 2 kHz to 20 kHz, 2 kHz to 15 kHz, 2 kHz to 10 kHz, or 2 kHz to 5 kHz. In some embodiments, the pulse frequency remains the same during the deposition process. In some embodiments, the pulse frequency is varied during the deposition process.
在一或多個實施例中,複數個間隙填充HFRF脈衝具有在5 MHz至20 MHz、5 MHz至15 MHz、5 MHz至10 MHz、10 MHz至20 MHz或10 MHz至15 MHz範圍內的間隙填充射頻。在一或多個實施例中,複數個間隙填充HFRF脈衝具有13.56 MHz的第一射頻。在一些實施例中,脈衝的射頻在沉積製程期間是相同的。在一些實施例中,脈衝的射頻在沉積製程期間變化。在一或多個實施例中,複數個間隙填充HFRF脈衝中的每一個獨立地具有在5 MHz至20 MHz、5 MHz至15 MHz、5 MHz至10 MHz、10 MHz至20 MHz或10 MHz至15 MHz範圍內的第一射頻。在一或多個實施例中,複數個間隙填充HFRF脈衝中的每一個獨立地具有13.56 MHz的第一射頻。In one or more embodiments, the plurality of gap-filling HFRF pulses have a gap-filling RF frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, the plurality of gap-filling HFRF pulses have a first RF frequency of 13.56 MHz. In some embodiments, the RF frequency of the pulses is the same during the deposition process. In some embodiments, the RF frequency of the pulses varies during the deposition process. In one or more embodiments, each of the plurality of gap-filling HFRF pulses independently has a first RF frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, each of the plurality of gap-filling HFRF pulses independently has a first RF frequency of 13.56 MHz.
在一或多個實施例中,複數個間隙填充HFRF脈衝中的每一個具有在1%至50%、1%至45%、1%至40%、1%至35%、1%至30%、1%至25%、1%至20%、1%至15%、1%至10%、5%至50%、5%至45%、5%至40%、5%至35%、5%至30%、5%至25%、5%至20%、5%至15%、5%至10%、10%至50%、10%至45%、10%至40%、10%至35%、10%至30%、10%至25%、10%至20%或10%至15%範圍內的間隙填充工作週期。在一些實施例中,脈衝的工作週期在沉積製程期間是相同的。在一些實施例中,脈衝的工作週期在沉積製程期間變化。In one or more embodiments, each of the plurality of gapfill HFRF pulses has a gapfill duty cycle in the range of 1% to 50%, 1% to 45%, 1% to 40%, 1% to 35%, 1% to 30%, 1% to 25%, 1% to 20%, 1% to 15%, 1% to 10%, 5% to 50%, 5% to 45%, 5% to 40%, 5% to 35%, 5% to 30%, 5% to 25%, 5% to 20%, 5% to 15%, 5% to 10%, 10% to 50%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In some embodiments, the duty cycle of the pulses is the same during the deposition process. In some embodiments, the duty cycle of the pulse is varied during the deposition process.
沉積製程220可以在任何合適的基板溫度下發生。在一些實施例中,在沉積製程220期間,將基板保持在15°C至250°C、15°C至225°C、15°C至200°C、15°C至175°C、15°C至150°C、15°C至125°C、15°C至100°C、25°C至250°C、25°C至225°C、25°C至200°C、25°C至175°C、25°C至150°C、25°C至125°C、25°C至100°C、50°C至250°C、50°C至225°C、50°C至200°C、50°C至175°C、50°C至150°C、50°C至125°C、50°C至100°C、75°C至250°C、75°C至225°C、75°C至200°C、75°C至175°C、75°C至150°C、75°C至125°C或75°C至100°C範圍內的間隙填充溫度。The
在一或多個實施例中,膜沉積製程220包括使第一載氣、前驅物或第一反應物中的一者或多者流動到基板表面上。在一些實施例中,載氣包括但不限於氬(Ar)、氦He、H
2或N
2。在一些實施例中,載氣包括氦(He)或基本上由氦(He)組成。在一些實施例中,載氣包括氬(Ar)。在一或多個實施例中,前驅物包括但不限於矽烷、二矽烷、二氯矽烷(DCS)、三矽烷或四矽烷。在一些實施例中,前驅物氣體包括矽烷(SiH
4)。在一些實施例中,前驅物氣體包括二矽烷(Si
2H
6)或基本上由二矽烷(Si
2H
6)組成。在一些實施例中,前驅物氣體在熱罐中被加熱以增加蒸氣壓並使用載氣輸送到腔室。在一些實施例中,第一反應物氣體包括H
2。
In one or more embodiments, the
在一或多個實施例中,間隙填充載氣、前驅物氣體或間隙填充反應物氣體中的每一者以40sccm至10000sccm、40sccm至5000sccm、40sccm至2000sccm、40sccm至1000sccm、40sccm至500sccm、40sccm至100sccm、100sccm至10000sccm、100sccm至5000sccm、100sccm至2000sccm、100sccm至1000sccm、100sccm至500sccm、250sccm至10000sccm、250sccm至5000sccm、250sccm至2000sccm、250sccm至1000sccm、250sccm至500sccm、500sccm至10000sccm、500sccm至5000sccm、500sccm至2000sccm或500sccm至1000sccm範圍內的劑量獨立地流動到基板表面上。In one or more embodiments, each of the gapfill carrier gas, the precursor gas, or the gapfill reactant gas is introduced at a flow rate of 40 sccm to 10000 sccm, 40 sccm to 5000 sccm, 40 sccm to 2000 sccm, 40 sccm to 1000 sccm, 40 sccm to 500 sccm, 40 sccm to 100 sccm, 100 sccm to 10000 sccm, 100 sccm to 5000 sccm, 100 sccm to 2000 sccm, 100 sccm to 1 Doses in the range of 100-2000 sccm, 100-500 sccm, 250-10000 sccm, 250-5000 sccm, 250-2000 sccm, 250-1000 sccm, 250-500 sccm, 500-10000 sccm, 500-5000 sccm, 500-2000 sccm, or 500-1000 sccm are independently flowed onto the substrate surface.
在一些實施例中,如圖3A所示,在沉積製程220期間沉積的膜370是連續膜。如本文所用,術語「連續」是指覆蓋整個暴露表面的層,其中沒有使下覆於沉積層的材料暴露的間隙或裸點。連續膜可具有間隙或裸點,所述間隙或裸點的表面積小於膜的總表面積的約1%。In some embodiments, as shown in FIG3A , the film 370 deposited during the
在沉積製程220之後,方法200到達決策點230。在決策點230處,評估特徵的填充條件。如果特徵110或間隙已經被完全填充,則可以停止方法200並且可以對基板進行可選的後處理260。如果特徵或間隙尚未被填充,則方法200移動到蝕刻處理240。After the
在一或多個實施例中,在沉積製程220之後但在蝕刻處理240之前,基板100經受淨化處理及/或真空處理。在一些實施例中,在沉積製程220和蝕刻處理240之間,將諸如氬氣之類的淨化氣體引入處理腔室中以淨化反應區或以其他方式從反應區移除任何殘留的反應性化合物或副產物。在一些實施例中,淨化氣體在整個方法200中連續地流入處理腔室。在一些實施例中,在沉積製程220和蝕刻處理240之間,將負壓施加到處理腔室中以從反應區移除任何殘留的反應性化合物或副產物。在一些實施例中,在整個方法200中連續地將負壓施加到處理腔室中。在一些實施例中,在後處理260之前施加淨化處理及/或真空處理。In one or more embodiments, the
在一或多個實施例中,蝕刻處理240蝕刻非保形膜。在一些實施例中,蝕刻處理240蝕刻的特徵110的側壁上的膜370的厚度T
s大於來自特徵110的底部的厚度T
b。在一或多個實施例中,蝕刻處理蝕刻的特徵110的側壁上的膜370的厚度T
s大於來自特徵110的頂部的厚度T
t。
In one or more embodiments, the
不受任何特定操作理論的約束,據信,定向電漿處理相對於側壁膜376優先地改性頂部膜374和底部膜372。改性膜似乎更耐蝕刻。這導致此後更高的側壁蝕刻速率。圖3B圖示根據本案的一或多個實施例的已經經受導致頂部膜384和底部膜382改性的膜蝕刻的特徵110。Without being bound by any particular theory of operation, it is believed that the directed plasma treatment preferentially modifies the top film 374 and the bottom film 372 relative to the sidewall film 376. The modified films appear to be more resistant to etching. This results in higher sidewall etching rates thereafter. FIG. 3B illustrates a
圖3C圖示根據本案的一或多個實施例的蝕刻膜。蝕刻膜370從特徵110移除基本上所有的側壁膜376,並留下頂部膜384和底部膜382中的一些。在一些實施例中,去除基本上所有的側壁膜376意味著側壁的表面積的至少約95%、98%或99%已經被蝕刻。在一些實施例中,去除基本上所有的側壁膜376包括用於後續沉積製程220的成核延遲。FIG. 3C illustrates an etch film according to one or more embodiments of the present invention. The etch film 370 removes substantially all of the sidewall film 376 from the
在一或多個實施例中,蝕刻處理240包括將基板表面暴露於蝕刻載氣或蝕刻反應物氣體中的一者或多者。在一些實施例中,第二載氣包括氬(Ar)、氦(He)或氮(N
2)中的一者或多者。在一些實施例中,第二反應物氣體包括Cl
2、H
2、NF
3或HCl中的一者或多者。在一些實施例中,第二反應物氣體包括H
2或基本上由H
2組成。在一些實施例中,第二載氣或第二反應物氣體中的每一者以40 sccm至10000 sccm、40 sccm至5000 sccm、40 sccm至2000 sccm、40 sccm至1000 sccm、40 sccm至500 sccm、40 sccm至100 sccm、100 sccm至10000 sccm、100 sccm至5000 sccm、100 sccm至2000 sccm、100 sccm至1000 sccm、100 sccm至500 sccm、250 sccm至10000 sccm、250 sccm至5000 sccm、250 sccm至2000 sccm、250 sccm至1000 sccm、250 sccm至500 sccm、500 sccm至10000 sccm、500 sccm至5000 sccm、500 sccm至2000 sccm或500 sccm至1000 sccm範圍內的流速獨立地流動到基板表面上。
In one or more embodiments, the
在一或多個實施例中,蝕刻處理240包括將基板100的溫度保持在15°C至250°C、15°C至225°C、15°C至200°C、15°C至175°C、15°C至150°C、15°C至125°C、15°C至100°C、25°C至250°C、25°C至225°C、25°C至200°C、25°C至175°C、25°C至150°C、25°C至125°C,25°C至100°C、50°C至250°C、50°C至225°C、50°C至200°C、50°C至175°C、50°C至150°C、50°C至125°C、50°C至100°C、75°C至250°C、75°C至225°C、75°C至200°C、75°C至175°C、75°C至150°C、75°C至125°C或75°C至100°C的範圍內。在一些實施例中,基板在沉積製程220和蝕刻處理240期間保持在相同溫度。在一些實施例中,在沉積製程220和蝕刻處理240期間,將基板保持在不同(ΔT>10°C)溫度。In one or more embodiments, the etching process 240 includes maintaining the temperature of the substrate 100 at 15°C to 250°C, 15°C to 225°C, 15°C to 200°C, 15°C to 175°C, 15°C to 150°C, 15°C to 125°C, 15°C to 100°C, 25°C to 250°C, 25°C to 225°C, 25°C to 200°C, 25°C to 175°C, 25°C to 150°C, 25°C to 125°C, 25°C, 75°C to 250°C, 75°C to 225°C, 75°C to 200°C, 75°C to 175°C, 75°C to 150°C, 75°C to 125°C, 75°C to 100°C, 75°C to 250°C, 75°C to 225°C, 75°C to 200°C, 75°C to 175°C, 75°C to 150°C, 75°C to 125°C, or 75°C to 100°C. In some embodiments, the substrate is maintained at the same temperature during the deposition process 220 and the etching process 240. In some embodiments, the substrate is maintained at different (ΔT>10° C.) temperatures during the
在一或多個實施例中,蝕刻處理240包括將基板100的壓力保持在0.1托至12托、0.5托至12托、1托至12托、2托至12托、3托至12托、4托至12托、0.1托至10托、0.5托至10托、1托至10托、2托至10托、3托至10托、4托至10托、0.1托至8托、0.5托至8托、1托至8托、2托至8托、3托至8托、4托至8托、0.1托至5托、0.5托至5托、1托至5托、2托至5托、3托至5托或4托至5托的範圍內。In one or more embodiments, the
在一些實施例中,蝕刻處理240包括蝕刻電漿。在一些實施例中,蝕刻電漿是導電耦合電漿(CCP)或電感耦合電漿(ICP)。在一些實施例中,蝕刻電漿是直接電漿或遠程電漿。在一些實施例中,蝕刻電漿在0 W至500 W、50 W至500 W、50 W至400 W、50 W至300 W、50 W至200 W、50 W至100 W、100 W至500 W、100 W至400 W、100 W至300 W、100 W至200 W、200 W至500 W、200 W至400 W或200 W至300 W的範圍內的功率下操作。在一些實施例中,電漿的最小功率大於0 W。In some embodiments, the
在一些實施例中,蝕刻製程以連續功率位凖發生。在一些實施例中,蝕刻製程與第二HFRF電漿脈衝一起發生。在一些實施例中,複數個第二HFRF電漿脈衝中的每一個在0 W至500 W、50 W至500 W、50 W至400 W、50 W至300 W、50 W至200 W、50 W至100 W、100 W至500 W、100 W至400 W、100 W至300 W、100 W至200 W、200 W至500 W、200 W至400 W或200 W至300 W範圍內的蝕刻功率下獨立地產生。在一些實施例中,最小第二電漿功率大於0W。在一些實施例中,脈衝的功率在蝕刻處理期間是相同的。在一些實施例中,脈衝的功率在蝕刻處理期間變化。In some embodiments, the etching process occurs at a continuous power level. In some embodiments, the etching process occurs with a second HFRF plasma pulse. In some embodiments, each of the plurality of second HFRF plasma pulses is independently generated at an etching power in the range of 0 W to 500 W, 50 W to 500 W, 50 W to 400 W, 50 W to 300 W, 50 W to 200 W, 50 W to 100 W, 100 W to 500 W, 100 W to 400 W, 100 W to 300 W, 100 W to 200 W, 200 W to 500 W, 200 W to 400 W, or 200 W to 300 W. In some embodiments, the minimum second plasma power is greater than 0 W. In some embodiments, the power of the pulse is the same during the etching process. In some embodiments, the power of the pulse varies during the etching process.
在一或多個實施例中,複數個第二HFRF電漿脈衝具有1%至50%、1%至45%、1%至40%、1%至35%、1%至30%、1%至25%、1%至20%、1%至15%、1%至10%、5%至50%、5%至45%、5%至40%、5%至35%、5%至30%、5%至25%、5%至20%、5%至15%、5%至10%、10%至50%、10%至45%、10%至40%、10%至35%、10%至30%、10%至25%、10%至20%或10%至15%範圍內的工作週期。在一些實施例中,脈衝的工作週期在蝕刻處理期間是相同的。在一些實施例中,脈衝的工作週期在蝕刻處理期間變化。In one or more embodiments, the plurality of second HFRF plasma pulses have a duty cycle in the range of 1% to 50%, 1% to 45%, 1% to 40%, 1% to 35%, 1% to 30%, 1% to 25%, 1% to 20%, 1% to 15%, 1% to 10%, 5% to 50%, 5% to 45%, 5% to 40%, 5% to 35%, 5% to 30%, 5% to 25%, 5% to 20%, 5% to 15%, 5% to 10%, 10% to 50%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In some embodiments, the duty cycles of the pulses are the same during the etching process. In some embodiments, the duty cycle of the pulse is varied during the etching process.
在一或多個實施例中,複數個第二HFRF電漿脈衝中的每一個具有在以下範圍內的脈衝寬度:5毫秒至50微秒、4毫秒至50微秒、3毫秒至50微秒、2毫秒至50微秒、1毫秒至50微秒、800微秒至50微秒、500微秒至50微秒、200微秒至50微秒、5毫秒至100微秒、4毫秒至100微秒、3毫秒至100微秒、2毫秒至100微秒、1毫秒至100微秒、800微秒至100微秒、500微秒至100微秒和200微秒至100微秒。在一些實施例中,脈衝的脈衝寬度在蝕刻處理期間是相同的。在一些實施例中,脈衝的脈衝寬度在蝕刻處理期間變化。In one or more embodiments, each of the plurality of second HFRF plasma pulses has a pulse width in the following range: 5 milliseconds to 50 microseconds, 4 milliseconds to 50 microseconds, 3 milliseconds to 50 microseconds, 2 milliseconds to 50 microseconds, 1 millisecond to 50 microseconds, 800 microseconds to 50 microseconds, 500 microseconds to 50 microseconds, 200 microseconds to 50 microseconds, 5 milliseconds to 100 microseconds, 4 milliseconds to 100 microseconds, 3 milliseconds to 100 microseconds, 2 milliseconds to 100 microseconds, 1 millisecond to 100 microseconds, 800 microseconds to 100 microseconds, 500 microseconds to 100 microseconds, and 200 microseconds to 100 microseconds. In some embodiments, the pulse widths of the pulses are the same during the etching process. In some embodiments, the pulse width of the pulse is varied during the etching process.
在一或多個實施例中,複數個第二HFRF電漿脈衝中的每一個獨立地具有在0.1 kHz至20 kHz、0.1 kHz至15 kHz、0.1 kHz至10 kHz、0.1 kHz至5 kHz、0.5 kHz至20 kHz、0.5 kHz至15 kHz、0.5 kHz至10 kHz、0.5 kHz至5 kHz、1 kHz至20 kHz、1 kHz至15 kHz、1 kHz至10 kHz、1 kHz至5 kHz、2 kHz至20 kHz、2 kHz至15 kHz、2 kHz至10 kHz或2 kHz至5 kHz範圍內的脈衝頻率。在一些實施例中,脈衝的頻率在蝕刻處理期間是相同的。在一些實施例中,脈衝的頻率在蝕刻處理期間變化。In one or more embodiments, each of the plurality of second HFRF plasma pulses independently has a pulse frequency in the range of 0.1 kHz to 20 kHz, 0.1 kHz to 15 kHz, 0.1 kHz to 10 kHz, 0.1 kHz to 5 kHz, 0.5 kHz to 20 kHz, 0.5 kHz to 15 kHz, 0.5 kHz to 10 kHz, 0.5 kHz to 5 kHz, 1 kHz to 20 kHz, 1 kHz to 15 kHz, 1 kHz to 10 kHz, 1 kHz to 5 kHz, 2 kHz to 20 kHz, 2 kHz to 15 kHz, 2 kHz to 10 kHz, or 2 kHz to 5 kHz. In some embodiments, the frequency of the pulses is the same during the etching process. In some embodiments, the frequency of the pulses is varied during the etching process.
在一或多個實施例中,複數個第二HFRF脈衝具有在5 MHz至20 MHz、5 MHz至15 MHz、5 MHz至10 MHz、10 MHz至20 MHz或10 MHz至15 MHz範圍內的蝕刻射頻。在一或多個實施例中,複數個第二HFRF脈衝具有13.56 MHz的第二射頻。在一些實施例中,脈衝的射頻在蝕刻處理期間是相同的。在一些實施例中,脈衝的射頻在蝕刻處理期間變化。在一或多個實施例中,複數個第二HFRF脈衝中的每一個獨立地具有在5 MHz至20 MHz、5 MHz至15 MHz、5 MHz至10 MHz、10 MHz至20 MHz或10 MHz至15 MHz範圍內的蝕刻射頻。在一或多個實施例中,複數個第二HFRF脈衝中的每一個獨立地具有13.56 MHz的第二射頻。In one or more embodiments, the plurality of second HFRF pulses have an etching RF frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, the plurality of second HFRF pulses have a second RF frequency of 13.56 MHz. In some embodiments, the RF frequency of the pulses is the same during the etching process. In some embodiments, the RF frequency of the pulses varies during the etching process. In one or more embodiments, each of the plurality of second HFRF pulses independently has an etching RF frequency in the range of 5 MHz to 20 MHz, 5 MHz to 15 MHz, 5 MHz to 10 MHz, 10 MHz to 20 MHz, or 10 MHz to 15 MHz. In one or more embodiments, each of the plurality of second HFRF pulses independently has a second RF frequency of 13.56 MHz.
在一或多個實施例中,方法200進一步包括重複沉積製程220和蝕刻膜240以用於間隙填充。在一些實施例中,重複沉積製程220和重複蝕刻膜240中的每一者包括HFRF電漿。在一些實施例中,間隙填充是無瑕疵的。圖3D圖示在藉由沉積-蝕刻-處理製程的多個循環之後已經被填充的特徵110。In one or more embodiments,
在一或多個實施例中,一或多個附加效應進一步使特徵的側壁上的非保形膜的蝕刻速率與特徵的底部上的非保形膜的蝕刻速率不同。在一些實施例中,一或多個附加效應包括:待沉積在基板表面上的材料(例如,Si)的成核速率、影響待沉積在基板表面上的材料的成核速率的基板表面的性質、或待沉積在基板表面上的材料(例如,Si)的蝕刻速率。In one or more embodiments, one or more additional effects further cause the etch rate of the non-conformal film on the sidewalls of the feature to be different from the etch rate of the non-conformal film on the bottom of the feature. In some embodiments, the one or more additional effects include: a nucleation rate of a material (e.g., Si) to be deposited on the substrate surface, a property of the substrate surface that affects the nucleation rate of a material to be deposited on the substrate surface, or an etch rate of a material (e.g., Si) to be deposited on the substrate surface.
一些實施例包括可選的後處理260製程。後處理260可用於改性膜370以改善膜的一些參數。在一些實施例中,後處理260包括對膜370進行退火。在一些實施例中,後處理260可以藉由在用於沉積220及/或蝕刻240的相同處理腔室中的原位退火來執行。合適的退火製程包括但不限於快速熱處理(RTP)或快速熱退火(RTA)、尖峰退火或UV固化、或電子束固化及/或鐳射退火。退火溫度可以在約500°C至900°C的範圍內。退火期間的環境的組成可以包括H
2、Ar、He、N
2、NH
3、SiH
4等中的一者或多者。退火期間的壓力可以在約100毫托至約1大氣壓的範圍內。
Some embodiments include an
本案的一些實施例涉及使用脈衝HFRF電漿製程沉積金屬摻雜碳膜的保形PECVD襯墊。如以這種方式使用的,「金屬摻雜碳」和「金屬碳化物」可互換使用以指具有金屬和碳原子的膜。Some embodiments of the present disclosure relate to conformal PECVD pads of metal-doped carbon films deposited using a pulsed HFRF plasma process. As used in this manner, "metal-doped carbon" and "metal carbide" are used interchangeably to refer to films having metal and carbon atoms.
本案的一些實施例涉及用於動態隨機存取記憶體(DRAM)裝置的金屬碳化物(例如,碳化鎢)襯墊。本案的一些實施例涉及金屬碳化物襯墊記憶體或邏輯應用。本案的一些實施例涉及用於形成金屬碳化物硬模的方法。Some embodiments of the present invention relate to metal carbide (e.g., tungsten carbide) pads for dynamic random access memory (DRAM) devices. Some embodiments of the present invention relate to metal carbide pad memory or logic applications. Some embodiments of the present invention relate to methods for forming metal carbide hard molds.
碳化鎢的一般電漿增強化學氣相沉積在窄溝槽的頂部形成「蘑菇形」膜,並且在側壁處形成非常薄的膜,從而導致差保形性的襯墊。不受任何特定操作理論的約束,據信,電漿不能充分滲透到深溝槽中,從而導致差的保形性。碳化鎢沉積的當前技術水平是藉由使用連續HFRF電漿的PECVD,但不能產生良好的保形性,其中對於具有約100nm的臨界尺寸(CD)的溝槽,最薄/最厚膜保形性為約22%。發明人驚奇地發現,使用脈衝HFRF,碳化鎢保形性可以提高到40%至70%或更高。在一些實施例中,脈衝HFRF電漿使保形性增加2倍或更大。Conventional plasma enhanced chemical vapor deposition of tungsten carbide forms a "mushroom shaped" film on top of narrow trenches and a very thin film at the sidewalls, resulting in a poorly conformal liner. Without being bound by any particular theory of operation, it is believed that the plasma does not adequately penetrate into deep trenches, resulting in poor conformality. The current state of the art for tungsten carbide deposition is by PECVD using a continuous HFRF plasma, but does not produce good conformality, with the thinnest/thickest film conformality being about 22% for trenches with a critical dimension (CD) of about 100 nm. The inventors surprisingly found that using pulsed HFRF, tungsten carbide conformality can be improved to 40% to 70% or more. In some embodiments, pulsed HFRF plasma increases conformality by a factor of 2 or more.
圖4A圖示本案的另一實施例,其中使用脈衝HFRF電漿形成金屬碳化物襯墊。一些實施例的金屬碳化物襯墊作為方法200的一部分在襯墊形成製程215期間形成。在一些實施例中,金屬碳化物襯墊作為與方法200中所示的方法不同的方法的一部分被形成。FIG4A illustrates another embodiment of the present disclosure in which a metal carbide pad is formed using a pulsed HFRF plasma. The metal carbide pad of some embodiments is formed during a
在所示實施例中,電子裝置300具有形成在特徵110的基板表面、側壁和底部上的金屬碳化物膜470。沉積在基板上的膜470將在特徵的側壁上具有膜厚度T
s,在特徵的頂部(即,在基板的表面上)具有膜厚度T
t,並且在特徵110的底部具有膜厚度T
b。金屬碳化物膜470具有在特徵110的底部處的底表面472、在特徵110的側壁處的側壁表面476和在特徵110的頂表面上的頂表面474。
In the illustrated embodiment, electronic device 300 has a metal carbide film 470 formed on the substrate surface, sidewalls, and bottom of
在一些實施例中,膜470保形地形成在至少一個特徵上。如本文所用,術語「保形」或「保形地」是指黏附到並均勻地覆蓋暴露表面的金屬碳化物層,其中側壁上的膜的厚度大於或等於特徵的頂部/底部上的膜的厚度的40%。在一些實施例中,金屬碳化物膜具有在40%至75%範圍內的保形性。在一些實施例中,金屬碳化物膜具有大於或等於40%、45%、50%、55%、60%、65%或70%的保形性。膜470具有比在沒有脈衝電漿(即,連續電漿)的情況下形成的膜(通常具有小於或等於25%的保形性)更大的保形性。In some embodiments, film 470 is conformally formed over at least one feature. As used herein, the term "conformal" or "conformally" refers to a metal carbide layer that adheres to and uniformly covers an exposed surface, wherein the thickness of the film on the sidewalls is greater than or equal to 40% of the thickness of the film on the top/bottom of the feature. In some embodiments, the metal carbide film has a conformality in the range of 40% to 75%. In some embodiments, the metal carbide film has a conformality greater than or equal to 40%, 45%, 50%, 55%, 60%, 65%, or 70%. Film 470 has greater conformality than films formed without pulsed plasma (i.e., continuous plasma), which typically have a conformality less than or equal to 25%.
在一些實施例中,在停止沉積之前,將膜470沉積至1nm至100nm、1nm至80nm、1nm至50nm、10nm至100nm、10nm至80nm、10nm至50nm、20nm至100nm、20nm至80nm或20nm至50nm範圍內的平均厚度。在一些實施例中,膜470被沉積至在5nm至100nm、5nm至80nm、5nm至40nm、5nm至30nm或10nm至30nm範圍內的平均厚度。In some embodiments, before stopping the deposition, the film 470 is deposited to an average thickness in the range of 1 nm to 100 nm, 1 nm to 80 nm, 1 nm to 50 nm, 10 nm to 100 nm, 10 nm to 80 nm, 10 nm to 50 nm, 20 nm to 100 nm, 20 nm to 80 nm, or 20 nm to 50 nm. In some embodiments, the film 470 is deposited to an average thickness in the range of 5 nm to 100 nm, 5 nm to 80 nm, 5 nm to 40 nm, 5 nm to 30 nm, or 10 nm to 30 nm.
用於沉積膜470的製程參數可影響特徵的側壁、特徵的頂部及/或特徵的底部處的膜厚度。例如,特定前驅物及/或反應性物質、電漿條件、溫度等。在一些實施例中,特徵的頂部處的厚度T t大於特徵的側壁處的厚度T s。在一些實施例中,特徵的底部處的厚度T b大於特徵的側壁處的厚度T s。在一些實施例中,特徵的頂部處的厚度T t大於特徵的底部處的厚度T b。在一些實施例中,特徵的底部處的厚度T b大於特徵的頂部處的厚度T t。 The process parameters used to deposit film 470 can affect the film thickness at the sidewalls of the feature, the top of the feature, and/or the bottom of the feature. For example, specific precursors and/or reactive species, plasma conditions, temperature, etc. In some embodiments, the thickness Tt at the top of the feature is greater than the thickness Ts at the sidewalls of the feature. In some embodiments, the thickness Tb at the bottom of the feature is greater than the thickness Ts at the sidewalls of the feature. In some embodiments, the thickness Tt at the top of the feature is greater than the thickness Tb at the bottom of the feature. In some embodiments, the thickness Tb at the bottom of the feature is greater than the thickness Tt at the top of the feature.
在膜沉積製程期間,將基板暴露於形成膜470的一或多個製程氣體及/或條件。在一些實施例中,處理氣體流入處理腔室的處理區域,並且由處理氣體形成脈衝HFRF電漿以沉積膜470。一些實施例的製程氣體包括金屬前驅物和載氣,並且載氣藉由HFRF功率點燃成電漿。在一些實施例中,金屬前驅物包括金屬鹵化物或基本上由金屬鹵化物組成。以這種方式使用的術語「基本上由……組成」意指金屬前驅物的活性物質大於或等於所闡明物質的95%、98%、99%或99.5%。在一些實施例中,金屬鹵化物包括氟原子或基本上由氟原子群組成。在一些實施例中,金屬鹵化物包括氯原子或基本上由氯原子群組成。During the film deposition process, the substrate is exposed to one or more process gases and/or conditions that form the film 470. In some embodiments, a process gas flows into a processing region of a processing chamber, and a pulsed HFRF plasma is formed by the process gas to deposit the film 470. The process gas of some embodiments includes a metal precursor and a carrier gas, and the carrier gas is ignited into a plasma by HFRF power. In some embodiments, the metal precursor includes a metal halide or consists essentially of a metal halide. The term "consisting essentially of..." used in this manner means that the active substance of the metal precursor is greater than or equal to 95%, 98%, 99% or 99.5% of the specified substance. In some embodiments, the metal halide includes fluorine atoms or consists essentially of a group of fluorine atoms. In some embodiments, the metal halide comprises or consists essentially of chlorine atoms.
在一些實施例中,金屬前驅物包括鎢(W)、鉬(Mo)或鎳(Ni)中的一者或多者。在一些實施例中,金屬前驅物包括六氟化鎢(WF 6)或基本上由六氟化鎢(WF 6)組成。在一些實施例中,金屬前驅物包括氟化鉬(V)(MoF 5)或基本上由氟化鉬(V)(MoF 5)組成。在一些實施例中,金屬前驅物包括氟化鎳(II)(NiF 2)或基本上由氟化鎳(II)(NiF 2)組成。在一些實施例中,金屬前驅物包括六氟化鎢、五氟化鉬或二氟化鎳中的一者或多者或基本上由六氟化鎢、五氟化鉬或二氟化鎳中的一者或多者組成。 In some embodiments, the metal precursor comprises one or more of tungsten (W), molybdenum (Mo), or nickel (Ni). In some embodiments, the metal precursor comprises or consists essentially of tungsten hexafluoride (WF 6 ). In some embodiments, the metal precursor comprises or consists essentially of molybdenum (V) fluoride (MoF 5 ). In some embodiments, the metal precursor comprises or consists essentially of nickel (II) fluoride (NiF 2 ) . In some embodiments, the metal precursor comprises or consists essentially of one or more of tungsten hexafluoride, molybdenum pentafluoride, or nickel difluoride.
在一或多個實施例中,線性脈衝HFRF電漿是導電耦合電漿(CCP)或電感耦合電漿(ICP)。在一些實施例中,線性脈衝HFRF電漿是直接電漿或遠端電漿。在一些實施例中,複數個線性HFRF脈衝中的每一個在500W至1500W的範圍內、或在600W至1400W的範圍內、或在700W至1300W的範圍內、或在800W至1200W的範圍內的線性功率下獨立地產生。在一些實施例中,最小襯墊電漿功率大於500W。在一些實施例中,所有線性脈衝具有相同的功率。在一些實施例中,襯墊HFRF電漿中的各個脈衝功率變化。In one or more embodiments, the linear pulsed HFRF plasma is a conductively coupled plasma (CCP) or an inductively coupled plasma (ICP). In some embodiments, the linear pulsed HFRF plasma is a direct plasma or a remote plasma. In some embodiments, each of the plurality of linear HFRF pulses is independently generated at a linear power in the range of 500W to 1500W, or in the range of 600W to 1400W, or in the range of 700W to 1300W, or in the range of 800W to 1200W. In some embodiments, the minimum pad plasma power is greater than 500W. In some embodiments, all linear pulses have the same power. In some embodiments, the power of each pulse in the liner HFRF plasma is varied.
在一或多個實施例中,複數個襯墊HFRF電漿脈衝具有高達99%且包括99%的襯墊工作週期。在一些實施例中,複數個襯墊HFRF電漿脈衝具有在1%至95%、1%至90%、1%至85%、1%至80%、1%至75%、1%至70%、1%至65%、1%至60%、1%至55%、5%至95%、5%至90%、5%至85%、5%至80%、5%至75%、5%至70%、5%至65%、5%至60%、5%至55%、10%至95%、10%至45%、10%至40%、10%至35%、10%至30%、10%至25%、10%至20%或10%至15%範圍內的襯墊工作週期。在一些實施例中,襯墊沉積製程期間的電漿脈衝中的每一者具有相同的工作週期。在一些實施例中,工作週期在襯墊沉積製程期間改變。In one or more embodiments, the plurality of pad HFRF plasma pulses have a pad duty cycle of up to and including 99%. In some embodiments, a plurality of liner HFRF plasma pulses have a liner duty cycle in a range of 1% to 95%, 1% to 90%, 1% to 85%, 1% to 80%, 1% to 75%, 1% to 70%, 1% to 65%, 1% to 60%, 1% to 55%, 5% to 95%, 5% to 90%, 5% to 85%, 5% to 80%, 5% to 75%, 5% to 70%, 5% to 65%, 5% to 60%, 5% to 55%, 10% to 95%, 10% to 45%, 10% to 40%, 10% to 35%, 10% to 30%, 10% to 25%, 10% to 20%, or 10% to 15%. In some embodiments, each of the plasma pulses during the pad deposition process has the same duty cycle. In some embodiments, the duty cycle changes during the pad deposition process.
在一或多個實施例中,複數個線性HFRF電漿脈衝中的每一個獨立地具有在以下範圍內的脈衝寬度:5毫秒至50微秒、4毫秒至50微秒、3毫秒至50微秒、2毫秒至50微秒、1毫秒至50微秒、800微秒至50微秒、500微秒至50微秒、200微秒至50微秒、5毫秒至100微秒、4毫秒至100微秒、3毫秒至100微秒、2毫秒至100微秒、1毫秒至100微秒、800微秒至100微秒、500微秒至100微秒和200微秒至100微秒。在一些實施例中,脈衝寬度中的每一者在沉積製程期間是相同的。在一些實施例中,脈衝寬度在沉積製程期間變化。In one or more embodiments, each of the plurality of linear HFRF plasma pulses independently has a pulse width in the range of 5 ms to 50 μsec, 4 ms to 50 μsec, 3 ms to 50 μsec, 2 ms to 50 μsec, 1 ms to 50 μsec, 800 μsec to 50 μsec, 500 μsec to 50 μsec, 200 μsec to 50 μsec, 5 ms to 100 μsec, 4 ms to 100 μsec, 3 ms to 100 μsec, 2 ms to 100 μsec, 1 ms to 100 μsec, 800 μsec to 100 μsec, 500 μsec to 100 μsec, and 200 μsec to 100 μsec. In some embodiments, each of the pulse widths is the same during a deposition process. In some embodiments, the pulse width is varied during the deposition process.
在一或多個實施例中,複數個線性HFRF電漿脈衝中的每一個獨立地具有在0.1 kHz至20 kHz、0.1 kHz至15 kHz、0.1 kHz至10 kHz、0.1 kHz至5 kHz、0.5 kHz至20 kHz、0.5 kHz至15 kHz、0.5 kHz至10 kHz、0.5 kHz至5 kHz、1 kHz至20 kHz、1 kHz至15 kHz、1 kHz至10 kHz、1 kHz至8 kHz、1 kHz至5 kHz、2 kHz至20 kHz、2 kHz至15 kHz、2 kHz至10 kHz或2 kHz至5 kHz範圍內的線性脈衝頻率。在一些實施例中,脈衝頻率在沉積製程期間保持相同。在一些實施例中,脈衝頻率在沉積製程期間變化。In one or more embodiments, each of the plurality of linear HFRF plasma pulses independently has a linear pulse frequency in the range of 0.1 kHz to 20 kHz, 0.1 kHz to 15 kHz, 0.1 kHz to 10 kHz, 0.1 kHz to 5 kHz, 0.5 kHz to 20 kHz, 0.5 kHz to 15 kHz, 0.5 kHz to 10 kHz, 0.5 kHz to 5 kHz, 1 kHz to 20 kHz, 1 kHz to 15 kHz, 1 kHz to 10 kHz, 1 kHz to 8 kHz, 1 kHz to 5 kHz, 2 kHz to 20 kHz, 2 kHz to 15 kHz, 2 kHz to 10 kHz, or 2 kHz to 5 kHz. In some embodiments, the pulse frequency remains the same during the deposition process. In some embodiments, the pulse frequency is varied during the deposition process.
作為方法200的一部分,襯墊形成製程215發生在沉積製程220之前,並且可以在任何合適的基板溫度下發生。襯墊形成製程215期間的基板溫度可以與沉積製程220或蝕刻240期間的基板溫度相同或不同。As part of the
在一些實施例中,在襯墊形成製程215期間,將基板保持在200°C至550°C、250°C至525°C、300°C至500°C、325°C至475°C或350°C至450°C範圍內的襯墊溫度。In some embodiments, during the
在一些實施例中,襯墊形成製程215包括電漿增強化學氣相沉積(CVD)製程。在一或多個實施例中,襯墊形成製程215包括使載氣、襯墊前驅物或襯墊反應物中的一者或多者流動到基板表面上。在一些實施例中,載氣包括但不限於氬(Ar)、氦He、H
2或N
2。
In some embodiments, the
在一或多個實施例中,襯墊載氣、襯墊前驅物氣體或襯墊反應物氣體中的每一者以10 sccm至500 sccm、15 sccm至350 sccm、20 sccm至200 sccm、25 sccm至150 sccm或50 sccm至125 sccm範圍內的劑量獨立地流動到基板表面上。In one or more embodiments, each of the liner carrier gas, liner precursor gas, or liner reactant gas is independently flowed onto the substrate surface at a dosage in the range of 10 sccm to 500 sccm, 15 sccm to 350 sccm, 20 sccm to 200 sccm, 25 sccm to 150 sccm, or 50 sccm to 125 sccm.
在一些實施例中,襯墊形成製程215產生具有拉伸應力的金屬碳化物膜470。在一些實施例中,金屬碳化物膜470的拉伸應力大於或等於1 GPa、1.25 GPa、1.5 GPa、1.75 GPa或2.0 GPa。發明人已經驚訝地發現,使用脈衝HFRF電漿形成的金屬碳化物膜470產生具有拉伸應力的膜,而藉由不同製程形成的典型金屬碳化物膜具有從低拉伸應力(例如,<1GPa)到壓縮應力(例如,負GPa)範圍內的應力。In some embodiments, the
在襯墊形成製程215之後,一些實施例的方法200進入膜沉積220的循環,隨後是決策點230和可選的蝕刻處理240以形成無瑕疵間隙填充。如圖4B所示,在一些實施例中,無論是根據方法200還是藉由不同的方法,間隙填充膜480形成在金屬碳化物襯墊470上的特徵110中。After the
在一些實施例中,金屬碳化物襯墊470被從基板的頂表面移除,從而使金屬碳化物襯墊470留在特徵110的側壁上。在一些實施例中,金屬碳化物襯墊470被從基板的頂表面和特徵110的底表面移除,從而使金屬碳化物襯墊基本上僅留在特徵的側壁上。In some embodiments, metal carbide liner 470 is removed from the top surface of the substrate, leaving metal carbide liner 470 on the sidewalls of
根據一或多個實施例,在形成層之前及/或之後對基板100進行處理。這種處理可以在同一腔室中或在一或多個分離的處理腔室中進行。在一些實施例中,將基板100從第一腔室移動到分離的第二腔室以用於進一步處理。基板100可以直接從第一腔室移動到分離的處理腔室,或者它可以從第一腔室移動到一或多個傳送腔室,然後移動到分離的處理腔室。因此,處理設備可以包括與傳送站連通的多個腔室。這種類型的裝置可以被稱為「集群工具」或「集群系統」等。According to one or more embodiments, the
通常,集群工具是包括多個腔室的模組化系統,所述多個腔室執行各種功能,包括基板中心檢視和定向、脫氣、退火、沉積220及/或蝕刻240。根據一或多個實施例,集群工具包括至少第一腔室和中央傳送腔室。中央傳送腔室可以容納機器人,所述機器人可以在處理腔室和裝載閘腔室之間和之中穿梭基板。傳送腔室通常保持在真空條件下,並提供用於將基板從一個腔室穿梭到另一個腔室及/或到定位在集群工具前端的裝載閘腔室的中間級。可以適用於本案的兩個眾所周知的集群工具是Centura®和Endura®,兩者均可從加利福尼亞州聖克拉拉市的應用材料公司(Applied Materials, Inc.)獲得。本文描述的實施例也可以使用其他合適的系統來執行。其他合適的系統包括但不限於Producer®、Producer®XP Precision或其均等物。然而,為了執行如本文所述的方法的特定步驟,可以改變腔室的確切佈置和組合。可以使用的其他處理腔室包括但不限於循環層沉積(CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、蝕刻、預清洗、化學清洗、熱處理(諸如RTP)、電漿氮化、脫氣、定向、羥基化和其他基板製程。藉由在集群工具上的腔室中進行製程,可以在沉積後續膜之前不發生氧化的情況下避免大氣雜質對基板的表面污染。Typically, a cluster tool is a modular system that includes multiple chambers that perform various functions, including substrate centering and orientation, degassing, annealing,
根據一或多個實施例,基板100持續處於真空或「裝載閘」條件下,並且當從一個腔室移動到下一個腔室時不暴露於環境空氣。因此,傳送腔室處於在真空壓力下被「泵送」的真空下。惰性氣體可以存在於處理腔室或傳送腔室中。在一些實施例中,惰性氣體用作淨化氣體以除去反應物中的一些或全部反應物。根據一或多個實施例,在沉積腔室的出口處注入淨化氣體以防止反應物從沉積腔室移動到傳送腔室及/或附加處理腔室。因此,惰性氣體流在腔室的出口處形成幕簾。According to one or more embodiments, the
可以在單個基板沉積腔室中處理基板,其中在處理另一基板之前裝載、處理和卸載單個基板。類似於輸送系統,也可以以連續方式處理基板,其中多個基板被單獨地裝載到腔室的第一部分中、移動通過腔室並且從腔室的第二部分被卸載。腔室和相關聯的輸送系統的形狀可以形成直線路徑或彎曲路徑。另外,處理腔室可以是轉盤,在轉盤中多個基板圍繞中心軸線移動,並且在整個轉盤路徑中暴露於沉積、蝕刻、退火、清潔等製程。Substrates may be processed in a single substrate deposition chamber where a single substrate is loaded, processed, and unloaded prior to processing another substrate. Similar to a conveyor system, substrates may also be processed in a serial manner where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and associated conveyor system may form a straight path or a curved path. Additionally, the processing chamber may be a turntable where multiple substrates are moved about a central axis and exposed to deposition, etching, annealing, cleaning, etc. processes throughout the turntable path.
在處理期間,基板100可以被加熱或冷卻。這種加熱或冷卻可以藉由任何合適的手段實現,包括但不限於改變基板支撐件的溫度和使加熱或冷卻的氣體流動到基板表面。在一些實施例中,基板支撐件包括加熱器/冷卻器,所述加熱器/冷卻器可以被控制以傳導地改變基板溫度。在一或多個實施例中,加熱或冷卻所採用的氣體(反應性氣體或惰性氣體)以局部改變基板溫度。在一些實施例中,加熱器/冷卻器被定位在鄰近基板表面的腔室內以對流地改變基板溫度。During processing, the
在處理期間,基板也可以是靜止的或旋轉的。旋轉基板可以連續地或以離散的步驟旋轉。例如,基板可以在整個製程中旋轉,或者基板可以在暴露於不同的反應物氣體或淨化氣體之間少量旋轉。在處理期間(連續地或分步地)旋轉基板可以藉由最小化例如氣流幾何形狀中的局部可變性的影響來幫助產生更均勻的沉積或蝕刻。The substrate may also be stationary or rotated during processing. Rotating the substrate may be done continuously or in discrete steps. For example, the substrate may be rotated throughout the process, or the substrate may be rotated a small amount between exposures to different reactant gases or purge gases. Rotating the substrate during processing (continuously or in steps) can help produce a more uniform deposition or etch by minimizing the effects of local variability in, for example, gas flow geometry.
貫穿本說明書對「一個實施例」、「某些實施例」、「一或多個實施例」或「實施例」的引用意指結合該實施例描述的特定特徵、結構、材料或特性被包括在本案的至少一個實施例中。因此,貫穿本說明書的各個地方出現的諸如「在一或多個實施例中」、「在某些實施例中」、「在一個實施例中」或「在實施例中」的短語不一定是指本案的相同實施例。此外,在一或多個實施例中,特定特徵、結構、材料或特性可以以任何合適的方式組合。References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the present invention. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.
儘管已經參考特定實施例描述了本文的公開內容,但是應當理解,這些實施例僅是對本案內容的原理和應用的說明。對於本領域技藝人士將顯而易見的是,可以在不脫離本案的精神和範圍的情況下對本案的方法和設備進行各種修改和變化。因此,本案旨在包括在所附申請專利範圍及其均等物的範圍內的修改和變化。Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.
100:基板 110:特徵 112:底表面 114:第一側壁 116:第二側壁 120:基板表面 200:方法 210:基板預處理 215:襯墊形成製程 220:沉積製程 230:決策點 240:蝕刻處理 260:後處理 300:電子裝置 350:第一表面 360:第二表面 370:膜 372:底部 374:頂部 376:側壁 382:底部膜 384:頂部膜 470:金屬碳化物膜 472:底表面 474:頂表面 476:側壁表面 480:間隙填充膜 100: substrate 110: feature 112: bottom surface 114: first sidewall 116: second sidewall 120: substrate surface 200: method 210: substrate pretreatment 215: pad formation process 220: deposition process 230: decision point 240: etching process 260: post-processing 300: electronic device 350: first surface 360: second surface 370: film 372: bottom 374: top 376: sidewall 382: bottom film 384: top film 470: metal carbide film 472: bottom surface 474: top surface 476: Side wall surface 480: Gap filling film
為了能夠詳細理解本案的上述特徵,可以藉由參考實施例對以上簡要概括的本案進行更具體的描述,其中一些實施例在附圖中示出。然而,應注意到,附圖僅圖示典型實施例,並且因此不應被視為限制其範圍,因為本案可允許其他等效的實施例。In order to be able to understand the above-mentioned features of the present invention in detail, the present invention briefly summarized above can be described in more detail by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments and therefore should not be considered to limit its scope, because the present invention may allow other equally effective embodiments.
圖1圖示根據本案的一或多個實施例的基板特徵的橫截面視圖;及FIG. 1 illustrates a cross-sectional view of a substrate feature according to one or more embodiments of the present disclosure; and
圖2圖示根據本案的一或多個實施例的製程流程。FIG. 2 illustrates a process flow according to one or more embodiments of the present invention.
圖3A至圖3D圖示根據本案的一或多個實施例的間隙填充製程的橫截面示意表示。3A-3D illustrate schematic cross-sectional representations of gapfill processes according to one or more embodiments of the present disclosure.
圖4A至圖4B圖示根據本案的一或多個實施例的金屬碳化物襯墊形成製程的橫截面示意表示。4A-4B illustrate schematic cross-sectional representations of a metal carbide pad formation process according to one or more embodiments of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None
300:電子裝置 300: Electronic devices
350:第一表面 350: First surface
360:第二表面 360: Second surface
470:金屬碳化物膜 470:Metal carbide film
480:間隙填充膜 480: Gap filling film
Claims (20)
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