TW202502164A - Semiconductor memory devices - Google Patents

Abstract

The embodiment provides a small and high-performance semiconductor memory device. The semiconductor memory device of the embodiment has multiple memory cell array layers, which have a first surface and a second surface opposite to the first surface and do not include a substrate, and comprises: multiple memory cells, which are three-dimensionally arranged in the memory cell array region; and a surface wiring layer embedded in the first surface and/or the second surface; wherein the surface wiring layers of each memory cell array layer are arranged in an overlapping manner when observing in a direction perpendicular to the first surface, and the surface wiring layers are mutually joined, thereby stacking multiple memory cell array layers.

Description

Semiconductor memory devices

An embodiment of the present invention relates to a semiconductor memory device.

The present invention proposes a 3D structured semiconductor memory device, wherein a plurality of electrode layers are stacked on a substrate with an insulating layer interposed therebetween to form a memory hole, and a silicon body serving as a channel is provided in the memory hole through a charge storage film interposed therebetween. In addition, a technique is proposed in which a control circuit of the 3D structured memory cell array is provided directly below or directly above the memory cell array.

However, in this example, the memory density per unit area cannot be sufficiently increased.

The embodiment provides a small and high-performance semiconductor memory device.

According to an implementation form, a semiconductor memory device is provided, which has a plurality of memory cell array layers, the memory cell array layer having a first surface and a second surface opposite to the first surface and not including a substrate, and including: a plurality of memory cells, which are three-dimensionally arranged in a memory cell array region; and a surface wiring layer, which is buried in the first surface or/and the second surface; and the surface wiring layers of each of the above-mentioned memory cell array layers are arranged in an overlapping manner when observed from a direction perpendicular to the above-mentioned first surface, and the above-mentioned surface wiring layers are mutually bonded, thereby stacking a plurality of the above-mentioned memory cell array layers.

Hereinafter, the embodiments will be described with reference to the drawings. In addition, the same elements in each drawing are marked with the same symbols.

(First embodiment) Figure 1 is a schematic cross-sectional view of a semiconductor memory device of the first embodiment. The semiconductor memory device of the first embodiment has the following structure: a peripheral circuit layer 100 including a control circuit for controlling data writing, erasing, and reading of memory cells and a first memory cell array layer 200 including a plurality of first memory cells arranged in three dimensions are joined and laminated in an opposing manner. Also, it has the following structure: the first memory cell array layer 200 and a second memory cell array layer 300 including a plurality of second memory cells arranged in three dimensions are joined and laminated in an opposing manner.

First, the first memory cell array layer 200 will be described. The first memory cell array layer 200 has a first surface (lower surface) Sa1 of FIG. 1 and a second surface (upper surface) Sa2 on the opposite side to the first surface, and has a first memory cell array 10a of a three-dimensional structure. FIG. 2 is a schematic three-dimensional diagram of a semiconductor memory device of the first embodiment, and is a schematic three-dimensional diagram of the first memory cell array 10a. In addition, in FIG. 2, the illustration of a part of the insulating layer such as the insulating layer between electrodes is omitted. Furthermore, FIG. 2 is the reverse of FIG. 1, and the upper side of FIG. 2 is the first surface side, and the lower side is the second surface side.

In FIG. 2 , two directions orthogonal to each other are defined as an X direction and a Y direction, and a direction orthogonal to the X direction and the Y direction (XY plane) in which a plurality of electrode layers WL are stacked is defined as a Z direction (stacking direction).

The first memory cell array 10a has: a first laminate 12a, in which a plurality of electrode layers WL and insulating layers 11 are alternately laminated layer by layer. In the first laminate 12a, a plurality of first columnar portions 13a extending in the Z direction are provided. The first columnar portion 13a is, for example, provided in a cylindrical or elliptical cylindrical shape. The plurality of first columnar portions 13a are arranged in a sawtooth grid or a square grid, for example, in the XY plane. The electrode layer WL is separated into a plurality of blocks in the Y direction and extends in the X direction.

The electrode layer WL is, for example, a layer including silicon as a main component. Furthermore, the electrode layer WL includes boron as an impurity for making the silicon layer conductive. Furthermore, the electrode layer WL may also include metal silicide.

The insulating layer 11 mainly contains silicon and oxygen, and is, for example, a silicon oxide film (SiO), a silicon oxynitride film (SiON), a silicon oxide film containing carbon (SiOC), or the like.

A drain side selection gate SGD is provided on the first surface Sa1 side, i.e., the upper portion, of the first columnar portion 13a, and a source side selection gate SGS is provided on the second surface Sa2 side, i.e., the lower portion. The drain side selection gate SGD is provided on the uppermost electrode layer WL through the dielectric insulating layer 11. The source side selection gate SGS is provided under the lowermost electrode layer WL through the dielectric insulating layer 11. Here, for example, the drain side selection gate SGD and the source side selection gate SGS may be formed thicker than the first electrode layer WL.

The first bit line 16a is connected to the first surface Sa1 side of the first columnar portion 13a, i.e., the upper end portion. A plurality of first bit lines 16a are provided, and metal is used. The plurality of first bit lines 16a are separated in the X direction and extend in the Y direction. The first bit line 16a is provided on the drain side selection gate SGD via the insulating layer 11 and the interlayer insulating layer 14.

The first source line 17a is connected to the second surface Sa2 side, i.e., the lower end of the first columnar portion 13a. The first source line 17a is provided below the source side selection gate SGS via the interlayer insulating layer 15. Furthermore, at the lower end of the first columnar portion 13a and further below the first source line 17a, a first source side wiring layer 19a is provided in the interlayer insulating layer 18. The interlayer insulating layer 18 may also be a stacked layer.

Fig. 3 is a schematic cross-sectional view of the semiconductor memory device of the first embodiment, and is a schematic cross-sectional view near the first columnar portion. Fig. 4 is a schematic cross-sectional view of a portion A near the first columnar portion in Fig. 3 that is enlarged. Figs. 3 and 4 show cross-sections parallel to the YZ plane of Fig. 2.

As shown in FIG3 , the first columnar portion 13a is formed in an I-shaped memory hole formed in the first multilayer body 12a including a plurality of electrode layers WL and a plurality of insulating layers 11. A channel body 20 serving as a semiconductor channel is provided in the memory hole. The channel body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than the impurity concentration of the electrode layer WL.

As shown in FIG4 , the memory cell MC has a memory film 21 between the inner wall of the memory hole and the channel main body 20. The memory film 21 includes, for example, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24. Between the electrode layer WL and the channel main body 20, the block insulating film 22, the charge storage film 23, and the tunnel insulating film 24 are sequentially provided from the electrode layer WL side.

The channel body 20 is provided in a cylindrical shape extending in the lamination direction of the laminate, and the memory film 21 is provided in a cylindrical shape extending in the lamination direction of the laminate so as to surround the outer peripheral surface of the channel body 20. The electrode layer WL surrounds the channel body 20 through the memory film 21. In addition, a core insulating film 25 is provided on the inner side of the channel body 20. The core insulating film 25 is, for example, a silicon oxide film.

The block insulating film 22 is in contact with the electrode layer WL, the tunnel insulating film 24 is in contact with the channel body 20, and a charge storage film 23 is provided between the block insulating film 22 and the tunnel insulating film 24.

The channel body 20 functions as a channel of the memory cell MC, and the electrode layer WL functions as a control gate of the memory cell. The charge storage film 23 functions as a data storage layer for storing the charge injected from the channel body 20. That is, a memory cell MC having a structure in which a control gate surrounds the channel is formed at the intersection of the channel body 20 and each electrode layer WL.

The semiconductor memory device of the first embodiment is a non-volatile semiconductor memory device that can electrically freely erase and write data and can retain memory contents even when the power is turned off.

The memory cell MC is, for example, a charge trapping type memory cell. The charge storage film 23 has a plurality of charge trapping sites, such as a silicon nitride film. It may also be a floating gate type memory cell.

The tunnel insulating film 24 serves as a potential barrier when charges are injected from the channel main body 20 into the charge storage film 23 or when charges stored in the charge storage film 23 diffuse into the channel main body 20. The tunnel insulating film 24 is, for example, a silicon oxide film.

Alternatively, a multilayer film (ONO film) having a structure of a silicon nitride film sandwiched by a pair of silicon oxide films may be used as the tunnel insulating film. If the ONO film is used as the tunnel insulating film, the erase operation can be performed at a lower electric field than a single layer of silicon oxide film.

The block insulating film 22 prevents the charges accumulated in the charge storage film 23 from diffusing to the electrode layer WL. The block insulating film 22 includes, for example, a silicon nitride film 221 provided in contact with the electrode layer WL and a silicon oxide film 222 provided between the silicon nitride film 221 and the charge storage film 23.

By providing the silicon nitride film 221 having a higher dielectric constant than the silicon oxide film 222 in contact with the electrode layer WL, it is possible to suppress the back-tunneling electrons injected from the electrode layer WL during erasing. That is, by using a multilayer film of silicon oxide film and silicon nitride film as the block insulating film 35, the charge blocking property can be improved.

As shown in FIG. 2 and FIG. 3 , a drain side selection transistor STD is provided on an upper portion of the first columnar portion 13 a , and a source side selection transistor STS is provided on a lower portion thereof.

The memory cell MC, the drain side select transistor STD, and the source side select transistor STS are vertical transistors that flow current in the stacking direction (Z direction) of the stacking body.

The drain side selection gate SGD functions as a gate electrode (control gate) of the drain side selection transistor STD. An insulating film 26 (FIG. 3) that functions as a gate insulating film of the drain side selection transistor STD is provided between the drain side selection gate SGD and the channel body 20. The channel body 20 of the drain side selection transistor STD provided in the first columnar portion 13a is connected to the bit line BL above the drain side selection gate SGD.

The source side selection gate SGS functions as a gate electrode (control gate) of the source side selection transistor STS. An insulating film 27 (FIG. 3) that functions as a gate insulating film of the source side selection transistor STS is provided between the source side selection gate SGS and the channel body 20. The channel body 20 of the source side selection transistor STS provided in the first columnar portion 13a is connected to the source line SL below the source side selection gate SGS.

Further below the source line SL, a first source-side wiring layer 19 a is provided in the interlayer insulating layer 18 .

The plurality of memory cells MC, drain side select transistors STD, and source side select transistors STS are connected in series through the channel body 20 to form an I-shaped memory string MS. By arranging a plurality of memory strings MS in the X direction and the Y direction, the plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction.

FIG1 shows the region at the end of the first memory cell array 10a in the X direction. At the end of the first memory cell array region 28a where a plurality of memory cells MC are arranged, a step structure portion 29 of an electrode layer WL extending in the X direction is formed. In the step structure portion 29, the ends of the electrode layers WL of each layer in the X direction are formed in a step shape. In the step structure portion 29, a plurality of contact plugs 30 connected to the electrode layers WL of each layer formed in a step shape are provided. The contact plugs 30 penetrate the interlayer insulating layer 31 and are connected to the electrode layers WL of each layer in the step shape.

Furthermore, in the step structure portion 29 , the selection gate SG (drain side selection gate SGD, source side selection gate SGS) is connected to the contact plug 32 .

The contact plug 30 connected to the electrode layer WL is connected to the word wiring layer 33. The contact plug 32 connected to the selection gate SG is connected to the selection gate wiring layer 34. The word wiring layer 33 and the selection gate wiring layer 34 are provided in the same layer.

The first memory cell array layer 200 does not include a substrate. Furthermore, a first source side wiring layer 19a is provided on the second surface side relative to the first source line SL.

At least a portion of the word wiring layer 33 and the select gate wiring layer 34 is led out to the outside of the first memory cell array region 28a when viewed from a direction perpendicular to the first plane as a word line lead-out portion 35 and a select gate line lead-out portion 36 through other wiring layers or plugs. The word line lead-out portion 35 and the select gate line lead-out portion 36 led out to the outside of the first memory cell array region 28a are connected to the first signal line lead-out electrode 37a provided on the outside of the first memory cell array region 28a.

In addition, the channel body 20 of the first columnar portion 13a is electrically connected to the first bit line BL and the first source line SL. In addition, at least a portion of the first bit line BL and the first source line SL is similarly led out to the outside of the first memory cell array region 28a when viewed from a direction perpendicular to the first plane as a first bit line lead portion and a first source line lead portion through other wiring layers or plugs (not shown). The first bit line lead portion and the first source line lead portion led out to the outside of the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided on the outside of the first memory cell array region 28a.

The first surface wiring layer 38a and the second surface wiring layer 39a are provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200. The first surface wiring layer 38a and the second surface wiring layer 39a are respectively buried in the first surface Sa1 and the second surface Sa2, and the surfaces are exposed from the interlayer insulating layer (not shown). Here, for example, the first signal line lead electrode 37a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a respectively provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200. The first signal line lead electrode 37 a , the first surface wiring layer 38 a , and the second surface wiring layer 39 a penetrate the first memory cell array layer 200 .

Furthermore, a first external connection electrode 40a is provided outside the first memory cell array region 28a. That is, the first external connection electrode 40a is provided in a region further outside the step structure portion of the memory cell array. The first external connection electrode 40a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a respectively provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200. The first surface wiring layer 38a and the second surface wiring layer 39a are respectively buried in the first surface Sa1 and the second surface Sa2, and the surface is exposed from the interlayer insulating layer not shown. The first external connection electrode 40 a , the first surface wiring layer 38 a , and the second surface wiring layer 39 a penetrate the first memory cell array layer 200 .

The peripheral circuit layer 100 includes a circuit substrate 1. The circuit substrate 1 of the peripheral circuit layer 100 is, for example, a silicon substrate. A control circuit is formed on the circuit forming surface of the circuit substrate 1 of the peripheral circuit layer. As a control circuit, it is formed as an integrated circuit including a transistor. As a transistor, it has a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure having a gate electrode, a source/drain region, etc. The source/drain region of the MOSFET is connected to the circuit side connection electrode 41 through other wiring layers or plugs. The circuit-side connection electrode 41 is electrically connected to a circuit-side wiring layer 42 provided on the circuit-forming surface of the peripheral circuit layer 100. The circuit-side wiring layer 42 is buried in the circuit-forming surface, and the surface is exposed from an interlayer insulating layer (not shown).

The second memory cell array layer 300 has the same structure as the first memory cell array layer 200 shown in Figures 1 to 4. That is, the second memory cell array layer 300 has the third surface (lower surface) Sb1 of Figure 1 and the fourth surface (upper surface) Sb2 on the opposite side of the third surface, and has a second memory cell array 10b with a three-dimensional structure. In addition, description of the same structure is omitted.

The second memory cell array layer 300 does not include a substrate. Furthermore, a second source side wiring layer 19b is provided on the fourth surface side relative to the second source line SL.

Similar to the first memory cell array layer 200, at least a portion of the word wiring layer 33 and the select gate wiring layer 34 is led out to the outside of the second memory cell array region 28b when viewed from a direction perpendicular to the third plane as a word line lead portion 35 and a select gate line lead portion 36 through other wiring layers or plugs. The word line lead portion 35 and the select gate line lead portion 36 led out to the outside of the second memory cell array region 28b are connected to the second signal line lead electrode 37b provided on the outside of the second memory cell array region 28b.

Furthermore, the channel body 20 of the second columnar portion 13b is electrically connected to the second bit line BL and the second source line SL. Furthermore, at least a portion of the second bit line BL and the second source line SL is led out to the outside of the second memory cell array region 28b when viewed from a direction perpendicular to the third plane as a second bit line lead portion and a second source line lead portion through other wiring layers or plugs. The second bit line lead portion and the second source line lead portion led out to the outside of the first memory cell array region 28b are connected to the second signal line lead electrode 37b provided on the outside of the second memory cell array region 28b. In addition, since the structure in the second memory cell array region 28b is the same as that in the first memory cell array layer 200, the description of the symbols is omitted.

The third surface wiring layer 38b and the fourth surface wiring layer 39b are provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300. The third surface wiring layer 38b and the fourth surface wiring layer 39b are respectively buried in the third surface Sb1 and the fourth surface Sb2, and the surfaces are exposed from the interlayer insulating layer (not shown). Here, for example, the second signal line lead electrode 37b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b respectively provided on the third surface and the fourth surface of the second memory cell array layer 300. The second signal line lead electrode, the third and fourth surface wiring layers penetrate the second memory cell array layer 300.

Furthermore, a second external connection electrode 40b is provided outside the second memory cell array region 28b. That is, the second external connection electrode 40b is provided in a region further outside the step structure portion of the memory cell array. The second external connection electrode 40b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b respectively provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300. The third surface wiring layer 38b and the fourth surface wiring layer 39b are respectively buried in the third surface Sb1 and the fourth surface Sb2, and the surface is exposed from the interlayer insulating layer not shown. The second external connection electrode 40b, the third surface wiring layer 38b, and the fourth surface wiring layer 39b penetrate the second memory cell array layer 300. In the fourth surface wiring layer 39b, an external connection pad 52 is provided on the surface wiring layer electrically connected to the second external connection electrode 40b.

As shown in FIG. 1 , the first surface wiring layer 38a disposed on the first surface Sa1 is bonded and joined to the circuit side wiring layer 42 disposed on the circuit forming surface. The first surface wiring layer 38a and the circuit side wiring layer 42 are, for example, copper or a copper alloy having copper as a main component. An insulating film (not shown) is provided around the first surface wiring layer 38a and the circuit side wiring layer 42. The insulating film is, for example, an inorganic film, a resin film, etc. The first memory cell array layer 200 is electrically connected to the peripheral circuit layer 100 via the first surface wiring layer 38a and the circuit side wiring layer 42.

Furthermore, as shown in FIG. 1 , the second surface wiring layer 39a disposed on the second surface Sa2 is bonded and joined to the third surface wiring layer 38b disposed on the third surface Sb1. The second surface wiring layer 39a and the third surface wiring layer 38b are, for example, copper or a copper alloy having copper as a main component. An insulating film (not shown) is provided around the second surface wiring layer 39a disposed on the second surface and the third surface wiring layer 38b disposed on the third surface Sb1. The insulating film is, for example, an inorganic film including a silicon nitride film. The first memory cell array layer and the second memory cell array layer are electrically connected via the second surface wiring layer 39a and the third surface wiring layer 38b.

In addition, when the insulating film around the wiring layer is an inorganic film, the wiring layers can be bonded to each other at the bonding surface, and the bonding using hydrogen bonding between the inorganic films can be performed. Therefore, if an inorganic film is used as the insulating film, it is not easy to generate a gap at the bonding surface, so it is better in that the bottom layer filling using a resin mold is not required.

FIG5 is a schematic three-dimensional diagram of the semiconductor memory device of the first embodiment, and is a schematic three-dimensional diagram related to the electrical connection state of the peripheral circuit layer, the first memory cell array layer, and the second memory cell array layer.

As shown in FIG5 , the peripheral circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 are electrically connected via the first signal line lead electrode, the second signal line lead electrode, the first external connection electrode, and the second external connection electrode (not shown). The signal line lead electrode is provided outside the memory cell array regions 28a and 28b, and the external connection electrode is provided outside the memory cell array region and in the region further outside the stepped structure portion of the memory cell array. The signal line lead electrodes and external connection electrodes of the memory cell array layer are respectively arranged in overlapping areas when viewed from a direction perpendicular to the first surface Sa1. The signal line lead electrodes are electrically connected to the surface wiring layers 39a and 39b, and the external connection electrodes of the second memory cell array layer 300, which is the uppermost layer, are electrically connected to the external connection pad 52. In addition, in FIG. 5, only a part of the electrical connection state of the first signal line lead electrode, the second signal line lead electrode, the first external connection electrode, and the second external connection electrode is shown, and the rest is omitted.

The method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to Figures 6 to 9. Figures 6 to 9 are cross-sectional views of the semiconductor memory device in relation to the method for manufacturing the semiconductor memory device according to the first embodiment.

As shown in FIG6 , a control circuit including transistors and the like is formed on a circuit substrate 1, and a peripheral circuit layer 100 having a circuit side wiring layer 42 whose surface is exposed from an insulating film (not shown) is formed. Furthermore, a first insulating layer 50 is formed under another substrate 2, such as a silicon oxide film as a buffer layer, and a first source line side wiring layer 19a and a first source line 17a are formed under the first insulating layer 50, and a first selection gate SG, a plurality of electrode layers WL, etc. are formed under the first source line 17a. Then, a memory string MS, a staircase structure portion 29, etc. are formed. Furthermore, a first surface wiring layer 38a is formed whose surface is exposed from the first external connection electrode 40a, the first signal line lead electrode 37a and the insulating film (not shown) to form the first memory cell array layer 200. Next, the circuit side wiring layer 42 of the peripheral circuit layer 100 and the first surface wiring layer 38a of the first memory cell array layer 200 are stacked in an opposing manner.

Next, as shown in FIG7 , the peripheral circuit layer 100 and the first memory cell array layer 200 are stacked. At this time, the circuit side wiring layer 42 and the first surface wiring layer 38a are joined. As a joining method, for example, mechanical pressure is applied to join and diffusion joining is performed. Alternatively, the joining surface is treated with an inert plasma and joined by hydrogen bonding generated by forming OH groups on the joining surface. Alternatively, an organic adhesive is used for joining. Thereafter, the substrate 2 is removed, for example, by using a solution such as KOH. At this time, the insulating films around each wiring layer may also be joined to each other.

It is believed that since the memory cell array layer does not have a substrate, it is easy to be deformed by the stress applied to the memory cell array layer, causing the stacked semiconductor memory device to bend. Therefore, the second insulating layer 51 is formed. The second insulating layer 51 is a layer having stress in the opposite direction to the bending generated after removing the substrate, and is formed as a stress adjustment film. As the second insulating layer 51, for example, a silicon nitride film is formed. In this way, the stress generated in the semiconductor memory device can be alleviated, and the bending of the semiconductor memory device can be suppressed.

Next, the first insulating layer 50 and the second insulating layer 51 are removed to form a groove so that the upper surfaces of the first external connection electrode 40a and the first signal line lead electrode 37a are exposed. As shown in FIG8 , the second surface wiring layer 39a, which becomes a bonding metal, is formed in the groove so that the upper surface of the second surface wiring layer 39a is exposed.

Next, following FIG8, the peripheral circuit layer 100 shown in FIG6 is replaced with the first memory cell array layer 200, and the first memory cell array layer 200 shown in FIG6 is replaced with the second memory cell array layer 300, and the same steps as FIG6 to FIG8 are repeated. As shown in FIG9, in the fourth surface wiring layer 39b exposed on the upper surface, an external connection pad 52 is formed on the surface wiring layer electrically connected to the second external connection electrode 40b. In this way, a semiconductor memory device having the peripheral circuit layer 100, the first memory cell array layer 200 and the second memory cell array layer 300 stacked thereon can be formed.

In the first embodiment, the second memory cell array layer 300 is stacked on the first memory cell array layer 200, but one or more other memory cell array layers may be stacked on the second memory cell array layer 300. In this case, at least a portion of the one or more other memory cell array layers may also include a substrate. In this case, the warp of the stacked semiconductor memory device can be reduced.

Furthermore, the peripheral circuit layer 100 may not be laminated, and only the memory cell array layer may be laminated.

(First variation) Figure 10 is a schematic cross-sectional view of a semiconductor memory device of the first variation of the first embodiment. A wiring layer 61 is provided to connect the memory string MS1 of the first memory cell array layer 200 and the memory string MS2 of the second memory cell array layer 300. The wiring layer 61 is provided inside the memory cell array region and is connected to the first source side wiring layer 19a of the first memory cell array layer 200 and the second bit line 16b of the second memory cell array layer 300. The first memory cell array layer and the second memory cell array layer are connected without using a signal line lead electrode disposed outside the memory cell array region.

In the first variation, the first memory cell array layer and the second memory cell array layer are connected using a wiring layer disposed inside the memory cell array region in addition to the signal line lead-out electrodes disposed outside the memory cell array region.

By forming in this way, the electrode area required for connecting the memory cell array layer can be reduced, and the chip area can be reduced.

(Second variation) Figure 11 is a schematic cross-sectional view of a semiconductor memory device of the second variation of the first embodiment. The description of the external connection electrode is omitted.

At least a portion of the word wiring layer and the select gate wiring layer of the first memory cell array layer 200 is led out as a word line lead-out portion 35 and a select gate line lead-out portion 36 through other wiring layers or plugs, and is folded back to the inner side of the first memory cell array region 28a when viewed from a direction perpendicular to the first plane Sa1. The word line lead-out portion 35 and the select gate line lead-out portion 36 led out to the inner side of the first memory cell array region 28a are connected to the first signal line lead-out electrode 37a provided on the inner side of the first memory cell array region 28a.

Similarly, at least a portion of the first bit line BL and the first source line SL is led out as a first bit line lead portion and a first source line lead portion through other wiring layers or plugs, and is folded back to the inner side of the first memory cell array region 28a (not shown) when viewed from a direction perpendicular to the first plane Sa1. The first bit line lead portion and the first source line lead portion led out to the inner side of the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided on the inner side of the first memory cell array region 28a.

Furthermore, the first source-side wiring layer 19a on the second surface Sa2 side is connected to the first signal line lead electrode 37a disposed inside the first memory cell array region 28a. Here, a portion of the first signal line lead electrode 37a may also be disposed outside the first memory cell array region 28a.

A first surface wiring layer 38a and a second surface wiring layer 39a are provided inside the memory cell array region on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200. The first surface wiring layer 38a and the second surface wiring layer 39a provided inside the memory cell array region are electrically connected to the first signal line lead electrode 37a.

The second memory cell array layer 300 is similar to the first memory cell array layer 200. At least a portion of the word wiring layer and the select gate wiring layer is led out as a word line lead-out portion 35 and a select gate line lead-out portion 36 through other wiring layers or plugs, and is folded back to the inner side of the second memory cell array region 28b when viewed from a direction perpendicular to the third surface Sb1. The word line lead-out portion 35 and the select gate line lead-out portion 36 led out to the inner side of the second memory cell array region 28b are connected to the second signal line lead-out electrode 37b provided on the inner side of the second memory cell array region 28b.

Furthermore, at least a portion of the second bit line BL and the second source line SL is led out as a second bit line lead portion and a second source line lead portion through another wiring layer or a plug, and is folded back to the inner side of the second memory cell array region 28b (not shown) when viewed from a direction perpendicular to the third surface. The second bit line lead portion and the second source line lead portion led out to the inner side of the second memory cell array region 28b are connected to the second signal line lead electrode 37b disposed on the inner side of the second memory cell array region 28b. Here, a portion of the second signal line lead electrode 37b may also be disposed outside the second memory cell array region 28b.

On the third surface Sb1 of the second memory cell array layer 300, a third surface wiring layer 38b is provided inside the memory cell array region. The third surface wiring layer 38 provided inside the memory cell array region is electrically connected to the second signal line lead electrode 37b. Here, on the fourth surface Sb2 of the second memory cell array layer 300, a fourth surface wiring layer (not shown) may also be provided inside the memory cell array region. In this case, the fourth surface wiring layer provided inside the memory cell array region is electrically connected to the second signal line lead electrode 37b.

Therefore, the signal line lead-out electrode of each memory cell array layer is connected to the surface wiring layer disposed inside the memory cell array region, and the surface wiring layer of each memory array layer can be disposed in overlapping regions when viewed from a direction perpendicular to the first surface. Thus, when multiple memory cell array layers are stacked, the chip area can be further reduced, and the wiring length can be suppressed, thereby suppressing the action delay.

According to the second variation, at least a portion of the bit lines or word lines are folded back to the inside of the memory cell array region. The signal line lead electrodes connected via the bit line lead portions and the word line lead portions are disposed inside the memory cell array region. Furthermore, the signal line lead electrodes of each memory cell array layer are connected to the surface wiring layer disposed inside the memory cell array region, and the surface wiring layers of each memory array layer can be disposed in overlapping regions when viewed from a direction perpendicular to the first surface. Thus, when multiple memory cell array layers are stacked, the chip area can be further reduced, and the wiring length can be suppressed, thereby suppressing the operation delay.

According to the first embodiment, the first memory cell array layer 200 and the second memory cell array layer 300 do not have a substrate (e.g., a silicon substrate). Therefore, when the first memory cell array layer 200 and the second memory cell array layer 300 are stacked and electrically connected, they can be connected without forming TSV (Through Silicon Via). Thereby, there is no need to perform a substrate etching step that costs money or processing time, or to form an insulating film to prevent a short circuit between the substrate and the through hole, which can reduce costs and increase processing throughput.

Furthermore, since the memory cell array layer and the peripheral circuit layer are formed by different wafer processes, when a high-temperature heat treatment is required when forming the memory cell array layer, adverse effects such as impurity diffusion of transistors in the peripheral circuit layer or degradation of the metal wiring layer can also be suppressed.

In addition, the memory cell array layer is stacked in a manner that the first surface faces the peripheral circuit layer. The bit line or word line is led out to the first surface side of the memory cell array layer, and the bit line or word line is connected to the signal line lead electrode. Since the memory cell array layer is stacked in a manner that the first surface faces the peripheral circuit layer, the wiring distance of the electrode layer can be reduced, and the adverse effect on the operation speed can be suppressed.

Furthermore, according to the first embodiment, a plurality of memory cell array layers are stacked on the peripheral circuit layer. Thus, when the stack of one memory cell array layer is 48 layers, for example, by stacking two memory cell array layers, a memory cell array of 96 layers, which is twice the number of 48 layers, can be realized using the 48-layer process technology. Therefore, the memory density can be easily increased.

Furthermore, at least a portion of the bit lines or word lines are led out of the memory cell array region, and the signal line lead electrodes connected through the bit line lead portions and the word line lead portions are arranged outside the memory cell array region. In addition, an external connection electrode is arranged outside the memory cell array region and in a region further outside the step structure portion of the memory cell array. The signal line lead electrodes and the external connection electrodes of each memory cell array layer are arranged in overlapping regions when viewed from a direction perpendicular to the first surface. Thus, when a plurality of memory cell array layers are stacked, the wiring length can be reduced and the operation delay can be reduced.

Alternatively, at least a portion of the bit lines or word lines are folded back to the inside of the memory cell array area. The signal line lead electrodes connected via the bit line lead portions and the word line lead portions are arranged inside the memory cell array area. Furthermore, the signal line lead electrodes of each memory cell array layer are connected to the surface wiring layer arranged inside the memory cell array area, and the surface wiring layers of each memory array layer are arranged in overlapping areas when observed from a direction perpendicular to the first surface. In this way, when a plurality of memory cell array layers are stacked, the chip area can be further reduced, and the wiring length can be suppressed, which can suppress the action delay.

Furthermore, the external connection electrode and the surface wiring layer connected to the external connection electrode are arranged in a manner that at least passes through the upper and lower layers sandwiched by the memory cell array layer or/and the peripheral circuit layer (here, the first memory cell array layer). Furthermore, the signal line lead electrode and the surface wiring layer connected to the signal line lead electrode are arranged in a manner that at least passes through the upper and lower layers sandwiched by the memory cell array layer or/and the peripheral circuit layer (here, the first memory cell array layer). Therefore, when a plurality of memory cell array layers are stacked, the wiring length can be further suppressed, the action delay can be further suppressed, and the reliability can be improved.

Furthermore, the external connection electrode can be arranged as if it is not connected to the memory cell, and the external signal can be input to the peripheral circuit layer from the external connection pad without passing through the memory cell. In this way, adverse effects such as operation delay can be further suppressed. In addition, since the signal line lead-out electrode is electrically connected to each memory cell array layer even if it is not connected to the memory cell path, the signal line of each layer is connected without passing through the memory cell. In this way, adverse effects such as operation delay can be further suppressed.

In addition, the memory cell array layer does not have a substrate, and there is no need to form a silicon through-electrode such as TSV. Instead of setting a substrate on the second surface side (fourth surface side) of the memory cell array layer, a source side wiring layer is set. In this way, the stacked memory cell array layers can be connected arbitrarily, and the wiring area can be increased without increasing the chip area.

Furthermore, the first source side wiring layer can be used as the first source lead portion of the first source line SL. The second source side wiring layer can be used as the second source line lead portion of the second source line SL. In this way, in a memory cell array having a columnar portion in an I-shaped memory cell string, by providing a source side wiring layer on the second side (fourth side) of the source line, the wiring length from the source line to the signal line lead electrode can be effectively suppressed.

Furthermore, the signal line lead-out electrode and the surface wiring layer of the second memory cell array layer can also be formed in a manner penetrating the second memory cell array layer in the same manner as the first memory cell array layer. In this case, it is preferable that the device structures of the first memory cell array layer and the second memory cell array layer can be made common, and the characteristics such as stress generated by the memory cell array layer can be made consistent. In addition, it is preferable that the manufacturing processes of the first memory cell array layer and the second memory cell array layer can be made common, and the memory cell array layer can be manufactured efficiently.

Furthermore, in the first memory cell array layer or the second memory cell array layer, the bit line or the word line is led out to the first surface side or the third surface side, and the bit line or the word line is connected to the signal line lead-out electrode. The first memory cell array layer is stacked in such a manner that the first surface is opposite to the peripheral circuit layer, and the second memory cell array layer is stacked in such a manner that the third surface is opposite to the first memory cell array layer. That is, the first memory cell array layer and the second memory cell array layer lead out the signal line in the same direction, and are stacked in such a manner that the first memory cell array layer and the second memory cell array layer have the same orientation. In this way, since the bit line or word line is led to the side where the peripheral circuit layer is provided (the lower side in FIG. 1 ) and is stacked on the peripheral circuit layer, the wiring distance of the electrode layer can be reduced, and the adverse effect on the operation speed can be suppressed.

Furthermore, assuming that the first memory cell array layer and the second memory cell array layer are stacked in a manner that they face each other while not facing each other, one memory cell array layer must be disposed on a tape, for example, and after removing the substrate from the tape, the layer is stacked in a manner that the surface after the substrate is removed faces the peripheral circuit or another memory cell array layer. If the first memory cell array layer and the second memory cell array layer are stacked in a manner that they face each other while not facing each other, there is no need to use a tape or the like. That is, the memory cell array layer formed on the substrate can be stacked directly on the peripheral circuit layer with the substrate surface on top, and the substrate can be removed to form the layer. Thereby, the memory cell array layer and the second memory cell array layer are stacked in the same orientation, which is also advantageous in that they can be easily formed without using a tape or the like.

(Second embodiment) Next, the semiconductor memory device of the second embodiment is described. In addition, the basic structure is the same as the first embodiment, so the description of the matters described in the first embodiment is omitted.

Fig. 12 is a schematic cross-sectional view of a semiconductor memory device of the second embodiment. In Fig. 12, a memory cell array layer is further stacked on the semiconductor memory device of Fig. 1, and a peripheral circuit layer 100, a first memory cell array layer 200, a second memory cell array layer 300, and a third memory cell array layer 400 are sequentially provided from the bottom.

Here, as shown in FIG12 , the second memory cell array layer 300 is provided with a wiring layer 71 connected to the memory string MS3 between the third surface wiring layer 38b provided on the third surface Sb1 and the fourth surface wiring layer 39b provided on the fourth surface Sb2. That is, the second memory cell array layer 300 is connected to the upper and lower memory cell array layers through the wiring layer 71 via the memory string MS3.

FIG. 13 is a circuit diagram of a semiconductor memory device of the second embodiment. FIG. 13 shows a portion of a circuit of a memory string MS3 connected to a wiring layer 71. A plurality of memory cells are provided, and a portion of the diagram is omitted. A drain side selection transistor STD and a source side selection transistor STS are provided in a plurality of memory cells, and an array layer ID provided in each memory cell array layer is stored. The circuit of the memory string MS3 functions as a portion of a selection circuit for selecting an array layer.

Fig. 14 is a block diagram showing the system configuration of the semiconductor memory device according to the second embodiment. Fig. 14 shows the system configuration of the semiconductor memory device including an array layer selection circuit provided in the memory string MS3 connected to the wiring layer 71.

In each memory cell array layer, an address line and an array layer selection signal line are input as a signal line. In the memory cell array layer, whether the memory cell array layer is selected is determined by the array layer selection signal line and the ID of the memory array layer, and an address line is input to the memory cell array.

By forming in this way, instead of using each signal line to select the memory cell array individually, the memory cell array layer can be selected using the transistors and memory cells in the memory string MS3. Even if the semiconductor memory device has a plurality of stacked memory cell array layers, the number of wiring can be greatly reduced.

In this case, each memory region or memory block of the second memory cell array layer can be connected to the upper and lower memory cell array layers using the wiring layer 71. By forming in this way, the memory region or memory block can be selected using each transistor and each memory cell in each memory string MS, and the number of wirings can be greatly reduced even for a semiconductor memory device having a plurality of stacked memory cell array layers.

The above description is directed to the embodiments with reference to the drawings, but the present invention is not limited thereto.

The present invention describes an example in which a circuit substrate is included, but a case in which only a memory cell array layer is stacked is also included in the scope of the present invention.

Various design changes made by technicians in this field regarding the structure of the memory cell array constituting the present invention are also included in the scope of the present invention as long as they do not deviate from the gist of the present invention.

According to yet another aspect, a semiconductor memory device is provided, characterized in that it has a three-dimensional memory cell array of another structure.

Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and can be omitted, replaced, and modified in a variety of ways without departing from the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the patent application and its equivalents.

1: Circuit substrate 2: Substrate 10a: 1st memory cell array 10b: 2nd memory cell array 11: Insulation layer 12a: 1st laminate 13a: 1st columnar portion 13b: 2nd columnar portion 14: Interlayer insulation film 15: Interlayer insulation film 16a: 1st bit line 16b: 2nd bit line 17a: 1st source line 18: Interlayer insulation film 19a: 1st source side wiring layer 19b: 2nd source side wiring layer 20: Channel body 21: Memory film 22: Block insulation film 23: Charge storage film 24: Tunnel insulation film 25: Core insulation film 26: Insulation film 27: Insulation film 28a: First memory cell array region 28b: Second memory cell array region 29: Step structure 30: Contact plug 31: Interlayer insulation layer 32: Contact plug 33: Word wiring layer 34: Select gate wiring layer 35: Word line lead-out section 36: Select gate line lead-out section 37a: First signal line lead-out electrode 37b: 2nd signal line lead electrode 38a: 1st surface wiring layer 38b: 3rd surface wiring layer 39a: 2nd surface wiring layer 39b: 4th surface wiring layer 40a: 1st external connection electrode 40b: 2nd external connection electrode 41: Circuit side connection electrode 42: Circuit side wiring layer 50: 1st insulation layer 51: 2nd insulation layer 52: External connection pad 61: Wiring layer 71: Wiring layer 100: Peripheral circuit layer 200: 1st memory cell array layer 221: Silicon nitride film 222: Silicon oxide film 300: 2nd memory cell array layer 400: 3rd memory cell array layer A: Partial BL: Bit line MC: Memory cell MS: Memory string MS1: Memory string MS2: Memory string MS3: Memory string Sa1: 1st side Sa2: 2nd side Sb1: 3rd side Sb2: 4th side SG: Select gate SGD: Drain side select gate SGS: Source side select gate SL: Source line STD: Drain side select transistor STS: Source side select transistor WL: Electrode layer X: direction Y: direction Z: direction

FIG. 1 is a schematic cross-sectional view showing a semiconductor memory device of the first embodiment. FIG. 2 is a schematic three-dimensional view showing a semiconductor memory device of the first embodiment. FIG. 3 is a schematic cross-sectional view showing a semiconductor memory device of the first embodiment. FIG. 4 is a schematic cross-sectional view showing a portion of the semiconductor memory device of the first embodiment in an enlarged manner. FIG. 5 is a schematic three-dimensional view showing a semiconductor memory device of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device of the first embodiment. FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device of the first embodiment. FIG8 is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device of the first embodiment. FIG9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor memory device of the first embodiment. FIG10 is a schematic cross-sectional view of a semiconductor memory device of the first variation of the first embodiment. FIG11 is a schematic cross-sectional view of a semiconductor memory device of the second variation of the first embodiment. FIG12 is a schematic cross-sectional view showing a semiconductor memory device of the second embodiment. FIG13 is a circuit diagram of a semiconductor memory device of the second embodiment. FIG14 is a block diagram showing a system configuration of a semiconductor memory device of the second embodiment.

1: Circuit board

10a: 1st memory cell array

10b: Second memory cell array

19a: 1st source side wiring layer

19b: Second source side wiring layer

28a: The first memory cell array area

28b: Second memory cell array area

29: Staircase structure

30: Contact plug

31: Interlayer insulation layer

32: Contact plug

33: Character wiring layer

34: Select the gate wiring layer

35: Character line lead-out section

36: Select the gate lead-out section

37a: The first signal line leads to the electrode

37b: The second signal line leads to the electrode

38a: 1st surface wiring layer

38b: 3rd surface wiring layer

39a: Second surface wiring layer

39b: 4th surface wiring layer

40a: 1st external connection electrode

40b: Second external connection electrode

41: Circuit side connection electrode

42: Circuit side wiring layer

52: External connection pad

100: Peripheral circuit layer

200: 1st memory cell array layer

300: Second memory cell array layer

BL: Bit Line

Sa1: Page 1

Sa2: Page 2

Sb1: Page 3

Sb2: Page 4

SG: Select Gate

SL: Source line

WL:Electrode layer

X: Direction

Z: Direction

Claims (10)

A semiconductor memory device, comprising: A first memory cell array, comprising: a first electrode film extending along a first direction, a second electrode film extending along the first direction and having the first electrode film laminated on the second direction side perpendicular to the first direction, and a third electrode film extending along the first direction and having the second electrode film laminated on the second direction side; A first external connection electrode, disposed on the second direction side relative to the first memory cell array; and A peripheral circuit, disposed opposite to the first memory cell array in the direction opposite to the second direction side, and driving the first memory cell array; The first length of the first electrode film along the first direction is shorter than the second length of the second electrode film along the first direction, and the second length is shorter than the third length of the third electrode film along the first direction. A semiconductor memory device as claimed in claim 1, comprising: A second memory cell array, comprising: a fourth electrode film disposed on the second direction side of the first memory cell array and extending along the first direction, a fifth electrode film extending along the first direction and having the fourth electrode film laminated on the second direction side, and a sixth electrode film extending along the first direction and having the fifth electrode film laminated on the second direction side; The fourth length of the fourth electrode film along the first direction is shorter than the fifth length of the fifth electrode film along the first direction, and the fifth length is shorter than the sixth length of the sixth electrode film along the first direction. A semiconductor memory device as claimed in claim 1, comprising: a first contact electrically connected to at least one of the first electrode film, the second electrode film, and the third electrode film; and a second contact electrically connected to the peripheral circuit; and the first contact is electrically connected to the second contact. A semiconductor memory device as claimed in claim 3, comprising: a first bonding electrode electrically connected to the first contact; and a second bonding electrode electrically connected to the second contact; the first bonding electrode and the second bonding electrode are bonded to each other at a first bonding surface, the diameter of the first bonding electrode near the first bonding surface is larger than the diameter of the first contact, and the diameter of the second bonding electrode is larger than the diameter of the second contact. The semiconductor memory device of claim 3 comprises: A third contact electrically connected to at least one of the fourth electrode film, the fifth electrode film, and the sixth electrode film; The first contact electrically connected to the third contact. A semiconductor memory device as claimed in claim 5, comprising: a third bonding electrode electrically connected to the first contact; and a fourth bonding electrode electrically connected to the third contact; the third bonding electrode and the fourth bonding electrode are bonded to each other at a second bonding surface, the diameter of the third bonding electrode near the second bonding surface is larger than the diameter of the first contact, and the diameter of the fourth bonding electrode is larger than the diameter of the third contact. A semiconductor memory device as claimed in claim 1, comprising: a first semiconductor column, which passes through the first electrode film, the second electrode film, and the third electrode film; and a fourth contact, which is electrically connected to the first semiconductor column. A semiconductor memory device as claimed in claim 7, wherein the end of the first semiconductor column on the second direction side is connected to the first source line. A semiconductor memory device as claimed in claim 7, comprising: a second semiconductor column, which passes through the fourth electrode film, the fifth electrode film, and the sixth electrode film; and a fifth contact, which is electrically connected to the second semiconductor column. A semiconductor memory device as claimed in claim 9, wherein the fourth contact is electrically connected to the fifth contact.