TW202509703A - System-on-chip including voltage droop detection circuit and operating method thereof - Google Patents

Abstract

A system-on-chip includes a functional circuit, a voltage droop detection circuit, a clock generation circuit, and a clock modulation. The voltage droop detection circuit includes a voltage droop detection controller, a reference voltage generator, and a detection signal generator. An operating method of the system-on-chip is also provided.

Description

System chip including voltage drop detection circuit and operation method thereof

[Cross reference to related applications]

This application claims priority to Korean Patent Application No. 10-2023-0052213 filed on April 20, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0094020 filed on July 19, 2023, in the Korean Intellectual Property Office. The disclosures of the above Korean patent applications are incorporated herein by reference in their entirety.

Embodiments of the inventive concept relate to a semiconductor circuit, and more particularly, to a system chip including a voltage drop detection circuit and an operating method thereof.

The supply voltage of a high-performance functional circuit (or semiconductor circuit) included in a system-on-chip (SoC) fluctuates according to the operating environment and the level of work performed. Generally, in order to prevent a droop phenomenon in which the voltage decreases significantly, a method of setting a protection band on the supply voltage so that the supply voltage has a value larger than the value used in a normal state is used. The protection band refers to a value that is additionally increased to the value of the supply voltage in a normal state in consideration of the droop. However, the power consumption of the SoC increases due to the setting of a high protection band, and thus the efficiency of the product may decrease.

Embodiments of the inventive concept provide a system chip and a method for operating the system chip, wherein the system chip includes a voltage drop detection circuit, and the voltage drop detection circuit can provide efficient power consumption of the functional circuit by controlling the frequency of an adaptive clock signal provided to the functional circuit when a drop in supply voltage has been detected.

According to an embodiment of the present invention, a system chip is provided, which includes: a functional circuit configured to receive a supply voltage and perform a processing operation; a voltage drop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a voltage drop has occurred; a clock generation circuit configured to output a clock signal; and a clock modulation circuit configured to receive the detection signal and the clock signal, generate an adaptive clock signal by modulating the clock signal to correspond to the detection signal, and provide the adaptive clock signal to the functional circuit. The voltage drop detection circuit includes: a voltage drop detection controller configured to control a reference voltage to remain constant; a reference voltage generator configured to generate the reference voltage; and a detection signal generator configured to generate the detection signal by comparing the reference voltage with the supply voltage.

According to an aspect of an embodiment of the inventive concept, a method for operating a system chip is provided, the method comprising monitoring a supply voltage by a voltage drop detection circuit included in the system chip. The supply voltage is received by a functional circuit included in the system chip, and the functional circuit is configured to perform a processing operation. The method further comprises: comparing the level of the supply voltage with the level of a reference voltage; generating a detection signal based on the result of the comparison; and adjusting the frequency of a clock signal based on the detection signal.

According to an embodiment of the present invention, a system chip is provided, which includes: a first functional circuit, configured to receive a supply voltage and perform a first processing operation; a first voltage drop detection circuit, configured to monitor the supply voltage and generate a first detection signal indicating whether a voltage drop has occurred; a second functional circuit, configured to receive the supply voltage and perform a second processing operation; a second voltage drop detection circuit, configured to monitor the supply voltage and generate a second detection signal indicating whether the voltage drop has occurred; a clock generation circuit, configured to output a clock signal; and a clock modulation circuit. The clock modulation circuit is configured to receive the first detection signal and the second detection signal and the clock signal, and generate a first adaptive clock signal and a second adaptive clock signal by modulating the clock signal to correspond to the first detection signal and the second detection signal, respectively, and provide the first adaptive clock signal and the second adaptive clock signal to the first functional circuit and the second functional circuit, respectively. The first voltage drop detection circuit includes: a first controller, configured to control a first reference voltage to remain constant; a first reference voltage generator, configured to generate the first reference voltage; and a first detection signal generator, configured to generate the first detection signal by comparing the first reference voltage with the supply voltage. The second voltage drop detection circuit includes: a second controller configured to control a second reference voltage to remain constant; a second reference voltage generator configured to generate the second reference voltage; and a second detection signal generator configured to generate the second detection signal by comparing the reference voltage with the supply voltage.

Embodiments of the present inventive concept will be more fully described hereinafter with reference to the accompanying drawings. Throughout the accompanying drawings, like reference numerals may refer to like elements.

It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an embodiment may be described as the "second" element in another embodiment.

It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly dictates otherwise.

As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As will be understood by one skilled in the art, herein, when two or more elements or values are described as being substantially the same or approximately equal to one another, it is understood that the elements or values are equivalent to one another, are equal to one another within measurement error, or, if significantly unequal, are close enough in value to be functionally equal to one another. For example, with respect to the measurements in question and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term "about" as used herein includes the stated value and means within an acceptable range of deviations of the particular value determined by one skilled in the art. For example, one skilled in the art will understand that "about" may mean within one or more standard deviations. Furthermore, it should be understood that although a parameter may be described herein as having "about" a certain value, depending on the embodiment, the parameter may be exactly a certain value or approximately a certain value within measurement error, as will be understood by those skilled in the art. Other uses of these and similar terms to describe relationships between components should be interpreted in a similar manner.

Fig. 1 is a block diagram schematically illustrating a system chip 10 according to an embodiment. Fig. 2 is a block diagram illustrating a system chip 10 according to an embodiment in detail. The system chip 10 of Fig. 1 may be referred to as an adaptive clock system.

1 , the system chip 10 may include a functional circuit 100 , a voltage drop detection circuit 200 , a temperature sensor 300 , and a clock controller 400 .

In more detail, referring to FIG. 2 , the functional circuit 100 may include a remote temperature sensor (RTS) 110 , the voltage droop detection circuit 200 may include a voltage droop detection (VDD) controller 210 and a reference voltage generator 220 , and the clock controller 400 may include a clock generation circuit 410 and a clock modulation circuit 420 .

1 and 2 together, the functional circuit 100 can perform a certain processing operation by receiving a supply voltage VSUP via a power line PL. In an embodiment, the functional circuit 100 can be implemented as hardware, such as (for example) a central processing unit (CPU), a graphics processing unit (GPU), a processor, a modem, or similar hardware. RTS 110 can be a sensor for measuring the temperature within the functional circuit 100.

The voltage drop detection circuit 200 can monitor the supply voltage VSUP via the power line PL, and can generate and provide a detection signal FLAG indicating whether the supply voltage VSUP has dropped to the clock modulation circuit 420.

In an embodiment, when the supply voltage VSUP drops below the reference voltage, the voltage drop detection circuit 200 can generate a high-level detection signal FLAG. For example, the voltage drop detection circuit 200 can use multiple reference voltages with different levels to generate the detection signal FLAG, and the detection signal FLAG includes multiple bits to indicate that the supply voltage VSUP drops and the degree of the drop.

The temperature sensor 300 can measure the temperature within the system chip 10. In some embodiments, the temperature sensor 300 can measure the temperature of the functional circuit 100. Temperature is a parameter that affects the operation of the functional circuit 100. When the temperature is too high, it may be difficult for the functional circuit 100 to smoothly perform processing operations in synchronization with the adaptive clock signal ACLK having a high frequency. Therefore, according to the embodiments of the inventive concept described above, when the temperature is approximately equal to or greater than the reference temperature, the clock modulation circuit 420 can reduce the frequency of the adaptive clock signal ACLK. The temperature sensor 300 can generate a temperature sensing signal TSS indicating the temperature state of the system chip 10.

In an embodiment, the voltage drop detection circuit 200 may generate a detection signal FLAG based on a temperature sensing signal TSS received from the temperature sensor 300.

In addition to the temperature sensor 300 , the system chip 10 may further include at least one sensor for sensing a parameter affecting the operation of the functional circuit 100 , and the clock modulation circuit 420 may modulate the frequency of the clock signal CLK based on the detection signal FLAG received from the voltage drop detection circuit 200 .

When the supply voltage VSUP in a normal state is provided to the functional circuit 100, the clock generation circuit 410 may generate a clock signal CLK having a frequency corresponding to the operating frequency of the functional circuit 100. The clock generation circuit 410 may be implemented as, for example, a phase-locked loop (PLL) or a frequency-locked loop (FLL).

The clock modulation circuit 420 can receive the detection signal FLAG and the clock signal CLK, generate the adaptive clock signal ACLK by modulating the clock signal CLK to correspond to the detection signal FLAG, and provide the adaptive clock signal ACLK to the functional circuit 100. In an embodiment, the clock modulation circuit 420 can adjust the frequency of the adaptive clock signal ACLK according to the degree of decrease of the supply voltage VSUP. When the degree of decrease increases, the clock modulation circuit 420 can set the frequency of the adaptive clock signal ACLK to be lower than the frequency of the clock signal CLK, and can adaptively adjust the frequency of the adaptive clock signal ACLK according to the operating environment of the functional circuit 100 and the level of work performed by the functional circuit 100, as further described with reference to Figures 6 to 8.

In an embodiment, the clock modulation circuit 420 may divide or multiplex the clock signal CLK in response to the detection signal FLAG to adjust the frequency of the clock signal CLK, thereby providing an adaptive clock signal ACLK. To this end, the clock modulation circuit 420 may include a plurality of frequency dividers and a multiplexer. Each of the plurality of frequency dividers may divide the frequency of the clock signal CLK, and the multiplexer may output at least one output of the plurality of frequency dividers to the adaptive clock signal ACLK. The detailed configuration of the clock modulation circuit 420 is explained with reference to FIG. 5.

The clock controller 400 according to the embodiment may modulate the frequency of the clock signal CLK to a low level when the supply voltage VSUP has dropped, and provide the clock signal CLK having the modulated frequency to the functional circuit 100.

The functional circuit 100 performs processing operations based on the adaptive clock signal ACLK whose frequency is lower than before the supply voltage VSUP drops, so that the power consumption of the functional circuit 100 can be reduced within a certain time period. Therefore, the system chip 10 can perform stable operations when the dropped supply voltage VSUP is quickly restored, and the guard band applied to the supply voltage VSUP can be reduced to reduce the total amount of power consumed by the system chip 10.

That is, when the supply voltage VSUP has decreased (voltage drop), the system chip 10 of FIG. 1 can detect the decrease to change the frequency of the clock signal CLK using the clock modulation circuit 420, thereby enabling the functional circuit 100 to operate at a low voltage.

FIG. 3 is a block diagram illustrating a voltage drop detection circuit 200 according to an embodiment.

3 , the voltage drop detection circuit 200 may include a VDD controller 210 , a reference voltage generator 220 , and a detection signal generator 230 .

The VDD controller 210 may control the overall operation in which the voltage drop detection circuit 200 detects whether a drop in the supply voltage VSUP has occurred.

The reference voltage generator 220 may provide a reference voltage VREF to the detection signal generator 230 in response to a control signal of the VDD controller 210. For example, the reference voltage generator 220 may provide a plurality of reference voltages VREF to the detection signal generator 230. The detailed configuration of the reference voltage generator 220 is explained below with reference to FIG. 4 .

The detection signal generator 230 can determine whether a drop has occurred by checking whether the supply voltage VSUP is less than the reference voltage VREF. The detection signal generator 230 can generate and provide a detection signal FLAG to the clock modulation circuit 420 of FIG2 based on the determination result. For example, the detection signal generator 230 can compare the supply voltage VSUP with each of the multiple reference voltages VREF to specifically determine the magnitude of the supply voltage VSUP, thereby generating a detection signal FLAG when a drop has occurred, and the detection signal FLAG includes a plurality of bits indicating the extent of the drop of the supply voltage VSUP. Furthermore, the detection signal generator 230 may include a comparator for comparing the supply voltage VSUP with the reference voltage VREF.

FIG. 4 is a block diagram illustrating a reference voltage generator 220 according to an embodiment.

4 , the reference voltage generator 220 may include a band gap reference (BGR) circuit 221 , a reference voltage buffer 222 , a digital-to-analog converter (DAC) 223 , and a DAC buffer 224 .

The BGR circuit 221 may generate a bandgap reference voltage. The reference voltage buffer 222 may receive the bandgap reference voltage and output a DAC reference voltage. The DAC 223 may convert the DAC reference voltage into an analog reference voltage according to an input code. The DAC 223 may output the analog reference voltage. The DAC buffer 224 may output an analog reference voltage VREF.

For example, the BGR circuit 221 may generate a bandgap reference voltage of approximately 0.35 volts, and the reference voltage buffer 222 may output a DAC reference voltage of approximately 0.8 volts. The DAC 223 may receive the DAC reference voltage and convert the DAC reference voltage into an analog reference voltage to output an analog reference voltage of approximately 0 volts to approximately 0.8 volts. The DAC buffer 224 may output an analog reference voltage VREF of approximately 0 volts to approximately 0.8 volts.

The method for adjusting the reference voltage by the reference voltage generator 220 is described below with reference to FIG. 8 .

FIG5 is a block diagram illustrating a clock modulation circuit 420 according to an embodiment.

5 , the clock modulation circuit 420 may include a plurality of frequency dividers 421 and 422 and a multiplexer 423 .

The plurality of frequency dividers 421 and 422 may receive a clock signal CLK and divide the clock signal CLK according to different division ratios to generate a first divided clock signal DCLK1 and a second divided clock signal DCLK2 having different frequencies. For example, the frequency of the first divided clock signal DCLK1 and the frequency of the second divided clock signal DCLK2 may be approximately equal to the frequency of the clock signal CLK, or the frequency of the first divided clock signal DCLK1 and the frequency of the second divided clock signal DCLK2 may be less than the frequency of the clock signal CLK.

FIG. 5 shows a case where the clock modulation circuit 420 includes two frequency dividers 421 and 422, but the clock modulation circuit 420 is not limited thereto and may include any number of frequency dividers.

The multiplexer 423 may output any one of the first frequency-divided clock signal DCLK1 and the second frequency-divided clock signal DCLK2 as the adaptive clock signal ACLK in response to the detection signal FLAG.

For example, when the supply voltage has dropped, the multiplexer 423 may select and output the first divided clock signal DCLK1 as the adaptive clock signal ACLK. The frequency of the first divided clock signal DCLK1 may be less than the frequency of the clock signal CLK. When the first divided clock signal DCLK1 is selected and output as the adaptive clock signal ACLK, the frequency of the output adaptive clock signal ACLK may be less than the frequency of the clock signal CLK.

When the supply voltage does not drop, the multiplexer 423 can select and output the second frequency-divided clock signal DCLK2 as the adaptive clock signal ACLK. In this article, the second frequency-divided clock signal DCLK2 can be a clock signal with a frequency approximately equal to the frequency of the clock signal CLK.

The clock modulation circuit 420 shown in FIG. 5 may adaptively adjust the frequency ratio according to various factors such as, for example, the extent of the supply voltage drop, the operating environment of the functional circuit, or the like.

FIG. 6 is a graph illustrating the operation of the voltage drop detection circuit 200 according to an embodiment.

2, 3 and 6, since the level of the supply voltage VSUP is greater than the level of the reference voltage VREF at the first time point t1, the detection signal FLAG may be at a first logic level (eg, a low level). The clock signal CLK output by the clock generation circuit 410 may be at a first logic level.

Since the level of the supply voltage VSUP is still greater than the level of the reference voltage VREF at the second time point t2, the detection signal FLAG can be maintained at the first logic level. The clock signal CLK output by the clock generation circuit 410 can be converted to a second logic level (eg, a high level).

Although the level of the supply voltage VSUP decreases at the third time point t3, the level of the supply voltage VSUP is greater than the level of the reference voltage VREF, and thus the detection signal FLAG can be maintained at the first logic level. The clock signal CLK output by the clock generation circuit 410 can be converted to the first logic level.

Although the level of the supply voltage VSUP decreases at the fourth time point t4, the level of the supply voltage VSUP is greater than the level of the reference voltage VREF, and thus the detection signal FLAG can be maintained at the first logic level. The clock signal CLK output by the clock generation circuit 410 can be converted to a second logic level.

Since the level of the supply voltage VSUP decreases and becomes less than the level of the reference voltage VREF at the fifth time point t5, the detection signal FLAG may be transferred to the second logic level.

That is, the detection signal generator 230 may compare the reference voltage VREF with the reduced supply voltage VSUP at the fifth time point t5 to generate the detection signal FLAG based on the comparison result. For example, when the level of the reduced supply voltage VSUP is less than the level of the reference voltage VREF, the detection signal generator 230 may generate the detection signal FLAG at a second logic level (e.g., a high level), and the detection signal FLAG indicates the state of the reduced supply voltage VSUP.

The clock modulation circuit 420 may receive the detection signal FLAG at the fifth time point t5 and modulate the clock signal CLK. For example, the clock modulation circuit 420 may divide the frequency of the clock signal CLK so that the clock signal CLK remains at the first logic level instead of changing to the second logic level.

Since the level of the supply voltage VSUP is still lower than the level of the reference voltage VREF at the sixth time point t6, the detection signal FLAG can be maintained at the second logic level, and the clock signal CLK can also be maintained at the first logic level.

Since the level of the supply voltage VSUP is still lower than the level of the reference voltage VREF at the seventh time point t7, the detection signal FLAG may be maintained at the second logic level, and the clock signal CLK may be converted to the second logic level.

The clock modulation circuit 420 may convert the clock signal CLK to the second logic level at the seventh time point t7 to modulate the frequency of the clock signal CLK and provide the adaptive clock signal ACLK to the functional circuit 100. That is, the functional circuit 100 may perform processing operations based on the adaptive clock signal ACLK having a frequency lower than that of the clock signal CLK, thereby being able to operate at a low voltage and also reducing power consumption.

Since the level of the supply voltage VSUP is still lower than the level of the reference voltage VREF at the eighth time point t8, the detection signal FLAG can be maintained at the second logic level, and the clock signal CLK can also be maintained at the second logic level.

Since the level of the supply voltage VSUP is still lower than the level of the reference voltage VREF at the ninth time point t9, the detection signal FLAG may be maintained at the second logic level, and the clock signal CLK may be converted to the first logic level.

The clock modulation circuit 420 may convert the clock signal CLK to the first logic level at the ninth time point t9 to modulate the frequency of the clock signal CLK and provide the adaptive clock signal ACLK to the functional circuit 100. That is, the functional circuit 100 may perform processing operations based on the adaptive clock signal ACLK having a frequency lower than that of the clock signal CLK, thereby being able to operate at a low voltage and also reducing power consumption.

Since the level of the supply voltage VSUP is approximately equal to the level of the reference voltage VREF at the tenth time point t10, the detection signal FLAG can be converted to the first logic level. The clock signal CLK can also be converted to the second logic level.

Since the level of the supply voltage VSUP is greater than the level of the reference voltage VREF at the eleventh time point t11, the detection signal FLAG can be maintained at the first logic level. The clock signal CLK can be converted to the first logic level.

The twelfth time point t12 may be maintained in the same state as that of the eleventh time point t11.

7A and 7B are graphs each showing a drop voltage level that varies according to temperature characteristics of elements of the functional circuit 100 according to an embodiment.

Referring to FIG. 7A and FIG. 7B , the horizontal axis represents temperature, and the vertical axis represents the drop voltage level of the supply voltage. Referring to FIG. 1 , FIG. 7A , and FIG. 7B together, the degree to which the supply voltage drops according to the temperature characteristics may vary according to the component characteristics of the functional circuit 100. Component characteristics may be distinguished by the process inflection point of the components (e.g., CPU or wafer) within the system chip. For example, component characteristics may be divided into a slow process inflection point, a normal process inflection point, and a fast process inflection point. For example, FIG. 7A shows a drop voltage level taking into account a gradient optimized according to the process, and FIG. 7B shows a drop voltage level taking into account an offset optimized according to the process.

7A and 7B, when the element of the functional circuit 100 has the first element characteristic SS (eg, when the element of the functional circuit 100 corresponds to a slow process corner), the drop voltage level may increase as the temperature of the system chip increases.

When the element of the functional circuit 100 has the second element characteristic NN (for example, when the element of the functional circuit 100 corresponds to the normal process inflection point), the drop voltage level may increase as the temperature of the system chip increases. As shown in FIG. 7A and FIG. 7B, the drop voltage level corresponding to the second element characteristic NN may be smaller than the drop voltage level corresponding to the first element characteristic SS.

When the device of the functional circuit 100 has the third device characteristic FF (eg, when the device of the functional circuit 100 corresponds to a fast process corner point), the drop voltage level may increase as the temperature of the system chip increases.

For example, referring to FIG. 7A , at 25 degrees Celsius, the voltage drop level caused by the first device characteristic SS, the voltage drop level caused by the second device characteristic NN, and the voltage drop level caused by the third device characteristic FF may be approximately the same, and at 85 degrees Celsius, the voltage drop level caused by the first device characteristic SS may be greater than the voltage drop level caused by the second device characteristic NN, and the voltage drop level caused by the second device characteristic NN may be greater than the voltage drop level caused by the third device characteristic FF. FIG. 7A shows the voltage drop level according to the temperature change of each process in consideration of the influence of the gradient.

For example, referring to FIG7B , at 25 degrees Celsius, the voltage drop level caused by the first device characteristic SS may be greater than the voltage drop level caused by the second device characteristic NN, and the voltage drop level caused by the second device characteristic NN may be greater than the voltage drop level caused by the third device characteristic FF. FIG7B shows the voltage drop level of each process in consideration of the effect of the offset.

As shown in FIG. 7A and FIG. 7B , the drop voltage level according to the device characteristics of the functional circuit 100 can be linearly (or almost linearly) changed according to the temperature change. Therefore, the reference voltage of the reference voltage generator can be optimized with respect to the drop voltage level corresponding to the temperature and process.

FIG. 8 is a diagram illustrating a method of adjusting a reference voltage according to an embodiment.

FIG8 is about a method of adjusting the reference voltage VREF (i.e., the minimum voltage Vmin) by comparing the supply voltage VSUP with the reference voltage VREF. The VSUP protection band may include a VSUP drop and an expected VSUP drop. When the VSUP protection band is determined, the minimum voltage Vmin of the reference voltage VREF may be determined. When the expected VSUP drop has significantly occurred, the supply voltage VSUP becomes lower than the minimum voltage Vmin, and thus the functional circuit may malfunction.

The level of the supply voltage VSUP may be increased to prevent the functional circuit from malfunctioning even when a drop has occurred. That is, the reference voltage generator 220 of FIG. 4 may output a plurality of reference voltages VREF. The voltage drop detection circuit may detect the drop by comparing the plurality of reference voltages VREF with the supply voltage VSUP, and generate a detection signal when the drop has occurred. The clock modulation circuit may modulate the frequency of the clock signal by receiving the detection signal, and provide an adaptive clock signal to the functional circuit.

As shown in FIG8 , the system chip according to the embodiment can reduce the power consumption of the functional circuit for a certain period of time by providing an adaptive clock signal having a frequency lower than the frequency of the adaptive clock signal previously provided to the functional circuit when the supply voltage has dropped. Therefore, the system chip can perform stable operation when the dropped supply voltage is quickly restored, and the guard band applied to the supply voltage can be reduced to reduce the total amount of power consumed by the system chip.

FIG. 9 is a flow chart illustrating an operating method of a system chip according to an embodiment.

2 and 9 , the voltage drop detection circuit 200 may monitor the supply voltage VSUP provided to the functional circuit 100 ( S110 ).

When the supply voltage VSUP has dropped, the voltage drop detection circuit 200 may generate a detection signal FLAG (S120). For example, the situation in which the supply voltage VSUP has dropped may refer to a situation in which the level of the supply voltage VSUP is less than the level of the reference voltage VREF.

1 and 9 together, the clock controller 400 may generate an adaptive clock signal ACLK by modulating the frequency of the clock signal CLK based on the detection signal FLAG (S130).

FIG. 10 is a flow chart illustrating an operating method of a system chip according to an embodiment.

Hereinafter, as described above with reference to FIG. 2 , it is assumed that the detection signal generator 230 may compare the supply voltage VSUP with each of the plurality of reference voltages VREF to generate the detection signal FLAG based on the comparison result.

1 , 2 , and 10 , the voltage drop detection circuit 200 may check the state of the supply voltage VSUP ( S210 ).

The detection signal generator 230 may compare the level of the supply voltage VSUP with the level of the reference voltage VREF (S220). When the level of the supply voltage VSUP is less than the level of the reference voltage VREF (at S220, yes), the detection signal generator 230 may generate a detection signal FLAG (S230). For example, when the supply voltage VSUP has dropped, the clock modulation circuit 420 may check the extent of the drop of the supply voltage VSUP according to the detection signal FLAG. The detection signal generator 230 may provide the detection signal FLAG to the clock modulation circuit 420.

The clock modulation circuit 420 can adjust the frequency of the clock signal CLK (S240). For example, referring to FIG5, the multiple frequency dividers 421 and 422 can receive the clock signal CLK and divide the clock signal CLK according to different frequency division ratios to generate a first frequency-divided clock signal DCLK1 and a second frequency-divided clock signal DCLK2 having different frequencies.

The clock modulation circuit 420 may generate an adaptive clock signal ACLK (S250). For example, referring to FIG. 5 , the multiplexer 423 may output any one of the first frequency-divided clock signal DCLK1 and the second frequency-divided clock signal DCLK2 as the adaptive clock signal ACLK in response to the detection signal FLAG.

According to the embodiment shown in FIG. 10 , when the supply voltage VSUP has decreased (voltage drop), the system chip can detect the decrease to change the frequency of the clock signal CLK, thereby allowing the functional circuits of the system chip to operate at a low voltage.

FIG11 is a block diagram illustrating a system chip 20 according to an embodiment. For the convenience of explanation, further description of the components and technical aspects previously described with reference to FIG1 is omitted.

11 , the system chip 20 may include a functional circuit 100, a voltage drop detection circuit 200, a temperature sensor 300, and a clock controller 400. Unlike FIG1 , FIG11 shows a case where the functional circuit 100 and the voltage drop detection circuit 200 are included in the same block 150 instead of having separate configurations. For example, the voltage drop detection circuit 200 may be arranged within the functional circuit 100, or the functional circuit 100 and the voltage drop detection circuit 200 may be arranged adjacent to each other in the block 150. When the functional circuit 100 and the voltage drop detection circuit 200 are arranged adjacent to each other, the voltage drop detection circuit 200 can quickly generate a detection signal FLAG indicating whether the supply voltage VSUP has dropped below the reference voltage when the supply voltage VSUP drops below the reference voltage.

FIG12 is a block diagram illustrating a system chip 30 according to an embodiment. For the convenience of explanation, further description of the components and technical aspects previously described with reference to FIG1 and FIG11 is omitted.

12 , the system chip 30 may include a first functional circuit 100_1, a first voltage drop detection circuit 200_1, a second functional circuit 100_2, a second voltage drop detection circuit 200_2, a clock generation circuit 410, and a clock modulation circuit 420. The system chip 30 may further include a temperature sensor.

Unlike the SoCs 10 and 20 of FIGS. 1 and 2 , the SoC 30 shown in FIG. 12 may include a voltage drop detection circuit for each functional circuit.

The first function circuit 100_1 and the second function circuit 100_2 can perform processing operations by receiving the supply voltage VSUP. The first voltage drop detection circuit 200_1 and the second voltage drop detection circuit 200_2 can monitor the supply voltage VSUP and can respectively generate detection signals FLAG1 and FLAG2 indicating whether the supply voltage VSUP has dropped and provide the detection signals FLAG1 and FLAG2 to the clock modulation circuit 420.

2 may be applied to the clock generation circuit 410 and the clock modulation circuit 420. For example, the clock modulation circuit 420 may receive the detection signals FLAG1 and FLAG2 and modulate the clock signal CLK to correspond to the detection signals FLAG1 and FLAG2 to generate the first adaptive clock signal ACLK1 and the second adaptive clock signal ACLK2, and provide the first adaptive clock signal ACLK1 and the second adaptive clock signal ACLK2 to the first functional circuit 100_1 and the second functional circuit 100_2, respectively.

In an embodiment, when the voltage drop degree of the first voltage drop detection circuit 200_1 is different from the voltage drop degree of the second voltage drop detection circuit 200_2, the frequency of the first adaptive clock signal ACLK1 may be different from the frequency of the second adaptive clock signal ACLK2.

FIG. 12 shows that the system chip 30 includes two functional circuits (a first functional circuit 100_1 and a second functional circuit 100_2) and two voltage drop detection circuits (a first voltage drop detection circuit 200_1 and a second voltage drop detection circuit 200_2), but the system chip 30 is not limited thereto and may include any number of functional circuits and voltage drop detection circuits.

FIG. 13 is a block diagram illustrating a data processing system 1000 including a system chip according to an embodiment.

13 , a data processing system 1000 may include an application processor (AP) 1100 , a power management integrated circuit (PMIC) 1200 , and a memory device 1300 .

The data processing system 1000 shown in FIG. 13 may correspond to various types of computing systems, such as a mobile system using an application processor 1100 .

The application processor 1100 may be implemented as a system chip according to an embodiment. The system chip may include a system bus to which a protocol having a certain standard bus specification is applied, and may include various types of intellectual property (IP) connected to the system bus. The advanced microcontroller bus architecture (AMBA) protocol of an advanced RISC machine (ARM) may be applied as a standard specification of the system bus.

The application processor 1100 may include a central processing unit (CPU) 510, a voltage droop detection circuit (VDDC) 520, a dynamic voltage and frequency scaling (DVFS) controller 530, a clock modulation circuit (CMC) unit 540, a clock generation circuit (CGC) 550, and a memory controller interface (MCI) 560. The CPU 510, the VDDC 520, the DVFS controller 530, the CMC 540, the CGC 550, and the memory controller interface 560 may each constitute a functional circuit. Therefore, the CPU 510, the VDDC 520, the DVFS controller 530, the CMC 540, the CGC 550, and the memory controller interface 560 may respectively correspond to the functional circuit 100 of FIG. 1 and FIG. 11.

The CPU 510 may control various types of functional blocks in the application processor 1100. The CPU 510 may send and receive data access requests to and from the memory device 1300 outside the data processing system 1000 via the memory controller interface 560. In an embodiment, by measuring the level of the supply voltage after applying the supply voltage to the CPU 510, it is possible to check whether the embodiment described with reference to FIGS. 1 to 12 is applicable to the data processing system 1000. In an embodiment, by measuring the level of the supply voltage after applying the supply voltage and the clock signal to the CPU 510, it is also possible to check whether the embodiment described with reference to FIGS. 1 to 12 is applicable to the data processing system 1000.

The CGC 550 may generate a clock signal CLK and provide the clock signal CLK to the CMC 540.

The CMC 540 may generate a first adaptive clock signal ACLK1 and a second adaptive clock signal ACLK2 based on the clock signal CLK, provide the first adaptive clock signal ACLK1 to the CPU 510, and provide the second adaptive clock signal ACLK2 to the MCI 560. For example, the CMC may modulate the frequency of the clock signal CLK based on the detection signal FLAG received from the VDDC 520 to generate the first adaptive clock signal ACLK1.

VDDC 520 may correspond to the voltage drop detection circuit 200 shown in FIG1 . VDDC 520 may monitor the supply voltage VSUP provided to CPU 510, and when the supply voltage VSUP has dropped, VDDC 520 may provide a detection signal FLAG indicating the drop to CMC 540 and DVFS controller 530. VDDC 520 may include VDD controller 210, reference voltage generator 220, and detection signal generator 230, as shown in FIG3 .

The DVFS controller 530 may provide a voltage control signal VCTL to the PMIC 1200 based on the detection signal FLAG, and the PMIC 1200 may adjust the level of the supply voltage VSUP based on the voltage control signal VCTL. The DVFS controller 530 may receive a status signal STS indicating an operating speed of the CPU 510 from the CPU 510. The DVFS controller 530 may determine or predict the operating speed of the CPU 510 and the memory device 1300 based on the status signal STS. The DVFS controller 530 may provide a voltage control signal VCTL reflecting the determined operating speed to the PMIC 1200.

The MCI 560 may provide a command to the memory device 1300 according to a request from the CPU 510. The MCI 560 may write data to the memory device 1300 or read data from the memory device 1300 according to an operation of the application processor 1100.

The memory device 1300 may be any type of semiconductor memory device. For example, the memory device 1300 may be a dynamic random memory (DRAM), such as double data rate synchronous DRAM (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random-access memory (RDRAM), or the like.

The memory device 1300 may adjust the level of the supply voltage VSUP from the PMIC 1200 in response to the voltage control signal VCTL, and accordingly generate an internal voltage having the adjusted level of the supply voltage VSUP as an operating voltage. According to an embodiment, the memory device 1300 may adjust the level of the operating voltage in advance before the operating speed changes or before the frequency of the second adaptive clock signal ACLK2 provided from the MCI 560 changes. According to an embodiment, the memory device 1300 may set the adjustment time point of the level of the operating voltage differently in response to the change in the operating speed.

The PMIC 1200 may provide a supply voltage VSUP to the application processor 1100 and the memory device 1300. The PMIC 1200 may provide a supply voltage VSUP having different power levels to the application processor 1100 and the memory device 1300. The PMIC 1200 and the application processor 1100 may form separate system chips or form a single system chip.

FIG. 14 is a block diagram illustrating a mobile system 2000 including a system chip according to an embodiment.

14 , a mobile system 2000 may include an adaptive clock system 2100, a processor (e.g., an application processor (AP) or an integrated modem application processor (MODAP) 2200), a storage device 2300, a display/touch module 2400, and a buffer memory 2500. The mobile system 2000 may include, for example, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or the like.

According to an embodiment, the mobile system 2000 may further include a security chip. The security chip may be implemented to provide overall security functions. The security chip may include software and/or anti-tampering hardware that implements a high level of security, and may operate in collaboration with a trusted execution environment (TEE) of the processor 2200. The security chip may include an operating system (OS) (e.g., a local operating system (OS)), an internal data storage (e.g., a secure storage device), an access control block that controls access to the security chip, a security function block that implements, for example, ownership management, key management, digital signatures, encryption/decryption, etc., and a firmware update block that updates the firmware of the security chip. The security chip may be, for example, a universal integrated circuit card (UICC) (e.g., a Universal Subscriber Identity Module (USIM), a CDMA2000 SIM (CSIM) and an integrated SIM (ISIM)), a SIM card, an embedded secure element (eSE), a micro secure digital (MicroSD), a sticker or the like.

The adaptive clock system 2100 can be implemented as the system chips 10, 20, and 30 shown in Figures 1 to 13. The adaptive clock system 2100 can be implemented to detect a drop in the supply voltage of at least one power line, generate an adaptive clock signal ACLK according to the detection result, and provide the adaptive clock signal ACLK to the processor 2200.

The processor 2200 may be implemented to control the overall operation and wired/wireless communication of the mobile system 2000. For example, the processor 2200 may be an AP or a MODAP. The processor 2200 may include the voltage drop detection circuit 200 described above with reference to FIGS. 1 to 13. Therefore, the drop of the supply voltage supplied to the processor 2200 may be improved, and the stability of the mobile system 2000 may be improved.

The storage device 2300 may include, for example, an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS), or a similar storage device. The storage device 2300 may include at least one non-volatile memory device. The at least one non-volatile memory device may include, for example, a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistive random-access memory (RRAM), a phase-change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random-access memory (FRAM), a spin transfer torque random-access memory (STT-RAM), or a similar non-volatile memory device. The storage device 2300 may store data inputted by the display/touch module 2400.

The display/touch module 2400 may display data processed by the processor 2200. The display/touch module 2400 may receive data input from a touch screen. A user may input data via the display/touch module 2400. In an embodiment, when the display/touch module 2400 receives data from the touch screen, the level of the supply voltage of the processor 2200 may be measured to check whether the embodiments described above with reference to FIGS. 1 to 13 are applicable to the mobile system 2000.

The buffer memory 2500 may store data utilized during processing operations of the mobile system 2000.

The mobile system 2000 according to the embodiment can detect the drop of the supply voltage consumed by the processor 2200 and modulate the frequency of the clock signal to prevent the supply voltage of the power line from dropping. Therefore, the operation of the mobile system 2000 can be stably implemented and unnecessary power consumption can be reduced.

As is generally described in the art of the inventive concept, embodiments are described and illustrated in the drawings from the perspective of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits), discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based or other manufacturing technologies. In the case where blocks, units and/or modules are implemented by a microprocessor or similar device, the blocks, units and/or modules may be programmed using software (e.g., microcode) to implement the various functions discussed herein and may be optionally driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for implementing some functions and a processor for implementing other functions (e.g., one or more programmed microprocessors and associated circuit systems).

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made thereto without departing from the spirit and scope of the inventive concept as defined by the following claims.

10, 20, 30: System chip 100: Functional circuit 100_1: First functional circuit 100_2: Second functional circuit 110: Remote temperature sensor (RTS) 150: Block 200: Voltage drop detection circuit 200_1: First voltage drop detection circuit 200_2: Second voltage drop detection circuit 210: Voltage drop detection (VDD) controller 220: Reference voltage generator 221: Bandgap reference (BGR) circuit 222: Reference voltage buffer 223: Digital/analog converter (DAC) 224: DAC buffer 230: Detection signal generator 300: Temperature sensor 400: Pulse controller 410: Pulse generation circuit 420: Pulse modulation circuit 421, 422: Frequency divider 423: Multiplexer 510: Central processing unit (CPU) 520: Voltage drop detection circuit (VDDC) 530: Dynamic voltage and frequency regulation (DVFS) controller 540: Pulse modulation circuit (CMC) unit 550: Pulse generation circuit (CGC) 560: Memory controller interface (MCI) 1000: Data processing system 1100: Application processor 1200: Power management integrated circuit (PMIC) 1300: Memory device 2000: Mobile system 2100: Adaptive clock system 2200: Integrated modem application processor (MODAP)/processor 2300: Storage device 2400: Display/touch module 2500: Buffer memory ACLK: Adaptive clock signal ACLK1: First adaptive clock signal ACLK2: Second adaptive clock signal CLK: Clock signal DCLK1: First frequency division clock signal DCLK2: Second frequency division clock signal FLAG: Detection signal/high level detection signal FLAG1, FLAG2: Detection signal FF: Third component characteristic NN: Second component characteristic PL: Power line S110, S120, S130, S210, S220, S230, S240, S250: Steps SS: First component characteristic STS: Status signal t1: First time point t2: Second time point t3: Third time point t4: Fourth time point t5: Fifth time point t6: Sixth time point t7: Seventh time point t8: Eighth time point t9: Ninth time point t10: Tenth time point t11: Eleventh time point t12: Twelfth time point TSS: Temperature sensing signal VCTL: Voltage control signal VREF: Reference voltage Vmin: Minimum voltage VSUP: Supply voltage

The above and other features of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the accompanying drawings, in which: FIG. 1 is a block diagram schematically illustrating a system chip according to an embodiment. FIG. 2 is a block diagram illustrating a system chip according to an embodiment in detail. FIG. 3 is a block diagram illustrating a voltage drop detection circuit according to an embodiment. FIG. 4 is a block diagram illustrating a reference voltage generator according to an embodiment. FIG. 5 is a block diagram illustrating a clock modulation circuit according to an embodiment. FIG. 6 is a diagram illustrating the operation of a voltage drop detection circuit according to an embodiment. FIG. 7A and FIG. 7B are graphs each showing a drop voltage level that varies according to the temperature characteristics of an element of a functional circuit according to an embodiment. FIG. 8 is a diagram illustrating a method of adjusting a reference voltage according to an embodiment. FIG. 9 is a flow chart illustrating an operation method of a system chip according to an embodiment. FIG. 10 is a flow chart illustrating an operation method of a system chip according to an embodiment. FIG. 11 is a block diagram illustrating a system chip according to an embodiment. FIG. 12 is a block diagram illustrating a system chip according to an embodiment. FIG. 13 is a block diagram illustrating a data processing system including a system chip according to an embodiment. FIG. 14 is a block diagram illustrating a mobile system including a system chip according to an embodiment.

10: System on Chip

100: Functional circuit

110: Remote Temperature Sensor (RTS)

200: Voltage drop detection circuit

210: Voltage drop detection (VDD) controller

220: Reference voltage generator

300: Temperature sensor

400: Clock controller

410: Clock generation circuit

420: Clock modulation circuit

ACLK: Adaptive clock signal

CLK: clock signal

FLAG: Detection signal/high-level detection signal

PL: Power lines

TSS: Temperature sensing signal

VSUP: Supply voltage

Claims (20)

A system chip, comprising: a functional circuit configured to receive a supply voltage and perform a processing operation; a voltage drop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a voltage drop has occurred; a clock generation circuit configured to output a clock signal; and a clock modulation circuit configured to receive the detection signal and the clock signal, generate an adaptive clock signal by modulating the clock signal to correspond to the detection signal, and provide the adaptive clock signal to the functional circuit, wherein the voltage drop detection circuit comprises: a voltage drop detection controller configured to control a reference voltage to remain constant; A reference voltage generator configured to generate the reference voltage; and a detection signal generator configured to generate the detection signal by comparing the reference voltage with the supply voltage. A system chip as described in claim 1, wherein the clock modulation circuit includes: a first frequency divider configured to divide the frequency of the clock signal and output a first divided clock signal; a second frequency divider configured to divide the frequency of the clock signal and output a second divided clock signal; and a multiplexer configured to select and provide any one of the first divided clock signal and the second divided clock signal to the functional circuit in response to the detection signal. The system chip as described in claim 2, wherein the multiplexer is further configured to output any one of the first frequency-divided clock signal and the second frequency-divided clock signal as the adaptive clock signal. A system chip as described in claim 2, wherein the frequency of the first divided-frequency clock signal is less than the frequency of the clock signal, and the frequency of the second divided-frequency clock signal is approximately equal to the frequency of the clock signal. A system chip as described in claim 2, wherein when the detection signal indicates that the voltage drop of the supply voltage has been detected, the multiplexer outputs and provides the adaptive clock signal to the functional circuit. A system chip as described in claim 2, wherein when the detection signal indicates that the voltage drop of the supply voltage has not been detected, the multiplexer provides the clock signal to the functional circuit. The system chip as described in claim 1 further includes: A temperature sensor configured to sense the temperature within the system chip and generate a sensing signal indicating the temperature state of the system chip. The system chip as described in claim 7, wherein the clock modulation circuit is further configured to output any one of the clock signal and the adaptive clock signal based on the sensing signal of the temperature sensor. The system chip as described in claim 7, wherein the clock modulation circuit is further configured to output the adaptive clock signal when the temperature in the system chip exceeds a reference temperature. A system chip as described in claim 1, wherein the voltage drop detection circuit is arranged adjacent to the functional circuit within the system chip. A system chip as described in claim 1, wherein the reference voltage generator includes: a bandgap reference circuit configured to generate a bandgap reference voltage; a reference voltage buffer configured to receive the bandgap reference voltage and output a digital/analog converter (DAC) reference voltage; a digital/analog converter configured to convert the digital/analog converter reference voltage into an analog reference voltage; and a buffer configured to output the analog reference voltage, wherein the analog reference voltage is the reference voltage. A method for operating a system chip, comprising: Monitoring a supply voltage by a voltage drop detection circuit included in the system chip, wherein the supply voltage is received by a functional circuit included in the system chip, and the functional circuit is configured to perform a processing operation; Comparing the level of the supply voltage with the level of a reference voltage; Generating a detection signal based on the result of comparing the level of the supply voltage with the level of the reference voltage; and Adjusting the frequency of a clock signal based on the detection signal. A method as claimed in claim 12, wherein the detection signal is a signal indicating whether a voltage drop has occurred in the supply voltage, and the detection signal is generated when the level of the supply voltage is less than the level of the reference voltage. The method of claim 12, wherein adjusting the frequency of the clock signal comprises: When the level of the supply voltage is less than the level of the reference voltage, adjusting the frequency of the clock signal and outputting an adaptive clock signal. The method of claim 14, wherein outputting the adaptive clock signal comprises: outputting a first divided clock signal obtained by dividing the frequency of the clock signal; outputting a second divided clock signal obtained by dividing the frequency of the clock signal; and selecting and outputting either the first divided clock signal or the second divided clock signal in response to the detection signal. A method as described in claim 15, wherein the frequency of the first divided-frequency clock signal is less than the frequency of the clock signal, and the frequency of the second divided-frequency clock signal is approximately equal to the frequency of the clock signal. The method of claim 12 further includes: sensing the internal temperature of the system chip; and generating a sensing signal indicating the temperature state of the system chip. A system chip, comprising: a first functional circuit configured to receive a supply voltage and perform a first processing operation; a first voltage drop detection circuit configured to monitor the supply voltage and generate a first detection signal indicating whether a voltage drop has occurred; a second functional circuit configured to receive the supply voltage and perform a second processing operation; a second voltage drop detection circuit configured to monitor the supply voltage and generate a second detection signal indicating whether the voltage drop has occurred; a clock generation circuit configured to output a clock signal; and The clock modulation circuit is configured to receive the first detection signal and the second detection signal and the clock signal, and generate a first adaptive clock signal and a second adaptive clock signal by modulating the clock signal to correspond to the first detection signal and the second detection signal respectively, and provide the first adaptive clock signal and the second adaptive clock signal to the first functional circuit and the second functional circuit respectively, wherein the first voltage drop detection circuit includes: a first controller, configured to control the first reference voltage to remain constant; a first reference voltage generator, configured to generate the first reference voltage; and a first detection signal generator, configured to generate the first detection signal by comparing the first reference voltage with the supply voltage, The second voltage drop detection circuit includes: A second controller configured to control the second reference voltage to remain constant; A second reference voltage generator configured to generate the second reference voltage; and A second detection signal generator configured to generate the second detection signal by comparing the second reference voltage with the supply voltage. A system chip as described in claim 18, wherein the first voltage drop detection circuit and the first functional circuit are arranged adjacent to each other in the system chip, and the second voltage drop detection circuit and the second functional circuit are arranged adjacent to each other in the system chip. A system chip as described in claim 18, wherein the clock modulation circuit includes: a first frequency divider configured to divide the frequency of the clock signal and output a first divided clock signal; a second frequency divider configured to divide the frequency of the clock signal and output a second divided clock signal; and a multiplexer configured to select any one of the first divided clock signal and the second divided clock signal as an adaptive clock signal in response to the first detection signal and the second detection signal and output the adaptive clock signal to the first functional circuit and the second functional circuit.

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