TW202508301A - Solid-state imaging device - Google Patents

Abstract

To provide a solid-state imaging device which is capable of performing global shutter operation and which can be miniaturized while maintaining high speed and low power consumption. A solid-state imaging device according to the present disclosure comprises a pixel array unit in which a plurality of pixels are arranged in a two-dimensionally arrayed manner. At least one pixel among the plurality of the pixels includes: a pixel circuit that generates, on the basis of photoelectric conversion, a pixel signal which is an analog signal; an AD conversion unit that converts the pixel signal to a digital signal on the basis of comparison between the pixel signal and a reference signal; and a digital data holding unit that holds data of the digital signal. The pixel circuit includes: a photoelectric conversion unit that generates electric charges from light by photoelectric conversion; a power storage unit that stores the electric charges generated by the photoelectric conversion unit; and a plurality of transfer transistors that control the transfer of the electric charges from the photoelectric conversion unit to the power storage unit.

Description

Solid-state imaging device

The present disclosure relates to a solid-state imaging device.

A solid-state imaging device that has an AD (Analog to Digital) conversion circuit and a digital data storage unit for each pixel (this configuration is called a pixel ADC (Analog to Digital Converter)) reads out the charge of all pixels at the same time and performs AD conversion, so it maintains high speed and can perform global shutter action. In addition, the wiring capacitance of the wiring connecting the floating diffusion unit to the AD conversion circuit is small, and the power consumption during charging and discharging is small. However, since this solid-state imaging device has an AD conversion circuit and a digital memory for each pixel, there is a limit to its miniaturization.

On the other hand, since the solid-state imaging device having an AD conversion circuit for each row (this configuration is called row ADC) reads the charge for each row and performs AD conversion, rolling shutter distortion occurs. In addition, the wiring capacitance of the common wiring connecting the floating diffusion part to the AD conversion circuit is large, and the power consumption during charging and discharging is large. [Prior technical literature] [Patent literature]

[Patent Document 1] International Publication No. 2016-009832

[The problem the invention is trying to solve]

To this end, in view of these problems, this disclosure provides a solid-state imaging device that maintains high speed and low power consumption and is capable of miniaturization. [Technical means to solve the problem]

The solid-state imaging device of the first aspect of the present disclosure includes a pixel array section formed by a plurality of pixels arranged in a two-dimensional array; and at least one pixel among the aforementioned plurality of pixels includes: a pixel circuit, which generates a pixel signal of an analog signal based on photoelectric conversion; an AD conversion section, which converts the aforementioned pixel signal into a digital signal based on a comparison between the aforementioned pixel signal and a reference signal; and a digital data holding section, which holds the data of the aforementioned digital signal; the aforementioned pixel circuit includes: a photoelectric conversion section, which generates charge from light by photoelectric conversion; a storage section, which stores the aforementioned charge generated by the aforementioned photoelectric conversion section; and a plurality of transfer transistors, which control the transfer of the aforementioned charge from the aforementioned photoelectric conversion section to the aforementioned storage section. Thus, by controlling a plurality of transmission transistors, the pixel circuit can prevent the reverse flow of charges and increase the capacitance of the storage unit. Furthermore, by increasing the capacitance of the storage unit, the pixel circuit can increase the conversion efficiency of the photoelectric conversion of the entire circuit.

Furthermore, in the first aspect, the AD conversion unit and the digital data holding unit are provided for each of the power storage units. Thus, the pixel circuit is connected to the AD conversion circuit via the power storage units of each, so that it can achieve high speed compared with the row ADC. Furthermore, the wiring capacitance of the wiring connecting the power storage unit to the AD conversion circuit is small, and the power consumption during charging and discharging is small. Therefore, the pixel circuit can achieve power saving compared with the row ADC.

Furthermore, in the first aspect, the plurality of transmission transistors are connected in series. Thus, by controlling the plurality of transmission transistors, the pixel circuit can prevent the reverse flow of charges and increase the capacitance of the storage unit. Furthermore, by increasing the capacitance of the storage unit, the pixel circuit can increase the conversion efficiency of the photoelectric conversion of the entire circuit.

Furthermore, in the first aspect, the plurality of transfer transistors include a first and a second transfer transistor, and a memory for holding charge is connected between the first and the second transfer transistors. Thus, the pixel circuit can temporarily store charge in the memory before transferring the charge to the storage unit. For example, the pixel circuit can transfer charge to the storage unit in stages by adjusting the amount of charge transferred from the photoelectric conversion unit to the memory and the amount of charge transferred from the memory to the storage unit based on control of the transfer transistor.

Furthermore, in the first aspect, the first transfer transistor controls the transfer of charge from the photoelectric conversion unit to the memory. Thus, the pixel circuit can temporarily store the charge in the memory before transferring the charge to the storage unit. For example, the pixel circuit can transfer the charge to the storage unit in stages by adjusting the amount of charge transferred from the photoelectric conversion unit to the memory and the amount of charge transferred from the memory to the storage unit based on the control of the transfer transistor.

Furthermore, in the first aspect, the second transfer transistor controls the transfer of charge from the memory to the storage unit. Thus, the pixel circuit can temporarily store the charge in the memory before transferring the charge to the storage unit. For example, the pixel circuit can transfer the charge to the storage unit in stages by adjusting the amount of charge transferred from the photoelectric conversion unit to the memory and the amount of charge transferred from the memory to the storage unit based on the control of the transfer transistor.

Furthermore, in the first aspect, the pixel further includes a discharge transistor for discharging charges. Thus, the photoelectric conversion unit can start exposure after discharging unnecessary charges accumulated in the photoelectric conversion unit.

Furthermore, in the first aspect, the discharge transistor is connected to the photoelectric conversion unit, so that the photoelectric conversion unit can start exposure after discharging unnecessary charges accumulated in the photoelectric conversion unit.

Furthermore, the solid-state imaging device of the second aspect of the present disclosure includes a pixel array section formed by arranging a plurality of pixels in a two-dimensional array; and at least one of the plurality of pixels includes: a pixel circuit that generates a pixel signal of an analog signal based on photoelectric conversion; an AD conversion section that converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and a digital data holding section that holds the data of the digital signal; the pixel circuit includes: a first photoelectric conversion section and a second photoelectric conversion section that generates electricity from light by photoelectric conversion. Charge; a storage unit that stores the aforementioned charge generated by the aforementioned first and second photoelectric conversion units; a plurality of transmission transistors of the first group that control the transmission of the aforementioned charge from the aforementioned first photoelectric conversion unit to the aforementioned storage unit; and a plurality of transmission transistors of the second group that control the transmission of the aforementioned charge from the aforementioned second photoelectric conversion unit to the aforementioned storage unit; the aforementioned storage unit is connected to the aforementioned first photoelectric conversion unit via the plurality of transmission transistors of the first group, and is connected to the aforementioned first photoelectric conversion unit via the plurality of transmission transistors of the second group. Thus, by controlling the plurality of transmission transistors, the pixel circuit can prevent the backflow of charge and increase the capacitance of the storage unit. In addition, by increasing the capacitance of the storage unit, the pixel can increase the conversion efficiency of the photoelectric conversion of the entire circuit. In addition, since the pixel circuit has a storage unit shared by a plurality of photoelectric conversion units, the circuit of the solid-state imaging device can be miniaturized.

Furthermore, in the second aspect, the plurality of transmission transistors of the first group and the second group are connected in series. Thus, by controlling the plurality of transmission transistors, the pixel circuit can prevent the reverse flow of charge and increase the capacitance of the storage part. Furthermore, by increasing the capacitance of the storage part, the pixel can increase the conversion efficiency of the photoelectric conversion of the entire circuit.

Furthermore, in the second aspect, regarding the plurality of transmission transistors of the aforementioned first group and the plurality of transmission transistors of the aforementioned second group, the aforementioned transmission transistors constituting the aforementioned first group and the aforementioned second group include the first and second transmission transistors, respectively, and a memory for holding charge is connected between the aforementioned first and second transmission transistors. Thereby, the pixel circuit can temporarily store the charge in the memory before transferring the charge to the storage unit. For example, the pixel circuit can transfer the charge to the storage unit in stages by adjusting the amount of charge transferred from the photoelectric conversion unit to the memory and the amount of charge transferred from the memory to the storage unit based on the control of the transmission transistor. In addition, since the pixel has a plurality of photoelectric conversion units sharing a storage unit, etc., the circuit of the solid-state imaging device can be miniaturized. In addition, each photoelectric conversion unit temporarily stores the charge in the memory, sequentially transmits the charge to the storage unit at a staggered timing, and inputs the pixel signal to the differential input circuit, thereby realizing a global shutter function. That is, according to this embodiment, the pixel can realize the miniaturization realized by sharing the storage unit and realize the global shutter function.

Furthermore, in the second aspect, regarding the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group, each of the first transmission transistors controls the transmission of the charge from the photoelectric conversion unit to the memory. Thus, the pixel circuit can temporarily store the charge in the memory before transmitting the charge to the storage unit. For example, the pixel circuit can transfer the charge to the storage unit in stages by adjusting the amount of charge transferred from the photoelectric conversion unit to the memory and the amount of charge transferred from the memory to the storage unit based on the control of the transmission transistor.

Furthermore, in the second aspect, regarding the plurality of transfer transistors of the first group and the plurality of transfer transistors of the second group, each of the second transfer transistors controls the transfer of charge from the memory to the storage unit. Thus, the pixel circuit can temporarily store the charge in the memory before transferring the charge to the storage unit. For example, the pixel circuit can transfer the charge to the storage unit in stages by adjusting the amount of charge transferred from the photoelectric conversion unit to the memory and the amount of charge transferred from the memory to the storage unit based on the control of the transfer transistor.

Furthermore, in the second aspect, the AD conversion unit and the digital data holding unit are provided for each of the power storage units. Thus, the pixel circuit is connected to the AD conversion circuit via the power storage unit of each pixel circuit, so that it is possible to achieve high speed compared with the row ADC. Furthermore, the wiring capacitance of the wiring connecting the power storage unit to the AD conversion circuit is small, and the power consumption during charging and discharging is small. Therefore, it is possible to achieve power saving compared with the row ADC.

In the second aspect, the pixel further includes a first discharge transistor and a second discharge transistor for discharging electric charges. Thus, the photoelectric conversion unit can start exposure after discharging unnecessary electric charges accumulated in the photoelectric conversion unit.

Furthermore, in the second aspect, the first discharge transistor is connected to the first photoelectric conversion unit, and the second discharge transistor is connected to the second photoelectric conversion unit. Thus, the photoelectric conversion unit can start exposure after discharging unnecessary charges accumulated in the photoelectric conversion unit.

Furthermore, in the first aspect, the plurality of transmission transistors include a plurality of transmission transistors of a first group connected in series with each other, and a plurality of transmission transistors of a second group connected in series with each other, the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group are connected in parallel with each other, and the storage unit is connected to the photoelectric conversion unit via the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group. Thus, one transmission transistor of the transmission transistors constituting each group has a function as a memory. Thus, the pixel circuit can temporarily store charge in the memory before transmitting the charge to the storage unit. For example, the pixel circuit can adjust the amount of charge transferred from the photoelectric conversion unit to the power storage unit by controlling the transfer transistors on the upstream and downstream sides of the transfer transistors that function as memory. In addition, since one photoelectric conversion unit shares the power storage unit via a group of transfer transistors connected in parallel, the circuit of the solid-state imaging device can be miniaturized.

Furthermore, in the second aspect, the pixel circuit further includes: a plurality of transmission transistors of the third group, which control the transmission of the aforementioned charge from the aforementioned first photoelectric conversion unit to the aforementioned power storage unit; and a plurality of transmission transistors of the fourth group, which control the transmission of the aforementioned charge from the aforementioned second photoelectric conversion unit to the aforementioned power storage unit; and the plurality of transmission transistors of the first group and the plurality of transmission transistors of the third group are connected in parallel to each other; the plurality of transmission transistors of the second group and the plurality of transmission transistors of the fourth group are connected in parallel to each other; the aforementioned power storage unit is connected to the aforementioned first photoelectric conversion unit via the plurality of transmission transistors of the first group and the third group, and is connected to the aforementioned second photoelectric conversion unit via the plurality of transmission transistors of the second group and the fourth group. Thus, one of the transmission transistors constituting each group of the pixel circuit has the function of a memory. Thus, the pixel circuit can temporarily store the charge in the memory before transferring the charge to the storage unit. For example, the pixel circuit can adjust the amount of charge transferred from the photoelectric conversion unit to the storage unit based on the control of the transmission transistors on the upstream and downstream sides of the transmission transistor that has the function of a memory. In addition, since one photoelectric conversion unit shares the storage unit through the group of transmission transistors connected in parallel, the circuit of the solid-state imaging device can be miniaturized.

Furthermore, the solid-state imaging device of the third aspect of the present disclosure includes a pixel array section formed by arranging a plurality of pixels in a two-dimensional array; and at least one of the plurality of pixels includes: a pixel circuit that generates a pixel signal of an analog signal based on photoelectric conversion; an AD conversion section that converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and a digital data holding section that holds the data of the digital signal; the pixel circuit includes: a photoelectric conversion section that generates electric charge from light by photoelectric conversion; the first and second 2 storage units, which store the aforementioned charges generated by the aforementioned photoelectric conversion unit; a plurality of transmission transistors of the first group, which control the transmission of the aforementioned charges from the aforementioned photoelectric conversion unit to the aforementioned first storage unit; and a plurality of transmission transistors of the second group, which control the transmission of the aforementioned charges from the aforementioned photoelectric conversion unit to the aforementioned second storage unit; the aforementioned first storage unit is connected to the aforementioned photoelectric conversion unit via the plurality of transmission transistors of the first group; the aforementioned second storage unit is connected to the aforementioned photoelectric conversion unit via the plurality of transmission transistors of the second group. In this way, the pixel circuit can input the charges accumulated in the photoelectric conversion unit to different differential input circuits respectively. In addition, since the data are not mixed, the output results can be treated as different data for processing.

Furthermore, in the third aspect, the AD conversion unit and the digital data storage unit are provided in the first storage unit and the second storage unit, respectively. Thus, each storage unit is connected to the AD conversion circuit, so that it is possible to achieve high speed compared with the row ADC. Furthermore, the wiring capacitance of the wiring connecting the storage unit to the AD conversion circuit is small, and the power consumption during charging and discharging is small. Therefore, it is possible to achieve power saving compared with the row ADC.

Hereinafter, the implementation form of the present disclosure will be described with reference to the drawings.

(First embodiment) FIG. 1 is a block diagram showing an example of a configuration of a camera device according to the first embodiment.

The imaging device 100 includes an imaging lens 210, a solid-state imaging device 200, a recording unit 220, a control unit 230, an analysis unit 240, a wireless communication unit 250, and a speaker unit 260. The imaging device 100 is, for example, a smart phone, a mobile phone, a PC (Personal Computer), or the like.

The imaging lens 210 collects incident light and guides it to the solid-state imaging device 200. The solid-state imaging device 200 has a plurality of grayscale pixels. Each grayscale pixel outputs a brightness signal corresponding to the amount of received light. In addition, grayscale pixels are sometimes referred to as "pixels" below.

The solid-state imaging device 200 can perform prescribed signal processing such as weighted addition at the analog signal stage, and output the processed data to the recording unit 220 via the signal line 209.

The recording unit 220 records data from the solid-state imaging device 200. The control unit 230 controls the entire imaging device 100. For example, the control unit 230 controls the solid-state imaging device 200 to capture image data.

The analysis unit 240 can perform recognition processing using, for example, a neural network. The analysis unit 240 has an operation processing unit 242. The operation processing unit 242 can cause the solid-state imaging device 200 to perform operation processing such as convolution operation on the data of each pixel imaged by the solid-state imaging device 200 at the stage of analog signals.

In addition, the analysis unit 240 can also use the calculation results of the calculation processing unit 242 to perform predetermined analysis processing, image processing, etc. For example, the calculation processing such as convolution calculation performed by the calculation processing unit 242 as described above is performed by the solid-state imaging device 200 at the stage of analog signals, and the subsequent calculation processing is performed by the calculation processing unit 242.

The wireless communication unit 250 performs wireless communication with an external device, thereby receiving content from an external server and recording it in the recording unit 220 via the control unit 230. The control unit 230 displays, for example, an image based on the content on the display unit 270.

The speaker unit 260 has a high directivity speaker and can transmit sound information only to the user. The speaker unit 260 can change the direction of sound transmission.

FIG2 is a schematic diagram showing the structure of the solid-state imaging device according to the first embodiment.

The solid-state imaging device 200 of FIG. 2 has a pixel array section 2 in which pixels 10 are arranged in a two-dimensional array on a semiconductor substrate 300 using a semiconductor such as silicon. A clock code transmission section (transmitter) 3 is also provided in the pixel array section 2 to transmit the clock code generated by the clock code generation section 6 to each pixel 10. In addition, a pixel driving circuit 4, a DAC (D/A converter) 5, a clock code generation section 6, a vertical driving circuit 7, an output section 8, and a timing generation circuit 9 are formed around the pixel array section 2 of the semiconductor substrate 300.

The pixel driving circuit 4 drives the circuit inside the pixel 10.

The DAC 5 generates a slope signal whose level (voltage) decreases monotonically with the passage of time, namely, a reference signal REF, and supplies it to each pixel 10.

There are a plurality of clock code generating units 6 for the pixel array unit 2, and clock code transmitting units 3 are provided in the pixel array unit 2 in the same number as the clock code generating units 6. That is, the clock code generating units 6 correspond to the clock code transmitting units 3 that transmit the clock codes generated therein.

The vertical driving circuit 7 controls the digital signals generated in the pixel 10 to be output to the output unit 8 in a predetermined sequence based on the timing signals supplied from the timing generation circuit 9. The digital signals output from the pixel 10 are output from the output unit 8 to the outside of the solid-state imaging device 200.

The output unit 8 performs prescribed digital signal processing such as black level correction processing or CDS (Corelated Double Sampling) processing to correct the black level as needed, and then outputs the signal to the outside.

The timing generation circuit 9 is composed of a timing generator that generates various timing signals, and supplies the generated various timing signals to the pixel driving circuit 4, DAC 5, vertical driving circuit 7, etc.

The solid-state imaging device 200 may be configured as described above. As shown in FIG. 2 , each circuit of the solid-state imaging device 200 may be configured to be disposed on one semiconductor substrate 300 or may be configured to be disposed on a plurality of semiconductor substrates 300 .

FIG3 is a block diagram of pixels, etc., of the first embodiment.

As shown in FIG3 , the pixel 10 includes a pixel circuit 40 and an ADC (A/D converter) 50. The pixel circuit 40 generates an analog pixel signal SIG based on the amount of light received by the photoelectric conversion unit PD in the pixel circuit 40, and outputs the analog pixel signal SIG to the ADC 50. The ADC 50 converts the analog pixel signal SIG supplied from the pixel circuit 40 into a digital signal.

The pixel circuit 40 includes: a photodiode (hereinafter referred to as the photoelectric conversion unit PD) that generates a charge signal corresponding to the amount of light received, a floating diffusion unit (hereinafter referred to as the storage unit FD) that maintains the charge, and a transfer transistor TG that transfers the charge generated by the photoelectric conversion unit PD to the storage unit FD. In addition, the pixel circuit 40 may include a discharge transistor OFG that discharges the charge generated by the photoelectric conversion unit PD. In addition, the pixel circuit 40 may include a reset transistor RST that resets the charge accumulated in the storage unit FD. In addition, the pixel circuit 40 may include a connection transistor FDG that electrically connects the reset transistor RST and the storage unit FD. The details of the circuit diagram are described later.

The photoelectric conversion section PD performs photoelectric conversion of the incident light. Making light incident on the photoelectric conversion section PD is called exposure of the photoelectric conversion section PD.

The power storage unit FD stores the charge generated by the photoelectric conversion unit PD. The power storage unit FD functions as a capacitor.

The transfer transistor TG transfers the charge generated by the above-mentioned photoelectric conversion to the power storage unit FD.

The drain transistor OFG is used when adjusting the exposure period. Specifically, if the drain transistor OFG is turned on at an arbitrary timing when the exposure period is to be started, the charge accumulated in the photoelectric conversion unit PD during the period up to that time is discharged. Therefore, the exposure period starts after the drain transistor OFG is turned off.

The reset transistor RST resets the charge held in the storage unit FD.

The connection transistor FDG electrically connects the reset transistor RST and the storage unit FD based on the on-off operation.

ADC 50 has an AD conversion circuit 70 and a digital data holding unit 80. AD conversion circuit 70 compares reference signal REF supplied from DAC 5 with pixel signal SIG, and outputs output signal VCO as a signal indicating the comparison result. AD conversion circuit 70 inverts output signal VCO when reference signal REF and pixel signal SIG become the same voltage. AD conversion circuit 70 is an example of an AD conversion unit.

In the digital data holding section 80, in the writing operation, the code value (clock code) at the time when the output signal VCO of the AD conversion circuit 70 is inverted is held. In the digital data holding section 80, in the reading operation, the code value is read as an output signal, and the digital value of the pixel signal SIG is output as a digitized value. The digital value is read out once by the clock code transmission section 3 via the local bit line, thereby realizing the global shutter function of the solid-state imaging device 200.

FIG. 4 is a block diagram of pixels, etc., of the first embodiment (details).

The AD conversion circuit 70 includes a differential input circuit 90, a voltage conversion circuit 94, and a positive feedback circuit 91. The AD conversion circuit 70 is an example of an AD conversion unit. In addition, the digital data holding unit 80 includes a latch control circuit 95 and a latch storage unit 96.

The differential input circuit 90 compares the pixel signal SIG output from the pixel circuit 40 with the reference signal REF output from the DAC 5, and outputs an output signal (current) when the pixel signal SIG is higher than the reference signal REF.

The voltage conversion circuit 94 converts the output signal HVO input from the differential input circuit 90 into a low voltage signal (conversion signal) LVI corresponding to the second power supply voltage VDDL, which enables the positive feedback circuit 91 to operate, and supplies the low voltage signal to the positive feedback circuit 91.

The positive feedback circuit 91 outputs a comparison result signal that is inverted when the pixel signal SIG is higher than the reference signal REF based on the conversion signal LVI. In addition, the positive feedback circuit 91 increases the switching speed of the output signal VCO output as the comparison result signal when it is inverted.

In addition to receiving the output signal VCO from the AD conversion circuit 70, the latch control circuit 95 also receives the xLATSEL signal related to the digital signal read operation, the LATSEL signal related to the digital signal write operation, and the xWORD signal for controlling the read timing of the pixel 10 in the digital signal read operation, which are supplied from the receiving pixel driving circuit 4. The latch control circuit 95 outputs latch control signals T, Lx, and TxL based on these signals to control the latch memory section 96. The latch memory section 96 is set with a number corresponding to the number of AD conversion bits.

The latch control circuit 95 stores the code value supplied from the clock code transmission unit 3 in the latch memory unit 96 during the writing operation. The code value represents a logical value of "0" or "1", and is updated for each unit time while the Hi (high level) signal VCO is input from the AD conversion circuit 70. When the output signal VCO supplied from the AD conversion circuit 70 is inverted to Lo (low level), the latch control circuit 95 stops writing (updating) the clock code to the latch memory unit 96, and finally keeps the clock code stored in the latch memory unit 96 in the latch memory unit 96. The timing code held by the latch memory unit 96 indicates the timing when the pixel signal SIG and the reference signal REF become equal, indicating data showing that the pixel signal SIG is the reference voltage at that timing, that is, the digitized light value.

In the read operation, the latch control circuit 95 outputs the clock code stored in the latch storage unit 96 to the clock code transmission unit 3 when the pixel 10 reaches its own read timing based on the xWORD signal that controls the read timing.

FIG5 is a circuit diagram of a pixel portion of the solid-state imaging device of the first embodiment.

In FIG. 5 , a circuit diagram of the pixel 10 is shown to illustrate the structure of the pixel ADC.

In this embodiment, the pixel 10 includes a pixel circuit 40, a differential input circuit 90, a voltage conversion circuit 94, a positive feedback circuit 91 and a digital data holding unit 80.

The pixel circuit 40 outputs a pixel signal SIG based on the photoelectric conversion of the photoelectric conversion unit PD.

In this embodiment, the pixel circuit 40 includes: a photoelectric conversion unit PD, a plurality of transfer transistors TG, a storage unit FD, a discharge transistor OFG, a reset transistor RST, and a connection transistor FDG.

Furthermore, the photoelectric conversion unit PD is connected to the power storage unit FD via a plurality of transmission transistors TG. In this example, the photoelectric conversion unit PD is connected to the power storage unit FD via two transmission transistors TG connected in series. In this example, the transmission transistor TG on the upstream side (the side where the photoelectric conversion unit PD is arranged) is called the first transmission transistor, and the transmission transistor TG on the downstream side (the side where the power storage unit FD is arranged) is called the second transmission transistor.

In this example, the pixel 10 is configured such that one power storage unit FD, one differential input circuit 90, one positive feedback circuit 91, and one digital data holding unit 80 are provided for one photoelectric conversion unit PD.

The number of transmission transistors TG connected between each photoelectric conversion unit PD and the power storage unit FD is not limited to 2. It is sufficient that a plurality of transmission transistors TG are connected in series to form one group 118.

The anode of the photoelectric conversion unit PD is electrically connected to the ground potential, and the cathode of the photoelectric conversion unit PD is electrically connected to the transfer transistor TG and the discharge transistor OFG.

One of the source and drain of the first transfer transistor is electrically connected to the photoelectric conversion unit PD, and the other of the source and drain of the first transfer transistor TG is connected to one of the source and drain of the second transfer transistor. The other of the source and drain of the second transfer transistor is electrically connected to the power storage unit FD.

The storage unit FD is connected to the transmission transistor TG and the connection transistor FDG. Furthermore, the transmission transistor TG is electrically connected to the gate of the transistor of the differential input circuit 90. Thus, the transistor of the differential input circuit 90 also functions as an amplification transistor of the pixel circuit 40.

The differential input circuit 90 is composed of transistors 131 and 132 forming a differential pair, transistors 133 and 134 forming a current mirror, a transistor 135 serving as a constant current source for supplying a current IB corresponding to an input bias current Vb, and a transistor 136 for outputting an output signal HVO of the differential input circuit 90.

In this example, transistors 131, 132, and 135 are formed of NMOS (Negative Channel MOS) transistors, and transistors 133, 134, and 136 are formed of PMOS (Positive Channel MOS) transistors.

The reference signal REF output from the DAC 5 is input to the gate of the transistor 131 of the differential pair of transistors 131 and 132, and the pixel signal SIG output from the pixel circuit 40 is input to the gate of the transistor 132. The sources of the transistors 131 and 132 are connected to the drain of the transistor 135, and the source of the transistor 135 is connected to GND (ground).

The drain of transistor 131 is connected to the gates of transistors 133 and 134 constituting a current mirror circuit and the drain of transistor 133, and the drain of transistor 132 is connected to the drain of transistor 134 and the gate of transistor 136. The sources of transistors 133, 134, and 136 are connected to the first power supply voltage VDDH.

The voltage conversion circuit 94 is constituted by, for example, an NMOS type transistor 137. The drain of the transistor 137 is connected to the drain of the transistor 136 of the differential input circuit 90, the source of the transistor 137 is connected to a predetermined connection point in the positive feedback circuit 91, and the gate of the transistor 137 is connected to the second power source VDDL.

The transistors 131 to 136 constituting the differential input circuit 90 are circuits that operate at a high voltage as high as the first power supply VDDH, and the positive feedback circuit 91 is a circuit that operates at a second power supply voltage VDDL that is lower than the first power supply voltage VDDH.

In this example, the positive feedback circuit 91 is composed of seven transistors 111 to 117. Here, transistors 111, 112, 114, and 116 are composed of PMOS transistors, and transistors 113, 115, and 117 are composed of NMOS transistors.

The output terminal of the voltage conversion circuit 94, i.e., the source of transistor 137, is connected to the drains of transistors 112 and 113, and the gates of transistors 114 and 115. The sources of transistors 111 and 114 are connected to the second power source VDDL, the drain of transistor 111 is connected to the source of transistor 112, and the gate of transistor 112 is connected to the drains of transistors 116 and 117, which are also the output terminals of the positive feedback circuit 91. The source of transistor 116 is connected to the drain of transistor 114. The sources of transistors 113, 115, and 117 are connected to GND. An initialization signal INI2 is supplied to the gate of the transistor 111, and an initialization signal INI1 is supplied to the gate of the transistor 113.

Transistors 114 to 117 form a NOR circuit. The gate of transistor 116 and the gate of transistor 117 are supplied with the second input signal, that is, the control signal TEST_VCO.

The connection point of the drain of transistor 116 and the drain of transistor 117 is the output terminal of the VCO outputting the output signal.

In the positive feedback circuit 91, when the control signal TEST_VCO is set to Hi, regardless of the state of the differential input circuit 90, the output signal VCO is set to Lo.

The gate voltage of the control transistor 137 is controlled to cut off the transistor 137. When the initialization signals INI1 and INI2 are set to Hi, the output signal VCO is set to Hi regardless of the state of the differential input circuit 90. Therefore, by combining the forced Hi output of the output signal VCO with the forced Lo output formed by the control signal TEST_VCO, the output signal VCO can be set to an arbitrary value regardless of the state of the differential input circuit 90 and the pixel circuit 40 and DAC 5 in the front stage thereof. With this function, for example, it is possible to test the circuit from the pixel 10 to the back stage only by the electrical signal input without relying on the optical input to the solid-state imaging device 200.

FIG6 is a circuit diagram of a pixel portion of a solid-state imaging device of a comparative example.

In the comparative example, the configuration of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 is the same as that of the first embodiment, and thus a detailed description thereof is omitted.

In the comparative example, the pixel circuit 40 has a photoelectric conversion unit PD, a transmission transistor TG, a storage unit FD, a discharge transistor OFG, a reset transistor RST, and a connection transistor FDG. In the comparative example, the pixel circuit 40 of the present embodiment has a different number of transmission transistors TG connected between the photoelectric conversion unit and the storage unit FD transistor.

FIG. 7 is an enlarged view of the transmission transistor portion of the circuit diagram of the pixel of the first embodiment.

FIG. 7a illustrates an example of an operation for preventing the reverse flow of electrons when two transfer transistors TG are connected between the photoelectric conversion unit PD and the power storage unit FD.

The following describes an example in which the gates of the upstream transfer transistor TG and the downstream transfer transistor TG are turned on to transfer the charge stored in the photoelectric conversion unit PD to the power storage unit FD. After the gates of the transfer transistors TG are turned on to transfer the charge to the power storage unit FD, the gate of the upstream transfer transistor TG is turned off, and then the downstream transfer transistor TG is turned off, so that the pixel circuit 40 can prevent the electrons drawn to the power storage unit FD from flowing back to the photoelectric conversion unit PD.

The order of turning on and off the gates of the transfer transistors TG is not limited thereto. The pixel circuit 40 can turn off the transfer transistor TG on the upstream side at any timing to prevent backflow after turning on the gate of the transfer transistor TG on the upstream side and extracting the charge accumulated in the photoelectric conversion unit PD.

FIG. 7b illustrates an example in which the capacitance of the power storage section FD increases when two transfer transistors TG are connected between the photoelectric conversion section PD and the power storage section FD.

The example of setting the gates of the transmission transistor TG on the upstream side and the transmission transistor TG on the downstream side to conduct and transferring the charge accumulated in the photoelectric conversion part PD to the storage part FD is described. After setting the gates of each transmission transistor TG to conduct and transferring the charge to the storage part FD side, the gate of the transmission transistor TG on the upstream side is set to be off, and the pixel circuit 40 can further increase the capacitance of the storage part FD by forming a diffusion layer of the transmission transistor TG on the downstream side. In Figure 7b, the portion surrounded by the solid line is the FD capacitance. In addition, since the FD capacitance is increased, the conversion efficiency of the photoelectric conversion of the entire circuit can be increased.

According to this embodiment, the pixel circuit 40 can be connected to the photoelectric conversion part PD through a plurality of transmission transistors TG between the storage part FD and the photoelectric conversion part PD. By controlling the plurality of transmission transistors TG, the pixel circuit 40 can prevent the backflow of charges and increase the capacitance of the storage part FD. In addition, the pixel 10 can increase the conversion efficiency of the photoelectric conversion of the entire circuit by increasing the capacitance of the storage part FD.

Furthermore, according to the present embodiment, the photoelectric conversion portion PD is connected to the discharge transistor OFG, and exposure can be started after the unnecessary charge accumulated in the photoelectric conversion portion PD is discharged.

Furthermore, according to this embodiment, since each power storage unit FD is connected to the AD conversion circuit 70, it is possible to achieve higher speed compared to the row ADC. Also, the wiring capacitance of the wiring connecting the power storage unit FD to the AD conversion circuit 70 is small, and the power consumption during charging and discharging is small. Therefore, it is possible to achieve power saving compared to the row ADC.

(Second embodiment) Figure 8 is a circuit diagram of the pixel portion of the solid-state imaging device of the second embodiment.

In this embodiment, the structures of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 are the same as those in the first embodiment, and thus their description is omitted.

In this embodiment, the pixel circuit 40 includes: a plurality of photoelectric conversion units PD, a plurality of transfer transistors TG, a storage unit FD, a plurality of discharge transistors OFG, a reset transistor RST, and a connection transistor FDG.

In this example, the pixel circuit 40 connects two transmission transistors TG in series to form a group 118. Furthermore, the pixel circuit 40 is composed of a plurality of photoelectric conversion units PD having a storage unit FD, a differential input circuit 90, a positive feedback circuit 91 and a digital data retention unit 80. Furthermore, each photoelectric conversion unit PD is connected to a storage unit FD via a plurality of transmission transistors TG. In this example, four photoelectric conversion units PD are connected to the storage unit FD via the transmission transistor TG of each group 118. In this example, the pixel circuit 40 inputs the pixel signal SIG to the differential input circuit 90 four times.

The number of transmission transistors TG connected to each photoelectric conversion unit PD is not limited to 2. It is sufficient that a plurality of transmission transistors TG are connected in series to form one group 118.

Furthermore, the transmission transistor TG includes a first group of multiple transmission transistors TG connected in series with each other, and a second group of multiple transmission transistors TG connected in series with each other, and the power storage unit FD only needs to be connected to the first photoelectric conversion unit via the transmission transistors of the first group and connected to the second photoelectric conversion unit via the transmission transistors of the second group.

The number of photoelectric conversion units PD shared by the power storage unit FD is not limited to 4. It is sufficient that a plurality of photoelectric conversion units PD are provided, including a first photoelectric conversion unit and a second photoelectric conversion unit.

Furthermore, the pixel circuit 40 may be configured as follows: it includes a plurality of discharge transistors OFG, including a first discharge transistor and a second discharge transistor, the first discharge transistor being connected to the first photoelectric conversion unit, and the second discharge transistor being connected to the second photoelectric conversion unit.

According to the present embodiment, the pixel circuit 40 is connected to the photoelectric conversion section PD via a plurality of transmission transistors TG between the storage section FD and the photoelectric conversion section PD. By controlling the plurality of transmission transistors TG, the pixel circuit 40 can prevent the reverse flow of charges and increase the capacitance of the storage section FD. In addition, by increasing the capacitance of the storage section FD, the conversion efficiency of the photoelectric conversion of the entire circuit can be increased.

Furthermore, according to this embodiment, since a plurality of photoelectric conversion units PD share a power storage unit FD, etc., the circuit of the solid-state imaging device 200 can be miniaturized.

(Third embodiment) Figure 9 is a circuit diagram of the pixel portion of the solid-state imaging device of the third embodiment.

In this embodiment, the structures of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 are the same as those in the first embodiment, and thus their description is omitted.

In this embodiment, the pixel circuit 40 includes a photoelectric conversion unit PD, a plurality of transfer transistors TG, a storage unit FD, a discharge transistor OFG, a reset transistor RST, and a connection transistor FDG, and also includes a memory MEM for storing a charge.

In this example, the pixel circuit 40 connects two transmission transistors TG in series, the transmission transistor TG on the upstream side is called the first transmission transistor, and the transmission transistor TG on the downstream side is called the second transmission transistor. A memory MEM is connected between the first and second transmission transistors TG. In addition, the power storage unit FD is connected to the photoelectric conversion unit PD via the two transmission transistors TG and the memory MEM.

In this embodiment, the memory MEM temporarily stores the charge generated by the photoelectric conversion unit PD through photoelectric conversion. The first transfer transistor controls the transfer of the charge from the photoelectric conversion unit PD to the memory MEM. Furthermore, the second transfer transistor controls the transfer of the charge from the temporarily stored memory MEM and controls the transfer to the storage unit FD.

The number of the transmission transistors TG connected between each photoelectric conversion unit PD and the power storage unit FD is not limited to 2. The transmission transistor TG only needs to include a first transmission transistor and a second transmission transistor, which are connected in series to form a group 118.

According to the present embodiment, the pixel circuit 40 has a plurality of transmission transistors TG between the photoelectric conversion unit PD and the storage unit FD, and further, the pixel circuit 40 has a memory MEM between the first and second transmission transistors. Thus, the pixel circuit 40 can temporarily store the charge in the memory MEM before transferring the charge to the storage unit FD. For example, the pixel circuit 40 can transfer the charge to the storage unit FD in stages by adjusting the amount of charge transferred from the photoelectric conversion unit PD to the memory MEM and the amount of charge transferred from the memory MEM to the storage unit FD based on the control of the transmission transistor TG. For example, the pixel circuit 40 can send an amount of charge that the storage unit FD cannot store at one time.

(Fourth embodiment) Figure 10 is a circuit diagram of the pixel portion of the solid-state imaging device of the fourth embodiment.

In this embodiment, the structures of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 are the same as those in the first embodiment, and thus their description is omitted.

In this embodiment, the pixel circuit 40 includes: a plurality of photoelectric conversion units PD, a plurality of transfer transistors TG, a storage unit FD, a plurality of discharge transistors OFG, a reset transistor RST, a connection transistor FDG, and a plurality of memories MEM.

In this example, the pixel circuit 40 connects two transmission transistors TG in series to form a group 118. The transmission transistor TG on the upstream side is called the first transmission transistor, and the transmission transistor TG on the downstream side is called the second transmission transistor. A memory MEM is connected between the first and second transmission transistors. In addition, the pixel circuit 40 is composed of a plurality of photoelectric conversion units PD having a storage unit FD, a differential input circuit 90, a positive feedback circuit 91 and a digital data retention unit 80. The four photoelectric conversion units PD are connected to the storage unit FD via the transmission transistor TG of each group 118 and a memory MEM. In this example, the pixel circuit 40 is composed of four photoelectric conversion units PD, one storage unit FD, one differential input circuit 90, one positive feedback circuit 91, and one digital data holding unit 80. In this example, each photoelectric conversion unit PD is connected to one storage unit FD via two serially connected transmission transistors TG and one memory MEM.

The number of photoelectric converters PD shared by the power storage unit FD is not limited to 4. The pixel circuit 40 only needs to include a plurality of photoelectric converters PD, including a first photoelectric converter PD and a second photoelectric converter PD.

The number of the transmission transistors TG connected between each photoelectric conversion unit PD and the power storage unit FD is not limited to 2. The transmission transistor TG only needs to include a first transmission transistor and a second transmission transistor, which are connected in series to form a group 118.

Furthermore, the transmission transistor TG only needs to include a first group of multiple transmission transistors connected in series with each other, and a second group of multiple transmission transistors connected in series with each other, and the power storage unit FD only needs to be connected to the first photoelectric conversion unit via the first group of transmission transistors and connected to the second photoelectric conversion unit via the second group of transmission transistors.

Furthermore, the number of memory MEM connected to one group of transfer transistors TG is not limited to 1. With respect to the first group of transfer transistors and the second group of transfer transistors, at least one memory MEM may be connected between the transfer transistors constituting each group.

Furthermore, the pixel circuit 40 may be configured as follows: it includes a plurality of discharge transistors OFG, including a first discharge transistor and a second discharge transistor, the first discharge transistor being connected to the first photoelectric conversion unit, and the second discharge transistor being connected to the second photoelectric conversion unit.

According to the present embodiment, the pixel circuit 40 is connected to at least one memory MEM between the transfer transistors constituting each group. Thus, the pixel circuit 40 can temporarily store the charge in the memory MEM before transferring the charge to the storage unit FD. For example, the pixel circuit 40 can transfer the charge to the storage unit FD in stages by adjusting the amount of charge transferred from the photoelectric conversion unit PD to the memory MEM and the amount of charge transferred from the memory MEM to the storage unit FD based on the control of the transfer transistor TG. For example, the pixel circuit 40 can send the amount of charge that the storage unit FD cannot store at one time.

Furthermore, according to this embodiment, since a plurality of photoelectric conversion units PD share the power storage unit FD, etc., the circuit of the solid-state imaging device 200 can be miniaturized.

Furthermore, according to the present embodiment, each photoelectric conversion unit PD temporarily stores charges in the memory MEM, sequentially transfers the charges to the storage unit FD at a staggered timing, and inputs the pixel signal SIG to the differential input circuit 90, thereby realizing a global shutter function. That is, according to the present embodiment, the pixel 10 can realize the miniaturization realized by the shared storage unit FD and realize the global shutter function.

(Fifth Implementation Form) Figure 11 is a circuit diagram of the pixel portion of the solid-state imaging device of the fifth implementation form.

In this embodiment, the structures of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 are the same as those in the first embodiment, and thus their description is omitted.

In this embodiment, the pixel circuit 40 includes: a photoelectric conversion unit PD, a plurality of transfer transistors TG, a storage unit FD, a discharge transistor OFG, a reset transistor RST, and a connection transistor FDG.

In this example, the pixel circuit 40 connects three transmission transistors TG in series to form one group 118. Furthermore, the transmission transistors TG of two groups 118 of the pixel circuit 40 are connected in parallel. Furthermore, the photoelectric conversion unit PD is connected to the power storage unit FD via the transmission transistors TG of the two groups 118 connected in parallel.

In this example, the central transfer transistor TG of each group has a function as a memory by turning on the gate to extract charge. The upstream transfer transistor TG has a function of transferring charge to the central transfer transistor TG, and the downstream transfer transistor TG has a function of transferring charge from the central transfer transistor TG to the storage unit FD.

The number of the serially connected transmission transistors is not limited to 3. The transmission transistors may include a first group of a plurality of transmission transistors TG connected in series with each other and a second group of a plurality of transmission transistors TG connected in series with each other.

Furthermore, the number of the group 118 of parallel-connected transmission transistors TG is not limited to 2. The transmission transistors TG include a first group of a plurality of transmission transistors TG connected in series with each other and a second group of a plurality of transmission transistors TG connected in series with each other. The first group of transmission transistors and the second group of transmission transistors only need to be connected in parallel with each other.

According to the present embodiment, one of the transfer transistors TG constituting each group of the pixel circuit 40 has a function as a memory. Thus, the pixel circuit 40 can temporarily store the charge in the memory before transferring the charge to the storage unit FD. For example, the pixel circuit 40 can adjust the amount of charge transferred from the photoelectric conversion unit PD to the storage unit FD based on the control of the transfer transistors TG on the upstream and downstream sides of the transfer transistor TG having a function as a memory.

Furthermore, according to the present embodiment, since one photoelectric conversion unit PD shares the power storage unit FD via the group 118 of parallel-connected transfer transistors TG, the circuit of the solid-state imaging device 200 can be miniaturized.

(Sixth embodiment) Figure 12 is a circuit diagram of the pixel portion of the solid-state imaging device of the sixth embodiment.

In this embodiment, the structures of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 are the same as those in the first embodiment, and thus their description is omitted.

In this embodiment, the pixel circuit 40 includes: a plurality of photoelectric conversion units PD, a plurality of transfer transistors TG, a storage unit FD, a plurality of discharge transistors OFG, a reset transistor RST, and a connection transistor FDG.

In this example, the pixel circuit 40 connects three transmission transistors TG in series to form a group 119 to 122. In addition, the pixel circuit 40 connects the three transmission transistors TG of the first group 119 and the three transmission transistors TG of the third group 121 in parallel, and connects the three transmission transistors TG of the second group 120 and the three transmission transistors TG of the fourth group 122 in parallel. In addition, one of the two photoelectric conversion units PD is connected to the power storage unit FD via the three transmission transistors TG of the first group 119 and the three transmission transistors TG of the third group 121 connected in parallel. Furthermore, another photoelectric conversion unit PD is connected to the same power storage unit FD via the three transmission transistors TG of the second group 120 connected in parallel and the three transmission transistors TG of the fourth group 122. That is, each photoelectric conversion unit PD shares the power storage unit FD via the transmission transistors TG of each group connected in parallel.

Furthermore, the pixel circuit 40 is composed of a plurality of photoelectric conversion units PD, a common storage unit FD, a differential input circuit 90, a positive feedback circuit 91 and a digital data holding unit 80.

In this example, the central transfer transistor TG of each group has a function as a memory by turning on the gate to extract charge. The upstream transfer transistor TG has a function of transferring charge to the central transfer transistor TG, and the downstream transfer transistor TG has a function of transferring charge from the central transfer transistor TG to the storage unit FD.

The number of serially connected transfer transistors TG is not limited to 3. The pixel circuit 40 only needs to include a first group of multiple transfer transistors TG serially connected to each other, a second group of multiple transfer transistors TG serially connected to each other, a third group of multiple transfer transistors TG serially connected to each other, and a fourth group of multiple transfer transistors TG serially connected to each other.

The number of groups of parallel-connected transfer transistors TG is not limited to 2. The pixel circuit 40 only needs to connect the first group of transfer transistors and the third group of transfer transistors in parallel with each other, and connect the second group of transfer transistors and the fourth group of transfer transistors in parallel with each other.

The number of photoelectric conversion units PD sharing the power storage unit FD is not limited to 2. As long as the photoelectric conversion unit PD includes a first photoelectric conversion unit and a second photoelectric conversion unit, the power storage unit FD is connected to the first photoelectric conversion unit via a plurality of transmission transistors in the first group and the third group, and is connected to the second photoelectric conversion unit via a plurality of transmission transistors in the second group and the fourth group.

According to the present embodiment, one of the transfer transistors TG constituting each group of the pixel circuit 40 has a function as a memory. Thus, the pixel circuit 40 can temporarily store the charge in the memory before transferring the charge to the storage unit FD. For example, the pixel circuit 40 can adjust the amount of charge transferred from the photoelectric conversion unit PD to the storage unit FD based on the control of the transfer transistors TG on the upstream and downstream sides of the transfer transistor TG having a function as a memory.

Furthermore, according to the present embodiment, since each photoelectric conversion unit PD shares the power storage unit FD via the group 118 of parallel-connected transfer transistors TG, the circuit of the solid-state imaging device 200 can be miniaturized.

(Seventh Implementation Form) Figure 13 is a circuit diagram of the pixel portion of the solid-state imaging device of the seventh implementation form.

In this embodiment, the structures of the differential input circuit 90, the positive feedback circuit 91 and the digital data holding unit 80 are the same as those in the first embodiment, and thus their description is omitted.

In this embodiment, the pixel circuit 40 includes: a photoelectric conversion unit PD, a plurality of transfer transistors TG, a plurality of storage units FD, a discharge transistor OFG, a plurality of reset transistors RST, and a plurality of connection transistors FDG.

In this example, the pixel circuit 40 connects three transmission transistors TG in series to form a group. Furthermore, one photoelectric conversion unit PD is connected to different storage units FD via the transmission transistors TG of the first group 119 and the transmission transistors TG of the second group 120. Furthermore, each storage unit FD is connected to a different differential input circuit 90, voltage conversion 94, circuit positive feedback circuit 91 and data storage unit 92.

The number of the transfer transistors TG connected in series is not limited to 3. The pixel circuit 40 only needs to include a first group of a plurality of transfer transistors TG connected in series with each other, and a second group of a plurality of transfer transistors TG connected in series with each other.

Furthermore, the number of power storage units FD shared by one photoelectric conversion unit PD is not limited to 2. The power storage unit FD only needs to include a first power storage unit and a second power storage unit, and the first power storage unit only needs to be connected to the photoelectric conversion unit PD via a first group of transmission transistors, and the second power storage unit only needs to be connected to the photoelectric conversion unit PD via a second group of transmission transistors.

According to this embodiment, one photoelectric conversion unit PD can be connected to a plurality of storage units FD via a plurality of transfer transistors TG, and the charges stored in the photoelectric conversion unit PD can be input to different differential input circuits 90. In addition, since the data are not mixed, the output results can be treated as different data.

<<Configuration example of vehicle control system>> FIG. 14 is a block diagram showing a configuration example of a vehicle control system 11 as an example of a mobile device control system to which the present technology is applied.

The vehicle control system 11 is installed in the vehicle 1 to perform processing related to driving support and automatic driving of the vehicle 1.

The vehicle control system 11 includes: a vehicle control ECU (Electronic Control Unit) 21, a communication unit 22, a map information storage unit 23, a position information acquisition unit 24, an external identification sensor 25, an in-vehicle sensor 26, a vehicle sensor 27, a memory unit 28, a driving support and automatic driving control unit 29, a DMS (Driver Monitoring System) 30, an HMI (Human Machine Interface) 31, and a vehicle control unit 32.

The vehicle control ECU 21, the communication unit 22, the map information storage unit 23, the position information acquisition unit 24, the external identification sensor 25, the in-vehicle sensor 26, the vehicle sensor 27, the memory unit 28, the driving support and automatic driving control unit 29, the driver monitoring system (DMS) 30, the human-machine interface (HMI) 31, and the vehicle control unit 32 are connected to each other via a communication network 41 so as to be communicable with each other. The communication network 41 is composed of, for example, an in-vehicle communication network or bus based on digital two-way communication standards such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), FlexRay (registered trademark), Ethernet (registered trademark), etc. The communication network 41 can be used separately according to the type of data to be transmitted. For example, CAN can be used for data related to vehicle control, and Ethernet can be used for large-capacity data. In addition, the components of the vehicle control system 11 are sometimes directly connected without going through the communication network 41, using wireless communication such as NFC (Near Field Communication) or Bluetooth (registered trademark) for communication at a shorter distance.

In addition, in the following, when the components of the vehicle control system 11 communicate via the communication network 41, the description of the communication network 41 is omitted. For example, when the vehicle control ECU 21 and the communication unit 22 communicate via the communication network 41, it is simply described that the vehicle control ECU 21 and the communication unit 22 communicate.

The vehicle control ECU 21 is composed of various processors such as a CPU (Central Processing Unit) and an MPU (Micro Processing Unit). The vehicle control ECU 21 can control the functions of the vehicle control system 11 as a whole or in part.

The communication unit 22 communicates with various devices inside and outside the vehicle, other vehicles, servers, base stations, etc. to send and receive various data. At this time, the communication unit 22 can use multiple communication methods to communicate.

The communication with the outside of the vehicle that the communication unit 22 can perform is briefly described. The communication unit 22 communicates with a server located on an external network (hereinafter referred to as an external server) through a base station or access point through a wireless communication method such as 5G (5th generation mobile communication system), LTE (Long Term Evolution), DSRC (Dedicated Short Range Communications), etc. The external network that the communication unit 22 communicates with is, for example, the Internet, a cloud network, or a company's inherent network. The communication method that the communication unit 22 uses with the external network is not particularly limited as long as it is a wireless communication method that can perform digital two-way communication at a communication speed above the specified distance.

For example, the communication unit 22 can use P2P (Peer To Peer) technology to communicate with a terminal located near the vehicle. The terminal located near the vehicle is, for example, a terminal installed on a mobile object moving at a relatively low speed such as a pedestrian or a bicycle, a terminal fixed in a store, etc., or an MTC (Machine Type Communication) terminal. Furthermore, the communication unit 22 can also perform V2X communication. V2X communication refers to, for example, vehicle-to-vehicle communication with other vehicles, vehicle-to-infrastructure communication with roadside devices, vehicle-to-home communication, and vehicle-to-pedestrian communication with terminals held by pedestrians.

The communication unit 22 can, for example, receive from the outside a program (Over The Air, wireless) for updating the software that controls the operation of the vehicle control system 11. The communication unit 22 can further receive map information, traffic information, information about the surroundings of the vehicle 1, etc. from the outside. Also, for example, the communication unit 22 can send information related to the vehicle 1 and information about the surroundings of the vehicle 1 to the outside. As information related to the vehicle 1 sent to the outside by the communication unit 22, for example, there are data indicating the state of the vehicle 1, the identification result of the identification unit 73, etc. Furthermore, for example, the communication unit 22 performs communication corresponding to a vehicle emergency notification system such as e-call.

For example, the communication unit 22 receives electromagnetic waves transmitted by a road traffic information communication system (VICS (Vehicle Information and Communication System) (registered trademark)) such as radio beacons, optical beacons, and FM multi-channel broadcasting.

The communication with the vehicle that the communication unit 22 can perform is briefly described. The communication unit 22 can communicate with the various devices in the vehicle using, for example, wireless communication. The communication unit 22 can communicate with the devices in the vehicle wirelessly using, for example, wireless LAN, Bluetooth, NFC, WUSB (Wireless USB), or other communication methods that can perform digital two-way communication at a communication speed above a prescribed speed. Not limited to this, the communication unit 22 can also communicate with the various devices in the vehicle using wired communication. For example, the communication unit 22 can communicate with the various devices in the vehicle through wired communication via a cable connected to a connection terminal not shown in the figure. The communication unit 22 can communicate with various devices in the vehicle through a communication method that can perform digital two-way communication at a communication speed above a specified speed through wired communication, such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), MHL (Mobile High-definition Link), etc.

Here, the in-car device refers to, for example, a device in the car that is not connected to the communication network 41. As the in-car device, for example, a mobile device or a wearable device held by a passenger such as a driver, and an information device temporarily installed in the car are assumed.

The map information storage unit 23 stores one or both of a map obtained from the outside and a map created by the vehicle 1. For example, the map information storage unit 23 stores a three-dimensional high-precision map, a global map with a lower precision than the high-precision map and covering a wide area, and the like.

High-precision maps include, for example, dynamic maps, point cloud maps, and vector maps. Dynamic maps include, for example, maps composed of four layers of dynamic information, quasi-dynamic information, quasi-static information, and static information, and are provided to the vehicle 1 from an external server or the like. Point cloud maps are maps composed of point clouds (point group data). Vector maps include, for example, maps that establish correspondence between traffic information such as the location of lanes and traffic lights and point cloud maps and are suitable for ADAS (Advanced Driver Assistance System) and AD (Autonomous Driving).

Point cloud maps and vector maps can be provided from an external server, etc., and can be prepared by the vehicle 1 based on the sensing results of the camera 51, radar 52, LiDAR 53, etc. as a map for matching with the regional map described later, and stored in the map information storage unit 23. In addition, in the case where the map is provided from an external server, etc. with high accuracy, the communication capacity is reduced, so the vehicle 1 obtains map data of, for example, several hundred square meters related to the planned route for the next driving from the external server, etc.

The position information acquisition unit 24 receives GNSS (Global Navigation Satellite System) signals from a GNSS satellite to acquire the position information of the vehicle 1. The acquired position information is provided to the driving support and automatic driving control unit 29. In addition, the position information acquisition unit 24 is not limited to the method of using GNSS signals, for example, a beacon can be used to acquire the position information.

The exterior recognition sensor 25 has various sensors for recognizing the conditions outside the vehicle 1, and supplies sensor data from each sensor to each part of the vehicle control system 11. The types and number of sensors included in the exterior recognition sensor 25 are arbitrary.

For example, the external identification sensor 25 includes a camera 51, a radar 52, a LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) 53, and an ultrasonic sensor 54. However, the external identification sensor 25 may include at least one of the camera 51, the radar 52, the LiDAR 53, and the ultrasonic sensor 54. The number of the camera 51, the radar 52, the LiDAR 53, and the ultrasonic sensor 54 is not particularly limited as long as it is the number that can be installed in the vehicle 1 in reality. Furthermore, the type of sensor included in the external identification sensor 25 is not limited to this example, and the external identification sensor 25 may include other types of sensors. Examples of the sensing area of each sensor included in the external identification sensor 25 will be described later.

In addition, the photographing method of the camera 51 is not particularly limited. For example, various photographing methods such as a ToF (Time Of Flight) camera, a stereo camera, a SLR camera, an infrared camera, etc., which are photographing methods capable of measuring distance, can be applied to the camera 51 as needed. However, the camera 51 may be irrelevant to measuring distance and may be used only to obtain photographic images.

For example, the external identification sensor 25 may include an environmental sensor for detecting the environment of the vehicle 1. The environmental sensor may be a sensor for detecting weather, meteorology, brightness, etc., for example, including various sensors such as raindrop sensors, fog sensors, sunshine sensors, snow sensors, and illumination sensors.

Furthermore, for example, the external recognition sensor 25 has a microphone for detecting sounds around the vehicle 1 and the position of the sound source.

The in-vehicle sensor 26 has various sensors for detecting information in the vehicle, and supplies sensor data from each sensor to each part of the vehicle control system 11. The types and numbers of the various sensors of the in-vehicle sensor 26 are not particularly limited as long as they can be installed in the vehicle 1 in reality.

For example, the in-vehicle sensor 26 may include one or more sensors selected from the group consisting of a camera, a radar, a seat sensor, a steering sensor, a microphone, and a biosensor. As the camera provided by the in-vehicle sensor 26, for example, a ToF camera, a stereo camera, a SLR camera, an infrared camera, and other cameras that can perform various photographic methods for distance measurement may be used. Not limited to this, the camera provided by the in-vehicle sensor 26 may also be unrelated to distance measurement and only used to obtain photographic images. The biosensor provided by the in-vehicle sensor 26 is, for example, installed on a seat or a steering wheel to detect various biometric information of a driver or other passenger.

The vehicle sensor 27 may include various sensors for detecting the state of the vehicle 1, and provide sensor data from each sensor to each part of the vehicle control system 11. The types and numbers of the various sensors included in the vehicle sensor 27 are not particularly limited as long as they can be installed in the vehicle 1 in reality.

For example, the vehicle sensor 27 includes: a speed sensor, an acceleration sensor, an angular velocity sensor (gyro sensor), and an inertial measurement device (IMU (Inertial Measurement Unit)) that integrates the above. For example, the vehicle sensor 27 includes: a steering angle sensor that detects the steering angle of the steering wheel, a yaw rate sensor, an accelerator sensor that detects the amount of operation of the accelerator pedal, and a brake sensor that detects the amount of operation of the brake pedal. For example, the vehicle sensor 27 includes: a rotation sensor that detects the speed of the engine and the motor, an air pressure sensor that detects the air pressure of the tire, a slip rate sensor that detects the slip rate of the tire, and a wheel speed sensor that detects the rotation speed of the wheel. For example, the vehicle sensor 27 includes a battery sensor for detecting the battery level and temperature, and a shock sensor for detecting external shock.

The memory unit 28 includes at least one of a non-volatile memory medium and a volatile memory medium, and stores data and programs. The memory unit 28 is used as, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory) and a RAM (Random Access Memory). As a memory medium, a magnetic memory device such as an HDD (Hard Disc Drive), a semiconductor memory device, an optical memory device, and a magneto-optical memory device can be applied. The memory unit 28 stores various programs and data used by various parts of the vehicle control system 11. For example, the memory unit 28 has an EDR (Event Data Recorder) or a DSSAD (Data Storage System for Automated Driving) to store information of the vehicle 1 before and after an accident or the like and information obtained from the in-vehicle sensor 26.

The driving support and automatic driving control unit 29 performs driving support and automatic driving control of the vehicle 1. For example, the driving support and automatic driving control unit 29 includes an analysis unit 61, an action planning unit 62, and an action control unit 63.

The analyzing unit 61 performs analysis processing of the vehicle 1 and the surrounding conditions. The analyzing unit 61 includes a self-position estimating unit 71 , a sensor fusion unit 72 , and an identification unit 73 .

The own position estimating unit 71 estimates the own position of the vehicle 1 based on the sensor data from the external identification sensor 25 and the high-precision map stored in the map information storage unit 23. For example, the own position estimating unit 71 generates a regional map based on the sensor data from the external identification sensor 25, and estimates the own position of the vehicle 1 by matching the regional map with the high-precision map. The position of the vehicle 1 can be based on the center of the rear wheel relative to the axle, for example.

An example of a regional map is a three-dimensional high-precision map or an occupancy grid map produced using technologies such as SLAM (Simultaneous Localization and Mapping). An example of a three-dimensional high-precision map is the above-mentioned point cloud map. An occupancy grid map divides the three-dimensional or two-dimensional space around the vehicle 1 into grids (grids) of a specific size and represents the occupancy status of objects in grid units. The occupancy status of an object is represented, for example, by the presence or absence of an object and the probability of its existence. The regional map is also used, for example, in the detection and identification processing of the external condition of the vehicle 1 by the identification unit 73.

In addition, the own position estimating unit 71 can estimate the own position of the vehicle 1 based on the position information acquired by the position information acquiring unit 24 and the sensor data from the vehicle sensor 27.

The sensor fusion unit 72 combines a plurality of different types of sensor data (for example, image data supplied from the camera 51 and sensor data supplied from the radar 52) to perform sensor fusion processing to obtain new information. Methods for combining different types of sensor data include integration, fusion, and union.

The recognition unit 73 executes: a detection process for detecting the state of the exterior of the vehicle 1 , and a recognition process for recognizing the state of the exterior of the vehicle 1 .

For example, the recognition unit 73 performs detection and recognition processing of the external condition of the vehicle 1 based on information from the external recognition sensor 25, information from the own position estimation unit 71, information from the sensor fusion unit 72, and the like.

Specifically, for example, the recognition unit 73 performs detection processing and recognition processing of objects around the vehicle 1. Object detection processing is, for example, processing for detecting the presence, size, shape, position, movement, etc. of an object. Object recognition processing is, for example, processing for recognizing properties such as the type of an object, or processing for recognizing a specific object. However, detection processing and recognition processing are not necessarily clearly separated and may be repeated.

For example, the recognition unit 73 detects objects around the vehicle 1 by clustering the point cloud based on the sensor data such as the radar 52 or the LiDAR 53, and classifying each block of the point group. In this way, the presence, size, shape, and position of the objects around the vehicle 1 are detected.

For example, the recognition unit 73 detects the movement of the object around the vehicle 1 by tracking the movement of the block of the point group classified by clustering. In this way, the speed and moving direction (movement vector) of the object around the vehicle 1 are detected.

For example, the recognition unit 73 detects or recognizes vehicles, people, bicycles, obstacles, structures, roads, traffic lights, traffic signs, road signs, etc. based on the image data provided by the camera 51. In addition, the recognition unit 73 can recognize the types of objects around the vehicle 1 by performing recognition processing such as semantic segmentation.

For example, the recognition unit 73 can perform recognition processing of traffic regulations around the vehicle 1 based on the map stored in the map information storage unit 23, the estimation result of the own position by the own position estimation unit 71, and the recognition result of the objects around the vehicle 1 by the recognition unit 73. Through this processing, the recognition unit 73 can recognize the position and state of the signal machine, the content of the traffic signs and road signs, the content of the traffic regulations, and the lanes available for driving.

For example, the recognition unit 73 may perform recognition processing of the environment around the vehicle 1. As the surrounding environment regarded as the recognition object by the recognition unit 73, weather, temperature, humidity, brightness, and road surface conditions are assumed.

The action plan unit 62 creates an action plan for the vehicle 1. For example, the action plan unit 62 creates an action plan by performing route planning and route tracking processes.

In addition, the path planning (Global path planning) is a process of planning the approximate path from the starting point to the end point. The path planning is called track planning. In the planned path, the movement characteristics of the vehicle 1 are considered, and the process of generating a track (Local path planning) that can travel safely and smoothly near the vehicle 1 is also included.

The so-called path following is a process of planning actions for safe and correct driving within a planned time on the path planned by the path planner. The action planning unit 62 can, for example, calculate the target speed and target angular velocity of the vehicle 1 based on the result of the path following process.

The action control unit 63 can control the action of the vehicle 1 in order to implement the action plan prepared by the action planning unit 62 .

For example, the motion control unit 63 controls the steering control unit 81, the brake control unit 82, and the drive control unit 83 included in the vehicle control unit 32 described later, and performs acceleration and deceleration control and direction control so that the vehicle 1 travels on the track calculated by the track plan. For example, the motion control unit 63 can perform coordinated control for the purpose of realizing ADAS functions such as collision avoidance or impact mitigation, following driving, speed maintenance driving, collision warning of the vehicle, lane departure warning of the vehicle, etc. For example, the motion control unit 63 can perform coordinated control for the purpose of automatic driving that is not restricted by the driver's operation and drives autonomously.

The DMS 30 performs driver authentication processing and driver status recognition processing based on sensor data from the in-vehicle sensor 26 and input data input to the HMI 31 described later. The driver's status to be recognized includes, for example, physical condition, sobriety, concentration, fatigue, gaze direction, drunkenness, driving operation, posture, etc.

In addition, the DMS 30 can perform authentication processing of passengers other than the driver and identification processing of the status of the passengers. For example, the DMS 30 can perform identification processing of the in-vehicle conditions based on the sensor data from the in-vehicle sensor 26. As the in-vehicle conditions to be identified, for example, temperature, humidity, brightness, odor, etc. are assumed.

The HMI 31 inputs various data and instructions, and presents various data to the driver.

The data input performed by the HMI 31 is briefly described. The HMI 31 has an input device for a person to input data. The HMI 31 generates an input signal based on the data and instructions inputted through the input device, and supplies it to each part of the vehicle control system 11. The HMI 31 has operating parts such as a touch panel, buttons, switches, and levers as input devices. Not limited to this, the HMI 31 may further have an input device that can input information by methods other than manual operation such as sound or gestures. Furthermore, the HMI 31 may use, for example, a remote control device using infrared or radio waves, or an external connection device such as a mobile device or a wearable device corresponding to the operation of the vehicle control system 11 as an input device.

The data presentation performed by the HMI 31 is briefly described. The HMI 31 generates visual information, auditory information, and tactile information for passengers or outside the vehicle. In addition, the HMI 31 performs output control such as output, output content, output timing, and output method of each generated information. For example, the HMI 31 generates and outputs images such as an operation screen, a status display of the vehicle 1, a warning display, and a surveillance image showing the status around the vehicle 1, or information represented by light as visual information. In addition, the HMI 31 generates and outputs information represented by sound such as voice guidance, warning sounds, and warning messages as auditory information. Furthermore, the HMI 31 generates and outputs information given to the passenger's sense of touch by force, vibration, movement, etc., as tactile information.

As an output device for outputting visual information of the HMI 31, for example, a display device that displays images to provide visual information, or a projector device that projects images to provide visual information can be applied. In addition, the display device may be a display device having a general display, or may be a device that displays visual information in the field of vision of a passenger, such as a vehicle-mounted display, a transparent display, or a wearable device having an AR (Augmented Reality) function. Furthermore, the HMI 31 may also use a display device provided in a navigation device, an instrument panel, a CMS (Camera Monitoring System), an electronic reflector, a lamp, etc., installed in the vehicle 1 as an output device for outputting visual information.

As an output device for the HMI 31 to output auditory information, for example, an audio speaker, a headset, or an earphone can be used.

As an output device for outputting tactile information of the HMI 31, for example, a tactile element using tactile technology can be applied. The tactile element is provided on a part of the vehicle 1 that is touched by a passenger, such as a steering wheel or a seat.

The vehicle control unit 32 controls various components of the vehicle 1. The vehicle control unit 32 includes a steering control unit 81, a brake control unit 82, a drive control unit 83, a vehicle system control unit 84, a light control unit 85, and a horn control unit 86.

The steering control unit 81 detects and controls the state of the steering system of the vehicle 1. The steering system includes, for example, a steering mechanism including a steering wheel, electric assisted steering, etc. The steering control unit 81 includes, for example, a steering ECU that controls the steering system, an actuator that drives the steering system, etc.

The brake control unit 82 detects and controls the state of the brake system of the vehicle 1. The brake system includes, for example, a brake mechanism including a brake pedal, ABS (Antilock Brake System), and a regenerative brake mechanism. The brake control unit 82 includes, for example, a brake ECU that controls the brake system and an actuator that drives the brake system.

The drive control unit 83 detects and controls the state of the drive system of the vehicle 1. The drive system includes, for example, an accelerator pedal, an internal combustion engine, or a drive motor, a drive force generating device for generating a drive force, and a drive force transmitting mechanism for transmitting the drive force to the wheels. The drive control unit 83 includes, for example, a drive ECU for controlling the drive system, and an actuator for driving the drive system.

The vehicle system control unit 84 detects and controls the state of the vehicle system of the vehicle 1. The vehicle system includes, for example, a keyless entry system, a smart key system, a power window device, a power seat, an air conditioning device, an air bag, a seat belt, and a gear lever. The vehicle system control unit 84 includes, for example, a vehicle system ECU for controlling the vehicle system and an actuator for driving the vehicle system.

The light control unit 85 detects and controls the states of various lights of the vehicle 1. As the lights to be controlled, for example, headlights, backlights, fog lights, turn signals, brake lights, projection, bumper displays, etc. are assumed. The light control unit 85 has a light ECU that controls the lights and an actuator that drives the lights.

The horn control unit 86 performs detection and control of the state of the horn of the vehicle 1. The horn control unit 86 includes, for example, a horn ECU for controlling the horn and an actuator for driving the horn.

Fig. 15 is a diagram showing an example of the sensing area of the camera 51, radar 52, LiDAR 53, and ultrasonic sensor 54 of the external recognition sensor 25 of Fig. 14. In addition, Fig. 15 schematically shows the state of the vehicle 1 viewed from above, with the left end side being the front end (front) side of the vehicle 1 and the right end side being the rear end (rear) side of the vehicle 1.

The sensing area 101F and the sensing area 101B are examples of sensing areas of the ultrasonic sensor 54. The sensing area 101F covers the front periphery of the vehicle 1 by a plurality of ultrasonic sensors 54. The sensing area 101B covers the rear periphery of the vehicle 1 by a plurality of ultrasonic sensors 54.

The sensing results of the sensing area 101F and the sensing area 101B are used, for example, for parking support of the vehicle 1 .

Sensing area 102F to sensing area 102B represent examples of sensing areas of radar 52 for short or medium distance. Sensing area 102F covers a position farther from the front of vehicle 1 than sensing area 101F. Sensing area 102B covers a position farther from the rear of vehicle 1 than sensing area 101B. Sensing area 102L covers the periphery behind the left side of vehicle 1. Sensing area 102R covers the periphery behind the right side of vehicle 1.

The sensing result of the sensing area 102F is used, for example, to detect vehicles or pedestrians in front of the vehicle 1. The sensing result of the sensing area 102B is used, for example, for collision avoidance behind the vehicle 1. The sensing results of the sensing areas 102L and 102R are used, for example, to detect objects in the blind spot on the side of the vehicle 1.

Sensing area 103F to sensing area 103B represent examples of sensing areas of camera 51. Sensing area 103F covers a position farther from the front of vehicle 1 than sensing area 102F. Sensing area 103B covers a position farther from the rear of vehicle 1 than sensing area 102B. Sensing area 103L covers the periphery of the left side of vehicle 1. Sensing area 103R covers the periphery of the right side of vehicle 1.

The sensing result of the sensing area 103F can be used, for example, for signal or traffic sign recognition, lane departure prevention support system, and automatic headlight control system. The sensing result of the sensing area 103B can be used, for example, for parking support and surround view system. The sensing results of the sensing area 103L and the sensing area 103R can be used, for example, for surround view system.

The sensing area 104 is an example of the sensing area of the LiDAR 53. The sensing area 104 covers a position farther in front of the vehicle 1 than the sensing area 103F. On the other hand, the left-right range of the sensing area 104 is narrower than that of the sensing area 103F.

The sensing results of the sensing area 104 are used, for example, for detecting objects such as surrounding vehicles.

The sensing area 105 is an example of the sensing area of the long-distance radar 52. The sensing area 105 covers a position farther in front of the vehicle 1 than the sensing area 104. On the other hand, the left-right range of the sensing area 105 is narrower than that of the sensing area 104.

The sensing result of the sensing area 105 is used, for example, for ACC (Adaptive Cruise Control), emergency braking, collision avoidance, etc.

In addition, the sensing area of each sensor of the camera 51, radar 52, LiDAR 53, and ultrasonic sensor 54 included in the external identification sensor 25 can also adopt various structures other than FIG. 15. Specifically, the ultrasonic sensor 54 can also sense the side of the vehicle 1, and the LiDAR 53 can sense the rear of the vehicle 1. In addition, the installation position of each sensor is not limited to the above examples. In addition, the number of each sensor can be one or more.

Furthermore, for example, the present disclosure may adopt the following configuration.

(1) A solid-state imaging device, comprising a pixel array section formed by a plurality of pixels arranged in a two-dimensional array; and at least one of the plurality of pixels comprises: a pixel circuit that generates a pixel signal of an analog signal based on photoelectric conversion; an AD conversion section that converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and a digital data holding section that holds data of the digital signal; the pixel circuit comprises: a photoelectric conversion section that generates charge from light by photoelectric conversion; a storage section that stores the charge generated by the photoelectric conversion section; and a plurality of transfer transistors that control the transfer of the charge from the photoelectric conversion section to the storage section.

(2) A solid-state imaging device as described in (1), wherein the AD conversion unit and the digital data storage unit are provided for each of the power storage units.

(3) A solid-state imaging device as in (1), wherein the plurality of transmission transistors are connected in series with each other.

(4) A solid-state imaging device as in (1), wherein the plurality of transmission transistors include a first transmission transistor and a second transmission transistor; and a memory for retaining charge is connected between the first transmission transistor and the second transmission transistor.

(5) A solid-state imaging device as in (4), wherein the first transfer transistor controls the transfer of charge from the photoelectric conversion unit to the memory.

(6) A solid-state imaging device as in (5), wherein the second transfer transistor controls the transfer of charge from the memory to the storage unit.

(7) A solid-state imaging device as in (1), wherein the aforementioned pixel further comprises a discharge transistor for discharging electric charge.

(8) A solid-state imaging device as in (7), wherein the discharge transistor is connected to the photoelectric conversion unit.

(9) A solid-state imaging device, comprising a pixel array section formed by a plurality of pixels arranged in a two-dimensional array; and at least one of the plurality of pixels comprises: a pixel circuit, which generates a pixel signal of an analog signal based on photoelectric conversion; an AD conversion section, which converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and a digital data holding section, which holds the data of the digital signal; the pixel circuit comprises: a first and a second photoelectric conversion section, which generate electric charge from light by photoelectric conversion; a storage section, which stores the electric charge generated by the first and second photoelectric conversion sections; a first group of a plurality of transmission transistors, which control the transmission of the electric charge from the first photoelectric conversion section to the storage section; and The plurality of transmission transistors of the second group control the transmission of the aforementioned charge from the aforementioned second photoelectric conversion unit to the aforementioned power storage unit; The aforementioned power storage unit is connected to the aforementioned first photoelectric conversion unit via the plurality of transmission transistors of the first group, and is connected to the aforementioned first photoelectric conversion unit via the plurality of transmission transistors of the second group.

(10) A solid-state imaging device as in (9), wherein the plurality of transmission transistors in the first group and the second group are connected in series with each other.

(11) A solid-state imaging device as in (9), wherein the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group are such that the transmission transistors of the first group and the second group respectively include the first and second transmission transistors; and a memory for retaining charge is connected between the first and second transmission transistors.

(12) A solid-state imaging device as in (11), wherein, with respect to the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group, each of the first transmission transistors controls the transmission of charge from the photoelectric conversion unit to the memory.

(13) A solid-state imaging device as in (12), wherein, with respect to the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group, each of the second transmission transistors controls the transfer of charge from the memory to the storage unit.

(14) A solid-state imaging device as in (11), wherein the AD conversion unit and the digital data storage unit are provided for each of the power storage units.

(15) A solid-state imaging device as described in (11), wherein the pixel further comprises a first discharge transistor and a second discharge transistor for discharging charge.

(16) A solid-state imaging device as in (15), wherein the first discharge transistor is connected to the first photoelectric conversion unit; and the second discharge transistor is connected to the second photoelectric conversion unit.

(17) A solid-state imaging device as in (1), wherein the plurality of transmission transistors include a plurality of transmission transistors of the first group connected in series with each other, and a plurality of transmission transistors of the second group connected in series with each other; and the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group are connected in parallel with each other; the power storage unit is connected to the photoelectric conversion unit via the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group.

(18) A solid-state imaging device as in (9), wherein the pixel circuit further comprises: a plurality of transmission transistors of the third group, which control the transmission of the aforementioned charge from the aforementioned first photoelectric conversion unit to the aforementioned storage unit; and a plurality of transmission transistors of the fourth group, which control the transmission of the aforementioned charge from the aforementioned second photoelectric conversion unit to the aforementioned storage unit; and the plurality of transmission transistors of the first group and the plurality of transmission transistors of the third group are connected in parallel with each other; the plurality of transmission transistors of the second group and the plurality of transmission transistors of the fourth group are connected in parallel with each other; The aforementioned power storage unit is connected to the aforementioned first photoelectric conversion unit via the aforementioned first group and third group of multiple transmission transistors, and is connected to the aforementioned second photoelectric conversion unit via the aforementioned second group and fourth group of multiple transmission transistors.

(19) A solid-state imaging device, comprising a pixel array section formed by a plurality of pixels arranged in a two-dimensional array; and at least one of the plurality of pixels comprises: a pixel circuit, which generates a pixel signal of an analog signal based on photoelectric conversion; an AD conversion section, which converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and a digital data holding section, which holds the data of the digital signal; the pixel circuit comprises: a photoelectric conversion section, which generates charge from light by photoelectric conversion; a first and a second storage section, which store the aforementioned charge generated by the photoelectric conversion section; a first group of a plurality of transfer transistors, which control the transfer of the aforementioned charge from the photoelectric conversion section to the first storage section; and The plurality of transmission transistors of the second group control the transmission of the aforementioned charge from the aforementioned photoelectric conversion unit to the aforementioned second storage unit; The aforementioned first storage unit is connected to the aforementioned photoelectric conversion unit via the plurality of transmission transistors of the first group; The aforementioned second storage unit is connected to the aforementioned photoelectric conversion unit via the plurality of transmission transistors of the second group.

(20) A solid-state imaging device as in (19), wherein the AD conversion unit and the digital data storage unit are respectively disposed in the first power storage unit and the second power storage unit.

1: Vehicle 2: Pixel array 3: Timing code transmission (transmitter) 4: Pixel drive circuit 5: DAC 6: Timing code generation 7: Vertical drive circuit 8: Output 9: Timing generation circuit 10: Pixel 11: Vehicle control system 21: Vehicle control ECU 22: Communication 23: Map information storage 24: Position information acquisition 25: External identification sensor 26: In-vehicle sensor 27: Vehicle sensor 28: Memory 29: Driving support, automatic driving control 30: DMS/driver monitoring system 31: HMI/Human Machine Interface 32: Vehicle Control Unit 40: Pixel Circuit 41: Communication Network 50: ADC 51: Camera 52: Radar 53: LiDAR 54: Ultrasonic Sensor 61: Analysis Unit 62: Action Planning Unit 63: Action Control Unit 70: AD Conversion Circuit 71: Self-Position Estimation Unit 72: Sensor Fusion Unit 73: Identification Unit 80: Digital Data Retention Unit 81: Steering Control Unit 82: Brake Control Unit 83: Drive Control Unit 84: Vehicle System Control Unit 85: Light Control Unit 86: Speaker Control Unit 90: Differential Input Circuit 91: Positive Feedback Circuit 94: voltage conversion circuit 95: latch control circuit 96: latch memory unit 100: camera device 101B, 101F, 102B, 102F, 102L, 102R, 103B, 103F, 103L, 103R, 104, 105: sensing area 111, 112, 113, 114, 115, 116, 117, 131, 132, 133, 134, 135, 136, 137: transistor 118: group 119: group 1/group 120: group 2 121: group 3 122: group 4 200: Solid-state imaging device 209: Signal line 210: Imaging lens 220: Recording unit 230: Control unit 240: Analysis unit 242: Calculation processing unit 250: Wireless communication unit 260: Speaker unit 270: Display unit 300: Semiconductor substrate FD: Storage unit FDG: Connection transistor HVO: Output signal INI1, INI2: Initialization signal LATSEL, xLATSEL, xWORD: Signal LVI: Signal (conversion signal) MEM: Memory OFG: Discharge transistor PD: Photoelectric conversion unit REF: Reference signal RST: Reset transistor SIG: Pixel signal T: Lock control signal TG: Transistor Vb: Input bias current VCO: Output signal/signal VDDH: 1st power supply voltage/1st power supply VDDL: 2nd power supply voltage/2nd power supply

FIG. 1 is a block diagram showing an example of a configuration of an imaging device of the first embodiment. FIG. 2 is a schematic diagram of a solid-state imaging device of the first embodiment. FIG. 3 is a block diagram of a pixel, etc. of the first embodiment. FIG. 4 is a block diagram (details) of a pixel, etc. of the first embodiment. FIG. 5 is a circuit diagram of a pixel portion of a solid-state imaging device of the first embodiment. FIG. 6 is a circuit diagram of a pixel portion of a solid-state imaging device of a comparative example. FIG. 7a and FIG. 7b are enlarged views of a transmission transistor portion of a circuit diagram of a pixel of the first embodiment. FIG. 8 is a circuit diagram of a pixel portion of a solid-state imaging device of the second embodiment. FIG. 9 is a circuit diagram of a pixel portion of a solid-state imaging device of the third embodiment. FIG. 10 is a circuit diagram of a pixel portion of a solid-state imaging device of the fourth embodiment. FIG. 11 is a circuit diagram of a pixel portion of a solid-state imaging device of the fifth embodiment. FIG. 12 is a circuit diagram of a pixel portion of a solid-state imaging device of the sixth embodiment. FIG. 13 is a circuit diagram of a pixel portion of a solid-state imaging device of the seventh embodiment. FIG. 14 is a block diagram showing an example of a configuration of a vehicle control system. FIG. 15 is a diagram showing an example of a sensing area.

10: Pixels

40: Pixel circuit

80: Digital data retention unit

90: Differential input circuit

91: Positive feedback circuit

94: Voltage conversion circuit

95: Lock control circuit

96: Lock memory

111,112,113,114,115,116,117,131,132,133,134,135,136,137: Transistor

118: Group

FD: Battery storage unit

FDG: Connecting transistors

INI1, INI2: Initialization signal

LATSEL,xLATSEL:signal

MEM: memory

OFG: discharge transistor

PD: Photoelectric conversion unit

REF: Reference signal

RST: Reset transistor

SIG: Pixel signal

T: Lock control signal

TG:Transmission transistor

Vb: Input bias current

VCO: output signal/signal

VDDH: 1st power supply voltage/1st power supply

VDDL: Second power supply voltage/second power supply

Claims (20)

A solid-state imaging device includes a pixel array section formed by arranging a plurality of pixels in a two-dimensional array; and At least one of the plurality of pixels includes: A pixel circuit that generates a pixel signal of an analog signal based on photoelectric conversion; An AD conversion section that converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and A digital data holding section that holds data of the digital signal; and The pixel circuit includes: A photoelectric conversion section that generates charge from light by photoelectric conversion; A storage section that stores the aforementioned charge generated by the photoelectric conversion section; and A plurality of transfer transistors that control the transfer of the aforementioned charge from the photoelectric conversion section to the storage section. A solid-state imaging device as claimed in claim 1, wherein the AD conversion unit and the digital data retention unit are provided for each of the power storage units. A solid-state imaging device as claimed in claim 1, wherein the plurality of transmission transistors are connected in series with each other. A solid-state imaging device as claimed in claim 1, wherein the plurality of transmission transistors include a first transmission transistor and a second transmission transistor; and a charge-retaining memory is connected between the first transmission transistor and the second transmission transistor. A solid-state imaging device as claimed in claim 4, wherein the first transfer transistor controls the transfer of charge from the photoelectric conversion unit to the memory. A solid-state imaging device as claimed in claim 5, wherein the second transfer transistor controls the transfer of charge from the memory to the storage unit. A solid-state imaging device as claimed in claim 1, wherein the aforementioned pixel further includes a discharge transistor for discharging charge. A solid-state imaging device as claimed in claim 7, wherein the aforementioned discharge transistor is connected to the aforementioned photoelectric conversion unit. A solid-state imaging device, comprising a pixel array section formed by a plurality of pixels arranged in a two-dimensional array; and At least one of the plurality of pixels comprises: A pixel circuit, which generates a pixel signal of an analog signal based on photoelectric conversion; An AD conversion section, which converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and A digital data holding section, which holds the data of the digital signal; and The pixel circuit comprises: A first and a second photoelectric conversion section, which generate electric charge from light by photoelectric conversion; A storage section, which stores the aforementioned electric charge generated by the first and second photoelectric conversion sections; A plurality of transmission transistors of the first group, which control the transmission of the aforementioned electric charge from the first photoelectric conversion section to the storage section; and The second group of multiple transmission transistors controls the transmission of the aforementioned charge from the aforementioned second photoelectric conversion unit to the aforementioned power storage unit. A solid-state imaging device as claimed in claim 9, wherein the plurality of transmission transistors of the first group and the second group are connected in series with each other. A solid-state imaging device as claimed in claim 9, wherein the plurality of transmission transistors of the aforementioned first group and the plurality of transmission transistors of the aforementioned second group, the aforementioned transmission transistors constituting the aforementioned first group and the aforementioned second group respectively include the first and second transmission transistors; and a memory for retaining charge is connected between the aforementioned first and second transmission transistors. A solid-state imaging device as claimed in claim 11, wherein, with respect to the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group, each of the first transmission transistors controls the transfer of charge from the photoelectric conversion unit to the memory. A solid-state imaging device as claimed in claim 12, wherein, with respect to the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group, each of the second transmission transistors controls the transfer of charge from the memory to the power storage unit. A solid-state imaging device as claimed in claim 11, wherein the AD conversion unit and the digital data retention unit are provided for each of the power storage units. A solid-state imaging device as claimed in claim 11, wherein the aforementioned pixel further includes a first discharge transistor and a second discharge transistor for discharging charge. A solid-state imaging device as claimed in claim 15, wherein the first discharge transistor is connected to the first photoelectric conversion unit; and the second discharge transistor is connected to the second photoelectric conversion unit. A solid-state imaging device as claimed in claim 1, wherein the plurality of transmission transistors include a plurality of transmission transistors of the first group connected in series with each other, and a plurality of transmission transistors of the second group connected in series with each other; and the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group are connected in parallel with each other; the power storage unit is connected to the photoelectric conversion unit via the plurality of transmission transistors of the first group and the plurality of transmission transistors of the second group. A solid-state imaging device as claimed in claim 9, wherein the aforementioned pixel circuit further comprises: A plurality of transmission transistors of the third group, which control the transmission of the aforementioned charge from the aforementioned first photoelectric conversion unit to the aforementioned storage unit; and A plurality of transmission transistors of the fourth group, which control the transmission of the aforementioned charge from the aforementioned second photoelectric conversion unit to the aforementioned storage unit; and The plurality of transmission transistors of the aforementioned first group and the plurality of transmission transistors of the aforementioned third group are connected in parallel to each other; The plurality of transmission transistors of the aforementioned second group and the plurality of transmission transistors of the aforementioned fourth group are connected in parallel to each other. A solid-state imaging device, comprising a pixel array section formed by a plurality of pixels arranged in a two-dimensional array; and At least one of the plurality of pixels comprises: A pixel circuit, which generates a pixel signal of an analog signal based on photoelectric conversion; An AD conversion section, which converts the pixel signal into a digital signal based on a comparison between the pixel signal and a reference signal; and A digital data holding section, which holds the data of the digital signal; and The pixel circuit comprises: A photoelectric conversion section, which generates charge from light by photoelectric conversion; First and second storage sections, which store the aforementioned charge generated by the photoelectric conversion section; A plurality of transmission transistors of the first group, which control the transmission of the aforementioned charge from the photoelectric conversion section to the first storage section; and The plurality of transmission transistors of the second group control the transmission of the aforementioned charge from the aforementioned photoelectric conversion unit to the aforementioned second storage unit; The aforementioned first storage unit is connected to the aforementioned photoelectric conversion unit via the plurality of transmission transistors of the first group; The aforementioned second storage unit is connected to the aforementioned photoelectric conversion unit via the plurality of transmission transistors of the second group. A solid-state imaging device as claimed in claim 19, wherein the AD conversion unit and the digital data retention unit are respectively arranged in the first power storage unit and the second power storage unit.