TW202446201A - Semiconductor device and method of manufacturing the same and level shifter circuit - Google Patents

Abstract

A medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. Moreover, the medium voltage transistor may include an n-type lightly-doped source/drain (NLDD) region in which an N ⁺source/drain region of the medium voltage transistor is included. The light doping in the NLDD region enables a threshold voltage (V _t) to be reduced while enabling medium voltage operation at the N ⁺source/drain region. To reduce the amount of current leakage in the medium voltage transistor due to the light doping in the NLDD region, a buffer layer may be included over and/or on a portion of the NLDD region under a gate structure of the medium voltage transistor. The NLDD region and the thermal region of the medium voltage transistor enables the threshold voltage of the medium voltage transistor while maintaining the same current leakage performance or reducing current leakage in the medium voltage transistor.

Description

Transistor structure and formation method

A level shifter circuit is an electronic circuit configured to shift an electronic signal from a first voltage level to a second voltage level. Many electronic devices may include one or more level shifter circuits, such as static random-access memory (SRAM) devices, driver integrated circuits in a panel driver of a display device, and/or input/output (I/O) integrated circuits, among other circuits.

The following disclosure provides a number of different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may reuse reference numbers and/or letters in various examples. Such repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

The level shifter circuit may include multiple transistors, such as a combination of low voltage (LV) transistors and medium voltage (MV) transistors. The low voltage transistors are sometimes referred to as core (or thin-gate) transistors and are configured to receive a low voltage input signal to the level shifter circuit. The medium voltage transistors are sometimes referred to as I/O (or thick-gate) transistors and are configured to process a medium voltage output signal of the level shifter circuit.

The medium voltage transistor in the level shifter circuit may include a gate oxide layer (e.g., high temperature oxide (HTO) and/or other types of gate oxide) thick enough to support the medium voltage (e.g., 6V, 8V) to which the medium voltage transistor is subjected. However, if the gate oxide layer is too thick, the medium voltage transistor may not be able to operate at the low voltage (core _Vdd ) of the low voltage transistor due to the high threshold voltage ( _Vt ) required for electrons to tunnel through the gate oxide layer. Reducing the dopant concentration in the well implantation in which the channel of the medium voltage transistor is included may enable the threshold voltage to be reduced, but may increase the current leakage of the medium voltage transistor (which may reduce device performance).

In some embodiments described herein, a medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. In addition, the medium voltage transistor may include an n-type lightly-doped source/drain (NLDD) region including an N ⁺ source/drain region of the medium voltage transistor. Depending on the context, the source/drain region may refer to the source or drain individually or collectively. Light doping in the NLDD region enables a reduction in the threshold voltage (V _t ) while enabling medium voltage operation at the N ⁺ source/drain region. To reduce the amount and/or likelihood of current leakage in the medium voltage transistor due to light doping in the NLDD region, a buffer layer may be included below the gate structure of the medium voltage transistor, above a portion of the NLDD region and/or on a portion of the NLDD region.

In this way, the NLDD region and the hot region of the medium voltage transistor can reach the threshold voltage of the medium voltage transistor (e.g., relative to the medium voltage transistor that does not include the NLDD region and the hot region), while maintaining the same current leakage performance or reducing the current leakage in the medium voltage transistor (e.g., relative to the medium voltage transistor that does not include the NLDD region and the hot region). This can make it possible for the medium voltage transistor to operate at the low voltage (core V _dd ) of the low voltage transistor included in the level shifter circuit. In addition, this can make it possible to reduce the low voltage of the low voltage transistor included in the level shifter circuit, thereby reducing the power consumption of the level shifter circuit.

FIG. 1 is a diagram of an example environment 100 in which the systems and/or methods described herein may be implemented. As shown in FIG. 1 , the environment 100 may include a plurality of semiconductor processing tools 102-114 and a wafer/die transport tool 116. The plurality of semiconductor processing tools 102-114 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and/or other types of semiconductor processing tools. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and/or a manufacturing facility, among other facilities.

The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some implementations, the example environment 100 includes multiple types of deposition tools 102.

The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme UV (EUV) source, and/or the like), an x-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from the mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching portions of a semiconductor device, and/or the like. In some implementations, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

The developing tool 106 is a semiconductor processing tool capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed portion or the unexposed portion of the photoresist layer using a chemical developer.

The etch tool 108 is a semiconductor processing tool capable of etching various types of materials for a substrate, wafer, or semiconductor device. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, and/or the like. In some embodiments, the etch tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etch tool 108 may etch one or more portions of the substrate using plasma etching or plasma-assisted etching, which may involve isotropically or directional etching of the one or more portions using an ionized gas.

Planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and/or other types of planarization tools that grind or planarize layers or surfaces of deposited or coated materials. Planarization tool 110 may grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive grinding). Planarization tool 110 may utilize abrasive and corrosive chemical slurries in combination with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head can rotate using different rotation axes to remove material and smooth out any irregular topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and/or the like) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper plating apparatus, an aluminum plating apparatus, a nickel plating apparatus, a tin plating apparatus, a compound material or alloy (e.g., tin-silver, tin-lead, and/or the like), and/or a plating apparatus for one or more other types of conductive materials, metals, and/or similar types of materials.

The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material (e.g., a gas or a solid) in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate so that the ions are implanted below the surface of the substrate.

The wafer/die transport tool 116 may be included in a cluster tool or other type of tool including multiple processing chambers, and may be configured to transport substrates and/or semiconductor devices between the multiple processing chambers, transport substrates and/or semiconductor devices between the processing chambers and a buffer area, transport substrates and/or semiconductor devices between the processing chambers and an interface tool (e.g., an equipment front end module (EFEM)), and/or transport substrates and/or semiconductor devices between the processing chambers and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer/die transport tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and/or other types of contaminants or byproducts from substrates and/or semiconductor devices) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

In some implementations, one or more of the semiconductor processing tools 102-114 and/or the wafer/die transport tool 116 may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102 to 114 and/or the wafer/die transport tool 116 may perform the following operations: a first doping region of a semiconductor device may be formed on a substrate, wherein the first doping region includes a first dopant type; a second doping region of a semiconductor device may be formed in the first doping region, wherein the second doping region includes a second dopant type; a buffer layer of the semiconductor device may be formed on the second doping region; a gate oxide layer of the semiconductor device may be formed on the first doping region, on the second doping region, and on the buffer layer; and/or a gate structure of the semiconductor device may be formed on the gate oxide layer; and other operations. As another example, one or more of the semiconductor processing tools 102 to 114 and/or the wafer/die transport tool 116 may perform the following operations: a mask layer may be formed over the first doped region and over the second doped region; a pattern may be formed in the mask layer; and/or a buffer layer may be formed based on the pattern in the mask layer; and other operations. As another example, one or more of the semiconductor processing tools 102 to 114 and/or the wafer/die transport tool 116 may perform the following operations: a portion of the second doped region may be etched based on the pattern; and/or a buffer layer may be deposited in the area occupied by the portion of the second doped region; and other operations. As another example, one or more of the semiconductor processing tools 102 to 114 and/or the wafer/die transport tool 116 may perform one or more etching operations based on the gate structure to remove a first portion of the gate oxide layer and remove a first portion of the buffer layer, wherein a second portion of the gate oxide layer remains under the gate structure, and wherein a second portion of the buffer layer also remains under the gate structure, and other operations may be performed. As another example, one or more of the semiconductor processing tools 102-114 and/or the wafer/die transport tool 116 may perform an etching operation to remove the mask layer, wherein the etching operation causes the top surface of the buffer layer to be approximately coplanar with the top surface of the first doped region, and may perform other operations.

As another example, one or more of the semiconductor processing tools 102 to 114 and/or the wafer/die transport tool 116 may perform the following operations: a substrate may be doped with a first dopant type to form a first doped region of a semiconductor device; a substrate may be doped with a second dopant type to form a semiconductor device; A second doped region adjacent to the first doped region may be formed; a buffer layer of a semiconductor device may be formed on the second doped region; a gate oxide layer of the semiconductor device may be formed on the first doped region, on the second doped region and on the buffer layer; and/or a gate structure of the semiconductor device may be formed on the gate oxide layer; and other operations.

One or more of the semiconductor processing tools 102-114 and/or the wafer/die transport tool 116 may perform other semiconductor processing operations described herein as well as other operations, for example in conjunction with FIGS. 5A-5M and/or FIG. 10.

The number and arrangement of devices shown in FIG. 1 are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG. 1 . Furthermore, two or more devices shown in FIG. 1 may be implemented within a single device, or a single device shown in FIG. 1 may be implemented as multiple distributed devices. Additionally or alternatively, one set of devices (e.g., one or more devices) of the example environment 100 may implement one or more functions described as being implemented by another set of devices of the example environment 100.

2A and 2B are diagrams of exemplary embodiments of driver circuits described herein. The driver circuits may be included in a driver integrated circuit (IC) device. The driver IC device may be configured to be used with a display panel (e.g., a liquid crystal display (LCD) panel and/or other types of display panels).

2A illustrates an example implementation of a source driver circuit 200. The source driver circuit may be included in a driver IC device and may be configured to operate as a data signal driver for supplying a data signal (eg, an analog signal) to a display panel.

As shown in FIG. 2A , the source driver circuit may include a control circuit 202, a shift register circuit 204 coupled to the control circuit 202. The source driver circuit may include a sampling latch circuit 206 coupled to the shift register circuit 204. The source driver circuit may include a converter circuit 208 coupled to the sampling latch circuit 206. The source driver circuit may include a hold latch circuit 210 coupled to the sampling latch circuit 206. The source driver circuit may include a level shifter circuit 212 coupled to the hold latch circuit 210. The source driver circuit may include a digital to analog converter (DAC) circuit 214 coupled to the level shifter circuit 212. The source driver circuit may include a voltage reference circuit 216 coupled to the DAC circuit 214. The source driver circuit may include an output buffer circuit 218 coupled to the DAC circuit 214. An output 220 from the output buffer circuit 218 may be provided to a display panel and/or other circuits in the driver IC device.

The control circuit 202 may include one or more electrical components and/or one or more circuits configured to control the timing of the source driver circuit. The graphic data signal is transmitted from the control circuit 202 to the source driver circuit, where the graphic data signal is converted from a digital signal to an analog signal (e.g., output 220) and supplied to the display panel as a driving voltage.

The source driver circuit may include one or more low voltage circuits that process the graphic data signal, such as shift register circuit 204, sampling latch circuit 206, and/or holding latch circuit 210, among others. The source driver circuit may include one or more medium to high voltage circuits that are configured to convert the graphic data signal into an analog signal (e.g., output 220), such as level shifter circuit 212, DAC circuit 214, and/or output buffer circuit 218, among others.

The shift register circuit 204 and the converter circuit 208 may include one or more electrical components and/or one or more circuits configured to provide one or more columns of serialized graphics data signals to the sample latch circuit 206. The converter circuit 208 may include a serial to parallel converter circuit configured to separate the graphics data signal into separate parallelized graphics data signals (e.g., a red graphics data signal, a blue graphics data signal, and a green graphics data signal, as well as other graphics data signals).

Holding latch circuit 210 may include one or more electrical components and/or one or more circuits configured to receive one or more graphics data signals from sampling latch circuit 206 and provide the one or more graphics data signals to level shifter circuit 212 .

Level shifter circuit 212 may include one or more electrical components and/or one or more circuits configured to increase the voltage of a graphics data signal from a low voltage (e.g., approximately 0 volts to approximately 1 volt) to a medium voltage to a high voltage (e.g., approximately 6 volts to approximately 8 volts or greater than approximately 8 volts).

DAC circuit 214 may include one or more electrical components and/or one or more circuits configured to convert the graphics data signal from a digital signal to an analog signal (eg, output 220 ) based on a reference voltage provided by voltage reference circuit 216 .

The output buffer circuit 218 may include one or more electrical components and/or one or more circuits configured to store or buffer an analog signal (eg, output 220) and provide the analog signal to a display panel and/or other circuits in a driver IC device.

2B shows an example implementation of a gate driver circuit 230. The gate driver circuit may be included in a driver IC device and may be configured to operate a scan signal driver for supplying a scan signal to a display panel during a pixel selection period.

As shown in FIG2B , the gate driver circuit may include a control circuit 202, a shift register circuit 204, a level shifter circuit 212, a voltage reference circuit 216, and/or an output buffer circuit 218, among other circuits. These circuits may perform operations similar to those described above in conjunction with FIG2A to provide a scan signal (e.g., output 220) for a display panel during a pixel selection cycle.

As indicated above, Figures 2A and 2B are provided as examples. Other examples may differ from the examples described with respect to Figures 2A and 2B.

3A and 3B are diagrams of example embodiments of the level shifter circuit 212 described herein. One or more of the example embodiments of the level shifter circuit 212 shown and described in conjunction with FIG. 3A and/or FIG. 3B may be included in a driver circuit, such as the example embodiment 200 of a gate driver circuit, the example embodiment 230 of a source driver circuit, and/or other types of driver circuits.

FIG3A illustrates an example implementation 300 of the level shifter circuit 212. As shown in FIG3A, the level shifter circuit 212 may include a low voltage input 302 (e.g., approximately 0 volts to approximately 1 volt) and a medium to high voltage output 304 (e.g., approximately 6 volts to approximately 8 volts or greater than approximately 8 volts). The low voltage input 302 may be coupled to an inverter 306. The inverter 306 may be coupled to the gate of an n-type transistor 308a so that an inverted version of the low voltage input 302 is provided to the gate of the n-type transistor 308a. A non-inverted version of the low voltage input 302 is provided to the gate of the n-type transistor 308b. Therefore, n-type transistor 308a and n-type transistor 308b can be operated based on a low gate voltage of approximately 0 V to approximately 1 V. However, other values within the range of gate voltages of n-type transistor 308a and n-type transistor 308b are also within the scope of the present disclosure.

The n-type transistor 308a and the n-type transistor 308b may each be electrically coupled to an electrical ground 310. For example, the source/drain of each of the n-type transistor 308a and the n-type transistor 308b may each be electrically coupled to the electrical ground 310. The output (e.g., source/drain) of the n-type transistor 308b may be coupled to the gate of the p-type transistor 312b, and the output (e.g., source/drain) of the n-type transistor 308a may be coupled to the gate of the p-type transistor 312b. The gates of the p-type transistor 312a and the p-type transistor 312b may be inverted so that the signals provided to the gates of the p-type transistor 312a and the p-type transistor 312b are inverted.

A first source/drain of p-type transistor 312a may be coupled to a source/drain of n-type transistor 308a and to a gate of p-type transistor 312b. A second source/drain of p-type transistor 312a may be coupled to a medium to high voltage source 314 (e.g., approximately 6 volts to approximately 8 volts or greater than approximately 8 volts). A first source/drain of p-type transistor 312b may be coupled to a source/drain of n-type transistor 308b and to a gate of p-type transistor 312a. A second source/drain of p-type transistor 312b may be coupled to a medium to high voltage source 314.

In operation, a low voltage input 302 to the gate of n-type transistor 308a and the gate of n-type transistor 308b can selectively control the output from n-type transistor 308a and n-type transistor 308b. For example, the low voltage input 302 can selectively turn n-type transistor 308a and n-type transistor 308b "on" (forming a conductive path between the source/drain of n-type transistor 308a and/or n-type transistor 308b) or "off" (not forming a conductive path between the source/drain of n-type transistor 308a and/or n-type transistor 308b). This selectively causes the output from n-type transistor 308a to be low (e.g., tied to electrical ground 310) or high (floating and tied to medium to high voltage source 314), and similarly for n-type transistor 308b. The outputs from n-type transistors 308a and 308b selectively control p-type transistors 312a and 312b, which selectively control the medium to high voltage output 304 from level shifter circuit 212.

3B illustrates an exemplary implementation 320 of the level shifter circuit 212. As shown in FIG3B, the exemplary implementation 320 of the level shifter circuit 212 includes components 302-314 similar to the components 302-314 in the exemplary implementation 300 of the level shifter circuit 212 in FIG3A.

3B , an exemplary embodiment 320 of the level shifter circuit 212 further includes a voltage buffer input 322 coupled to the gate of the n-type transistor 308 a and the gate of the n-type transistor 308 b. Here, the voltage buffer input 322 may be used to selectively control (or buffer) the input to the gate of the p-type transistor 312 a and the gate of the p-type transistor 312 b.

The exemplary embodiment 320 of the level shifter circuit 212 further includes a low voltage n-type transistor 324a and a low voltage n-type transistor 324b configured to receive the low voltage input 302. A first source/drain of the low voltage n-type transistor 324a may be coupled to the electrical ground 310. Similarly, a first source/drain of the low voltage n-type transistor 324b may be coupled to the electrical ground 310. A second source/drain of the low voltage n-type transistor 324a may be coupled to the source/drain of the n-type transistor 308a. Similarly, the second source/drain of the low voltage n-type transistor 324b may be coupled to the source/drain of the n-type transistor 308b.

As indicated above, Figures 3A and 3B are provided as examples. Other examples may differ from the examples described with respect to Figures 3A and 3B.

4A and 4B are diagrams of an example semiconductor device 400 described herein. The semiconductor device 400 may include a transistor structure. Specifically, the semiconductor device 400 may include a medium voltage transistor structure (e.g., a transistor structure that operates based on a gate voltage (V _g ) included in a range of approximately 6 volts to approximately 8 volts), a high voltage transistor structure (e.g., a transistor structure that operates based on a gate voltage (V _g ) greater than approximately 8 volts), and/or other types of transistor structures. One or more of the n-type transistors 308 a, 308 b and/or one or more of the p-type transistors 312 a, 312 b may be implemented by the semiconductor device 400.

As shown in FIG. 4A , semiconductor device 400 may include substrate 402. Substrate 402 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium substrate (Ge), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates. Substrate 402 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 402 may include compound semiconductors and/or alloy semiconductors. Substrate 402 may include various doping configurations to meet one or more design parameters.

As further shown in FIG. 4A , the semiconductor device 400 may include a deep well 404 located above and/or on the substrate. The deep well 404 may include a deep n-well, a deep p-well, and/or other types of deep wells. A deep n-well may refer to a region of the semiconductor device 400 that includes a semiconductor material (e.g., silicon (Si) and/or other semiconductor materials) doped with one or more n-type dopants. Examples of n-type dopants include phosphorus (P), arsenic (As), and/or antimony (Sb), among other materials. A deep p-well may refer to a region of the semiconductor device 400 that includes a semiconductor material (e.g., silicon (Si) and/or other semiconductor materials) doped with one or more p-type dopants. Examples of p-type dopants include boron (B), gallium (Ga), and/or indium (In), among others.

4A , the semiconductor device 400 may include a p-well region 406 located above and/or on the deep well 404. The p-well region 406 may include a region of the semiconductor device 400 that includes a semiconductor material (e.g., silicon (Si) and/or other semiconductor materials) doped with one or more p-type dopants (e.g., boron (B), gallium (Ga) and/or indium (In) and other materials).

4A , the semiconductor device 400 may include an n-type lightly doped source/drain (NLDD) region 408 in the p-well region 406. The NLDD region 408 may include a region of the semiconductor device 400 that includes a semiconductor material (e.g., silicon (Si) and/or other semiconductor materials) lightly doped with one or more n-type dopants (e.g., phosphorus (P), arsenic (As), and/or antimony (Sb), among other materials). For example, NLDD region 408 may be “lightly doped” in that NLDD region 408 may include a dopant concentration in a range of approximately 1E ¹¹ n-type ions per square centimeter (1E ¹¹ n-type ions/cm ² ) to approximately 5E ¹³ n-type ions per square centimeter. Light doping in NLDD region 408 enables a reduced threshold voltage (V _t ) of semiconductor device 400 while enabling medium to high voltage operation at one or more source/drain regions of semiconductor device 400.

To reduce the amount and/or likelihood of current leakage in the semiconductor device 400 due to light doping in the NLDD region 408, a buffer layer 410 may be included over and/or on a portion of the NLDD region 408. The buffer layer 410 may reduce the amount and/or likelihood of current leakage in the semiconductor device 400 by suppressing subthreshold leakage in the semiconductor device 400, which is current leakage that occurs when the semiconductor device 400 operates at a gate voltage (V _G ) that is less than a threshold voltage (V _t or V _th ) of the semiconductor device 400. The buffer layer 410 may include: oxide materials such as silicon oxide (SiO _x , such as SiO ₂ ) and/ _{or other oxide materials; oxide-nitride materials such as silicon oxynitride (SiON); nitride materials such as silicon nitride (SixNy ,} such as Si ₃ N ₄ ); and/or other types of dielectric materials.

The semiconductor device 400 may include a source/drain region 412 and a source/drain region 414. The source/drain region 412 and the source/drain region 414 may each include silicon (Si) with one or more dopants such as: p-type material (e.g., boron (B) or germanium (Ge) and other p-type materials), n-type material (e.g., phosphorus (P) or arsenic (As) and other n-type materials), and/or other types of dopants. The source/drain region 412 may be included in the p-well region 406. The source/drain region 414 may be included in the NLDD region 408 and adjacent to the buffer layer 410.

In some embodiments, source/drain region 412 corresponds to a source region of semiconductor device 400, and source/drain region 414 corresponds to a drain region of semiconductor device 400. In these embodiments, source/drain region 414 can be configured to operate at a medium to high voltage (e.g., up to approximately 6 volts, approximately 8 volts, and/or greater than approximately 8 volts). Thus, source/drain region 414 is configured to operate at a relatively large operating voltage relative to an operating voltage of a gate structure of semiconductor device 400. In some embodiments, source/drain region 412 corresponds to a drain region of semiconductor device 400, and source/drain region 414 corresponds to a source region of semiconductor device 400. In some embodiments, source/drain region 412 corresponds to a source region of semiconductor device 400 and a source region or a drain region of another semiconductor device. In some embodiments, source/drain region 414 corresponds to a drain region of semiconductor device 400 and a source region or a drain region of another semiconductor device.

The dopant concentration in the source/drain region 412 and the source/drain region 414 may be greater than the dopant concentration in the NLDD region 408 . For example, NLDD region 408 may be “lightly doped” in that NLDD region 408 may include a dopant concentration in a range of approximately 1E ¹¹ n-type ions per square centimeter to approximately 5E ¹³ n-type ions per square centimeter, while source/drain region 412 and source/drain region 414 may each include a dopant concentration in a range of approximately 1E ¹⁴ n-type ions per square centimeter to approximately 1E ¹⁶ n-type ions per square centimeter.

The NLDD region 408 may include a dopant concentration in a range of approximately 1E ¹¹ n-type ions per square centimeter to approximately 5E ¹³ n-type ions per square centimeter to achieve a sufficiently high on-mode current of the semiconductor device 400 and/or a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

Source/drain regions 412 and source/drain regions 414 may each include a dopant concentration in a range of approximately 1E ¹⁴ n-type ions per square centimeter to approximately 1E ¹⁶ n-type ions per square centimeter to achieve a sufficiently high on-mode current of semiconductor device 400 and/or a sufficiently low off-mode current leakage of semiconductor device 400. However, other values within these ranges are also within the scope of the present disclosure.

In some embodiments, the dopant concentration in the p-well region 406 may be in a range of approximately 1E ¹¹ p-type ions per square centimeter to approximately 5E ¹³ p-type ions per square centimeter. However, other values within the range are also within the scope of the present disclosure.

The semiconductor device 400 may include a gate structure 416 between the source/drain region 412 and the source/drain region 414. The gate structure 416 may be formed of one or more layers and/or one or more materials. The gate structure 416 may include one or more metal materials, one or more high dielectric constant (high-k) materials, and/or one or more other types of materials. For example, the gate structure 416 may include a work function tuning layer, an interface layer, and/or a metal electrode layer, among other layers.

The semiconductor device 400 may include a gate oxide layer 418. The gate oxide layer 418 may include an oxide material (e.g., HTO and/or other types of gate oxides) and/or other types of dielectric materials. The gate oxide layer 418 may have a sufficient thickness to support the medium to high voltages (e.g., 6 volts, 8 volts, and/or greater) to which the semiconductor device 400 is subject. For example, the thickness of the gate oxide layer 418 may be included in a range of approximately 150 angstroms to approximately 300 angstroms to support the medium to high voltages to which the semiconductor device 400 is subject. However, other values within the range are also within the scope of the present disclosure.

The semiconductor device 400 may include a gate oxide layer 418 located below the gate structure 416. The gate oxide layer 418 may be located between the source/drain region 412 and the source/drain region 414. In addition, the gate oxide layer 418 may be located on and/or on (and may contact) a portion of the p-well region 406 located between the source/drain region 412 and the NLDD region 408. In addition, the gate oxide layer 418 may be located on and/or on (and may contact) the buffer layer 410. In addition, gate oxide layer 418 may be located above and/or on (and may contact) extension region 420 of NLDD region 408. Extension region 420 may include a portion of NLDD region 408 that extends along a sidewall of buffer layer 410 and an opposite sidewall of p-well region 406 and contacts gate oxide layer 418.

One or more spacer layers 422 may be included on and/or on the sidewalls of the gate structure 416. The one or more spacer layers 422 may include one or more low dielectric constant (low-k) materials having a dielectric constant smaller than _that of silicon oxide (e.g., less than approximately 3.9), silicon oxide ( _SiOx ), silicon oxynitride (SiON), silicon nitride ( _SixNy ), silicon oxycarbon nitride (SiOCN), and/or other suitable dielectric materials.

A contact structure 424 (e.g., a source/drain contact or MD) may be included above and/or on the source/drain region 412. A contact structure 426 (e.g., a source/drain contact or MD) may be included above and/or on the source/drain region 414. The contact structure 424 and the contact structure 426 may each include a via, an interconnect, a trench, a contact plug, and/or other types of conductive structures. The contact structure 424 and the contact structure 426 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), as well as other examples of conductive materials.

The contact structure 424 and the contact structure 426 may be included in an interlayer dielectric (ILD) layer 428. The ILD layer 428 may be included over the source/drain regions 412 and the source/drain regions 414 of the semiconductor device 400 and/or over the gate structure 416. The ILD layer 428 may be included to provide electrical isolation and/or insulation between the gate structure 416 and/or the source/drain regions 412 and the source/drain regions 414 of the semiconductor device 400, among other examples. The ILD layer 428 may include silicon nitride (SiN _x ), oxide (eg, silicon oxide (SiO _x ) and/or other oxide materials), and/or other types of dielectric materials.

The dopant types for the various regions and/or layers shown and described in conjunction with FIG4A are merely examples, and the semiconductor device 400 may include other configurations of dopant types for the various regions and/or layers. For example, the p-well region 406 may alternatively include an n-well region, the NLDD region 408 may alternatively include a p-well lightly doped source/drain region, and/or the source/drain region 412 and the source/drain region 414 may include p-type doped source/drain regions.

In general, the semiconductor device 400 may include a first doped region (e.g., p-well region 406) including a first dopant type. The semiconductor device 400 may include a second doped region (e.g., NLDD region 408) located in the first doped region, the second doped region being lightly doped and including the second dopant type. The semiconductor device 400 may include a third doped region (e.g., source/drain region 412) located in the first doped region, the third doped region including the second dopant type, wherein the third doped region corresponds to the first source/drain region of the semiconductor device 400. The semiconductor device 400 may include a fourth doped region (e.g., source/drain region 414) in the second doped region, the fourth doped region including the second dopant type, wherein the fourth doped region corresponds to the second source/drain region of the semiconductor device 400. The semiconductor device 400 may include a buffer layer 410 located on a portion of the second doped region. The semiconductor device 400 may include a gate oxide layer 418 located on a portion of the first doped region, on the buffer layer 410, and on an extension region 420 of the second doped region. The semiconductor device 400 may include a gate structure 416 located on the gate oxide layer 418.

4B illustrates one or more example dimensions of semiconductor device 400. As shown in FIG4B, semiconductor device 400 may include example dimension D1, example dimension D2, example dimension D3, and/or example dimension D4, among other example dimensions.

An example dimension D1 may correspond to the length of the p-well region 406 between the source/drain region 412 and the NLDD region 408. In some embodiments, the length of the p-well region 406 may be the length of the portion of the p-well region 406 that is located below the gate oxide layer 418. In some embodiments, the dimension D1 may be included in a range of approximately 0.2 microns to approximately 2 microns to achieve a sufficiently high on-mode current of the semiconductor device 400 and/or to achieve a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

An example dimension D2 may correspond to a length of an extension region 420 of the NLDD region 408 between the p-well region 406 and the buffer layer 410. In some embodiments, the dimension D2 may be included in a range of approximately 0.05 microns to approximately 1 micron to achieve a sufficiently high on-mode current of the semiconductor device 400 and/or to achieve a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

An example dimension D3 may correspond to the length of the buffer layer 410 between the source/drain region 414 and the NLDD region 408. In some implementations, the dimension D3 may be included in a range of approximately 0.1 microns to approximately 5 microns to achieve a sufficiently high on-mode current of the semiconductor device 400, and/or to achieve a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

An example dimension D4 may correspond to the thickness of the buffer layer 410. In some embodiments, the dimension D4 may be included in a range of approximately 10 nanometers to approximately 100 nanometers to achieve a sufficiently high gate-to-drain breakdown voltage of the semiconductor device 400 and/or a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

As indicated above, Figures 4A and 4B are provided as examples. Other examples may differ from the examples described with respect to Figures 4A and 4B.

5A-5M are diagrams of an example embodiment 500 described herein. The example embodiment 500 includes an example of forming a semiconductor device 400 described herein. In some embodiments, one or more of the semiconductor processing operations described in conjunction with the example embodiment 500 may be performed by one or more of the semiconductor processing tools 102-114 and/or by the wafer/die transport tool 116. In some embodiments, one or more of the semiconductor processing operations described in conjunction with the example embodiment 500 may be performed by other semiconductor processing tools.

Turning to FIG. 5A , a substrate 402 may be provided. The substrate 402 may be provided as a semiconductor wafer, a semiconductor die, and/or other types of semiconductor substrates. In some embodiments, the substrate 402 may be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and/or other types of doped substrates. In some embodiments, the substrate 402 has a bulk resistivity (or volumetric resistivity) included in a range of approximately 1 ohm-centimeter to approximately 100 ohm-centimeter. However, other values within the range are also within the scope of the present disclosure.

5A , one or more layers and/or regions may be formed in, above, and/or on substrate 402. For example, deep well 404 may be formed in and/or on substrate 402. As another example, p-well region 406 may be formed in substrate 402 and/or on deep well 404.

In some embodiments, the ion implantation tool 114 forms the deep well 404 by performing an ion implantation operation to implant ions (e.g., p-type ions, n-type ions) into the substrate 402 to form the deep well 404. The ion implantation tool 114 may direct an ion beam toward the substrate 402 so that the ions are implanted below the surface of the substrate 402 to dope the substrate 402. Additionally and/or alternatively, the deposition tool 102 may deposit the deep well 404 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, other types of deposition operations described in conjunction with FIG. 1 , and/or other suitable deposition operations. In some implementations, after the deposition tool 102 deposits the deep well 404 , the planarization tool 110 planarizes the deep well 404 .

In some embodiments, the ion implantation tool 114 forms the p-well region 406 by performing an ion implantation operation to implant ions (e.g., p-type ions, n-type ions) into the substrate 402 to form the p-well region 406. The ion implantation tool 114 may direct an ion beam toward the substrate 402 so that the ions are implanted below the surface of the substrate 402 to dope the substrate 402. Additionally and/or alternatively, the deposition tool 102 may deposit the p-well region 406 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, other types of deposition operations described in conjunction with FIG. 1 , and/or other suitable deposition operations. In some embodiments, after the deposition tool 102 deposits the p-well region 406, the planarization tool 110 planarizes the p-well region 406. In some embodiments, the p-well region 406 can be formed such that the dopant concentration in the p-well region 406 can be included in a range of approximately 1E ¹¹ p-type ions per square centimeter to approximately 5E ¹³ p-type ions per square centimeter. However, other values within the range are also within the scope of the present disclosure.

5B , the NLDD region 408 may be formed in a portion of the p-well region 406. In some embodiments, an implantation mask is used to shield another portion of the p-well region 406 so that the NLDD region 408 is formed only in a portion of the p-well region 406. In some embodiments, the ion implantation tool 114 forms the NLDD region 408 by implanting ions (e.g., p-type ions, n-type ions) into the substrate 402 by performing an ion implantation operation to form the NLDD region 408 in the p-well region 406. The ion implantation tool 114 may direct an ion beam toward the p-well region 406 so that the ions are implanted in the p-well region 406 to form the NLDD region 408. The NLDD region 408 may be formed to include a dopant concentration in a range of approximately 1E ¹¹ n-type ions per square centimeter to approximately 5E ¹³ n-type ions per square centimeter to achieve a sufficiently high on-mode current of the semiconductor device 400 and/or to achieve a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

As shown in FIG5C , a mask layer 502 may be formed on the top surface of the p-well region 406 and/or on the top surface of the p-well region 406 and/or on the top surface of the NLDD region 408 and/or on the top surface of the NLDD region 408. In some embodiments, the mask layer 502 includes a hard mask formed of, for example, the following dielectric materials: oxide materials, such as silicon oxide (SiO _x , such as SiO ₂ ) and/or other oxide materials; oxide-nitride materials, such as silicon oxynitride (SiON); nitride materials, such as silicon nitride (Si _x N _y , such as Si ₃ N ₄ ); and/or other types of dielectric materials. In some embodiments, the mask layer 502 includes a photoresist layer. The deposition tool 102 may deposit the mask layer 502 in a PVD operation, an ALD operation, a CVD operation, a spin coating operation, an epitaxy operation, an oxidation operation, other types of deposition operations described in connection with FIG. 1 , and/or other suitable deposition operations. In some embodiments, after the deposition tool 102 deposits the mask layer 502, the planarization tool 110 planarizes the mask layer 502.

5D , a first portion of the mask layer 502 may be removed. A second portion of the mask layer 502 remains on the semiconductor device 400 and corresponds to the pattern in the mask layer 502. A portion 504 of the NLDD region 408 is exposed through the pattern in the mask layer 502. The second portion of the mask layer 502 may remain on the top surface of the p-well region 406 and on the top surface of the portion 506 of the NLDD region 408. The width of the portion 506 may correspond to the width of the extension region 420 of the NLDD region 408 (e.g., dimension D2).

In some embodiments, the mask layer 502 is etched using the pattern in the photoresist layer to form a pattern in the mask layer 502. In these embodiments, the deposition tool 102 forms a photoresist layer on the mask layer 502. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops some portions of the photoresist layer and removes some portions of the photoresist layer to expose the pattern. The etching tool 108 etches the mask layer 502 based on the pattern to form a pattern in the mask layer 502. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or other types of etching operations. In some implementations, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or other techniques). In some implementations, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or other techniques).

5E , a buffer layer 410 may be formed over and/or on the NLDD region 408. The buffer layer 410 may be formed over and/or on the portion 504 of the NLDD region 408 that is exposed by the pattern in the buffer layer 410. The deposition tool 102 may deposit the buffer layer 410 in a PVD operation, an ALD operation, a CVD operation, a spin coating operation, an epitaxial operation, an oxidation operation, other types of deposition operations described in connection with FIG. 1 , and/or other suitable deposition operations. In some embodiments, deposition tool 102 forms buffer layer 410 using a thermal oxidation technique in which deposition tool 102 provides an oxygen-containing reactant to the top surface of NLDD region 408. The oxygen-containing reactant may react with silicon in NLDD region 408 at a high temperature, which oxidizes the silicon to grow silicon oxide (SiO _x , such as SiO ₂ ) on NLDD region 408.

In some implementations, before forming the buffer layer 410, the etching tool 108 may etch the NLDD region 408 based on the pattern in the mask layer 502 to remove material from the NLDD region 408. After etching the NLDD region 408, the buffer layer 410 may then be formed on the NLDD region 408. Alternatively, the buffer layer 410 may be formed in and/or on the NLDD region 408 (e.g., by thermal oxidation) without etching the NLDD region 408.

5F , after forming the buffer layer 410, the mask layer 502 may be removed from the semiconductor device 400. In some embodiments, the planarization tool 110 planarizes the mask layer 502 to remove the mask layer 502. Here, the planarization tool 110 may planarize the mask layer 502 and may planarize the buffer layer 410 to remove excess material from the buffer layer 410 until the top surface of the p-well region 406, the top surface of the extension region 420 of the NLDD region 408, and the top surface of the buffer layer 410 are approximately coplanar.

Additionally and/or alternatively, the etching tool 108 can remove the mask layer 502 by etching the mask layer 502 in an etching operation. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or other types of etching operations.

5G , a gate oxide layer 418 may be formed on and/or on the top surface of the p-well region 406, on and/or on the top surface of the extension region 420 of the NLDD region 408, and/or on and/or on the top surface of the buffer layer 410. The deposition tool 102 may deposit the gate oxide layer 418 in a PVD operation, an ALD operation, a CVD operation, a spin coating operation, an epitaxial operation, an oxidation operation (e.g., a high temperature thermal oxidation operation), other types of deposition operations described in conjunction with FIG. 1 , and/or other suitable deposition operations. In some implementations, after the deposition tool 102 deposits the gate oxide layer 418 , the planarization tool 110 planarizes the gate oxide layer 418 .

5H , the gate structure 416 and the spacer layer 422 may be formed on and/or on the gate oxide layer 418. The deposition tool 102 and/or the plating tool 112 may deposit the gate structure 416 in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, other deposition operations described above in connection with FIG. 1 , and/or other suitable deposition operations. In some embodiments, a seed layer is deposited first, and the gate structure 416 is deposited on the seed layer.

The deposition tool 102 may deposit the spacer layer 422 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, other types of deposition operations described in connection with FIG. 1 , and/or other suitable deposition operations. In some embodiments, the deposition tool 102 conformally deposits the material of the spacer layer 422 on the sidewalls and top surface of the gate structure 416 and on the top surface of the gate oxide layer 418. The etching tool 108 may then perform an etch-back operation to remove the material of the spacer layer 422 from the top surface of the gate oxide layer 418 and the top surface of the gate structure 416. Therefore, the spacer layer 422 may remain on the sidewalls of the gate structure 416.

5I , some portions of the gate oxide layer 418 that are not under and/or covered by the gate structure 416 and the spacer layer 422 may be removed, and some portions of the buffer layer 410 that are not under and/or covered by the gate structure 416 and the spacer layer 422 may be removed. The etching tool 108 may perform an etching operation to remove the portions of the gate oxide layer 418 and the portions of the buffer layer 410 so that the gate oxide layer 418 and the buffer layer 410 remain only under the gate structure 416 and the spacer layer 422. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or other types of etching operations. As shown in the example of FIG. 5I , the etching operation rounds the outer sidewalls of the spacer layer 422.

5J , source/drain regions 412 may be formed in the p-well region 406 at a first side of the gate structure 416. Source/drain regions 414 may be formed in the NLDD region 408 at a second side of the gate structure 416 opposite to the first side. In some embodiments, the ion implantation tool 114 forms the source/drain regions 412 by implanting ions (e.g., p-type ions, n-type ions) into the p-well region 406 by performing an ion implantation operation to form the source/drain regions 412 in the p-well region 406. The ion implantation tool 114 may direct an ion beam toward the p-well region 406 so that ions are implanted into the p-well region 406 to form source/drain regions 412. In some embodiments, the ion implantation tool 114 forms the source/drain regions 414 by performing an ion implantation operation to implant ions (e.g., p-type ions, n-type ions) into the NLDD region 408 to form the source/drain regions 414 in the NLDD region 408. The ion implantation tool 114 may direct an ion beam toward the NLDD region 408 so that ions are implanted into the NLDD region 408 to form the source/drain regions 414.

Source/drain regions 412 and source/drain regions 414 may each be formed to include a dopant concentration in a range of approximately 1E ¹⁴ n-type ions per square centimeter to approximately 1E ¹⁶ n-type ions per square centimeter to achieve a sufficiently high on-mode current of semiconductor device 400 and/or to achieve a sufficiently low off-mode current leakage of semiconductor device 400. However, other values within these ranges are also within the scope of the present disclosure.

5K , an ILD layer 428 may be formed over and/or on the source/drain regions 412 and 414, over and/or on the spacer layer 422, and/or over and/or on the gate structure 416, etc. The deposition tool 102 may deposit the ILD layer 428 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, other types of deposition operations described in conjunction with FIG. 1 , and/or other suitable deposition operations. In some implementations, after the deposition tool 102 deposits the ILD layer 428 , the planarization tool 110 planarizes the ILD layer 428 .

5L , a recess 508 may be formed in the ILD layer 428 and/or through the ILD layer 428 to reach the top surface of the source/drain region 412. The top surface of the source/drain region 412 is exposed through the recess 508. Alternatively, in an embodiment in which one or more silicide layers (e.g., metal silicide layers, such as titanium silicide layers) are included on the source/drain region 412 to reduce the contact resistance of the source/drain region 412, the recess 508 may be formed to the one or more silicide layers such that the one or more silicide layers are exposed through the recess 508.

In some embodiments, the ILD layer 428 is etched using the pattern in the photoresist layer to form the recess 508. In these embodiments, the deposition tool 102 forms the photoresist layer on the ILD layer 428. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops some portions of the photoresist layer and removes some portions of the photoresist layer to expose the pattern. The etching tool 108 etches the ILD layer 428 based on the pattern to form the recess 508 in the ILD layer 428. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or other types of etching operations. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and/or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the ILD layer 428. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and/or other techniques).

5L , a recess 510 may be formed in the ILD layer 428 and/or through the ILD layer 428 to reach the top surface of the source/drain region 414. The top surface of the source/drain region 414 is exposed through the recess 510. Alternatively, in an embodiment in which one or more silicide layers (e.g., metal silicide layers, such as titanium silicide layers) are included on the source/drain region 414 to reduce the contact resistance of the source/drain region 414, the recess 510 may be formed to the one or more silicide layers such that the one or more silicide layers are exposed through the recess 510.

In some embodiments, the ILD layer 428 is etched using the pattern in the photoresist layer to form the recess 510. In these embodiments, the deposition tool 102 forms the photoresist layer on the ILD layer 428. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops some portions of the photoresist layer and removes some portions of the photoresist layer to expose the pattern. The etching tool 108 etches the ILD layer 428 based on the pattern to form the recess 510 in the ILD layer 428. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and/or other types of etching operations. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and/or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the ILD layer 428. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and/or other techniques).

5M, a contact structure 424 may be formed in the recess 508 such that the contact structure 424 lands on the source/drain region 412 (or on the one or more silicide layers included on the source/drain region 412). A contact structure 426 may be formed in the recess 510 such that the contact structure 426 lands on the source/drain region 414 (or on the one or more silicide layers included on the source/drain region 414).

The deposition tool 102 and/or the coating tool 112 may deposit the contact structure 424 and/or the contact structure 426 in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, other deposition operations described above in conjunction with FIG. 1 , and/or other suitable deposition operations. In some embodiments, a seed layer is deposited first, and the contact structure 424 and/or the contact structure 426 is deposited on the seed layer. In some embodiments, after the deposition tool 102 and/or the coating tool 112 deposits the contact structure 424 and/or the contact structure 426, the planarization tool 110 planarizes the contact structure 424 and/or the contact structure 426.

As indicated above, Figures 5A to 5M are provided as examples. Other examples may differ from the examples described with respect to Figures 5A to 5M.

FIG. 6 is a diagram of an example implementation 600 of a doping profile of a portion of a semiconductor device 400 described herein.

In some embodiments, the p-well region 406 may include a p-type doping profile, and the NLDD region 408 and the source/drain regions 412 and 414 may include an n-type doping profile. Alternatively, the p-well region 406 may be an n-well region including an n-type doping profile, and the NLDD region 408 and the source/drain regions 412 and 414 may include a p-type doping profile. The buffer layer 410 may include an undoped oxide material such as a high temperature oxide (HTO).

The dopant concentration in the source/drain region 412 and the source/drain region 414 may be greater than the dopant concentration in the NLDD region 408 . For example, NLDD region 408 may be “lightly doped” in that NLDD region 408 may include a dopant concentration in a range of approximately 1E ¹¹ n-type ions per square centimeter to approximately 5E ¹³ n-type ions per square centimeter, while source/drain region 412 and source/drain region 414 may each include a dopant concentration in a range of approximately 1E ¹⁴ n-type ions per square centimeter to approximately 1E ¹⁶ n-type ions per square centimeter.

The NLDD region 408 may include a dopant concentration in a range of approximately 1E ¹¹ n-type ions per square centimeter to approximately 5E ¹³ n-type ions per square centimeter to achieve a sufficiently high on-mode current of the semiconductor device 400 and/or a sufficiently low off-mode current leakage of the semiconductor device 400. However, other values within the range are also within the scope of the present disclosure.

Source/drain regions 412 and source/drain regions 414 may each include a dopant concentration in a range of approximately 1E ¹⁴ n-type ions per square centimeter to approximately 1E ¹⁶ n-type ions per square centimeter to achieve a sufficiently high on-mode current of semiconductor device 400 and/or a sufficiently low off-mode current leakage of semiconductor device 400. However, other values within these ranges are also within the scope of the present disclosure.

In some embodiments, the dopant concentration in the p-well region 406 may be in a range of approximately 1E ¹¹ p-type ions per square centimeter to approximately 5E ¹³ p-type ions per square centimeter. However, other values within the range are also within the scope of the present disclosure.

As indicated above, FIG. 6 is provided as an example. Other examples may differ from the example described with respect to FIG. 6.

7 is a diagram of an example embodiment 700 of a current profile of a semiconductor device 400 described herein. Current in the semiconductor device 400 may generally flow between the source/drain region 412 and the source/drain region 414 and under the gate structure 416. The current may flow through a portion of the p-well region 406 and the NLDD region 408. In some embodiments, the drain saturation current (I _d,sat ) of the semiconductor device 400 may be approximately 4 times greater than the drain saturation current of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410. For example, the drain saturation current of the semiconductor device 400 may be approximately 44 microamps per micron (44 microamps/micron), while the drain saturation current of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410 may be approximately 11.1 microamps per micron. However, other values are also within the scope of the present disclosure. In some embodiments, the off-state breakdown voltage (BV _off ) of the semiconductor device 400 may be greater than the off-state breakdown voltage of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410. For example, the off-state breakdown voltage of the semiconductor device 400 may be approximately 12.5 V, while the off-state breakdown voltage of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410 may be approximately 10.8 V. However, other values are also within the scope of the present disclosure.

As indicated above, FIG. 7 is provided as an example. Other examples may differ from the example described with respect to FIG. 7.

FIG8 is a diagram of an exemplary embodiment 800 of off current distribution profiles of multiple semiconductor devices. FIG8 shows the off current distribution profile as a function of an off current (I _off ) 802 (in picoamps per micrometer) and a voltage threshold saturation voltage (V _t,sat ) 804 (in volts). The off current distribution profile includes an off current distribution profile 806 of the semiconductor device 400 described herein, and an off current distribution profile 808 of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410 included in the semiconductor device 400.

The off current 802 may correspond to the amount of current flowing through the channel of the semiconductor device 400 when the semiconductor device 400 is “off” (e.g., when the channel is in a non-conductive configuration), and may be similar for other semiconductor devices that do not include the NLDD region 408 and the buffer layer 410. The voltage threshold saturation voltage 804 may correspond to the gate voltage (V _G ) at which the channel of the semiconductor device 400 begins to saturate when the semiconductor device 400 is “on,” and may be similar for another semiconductor device that does not include the NLDD region 408 and the buffer layer 410. Semiconductor device 400 may be configured to operate based on a gate voltage of approximately 0.7 volts, while another semiconductor device that does not include NLDD region 408 and buffer layer 410 may be configured to operate based on a gate voltage of approximately 0.9 volts. However, other values are also within the scope of the present disclosure.

8 , the turn-off current 802 in the turn-off current distribution profile 806 and the turn-off current distribution profile 808 is generally larger at a higher operating temperature and smaller at a lower operating temperature. In addition, the voltage threshold saturation voltage 804 in the turn-off current distribution profile 806 and the turn-off current distribution profile 808 is generally larger at a lower operating temperature and smaller at a higher operating temperature.

As further shown in FIG. 8 , the NLDD region 408 and the buffer layer 410 included in the semiconductor device 400 enable the semiconductor device 400 to operate using a lower voltage threshold saturation voltage 804 than another semiconductor device that does not include the NLDD region 408 and the buffer layer 410, and enable the semiconductor device 400 to achieve a turn-off current 802 that is approximately the same as or smaller than another semiconductor device that does not include the NLDD region 408 and the buffer layer 410.

In some embodiments, the voltage threshold saturation voltage 804 of the semiconductor device 400 may be as low as approximately 0.37 volts or less, while the voltage threshold saturation voltage 804 of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410 may be approximately 0.445 volts. However, other values are also within the scope of the present disclosure. In some embodiments, the turn-off current 802 of the semiconductor device 400 may be as low as approximately 2 picoamps per micron or less, while the turn-off current 802 of another semiconductor device that does not include the NLDD region 408 and the buffer layer 410 may be approximately 6.3 picoamps per micron. However, other values are also within the scope of the present disclosure.

As indicated above, FIG8 is provided as an example. Other examples may differ from the example described with respect to FIG8.

FIG9 is a diagram of example components of an apparatus 900 as described herein. In some implementations, one or more of the semiconductor processing tools 102-114 and/or the wafer/die transport tool 116 may include one or more apparatuses 900 and/or one or more components of the apparatus 900. As shown in FIG9 , the apparatus 900 may include a bus 910, a processor 920, a memory 930, an input component 940, an output component 950, and/or a communication component 960.

The bus 910 may include one or more components that enable wired and/or wireless communication between components of the device 900. The bus 910 may couple two or more components shown in Figure 9 together (e.g., via operational coupling, communication coupling, electronic coupling, and/or electrical coupling). For example, the bus 910 may include electrical connectors (e.g., wiring, traces, and/or leads) and/or wireless buses. The processor 920 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and/or other types of processing components. The processor 920 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 920 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

The memory 930 may include volatile memory and/or non-volatile memory. For example, the memory 930 may include random access memory (RAM), read only memory (ROM), a hard drive, and/or other types of memory (e.g., flash memory, magnetic memory, and/or optical memory). The memory 930 may include internal memory (e.g., RAM, ROM, or a hard drive) and/or removable memory (e.g., removable via a universal serial bus connection). The memory 930 may be a non-transitory computer-readable medium. The memory 930 may store information related to the operation of the device 900, one or more instructions, and/or software (e.g., one or more software applications). In some implementations, the memory 930 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 920), for example, via the bus 910. The communicative coupling between the processor 920 and the memory 930 may enable the processor 920 to read and/or process information stored in the memory 930 and/or store information in the memory 930.

Input components 940 may enable device 900 to receive input, such as user input and/or sensed input. For example, input components 940 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a GPS sensor, a GPS sensor, an accelerometer, a gyroscope, and/or an actuator. Output components 950 may enable device 900 to provide output, such as via a display, a speaker, and/or a light-emitting diode. Communication components 960 may enable device 900 to communicate with other devices via a wired connection and/or a wireless connection. For example, communication component 960 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

The device 900 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 930) may store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 920. The processor 920 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, the set of instructions is executed by one or more processors 920 so that the one or more processors 920 and/or the device 900 perform one or more operations or processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 920 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown in FIG. 9 are provided as examples. Device 900 may include additional components, fewer components, different components, or differently arranged components than those shown in FIG. 9 . Additionally or alternatively, a set of components (e.g., one or more components) of device 900 may implement one or more functions described as being implemented by another set of components of device 900.

FIG. 10 is a flow chart of an exemplary process 1000 associated with forming the transistor structures described herein. In some implementations, one or more process blocks of FIG. 10 are performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-116). Additionally or alternatively, one or more process blocks shown in FIG. 10 may be performed by one or more components of device 900 (e.g., processor 920, memory 930, input component 940, output component 950, and/or communication component 960).

10 , process 1000 may include doping a substrate with a first dopant type to form a first doped region of a semiconductor device (block 1010). For example, as described herein, one or more of semiconductor processing tools 102-116 may dope substrate 402 with a first dopant type to form a first doped region (e.g., p-well region 406) of semiconductor device 400. In some embodiments, the first doped region includes the first dopant type (e.g., a p-type dopant).

10 , the process 1000 may include doping the substrate with a second dopant type to form a second doped region of the semiconductor device adjacent to the first doped region (block 1020). For example, as described herein, one or more of the semiconductor processing tools 102 to 116 may dope the substrate 402 with a second dopant type to form a second doped region (e.g., NLDD region 408) adjacent to the first doped region of the semiconductor device 400. In some embodiments, the second doped region includes the second dopant type (e.g., an n-type dopant).

10 , the process 1000 may include forming a buffer layer of the semiconductor device on the second doped region (block 1030 ). For example, as described herein, one or more of the semiconductor processing tools 102 - 116 may form the buffer layer 410 of the semiconductor device 400 on the second doped region.

10 , the process 1000 may include forming a gate oxide layer 418 of the semiconductor device over the first doped region, over the second doped region, and over the buffer layer (block 1040). For example, one or more of the semiconductor processing tools 102 to 116 may form the gate oxide layer 418 of the semiconductor device 400 over the first doped region, over the second doped region, and over the buffer layer 410 as described herein.

10 , the process 1000 may include forming a gate structure of a semiconductor device on the gate oxide layer (block 1050 ). For example, one or more of the semiconductor processing tools 102 - 116 may form the gate structure 416 of the semiconductor device on the gate oxide layer 418 as described herein.

The process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and/or in combination with one or more other processes described elsewhere herein.

In the first embodiment, forming the buffer layer 410 includes: forming a mask layer 502 on the first doped region and on the second doped region, forming a pattern in the mask layer 502, and forming the buffer layer 410 based on the pattern in the mask layer.

In a second embodiment (alone or in combination with the first embodiment), a first portion 504 of the second doped region is exposed via a pattern, and wherein a second portion 506 of the second doped region remains covered by the mask layer 502 when the buffer layer 410 is formed.

In a third embodiment (alone or in combination with one or more of the first and second embodiments), the second portion 506 of the second doped region corresponds to an extension region 420 of the second doped region, wherein the buffer layer 410 contacts a first side of the extension region 420, and wherein the first doped region contacts a second side of the extension region 420 opposite to the first side.

In a fourth embodiment (alone or in combination with one or more of the first to third embodiments), forming the buffer layer based on a pattern includes: etching a portion of the second doped region based on the pattern; and depositing the buffer layer in a region occupied by the portion of the second doped region.

In a fifth embodiment (alone or in combination with one or more of the first to fourth embodiments), process 1000 includes performing one or more etching operations based on the gate structure 416 to remove a first portion of the gate oxide layer 418 and remove a first portion of the buffer layer 410, a second portion of the gate oxide layer 418 remains under the gate structure 416, and wherein a second portion of the buffer layer 410 remains under the gate structure 416.

In a sixth embodiment (alone or in combination with one or more of the first to fifth embodiments), the process 1000 includes performing an etching operation to remove the mask layer 502, wherein the etching operation makes the top surface of the buffer layer 410 approximately coplanar with the top surface of the first doped region.

Although FIG10 illustrates example blocks of process 1000, in some implementations, process 1000 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG10. Additionally or alternatively, two or more of the blocks of process 1000 may be performed in parallel.

In this manner, a medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. In addition, the medium voltage transistor may include a NLDD region including an N ⁺ source/drain region of the medium voltage transistor. Light doping in the NLDD region enables a reduction in the threshold voltage ( _Vt ) while enabling medium voltage operation at the N ⁺ source/drain region. To reduce the amount and/or likelihood of current leakage in the medium voltage transistor due to light doping in the NLDD region, a buffer layer may be included above a portion of the NLDD region and/or on a portion of the NLDD region below a gate structure of the medium voltage transistor. The NLDD region and the hot region of the medium voltage transistor can achieve the threshold voltage of the medium voltage transistor (e.g., relative to the medium voltage transistor that does not include the NLDD region and the hot region) while maintaining the same current leakage performance or reducing the current leakage in the medium voltage transistor (e.g., relative to the medium voltage transistor that does not include the NLDD region and the hot region). This can make it possible for the medium voltage transistor to operate at the low voltage (core V _dd ) of the low voltage transistor included in the level shifter circuit. In addition, this can make it possible to reduce the low voltage of the low voltage transistor included in the level shifter circuit, thereby reducing the power consumption of the level shifter circuit.

As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first doping region including a first doping type. The semiconductor device includes a second doping region located in the first doping region, the second doping region including a second doping type. The semiconductor device includes a third doping region located in the first doping region, the third doping region including the second doping type, wherein the third doping region corresponds to a first source/drain region of the semiconductor device. The semiconductor device includes a fourth doped region located in the second doped region, the fourth doped region includes a second dopant type, wherein the fourth doped region corresponds to a second source/drain region of the semiconductor device. The semiconductor device includes a buffer layer located on a portion of the second doped region. The semiconductor device includes a gate oxide layer located on a portion of the first doped region, on the buffer layer, and on an extension region of the second doped region. The semiconductor device includes a gate structure located on the gate oxide layer.

As described in more detail above, some embodiments described herein provide a method. The method includes forming a first doping region of a semiconductor device on a substrate, wherein the first doping region includes a first dopant type. The method includes forming a second doping region of the semiconductor device in the first doping region, wherein the second doping region includes a second dopant type. The method includes forming a buffer layer of the semiconductor device on the second doping region. The method includes forming a gate oxide layer of the semiconductor device on the first doping region, on the second doping region, and on the buffer layer. The method includes forming a gate structure of the semiconductor device on the gate oxide layer.

As described in more detail above, some embodiments described herein provide a level shifter circuit. The level shifter circuit includes an inverter circuit electrically coupled to an input. The level shifter circuit includes a plurality of n-type transistors, the plurality of n-type transistors including a first n-type transistor electrically coupled to the inverter circuit and a second n-type transistor electrically coupled to the input. The level shifter circuit includes a plurality of p-type transistors electrically coupled to the plurality of n-type transistors, wherein at least one of the plurality of n-type transistors or at least one of the plurality of p-type transistors includes: a gate oxide layer; a first doped region located below the gate oxide layer, the first doped region including a first dopant type; a lightly doped second doped region located below the gate oxide layer and aligned with the first doped region, the lightly doped second doped region including a second dopant type; and a buffer layer located below the gate oxide layer and aligned with the lightly doped second doped region.

As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first doping region located in a substrate, the first doping region including a first dopant type. The semiconductor device includes a second doping region located in the substrate and adjacent to the first doping region, the second doping region including a second dopant type. The semiconductor device includes a first source/drain region located in the substrate and on the first doping region, the first source/drain region including a second dopant type. The semiconductor device includes a second source/drain region located in the substrate and on the second doped region, the second source/drain region including a second dopant type. The semiconductor device includes a buffer layer located on a portion of the second doped region. The semiconductor device includes a gate oxide layer located on a portion of the first doped region, on the buffer layer, and on an extension region of the second doped region. The semiconductor device includes a gate structure located on the gate oxide layer.

As described in more detail above, some embodiments described herein provide a method. The method includes doping a substrate with a first doping agent type to form a first doping region of a semiconductor device. The method includes doping the substrate with a second doping agent type to form a second doping region of the semiconductor device adjacent to the first doping region. The method includes forming a buffer layer of the semiconductor device on the second doping region. The method includes forming a gate oxide layer of the semiconductor device on the first doping region, on the second doping region, and on the buffer layer. The method includes forming a gate structure of the semiconductor device on the gate oxide layer.

As used herein, “satisfying a threshold value” may refer to a value that is greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, or the like, depending on the context.

The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present disclosure.

100: Environment 102: Deposition tool/semiconductor processing tool 104: Exposure tool/semiconductor processing tool 106: Development tool/semiconductor processing tool 108: Etching tool/semiconductor processing tool 110: Planarization tool/semiconductor processing tool 112: Plating tool/semiconductor processing tool 114: Ion implantation tool/semiconductor processing tool 116: Wafer/die transport tool/semiconductor processing tool 20 0, 230, 300, 320, 500, 600, 700, 800: Example implementation 202: Control circuit 204: Shift register circuit 206: Sample latch circuit 208: Converter circuit 210: Hold latch circuit 212: Level shifter circuit 214: Digital to analog converter (DAC) circuit 216: Voltage reference circuit 218: Output buffer circuit 220: Output 302 : low voltage input/component 304: medium to high voltage output/component 306: inverter/component 308a, 308b: n-type transistor/component 310: electrical ground/component 312a, 312b: p-type transistor/component 314: medium to high voltage source/component 322: voltage buffer input 324a, 324b: low voltage n-type transistor 400: semiconductor device 402: substrate 404: deep well 40 6: p-well region 408: n-type lightly doped source/drain (NLDD) region 410: buffer layer 412, 414: source/drain region 416: gate structure 418: gate oxide layer 420: extension region 422: spacer layer 424, 426: contact structure 428: inter-layer dielectric (ILD) layer 502: mask layer 504, 506: portion 508, 510: recess 802: turn-off current (I _off ) 804: voltage threshold saturation voltage (V _t,sat ) 806, 808: off current distribution profile 900: device 910: bus 920: processor 930: memory 940: input component 950: output component 960: communication component 1000: process 1010, 1020, 1030, 1040, 1050: blocks D1, D2, D3, D4: size

The present disclosure is best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a diagram of an exemplary environment in which the systems and/or methods described herein may be implemented. FIGS. 2A and 2B are diagrams of an exemplary implementation of the driver circuit described herein. FIGS. 3A and 3B are diagrams of an exemplary implementation of the level shifter circuit described herein. FIGS. 4A and 4B are diagrams of an exemplary semiconductor device described herein. FIGS. 5A to 5M are diagrams of an exemplary implementation described herein. FIG. 6 is a diagram of an exemplary embodiment of a doping profile of a portion of a semiconductor device described herein. FIG. 7 is a diagram of an exemplary embodiment of a current pattern of a semiconductor device described herein. FIG. 8 is a diagram of an exemplary embodiment of a turn-off current of a semiconductor device described herein. FIG. 9 is a diagram of an exemplary assembly of a device described herein. FIG. 10 is a flow chart of an exemplary process associated with forming a transistor structure described herein.

400:Semiconductor devices

402: Base

404: Deep Trap

406: p-well region

408: n-type lightly doped source/drain (NLDD) region

410: Buffer layer

412, 414: Source/drain region

416: Gate structure

418: Gate oxide layer

420: Extension area

422: Spacer layer

424, 426: Contact structure

428: Interlayer dielectric (ILD) layer

Claims (20)

A semiconductor device, comprising: A first doping region, comprising a first dopant type, located in a substrate; A second doping region, comprising a second dopant type, located in the substrate and adjacent to the first doping region; A first source/drain region, comprising the second dopant type, located in the substrate and located on the first doping region; A second source/drain region, comprising the second dopant type, located in the substrate and located on the second doping region; A buffer layer, located on a portion of the second doping region; A gate oxide layer is located on a portion of the first doped region, on the buffer layer, and on an extension region of the second doped region; and a gate structure is located on the gate oxide layer. A semiconductor device as described in claim 1, wherein the dopant concentration of the second dopant type in the second dopant region is smaller than the dopant concentration of the second dopant type in the first source/drain region and the second source/drain region. A semiconductor device as described in claim 1, wherein the buffer layer contacts the gate oxide layer on a first side of the buffer layer; and wherein the buffer layer contacts the portion of the second doped region on a second side of the buffer layer opposite to the first side. A semiconductor device as described in claim 3, wherein the buffer layer contacts the extension region of the second doped region on a third side of the buffer layer. A semiconductor device as described in claim 1, wherein the extension region of the second doped region is located between the first doped region and the buffer layer below the gate oxide layer. A semiconductor device as described in claim 1, wherein the extension region of the second doped region contacts the gate oxide layer. A semiconductor device as described in claim 1, wherein the second source/drain region is configured to operate at an operating voltage that is larger than an operating voltage of the gate structure. A method, comprising: doping a substrate with a first doping agent type to form a first doping region of a semiconductor device; doping the substrate with a second doping agent type to form a second doping region of the semiconductor device adjacent to the first doping region; forming a buffer layer of the semiconductor device on the second doping region; forming a gate oxide layer of the semiconductor device on the first doping region, on the second doping region and on the buffer layer; and forming a gate structure of the semiconductor device on the gate oxide layer. The method of claim 8, wherein forming the buffer layer comprises: forming a mask layer on the first doped region and on the second doped region; forming a pattern in the mask layer; and forming the buffer layer based on the pattern in the mask layer. A method as described in claim 9, wherein a first portion of the second doped region is exposed through the pattern; and wherein when the buffer layer is formed, a second portion of the second doped region remains covered by the mask layer. The method of claim 10, wherein the second portion of the second doped region corresponds to an extension region of the second doped region; wherein the buffer layer contacts a first side of the extension region; and wherein the first doped region contacts a second side of the extension region opposite to the first side. The method of claim 9, wherein forming the buffer layer based on the pattern comprises: etching a portion of the second doped region based on the pattern; and depositing the buffer layer in a region occupied by the portion of the second doped region. The method of claim 9 further comprises: performing one or more etching operations based on the gate structure to remove a first portion of the gate oxide layer and a first portion of the buffer layer, wherein a second portion of the gate oxide layer remains under the gate structure, and wherein a second portion of the buffer layer remains under the gate structure. The method as described in claim 9 further includes: performing an etching operation to remove the mask layer, wherein the etching operation makes the top surface of the buffer layer approximately coplanar with the top surface of the first doped region. A level shifter circuit comprises: an inverter circuit electrically coupled to an input; a plurality of n-type transistors, comprising: a first n-type transistor electrically coupled to the inverter circuit; and a second n-type transistor electrically coupled to the input; and a plurality of p-type transistors electrically coupled to the plurality of n-type transistors, wherein at least one of the plurality of n-type transistors or at least one of the plurality of p-type transistors comprises: a gate oxide layer; a first doped region disposed below the gate oxide layer, the first doped region comprising a first dopant type; A lightly doped second doped region, located below the gate oxide layer and parallel to the first doped region, the lightly doped second doped region comprising a second dopant type; and a buffer layer, located below the gate oxide layer and parallel to the lightly doped second doped region. A level shifter circuit as described in claim 15, wherein at least one of the plurality of n-type transistors or at least one of the plurality of p-type transistors further comprises: a first source/drain region, arranged side by side with the first doped region; and a second source/drain region, arranged side by side with the lightly doped second doped region. A level shifter circuit as described in claim 16, wherein the second source/drain region is located below the buffer layer. A level shifter circuit as described in claim 16, wherein the top surface of the first source/drain region is approximately coplanar with the top surface of the buffer layer. A level shifter circuit as described in claim 16, wherein the lightly doped second doped region extends below the buffer layer and below the second source/drain region. A level shifter circuit as described in claim 16, wherein the first doped region extends below the first source/drain region and below the lightly doped second doped region.

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