TW202401206A - Power sequence control system and electronic device having the same - Google Patents

Abstract

The present invention discloses a power sequence control system for being integrated in an electronic device such as server, and the power sequence control system comprises a BMC chip and a microcontroller chip. In which, the microcontroller chip comprises a power sequencer and a memory, and is allowed to be in communication with an external electronic device. Particularly, user is allowed to design a timing diagram of each of N power signals by operate the electronic device. After that, the N timing diagrams can be converted to be a code file for describing the N timing diagrams, and then the code file is stored in the memory of the microcontroller chip through the BMC chip. As such, after receiving a power good (PG) signal from a power device of the electronic device, the power sequencer generates a power sequence controlling signal according to the code file, such that the power device is controlled by the power sequence controlling signal so as to output N power signals in an ordered sequence. As a result, each of the N power signals is enabled at correspondingly designated timing point.

Description

Power supply sequence control system and electronic device having the same

The present invention relates to the technical field of power supply sequence management, and in particular, to a power supply sequence control system that can real-time fine tune the outputting sequence of multiple power signals of a power supply device.

With the development of complexity and diversification of electronic products, the power-on sequence and power-off sequence of the power supply devices they have have become increasingly important. For example, if the power supply sequence of various electronic components inside an electronic product is incorrect, for example: electronic component A supplies power too quickly and electronic component B supplies power too slowly, it will cause the electronic components of the electronic product to work abnormally or be damaged.

Therefore, it has become extremely important to detect and monitor the power sequence of electronic products. The conventional method is to use an oscilloscope or a multimeter to measure the outputting sequence of multiple power signals of the power supply device one by one to confirm the enablement of each power signal. Is the time point correct and whether the enabling time point needs to be adjusted. However, the conventional methods show the following shortcomings in practical applications:

(1) Using an oscilloscope to measure each power signal of the power supply device one by one obviously costs too much manpower and time, and it is difficult to avoid human errors.

(2) After the power supply device, motherboard and other necessary electronic components have been installed in the host casing, it is difficult for engineers to use an oscilloscope to measure each power signal of the power supply device one by one, making it impossible to detect and analyze the power supply in real time. Fine-tune (real-time monitor and fine tune) the enable time point of each power signal.

From the foregoing description, it can be seen that the conventional power supply timing detection and adjustment methods have obvious flaws that need to be improved. In view of this, the inventor of this case worked hard on research and invention, and finally developed a power supply timing control system of the present invention.

The main purpose of the present invention is to provide a power supply sequence control system, which is applied in an electronic device such as a server and mainly includes: a substrate management chip and a micro control chip (such as a CPLD chip). According to the design of the present invention, the microcontrol chip includes a power sequence controller and a memory, and the substrate management chip can be information-linked with an external electronic device. In particular, the user can operate the external electronic device to design the waveforms of a plurality of power signals, then convert them into a power sequence code, and write the power sequence code into the memory through the substrate management chip. According to this design, after receiving the power good signal transmitted by the power supply device, the power sequence controller generates a power sequence control signal according to the power sequence code stored in the memory, and uses the power sequence control signal The power supply device is controlled to output a plurality of power signals in a specific sequence, so that each power signal is enabled at a specified time point, thereby ensuring that the power supply sequence of the electronic components inside the electronic device is correct.

To achieve the above object, the present invention proposes an embodiment of the power supply sequence control system, which is applied in an electronic device and includes: a substrate management chip; and a microcontrol chip, coupling the substrate management chip and a power supply device of the electronic device, and including a power sequence controller and a memory; Among them, operating an external electronic device can information-link the substrate management chip, thereby writing an edited power timing code into the memory through the substrate management chip; Wherein, after receiving a power good indication signal transmitted by the power device, the micro control chip activates its power sequence controller to generate a power supply according to the power sequence code stored in the memory. The timing control signal is then sent to the power supply device to control the power supply device to output a plurality of power signals in a specific sequence.

In one embodiment, the substrate management chip has a network interface and is information-connected to the external electronic device through the network interface.

In one embodiment, the network interface is a wired network interface or a wireless network interface.

In one embodiment, the electronic device is selected from the group consisting of servers, cloud computing computers, industrial computers, desktop computers, all-in-one computers, and notebook computers. any of.

In one embodiment, the power device is any one selected from the group consisting of a power supply, a battery backup unit (BBU), and an electrical energy storage device.

In one embodiment, the external electronic device is any one selected from the group consisting of cloud computing computers, industrial computers, desktop computers, notebook computers, tablet computers, and smartphones.

In one embodiment, the microcontroller chip is selected from the group consisting of a Field Programmable Gate Array (FPGA) chip and a Complex Programmable Logic Device (CPLD) chip. any one in the group.

In one embodiment, the micro control chip is further coupled to the plurality of power signals output by the power device, and further includes a signal detection unit.

In one embodiment, the signal detection unit detects an enabling time point of each of the power signals, and then stores a detection data including a plurality of the enabling time points in the memory. Furthermore, the signal detection unit determines the enabling time point by detecting a level sudden change point of the power signal.

In one embodiment, the external electronic device can read the detection data from the memory through the substrate management chip, generate a plurality of detection power signals according to a plurality of the enable time points, and then confirm the plurality of the enable time points. Detect the power sequence of the power signal.

Furthermore, the present invention also provides an electronic device, which includes: a motherboard, a power supply device, and a plurality of electronic components disposed on the motherboard; characterized in that, the electronic device has the above-described features of the present invention. The power supply sequence control system. Moreover, the electronic device is any one selected from the group consisting of servers, cloud computing computers, industrial computers, desktop computers, all-in-one computers, and notebook computers. By.

In order to describe the power supply sequence control system proposed by the present invention more clearly, the preferred embodiments of the present invention will be described in detail below with reference to the drawings.

First embodiment

Please refer to FIG. 1 , which shows a block diagram of a power supply timing control system according to a first embodiment of the present invention. Moreover, FIG. 2 shows a perspective view of an electronic device equipped with the power supply timing control system of the present invention. As shown in FIGS. 1 and 2 , the power supply sequence control system 1 of the present invention is applied to an electronic device 1E such as a server. Generally, the electronic device 1E includes: a motherboard 1E0, a power supply device 1E1, and a plurality of electronic components disposed on the motherboard 1E0. To explain in more detail, the power supply timing control system 1 of the present invention mainly includes: a substrate management chip 11 and a micro control chip 12, and the substrate management chip 11 and the micro control chip 12 are both disposed on the motherboard 1E0.

According to the design of the present invention, the micro control chip 12 is coupled to the substrate management chip 11 and the power device 1E1, and includes a power sequence controller 121 and a memory 122. Furthermore, the substrate management chip 11 has a network interface 111 and can be connected to an external electronic device 2 through the network interface 111 . In a feasible embodiment, the network interface 111 may be a wired network interface or a wireless network interface.

In particular, the user can operate the external electronic device 2 to design waveforms of a plurality of power signals, as shown in FIG. 3 . After completing the waveform design of the plurality of power signals, they are then converted into a power timing code, as shown in Figure 4. Finally, the external electronic device 2 is operated to connect information with the substrate management chip 11 , so that the power supply timing code is written into the memory 122 through the substrate management chip 11 . In this way, after receiving a power good indication signal PG transmitted by the power device 1E1, the microcontrol chip 12 will activate its power sequence controller 121 according to the power sequence stored in the memory 122. The timing encoding generates a power supply timing control signal EN, and then the power supply timing control signal EN is sent to the power supply device 1E1, thereby controlling the power supply device 1E1 to output a plurality of power signals in a specific sequence. Simply put, under the control of the power sequence control signal EN, the waveform of each power signal will be as shown in Figure 4, and will be enabled at a specified time point, thereby ensuring the safety of the electronic components inside the electronic device. The power supply sequence is correct to ensure that the electronic components mentioned above will not work abnormally or be damaged due to incorrect power supply sequence.

The present invention does not limit the electronic device 1E to be a server. In a feasible embodiment, the electronic device 1E can also be a cloud computing computer, an industrial computer, a desktop computer, an all-in-one computer, or a notebook computer. It is worth noting that when the electronic device 1E is a server or an industrial computer, it usually includes both a power supply and a power backup unit (Battery backup unit, BBU). Therefore, the power supply device 1E1 shown in FIG. 1 refers to a power supply, a power backup unit (BBU) and/or an electrical energy storage device (such as a battery).

Likewise, the present invention does not limit the types of the micro control chip 12 and the external electronic device 2 . In a feasible embodiment, the micro control chip 12 may be an FPGA chip or a CPLD chip. To explain in more detail, the FPGA chip is a Field Programmable Gate Array (FPGA) chip, and the CPLD chip is a Complex Programmable Logic Device (CPLD) chip. On the other hand, the external electronic device 2 can be any one from the group consisting of a cloud computing computer, an industrial computer, a desktop computer, a notebook computer, a tablet computer, and a smart phone.

Second embodiment

Please refer to FIG. 5 , which shows a block diagram of a power supply timing control system according to a second embodiment of the present invention. In the second embodiment, the micro control chip 12 is also coupled to the plurality of power signals output by the power supply device 1E1, and further includes a signal detection unit 123. When the power supply sequence control system 1 of the present invention operates in a measurement mode (Measurement mode), the signal detection unit 123 detects an enable time point of each power signal, and then detects an enable time point including a plurality of the enable time points. A detection data is stored in the memory 122 . For example, the signal detection unit 123 determines the enabling time point by detecting a level sudden change point of the power signal. To explain in more detail, as shown in FIG. 3 , the level sudden change point refers to the time point when High turns to Low or Low turns to High in the waveform of the power signal.

After completing the measurement of each power signal and the storage of the detection data, the user can operate the external electronic device 2 to connect information with the substrate management chip 11, and then read the information from the memory 122 through the substrate management chip 11. Detection data. Finally, the user can operate the external electronic device 2 to convert the detection data into a plurality of detection power signals, and then can check the level sudden change point (ie, enable time point) in each detection power signal, and complete Checking the power sequence of a plurality of said detected power signals. If it is found during the inspection that the enable time points of certain power signals are too early or too late, you can modify the waveform design of multiple power signals, then convert them into the modified power sequence code, and write it again. The memory 122.

In this way, the above has completely and clearly explained the power supply sequence control system of the present invention. It must be emphasized that the above detailed description is a specific description of possible embodiments of the present invention. However, the embodiments are not intended to limit the patent scope of the present invention. Any equivalent implementation or modification that does not deviate from the technical spirit of the present invention will All should be included in the patent scope of this case.

1: Power supply sequence control system 11:Substrate management chip 111:Network interface 12:Micro control chip 121:Power sequence controller 122:Memory 123: Signal detection unit 1E: Electronic devices 1E0: motherboard 1E1: Power supply unit 2:External electronic devices

Figure 1 is a block diagram of a first embodiment of a power supply sequence control system according to the present invention; Figure 2 is a perspective view of an electronic device with the power supply timing control system of the present invention; Figure 3 shows the waveform diagrams of multiple power signals; Figure 4 is a schematic diagram of power supply timing encoding; and FIG. 5 is a block diagram of a second embodiment of the power supply sequence control system of the present invention.

1: Power supply sequence control system

11:Substrate management chip

111:Network interface

12:Micro control chip

121:Power sequence controller

122:Memory

1E0: motherboard

1E1: Power supply unit

2:External electronic devices

Claims (13)

A power supply sequence control system is applied to an electronic device and includes: a substrate management chip; and a microcontrol chip, coupling the substrate management chip and a power supply device of the electronic device, and including a power sequence controller and a memory; Among them, operating an external electronic device can information-link the substrate management chip, thereby writing an edited power timing code into the memory through the substrate management chip; Wherein, after receiving a power good indication signal transmitted by the power device, the micro control chip activates its power sequence controller to generate a power supply according to the power sequence code stored in the memory. The timing control signal then transmits the power timing control signal EN to the power supply device, thereby controlling the power supply device to output a plurality of power signals in a specific sequence. The power supply timing control system of claim 1, wherein the substrate management chip has a network interface and is information-connected to the external electronic device through the network interface. The power supply timing control system of claim 1, wherein the micro control chip is further coupled to the plurality of power signals output by the power supply device, and further includes a signal detection unit. The power sequence control system as described in claim 1, wherein the electronic device is selected from the group consisting of servers, cloud computing computers, industrial computers, desktop computers, all-in-one computers, and notebooks. Any one of a group of computers. The power sequence control system of claim 1, wherein the power device is any one selected from the group consisting of a power supply, a power backup unit (Battery backup unit, BBU) and an electric energy storage device. By. The power sequence control system of claim 1, wherein the external electronic device is selected from the group consisting of cloud computing computers, industrial computers, desktop computers, notebook computers, tablet computers, and smart phones. any of them. The power supply timing control system as described in claim 1, wherein the microcontrol chip is selected from a field programmable gate array (FPGA) and a complex programmable logic device (Complex Programmable Logic). Device, CPLD) chip group. The power sequence control system of claim 2, wherein the network interface is a wired network interface or a wireless network interface. The power supply sequence control system according to claim 3, wherein the signal detection unit detects an enable time point of each of the power signals, and then stores a detection data including a plurality of the enable time points in the memory. in the body. The power supply timing control system of claim 9, wherein the signal detection unit determines the enabling time point by detecting a level sudden change point of the power signal. The power sequence control system of claim 9, wherein the external electronic device can read the detection data from the memory through the substrate management chip and generate a plurality of detection power supplies based on a plurality of the enable time points. signal, and then confirm the power sequence of a plurality of said detected power signals. An electronic device, including: a motherboard, a power supply device and a plurality of electronic components disposed on the motherboard; characterized in that the electronic device has any one of claims 1 to 11. The power supply sequence control system is described. The electronic device according to claim 12, wherein the electronic device is selected from the group consisting of servers, cloud computing computers, industrial computers, desktop computers, all-in-one computers, and notebook computers. Any member of a group of computers.