TW202338811A - Capacitor string structure, memory device and electronic device - Google Patents

Abstract

A capacitor string structure, a memory device and an electronic device are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.

Description

Capacitor string structures, memory devices and electronic devices

The present invention relates to a capacitor string structure, a memory device and an electronic device, and in particular to a capacitor string structure formed on a word line of a memory device, and an electronic device constructed based on the capacitor structure.

In the field of memory technology, it is a necessary choice to install a charge pump circuit in a memory device. The charge pump circuit can be used to increase the word line voltage on the word line to start the programmed action of the memory cell.

Based on the charge pump circuit, multiple corresponding capacitors need to be set. Capacitors require a large amount of layout area in the layout of integrated circuits. Therefore, how to save the layout area of capacitors in integrated circuits is an important issue for those skilled in the art.

The present invention provides a capacitor string structure, which is formed by using multiple word lines in a memory device, which can reduce the area required for circuit layout.

The present invention provides a memory device and an electronic device, which can reduce the area required for circuit layout by cooperating with the above capacitor string structure.

The capacitor string structure of the present invention includes multiple conductive plates. The conductive plate is disposed in the memory device. The conductive plates are stacked on each other to form multiple word lines in the memory device, and a capacitor is formed between two adjacent conductive plates.

The electronic device of the present invention includes a core circuit and a plurality of first capacitors. The core circuit is coupled to the first capacitor. The first capacitor forms a capacitor string structure. The capacitor string structure is formed from multiple conductive plates. The conductive plate is disposed in the memory device. The conductive plates are stacked on each other to form a plurality of word lines in the memory device, wherein first capacitors are formed between two adjacent conductive plates.

The memory device of the present invention includes a plurality of word lines and a charge pump circuit. Each word line is coupled to a plurality of memory cells. The word lines are respectively formed by a plurality of conductive plates, and the conductive plates form a capacitor string structure. The charge pump circuit is coupled to the capacitor string structure, and performs a charge pump operation on a plurality of first capacitors in the capacitor structure according to a plurality of clock signals to generate an output voltage.

Based on the above, the capacitor string structure of the present invention is formed by a plurality of word lines stacked on each other in a memory device. The capacitor string structure of the present invention can provide a medium for charge storage and transfer in memory devices and electronic devices. Since the capacitor string structure is formed by stacking multiple word lines in a memory device, the capacitor string structure does not need to occupy additional circuit layout area, effectively reducing circuit costs.

Please refer to FIG. 1 , which is a schematic diagram of a capacitor string structure according to an embodiment of the present invention. The capacitor string structure includes series-coupled capacitors C1 to C8. Capacitors C1 - C8 are formed by a plurality of conductive plates forming word lines WL1 - WL8 of memory device 100 . In this embodiment, the conductive plates forming the word lines WL1 to WL8 are stacked in sequence. The two conductive plates of adjacent word lines WL1 and WL2 form a capacitor C1; the two conductive plates of adjacent word lines WL2 and WL3 form a capacitor C2; ...; the two conductive plates of adjacent word lines WL7 and WL8 form a capacitor C2. Capacitor C8.

In this embodiment, the memory device 100 can be a non-volatile memory (such as a flash memory) or a volatile memory, without certain limitations.

In this embodiment, the memory device 100 is a three-dimensional architecture memory device. The memory device 100 has a conductive plate forming a memory string selection line SSL and a common source line GSL. The conductive plates forming the word lines WL1 to WL8 are sequentially disposed between the two conductive plates of the memory string selection line SSL and the common source line GSL. It is worth mentioning that the embodiment of the present invention uses the conductive plates forming the word lines WL1 ~ WL8 in the memory device 100 to form a capacitor string structure including the capacitors C1 ~ C8, which can generate a circuit without requiring additional layout area. the required capacitance.

It is worth mentioning that in the memory device 100 , the conductive plates forming the word lines WL1 to WL8 may be conductive plates with string holes or conductive plates without string holes. In the embodiment of the present invention, the conductive plate used to form the word lines WL1 to WL8 may be a conductive plate without hole strings, or may be a conductive plate with hole strings, and there is no fixed limit.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram of a capacitor string structure according to an embodiment of the present invention. The capacitor string structure 200 is formed by a plurality of conductive plates forming word lines WL1 to WL20. Among the word lines WL1 to WL20, two adjacent conductive plates form capacitors C1 to C19 respectively. In this embodiment, the first conductive plates forming the word lines WL1, WL3 and WL5 can be coupled to the end point N1 through the transmission wire WR1, and the second conductive plates forming the word lines WL2 and WL4 can be coupled to each other through the transmission wire WR1. WR2 are mutually coupled to terminal M1. In this way, the capacitors C1 ~ C4 can be coupled in parallel between the terminals N1 and M1.

In addition, the first conductive plates forming the word lines WL6, WL8 and WL10 can be coupled to each other through the transmission conductor WR3 to the end point N3; the second conductive plates forming the word lines WL7 and WL9 can be coupled to each other through the transmission conductor WR4. to the endpoint M3; the first conductive plates forming the word lines WL11, WL13 and WL15 can be coupled to each other to the endpoint N2 through the transmission conductor WR5; the second conductive plates forming the word lines WL12 and WL14 can be coupled to the endpoint N2 through the transmission conductor WR6 are coupled to each other to the endpoint M2; the first conductive plates forming the word lines WL16, WL18 and WL20 can be coupled to the endpoint N4 through the transmission wire WR7; the second conductive plates forming the word lines WL17 and WL19 can be coupled to each other to the endpoint N4. Transmission wires WR8 are mutually coupled to terminal M4. The plurality of first conductive plates mentioned above are not directly adjacent to each other, and the plurality of second conductive plates are not directly adjacent to each other.

Through the above coupling relationship, the capacitors C6 ~ C10 can be coupled in parallel between the terminals M3 and N3, the capacitors C11 ~ C14 can be coupled in parallel between the terminals M2 and N2, and the capacitors C15 ~ C19 can be coupled in parallel. Coupled between terminals M4 and N4. The capacitance between the terminals M1 and N1, the capacitance between the terminals M3 and N3, the capacitance between the terminals M2 and N2, and the capacitance between the terminals M4 and N4 are sequentially coupled in series.

Incidentally, the number of word lines WL1 to WL20 in this embodiment is only an example for illustration and is not intended to limit the scope of the present invention. A person skilled in the art can generate different numbers of capacitors according to the actual number of word lines in the memory device, without any specific limitation.

In addition, in this embodiment, the number of capacitors connected in parallel between any two terminals can be adjusted according to design requirements and is not limited to four in this embodiment. By adjusting the number of capacitors connected in parallel between the two terminals, the equivalent capacitance provided between the two terminals can be adjusted.

Please refer to FIGS. 3A to 3C below. FIGS. 3A to 3C respectively illustrate schematic diagrams of different implementations of capacitor string structures according to embodiments of the present invention. In FIG. 3A, the capacitor string structure 310 includes a plurality of conductive plates WLP1˜WLP5 forming word lines of the memory device and a plurality of dielectric layers ISP1˜ISP4. The conductive plates WLP1~WLP5 are staggered with the dielectric layers ISP1~IP4 respectively. Among them, the spaces between conductive plates WLP1 and WLP2, the spaces between conductive plates WLP2 and WLP3, the spaces between WLP3 and WLP4, and the spaces between conductive plates WLP4 and WLP5 can be divided into capacitors. In this embodiment, the conductive plates WLP1 to WLP5 are stacked on each other in a ladder shape, and the conductive plates WLP1 to WLP5 have exposed portions NP1 to NP5 respectively.

In addition, the capacitor string structure 310 also includes transmission wires WR1 and WR2. The transmission wire WR1 is coupled to the exposed portions NP1, NP3 and NP5 of the conductive plates WLP1, WLP3 and WLP5 respectively. The transmission wire WR1 can be coupled to the terminal M1. The transmission wire WR2 is coupled to the exposed portions NP2 and NP4 of the conductive plates WLP2 and WLP4 respectively. The transmission wire WR2 can be coupled to the terminal N1. Through the transmission wires WR1 and WR2, the capacitance formed between the conductive plates WLP1~WLP5 can be coupled in parallel between the terminals M1 and N1.

In FIG. 3B , the capacitor string structure 320 includes conductive plates WLP1 to WLP8. The conductive plates WLP1 ~ WLP8 are respectively used to form word lines WL(n) ~ WL(n+7) in the memory device. The conductive plates WLP1 ~ WLP8 are arranged to overlap each other, and a plurality of capacitors are respectively formed between the two adjacent conductive plates WLP1 ~ WLP8. The conductive plates WLP1, WLP3, WLP5 and WLP7 have overlapping protrusions PP1, PP3, PP5 and PP7 respectively, and the conductive plates WLP2, WLP4, WLP6 and WLP8 have overlapping protrusions PP2, PP4, PP6 and PP8 respectively. The respective protruding parts PP1, PP3, PP5 and PP7 do not overlap with the respective protruding parts PP2, PP4, PP6 and PP8. The capacitor string structure 320 also includes transmission wires WR1 and WR2. The transmission wire WR1 is coupled to the protruding parts PP1, PP3, PP5 and PP7, and the transmission wire WR2 is coupled to the protruding parts PP2, PP4, PP6 and PP8. Multiple capacitors formed by the conductive plates WLP1 ~ WLP8 can be coupled to each other in parallel.

In FIG. 3C , the capacitor string structure 330 includes a plurality of conductive plates WLP1 - WLP5 forming word lines of the memory device. The conductive plates WLP1~WLP5 can be stacked on each other in a ladder shape. In this embodiment, the transmission wire WR1 is coupled to the conductive plate WLP1 and the conductive plate WLP5, and is not directly connected to the conductive plates WLP2 and WLP4 (the third conductive plate), and the transmission wire WR2 is coupled to the conductive plate WLP3, so as to An equivalent circuit 331 is formed. Among them, the transmission wire WR1 is further coupled to the end point N1, and the transmission wire WR2 is further coupled to the end point M1.

In the equivalent circuit 331, the equivalent capacitance C31 formed between the conductive plates WLP1 and WLP2 and the equivalent capacitance C32 formed between the conductive plates WLP2 and WLP3 are coupled in series between the terminals N1 and M1. The equivalent capacitance C33 formed between the conductive plates WLP3 and WLP4 and the equivalent capacitance C34 formed between the conductive plates WLP4 and WLP5 are coupled in series between the terminals M1 and N1.

Through the coupling configuration of the embodiment in FIG. 3C , relatively many capacitors can be connected in series between the terminals N1 and M1 . Therefore, the withstand voltage capability between terminals N1 and M1 can be improved.

Of course, the implementation of having two capacitors connected in series between the two terminals N1 and M1 in FIG. 3C is just an example for illustration. The designer can also have three or more capacitors connected in series between the two terminals N1 and M1. Among them, the number of series-connected capacitors at the two terminals N1 and M1 can be decided by the designer without any special restrictions.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device may be a charge pump circuit 400. The charge pump circuit 400 includes a core circuit having a plurality of unit circuits 411 to 415 and a capacitor string structure 420. The capacitor string structure 420 is composed of capacitances between conductive plates of a plurality of word lines WL. The unit circuits 411 to 415 are coupled in series, and the first-stage unit circuit 411 receives the reference voltage VCC. The output terminals of the unit circuits 411 to 415 are coupled to the terminal points M1 to M5 respectively. The terminal M5 may be the output terminal of the charge pump circuit 400 and generate the output voltage VOUT. The output terminals of the unit circuits 411 to 414 are coupled to the input terminals of the subsequent unit circuits 412 to 415 respectively.

In the capacitor string structure 420, the other endpoints N1 and N3 of the plurality of capacitors are used to receive the clock signal P2; the endpoints N2 and N4 are used to receive the clock signal P3; and the endpoint N5 is coupled to the reference ground terminal VSS. The clock signal P3 and the clock signal P2 may have different phases. The clock signal P3 and the clock signal P2 are interleaved so that the terminals N1 to N4 of the corresponding connected capacitors are interleaved to switch between different first voltages and second voltages.

Corresponding to the staggered voltage switching operation of multiple capacitors in the capacitor string structure 420, the unit circuits 411 to 415 can perform charge transfer operations. The charge pump circuit 400 can generate an output voltage VOUT that is several times the reference voltage VCC through a voltage pumping operation based on the reference voltage VCC.

It is worth mentioning that in this embodiment, the unit circuits 411 to 415 can be implemented using a charge pump unit circuit in a multi-stage charge pump circuit that is well known to those skilled in the art, and there is no fixed limitation.

The implementation details of the capacitor string structure 420 have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.

Please refer to FIG. 5A below. FIG. 5A is a schematic diagram of an electronic device according to another embodiment of the present invention. The electronic device may be a charge pump circuit 500 . The charge pump circuit 500 includes a core circuit having a plurality of unit circuits 511 to 515 and a plurality of inverters IV1 to IV4, and a capacitor string structure 520. The capacitor string structure 520 is composed of conductive plates between a plurality of word lines WL. Composed of capacitors. In this embodiment, unit circuit 511 includes transistors T1, T2 and capacitor CG1; unit circuit 512 includes transistors T3, T4 and capacitor CG2; unit circuit 513 includes transistors T5, T6 and capacitor CG3; unit circuit 511 includes transistors T5, T6 and capacitor CG3. Crystals T7, T8 and capacitor CG4; the unit circuit 514 includes transistors T9, T10 and capacitor CG5. Among them, in the unit circuit 511 of the first stage, the first terminal of the transistor T1 receives the reference voltage VCC, and the control terminal of the transistor T1 is coupled to the output terminal of the unit circuit 511 and coupled to the terminal point M1. The second terminal of the transistor T1 is coupled to the control terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the first terminal of the transistor T1, and the second terminal of the transistor T2 is coupled to the control terminal of the transistor T1. In addition, one end of the capacitor CG1 receives the clock signal P4, and the other end of the capacitor CG1 is coupled to the control end of the transistor T2. In the second to last stage unit circuits 512~515, the first terminals of the transistors T3, T5, T7 and T9 are coupled to the output terminals of the previous stage unit circuits 511~514, and the last stage unit The output terminal of circuit 515 is used to generate the output voltage VOUT. In the unit circuits 512 to 515 of the second to last stages, the capacitors CG2 and CG4 receive the clock signal P1, and the capacitors CG3 and CG5 receive the clock signal P4.

In addition, the inverter IV1 is composed of transistors TI1 and TI2 connected in series; the inverter IV2 is composed of transistors TI3 and TI4 connected in series; the inverter IV3 is composed of transistors TI5 and TI6 connected in series; and, the inverter IV3 is composed of transistors TI5 and TI6 connected in series; Diverter IV4 is composed of transistors TI7 and TI8 connected in series. The inverter IV1 receives the clock signal P2 and provides the reverse signal of the clock signal P2 to the end point N1; the inverter IV2 receives the clock signal P3 and provides the reverse signal of the clock signal P3 to the end point N2; reverse direction The inverter IV3 receives the clock signal P2 and provides the inverse signal of the clock signal P2 to the end point N3; the inverter IV4 receives the clock signal P3 and provides the inverse signal of the clock signal P3 to the end point N4. Among them, the clock signals P1 to P4 respectively have different phases.

In this embodiment, the transistors T1 to T10 and the transistors TI2, TI4, TI6, and TI8 may all be N-type transistors. Transistors TI1, TI3, TI5, and TI7 may be P-type transistors.

In Figure 5B, the electronic device may be a bi-phase charge pump circuit 501. The bi-phase charge pump circuit 501 includes a core circuit 5011 and a capacitor COUT, where the capacitor COUT is a capacitor string structure formed by a plurality of conductive plates forming word lines in the memory. The capacitor COUT is coupled to the output terminal of the core circuit 5011. Details of the capacitor COUT can be found in the capacitor string structure 520 of the embodiment of FIG. 5A. The core circuit 5011 includes transistors M51~M55 connected in series. Each transistor M51~M55 is coupled into a diode configuration. Transistor M51 receives the reference voltage VB, transistors M52 and M54 receive the clock signal CLK through capacitors C51 and C53, and transistors M53 and M55 receive the reverse clock signal through capacitors C52 and C54. The core circuit 5011 pumps up the reference voltage VB to generate the output voltage VOUT at the output terminal of the core circuit 5011.

In FIG. 5C, the electronic device may be a voltage regulator 502. The voltage regulator 502 includes a core circuit 5021 and a capacitor COUT, where the capacitor COUT is a capacitor string structure formed by a plurality of conductive plates forming word lines in the memory. The capacitor COUT is coupled to the output terminal of the core circuit 5021. Details of the capacitor COUT can be found in the capacitor string structure 520 of the embodiment of FIG. 5A. The core circuit 5021 includes a reference voltage generator 50211, an amplifier OP1, a power transistor MP5, and resistors R51 and R52. The reference voltage generator 50211 may be a bandgap voltage generator and is used to provide a reference voltage to the amplifier OP1. Resistors R51 and R52 are used to divide the output voltage VOUT to generate a feedback voltage to the amplifier OP1. Voltage regulator 502 is a low dropout voltage regulator.

In Figure 5D, the electronic device may be a time delay 503. The time delay 503 includes a core circuit 5031 and a capacitor CD, where the capacitor CD is a capacitor string structure formed by a plurality of conductive plates forming word lines in the memory. Details of the capacitor CD can be found in the capacitor string structure 520 of the embodiment of FIG. 5A. The core circuit 5031 includes buffers BUF1, BUF2 and resistor R53. The buffers BUF1 and BUF2 are coupled in series to receive the input signal IN and generate the output signal OUT by delaying the input signal IN. The resistor R53 is coupled between the buffers BUF1 and BUF2, and the capacitor CD is coupled between the resistor R53 and the ground terminal. The time delay of the time delay device 503 can be determined by the resistor R53 and the capacitor CD.

In Figure 5E, the electronic device may be a voltage booster 504. The voltage booster 504 includes a core circuit 5041 and a capacitor COUT, where the capacitor COUT is a capacitor string structure formed by a plurality of conductive plates forming word lines in the memory. The capacitor COUT is coupled to the output terminal of the core circuit 5041. Details of the capacitor COUT can be found in the capacitor string structure 520 of the embodiment of FIG. 5A. The core circuit 5041 includes transistors MB1~MB5 and capacitor CB1. Transistors MB1 and MB2 form an inverter to receive the clock signal CLK and generate an inverted clock signal. The transistors MB3~MB5 form a plurality of switches and are used to generate the output voltage VOUT by boosting the reference voltage VCC.

Please note here that the capacitor string structure formed by multiple conductive plates forming word lines in the memory can also be applied to any other circuit architecture. The embodiments in FIGS. 5A to 5E are only examples for illustration and are not intended to limit the scope of the present invention.

Please refer to FIG. 6 below, which is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 600 is a three-dimensional structure memory device. The memory device 600 includes a memory cell array 610, X drivers 621-622, charge pump circuits 631-632, a capacitor string structure 640, a page buffer 650 and a peripheral circuit 660. The memory cell array 610 may have a plurality of memory cells stacked in a three-dimensional manner. The X driver 621 can be disposed on the side of the memory cell array 610 .

In addition, based on the layout direction of the word lines WL1 ~ WLN in the memory cell array 610 , the capacitor string structure 640 can be formed on the other side of the memory cell array 610 . Corresponding to the position of the capacitor string structure 640 , all or part of the elements of the charge pump circuit 631 may be disposed adjacent to the capacitor string structure 640 and coupled to the capacitor string structure 640 . In some embodiments, the charge pump circuit 631 may also be disposed below the memory cell array 610 .

In this embodiment, the X drivers 621 to 622 can be stacked in the memory device 600 at multiple levels. Correspondingly, the charge pump circuits 631 to 632 can also be stacked in multiple levels in the memory device 600 and disposed on the sides of the X drivers 621 to 622 respectively. In this way, the charge pump circuits 631 to 632 do not need to be disposed within the layout range of the peripheral circuit 660 , effectively reducing the layout area requirement.

Incidentally, the page buffer 650 and the peripheral circuit 660 in this embodiment can be arranged at the bottom of the memory device 600 and covered by the memory cell array 610 . In addition, the X drivers 621 to 622, the page buffer 650 and the peripheral circuit 660 in this embodiment can all be implemented using a circuit architecture well known to those skilled in the art, and there are no fixed limitations.

The implementation details of the charge pump circuit 631 and the capacitor string structure 640 have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.

In summary, the present invention utilizes word line conductive plates formed in a memory device to form a capacitor string structure. The capacitor string structure is formed without occupying additional layout area in the three-dimensional memory device. Moreover, the memory device and the electronic device of the present invention can be operated with the above-mentioned capacitor string structure, so as to achieve the purpose of reducing the layout area of the memory device and reducing the circuit cost.

100, 600: Memory device 200, 310, 320, 420, 520: capacitor string structure 331: Equivalent circuit 400: Charge pump circuit 411~415, 511~515: unit circuit 500, 501, 502, 503, 504: Electronic devices 5011, 5021, 5031, 5041: core circuit 52111: Reference voltage generator 610:Memory cell array 621~622:X drive 631~632: Charge pump circuit 640: Capacitor string structure 650: Page buffer 660: Peripheral circuit BUF1, BUF2: buffer C1~C19, CG1~CG5, COUT, CD, C51~C54: capacitor C31~C34: equivalent capacitance CLK: clock signal GSL: common source line ISP1~ISP4: dielectric layer IV1~IV4: reverser N1~N5, M1~M5: endpoints NP1~NP5: exposed part P1~P4: Clock signal PP1~PP10: protruding part R51, R52, R53: Resistors SSL: memory string selection line T1~T10, TI1~TI8, M51~M55, MP1, MB1~MB5: transistor VCC, VB: reference voltage VOUT: output voltage VSS: reference ground terminal WL, WL1~WLN, WL(n)~WL(n+7): character lines WL1~WL8: character lines WLP1~WLP5: conductive plate WR1~WR8: Transmission wire

FIG. 1 is a schematic diagram of a capacitor string structure according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a capacitor string structure according to an embodiment of the present invention. 3A to 3C are schematic diagrams of different implementations of capacitor string structures according to embodiments of the present invention. FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the invention. 5A to 5E are schematic diagrams of multiple electronic devices according to embodiments of the present invention. FIG. 6 is a schematic diagram of a memory device according to an embodiment of the invention.

100:Memory device

C1~C8: capacitor

GSL: common source line

SSL: memory string selection line

WL1~WL8: character lines

Claims (20)

A capacitor string structure including: A plurality of conductive plates are arranged in a memory device. The conductive plates are stacked on each other to form a plurality of word lines in the memory device. A capacitor is formed between two adjacent conductive plates. The capacitor string structure as described in claim 1 further includes: A plurality of dielectric layers are arranged alternately with the conductive plates respectively. The capacitor string structure of claim 1, wherein the conductive plates are stacked on each other in a ladder shape, and the conductive plates each have a plurality of exposed parts. The capacitor string structure further includes: a first transmission wire electrically connected to the exposed portions of the plurality of first conductive plates; and A second transmission wire is electrically connected to the exposed portions of the plurality of second conductive plates. The capacitor string structure of claim 1, wherein among the conductive plates, a plurality of first conductive plates have a plurality of first protrusions overlapping each other, and a plurality of second conductive plates have a plurality of second protrusions overlapping each other. parts, the first protruding parts and the second protruding parts do not overlap. The capacitor string structure as described in claim 4 further includes: a first transmission wire electrically connected to the first protrusions of the first conductive plates; and A second transmission wire is electrically connected to the second protrusions of the second conductive plates. The capacitor string structure of claim 4, wherein the first conductive plates are not directly adjacent to each other, and the second conductive plates are not directly adjacent to each other. The capacitor string structure of claim 6, wherein at least one third conductive plate is further included between each first conductive plate and each second conductive plate. An electronic device including: a core circuit; and A plurality of first capacitors form a capacitor string structure to be coupled to the core circuit. The capacitor string structure is formed of a plurality of conductive plates. The conductive plates are disposed in a memory device. The conductive plates are stacked on each other, respectively. A plurality of word lines in the memory device are formed, wherein each first capacitor is formed between adjacent two of the conductive plates. The electronic device of claim 8, wherein the conductive plates are stacked on each other in a ladder shape, each of the conductive plates has a plurality of exposed parts, and the capacitor string structure further includes: a first transmission wire electrically connected to the exposed portions of the plurality of first conductive plates; and A second transmission wire is electrically connected to the exposed portions of the plurality of second conductive plates. The electronic device according to claim 8, wherein among the conductive plates, a plurality of first conductive plates have a plurality of first protrusions overlapping each other, and a plurality of second conductive plates have a plurality of second protrusions overlapping each other. , the first protruding parts and the second protruding parts do not overlap. The electronic device as claimed in claim 10, wherein the capacitor string structure further includes: a first transmission wire electrically connected to the first protrusions of the first conductive plates; and A second transmission wire is electrically connected to the second protrusions of the second conductive plates. The electronic device as claimed in claim 10, wherein the first conductive plates are not directly adjacent, and the second conductive plates are not directly adjacent. The electronic device according to claim 8, wherein the electronic device is a charge pump circuit, a voltage regulator, a voltage booster or a time delay. A memory device including: A plurality of word lines, each of which is coupled to a plurality of memory cells, the word lines are respectively formed of a plurality of conductive plates, and the conductive plates form a capacitor string structure; and A charge pump circuit is coupled to the capacitor string structure and performs a charge pump operation on a plurality of first capacitors in the capacitor structure according to a plurality of clock signals to generate an output voltage. The memory device of claim 14, wherein the conductive plates are stacked on each other in a ladder shape, each of the conductive plates has a plurality of exposed parts, and the capacitor string structure further includes: a first transmission wire electrically connected to the exposed portions of the plurality of first conductive plates; and A second transmission wire is electrically connected to the exposed portions of the plurality of second conductive plates. The memory device of claim 14, wherein among the conductive plates, a plurality of first conductive plates have a plurality of first protrusions overlapping each other, and a plurality of second conductive plates have a plurality of second protrusions overlapping each other. Protruding parts, the first protruding parts and the second protruding parts do not overlap, The capacitor string structure further includes: a first transmission wire electrically connected to the first protrusions of the first conductive plates; and A second transmission wire is electrically connected to the second protrusions of the second conductive plates. The memory device of claim 16, wherein the first conductive plates are not directly adjacent, and the second conductive plates are not directly adjacent. The memory device of claim 14, wherein the charge pump circuit includes: A plurality of unit circuits are connected in series with each other, and each unit circuit is controlled by a second clock signal and a fourth clock signal, or controlled by a first clock signal and a third clock signal. pulse signal; and the first capacitors, wherein the first terminal of each first capacitor receives the second clock signal, the third clock signal or the reference ground voltage, and the second terminal of each capacitor is coupled to the corresponding unit the output of the circuit. The memory device as claimed in claim 18, wherein each unit circuit includes: A first transistor has a first end that receives a reference voltage or is coupled to the output end of the unit circuit of the previous stage, and the control end of the first transistor is coupled to the output end of each unit circuit; A second transistor has a first terminal coupled to the first terminal of the first transistor, a control terminal of the second transistor coupled to the second terminal of the first transistor, and a second terminal of the second transistor. The second terminal is coupled to the output terminal of each unit circuit; and A second capacitor has a first terminal to receive the fourth clock signal, and a second terminal of the second capacitor is coupled to the control terminal of the second transistor. The memory device as claimed in claim 19, further comprising: A memory cell array having the memory cells stacked in a three-dimensional manner; and An X driver is arranged adjacent to a first side of the memory cell array, The charge pump circuit is formed under the memory cell array and coupled with the capacitor string structure.

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