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TW202310569A - System of frequency modulation based on pll two path modulation - Google Patents

System of frequency modulation based on pll two path modulation Download PDF

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TW202310569A
TW202310569A TW110131997A TW110131997A TW202310569A TW 202310569 A TW202310569 A TW 202310569A TW 110131997 A TW110131997 A TW 110131997A TW 110131997 A TW110131997 A TW 110131997A TW 202310569 A TW202310569 A TW 202310569A
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switchable capacitors
frequency
turned
capacitors
capacitor bank
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一平 范
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達盛電子股份有限公司
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Abstract

A two path direct frequency modulation system is disclosed. The system includes a Varactor, a voltage-controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors, and a frequency deviation capacitor bank including a second plurality of switchable capacitors. The method includes switching on or off a number of the first plurality of switchable capacitors to obtain a desired frequency band and determining number of cycles within a first predetermined time to obtain a first count, switching on or off a number of the first plurality of switchable capacitors or of the second plurality of switchable capacitors to change the desired frequency band and determining number of cycles within a second predetermined time to obtain a second count, and modulating a data signal by switching on or off a switchable capacitors of the second plurality of switchable capacitors according to the first and the second count.

Description

基於鎖相迴路兩路調變的頻率調變系統Frequency modulation system based on phase-locked loop two-way modulation

本發明有關於一種操作兩路直接頻率調變系統的方法,特別是一種有關於一種數位化操作兩路直接頻率調變系統的系統和方法。The present invention relates to a method for operating a two-way direct frequency modulation system, in particular to a system and method for digitally operating a two-way direct frequency modulation system.

頻率調變,如頻率鍵移(Frequency Shift Keying; FSK)、最小移鍵 (MSK)、高斯頻率鍵移(GFSK)和高斯最小鍵移 (GMSK) 等應用於無線通訊,係因其設計簡單且成本低廉。當頻率調變 指數為 0.5 時,FSK 成為 MSK。即 MSK 是 FSK 的特例。Frequency modulation, such as Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), Gaussian Frequency Shift Keying (GFSK) and Gaussian Minimum Keying (GMSK), are used in wireless communications because of their simple design and low cost. When the frequency modulation index is 0.5, FSK becomes MSK. That is, MSK is a special case of FSK.

在傳統設計中,FSK 通常採用直接電壓控制振蕩器(VCO)   數據或 I/Q正交調變來實現。當數據速率較低時,例如低於鎖相迴路或鎖相環 (PLL) 帶寬,它可以通過 Delta -Sigma () 調變器非常有效地實現,Δ-∑ 調變器通常用於實現分數頻率合成器。 後一種方法有效地結合了頻率合成和頻率調變,例如 FSK 及其變體。In traditional designs, FSK is usually implemented using direct voltage-controlled oscillator (VCO) data or I/Q quadrature modulation. When the data rate is low, such as below the bandwidth of a phase-locked loop or phase-locked loop (PLL), it can be achieved very efficiently with a Delta-Sigma () modulator, a delta-sigma modulator typically used to achieve fractional frequencies synthesizer. The latter approach effectively combines frequency synthesis and frequency modulation, such as FSK and its variants.

然而,當數據速率超過 PLL 帶寬時,後面的方法將不起作用,因為信號能量被環路濾波器濾除。However, when the data rate exceeds the PLL bandwidth, the latter method will not work because the signal energy is filtered out by the loop filter.

為了補償濾波後的信號能量,引用了雙路徑直接頻率調變系統100,如圖1所示,其中第二條信號路徑被添加到 VCO 的壓控可變電容器。To compensate the filtered signal energy, a dual-path direct frequency modulation system 100 is introduced, as shown in Figure 1, where a second signal path is added to the voltage-controlled variable capacitor of the VCO.

路徑直接頻率調變系統100包括第一路徑,通常使用數位類比轉換器(DAC) 140將從基帶調變器110輸出的數位信號轉換成類比信號,該類比信號經由低通濾波器135輸入被饋送到VCO 120。還包括第二路徑,其中基帶調變器110輸出到Δ-∑調變器130。預分頻器(prescale)123接收來自Δ-∑調變器130和分頻器125的輸出並輸出 經由串聯耦合的相位頻率檢測器(PFD)115、電荷泵117和環路濾波器119到VCO 120。 來自晶體振盪器的參考時鐘(Ref Clock)也輸入到串聯耦合的相位頻率檢測器(PFD)115,允許PFD 115將相位誤差輸出到電荷泵117、環路濾波器119,並最終輸出到 VCO 120 以校正 VCO 120 的頻率。 VCO 120輸出到分頻器125,分頻器125接著輸出本地振盪器(LO)的信號輸出。Path The direct frequency modulation system 100 includes a first path, typically using a digital-to-analog converter (DAC) 140 to convert the digital signal output from the baseband modulator 110 into an analog signal, which is fed via a low-pass filter 135 input to VCO 120. A second path is also included, where the baseband modulator 110 outputs to the delta-sigma modulator 130 . Prescaler (prescale) 123 receives the output from delta-sigma modulator 130 and frequency divider 125 and outputs to VCO via series coupled phase frequency detector (PFD) 115, charge pump 117 and loop filter 119 120. The reference clock (Ref Clock) from the crystal oscillator is also input to the series coupled phase frequency detector (PFD) 115, allowing the PFD 115 to output the phase error to the charge pump 117, the loop filter 119, and finally to the VCO 120 to correct the frequency of the VCO 120 . The VCO 120 outputs to the frequency divider 125, which in turn outputs the signal output of the local oscillator (LO).

第一路徑具有高通特性,而第二路徑具有低通特性。所要的結果是低通和高通信號的組合,並且在 VCO 120 輸出端產生未失真的信號。研究顯示,如果第一條路徑和第二條路徑具有適當的增益匹配,則可以實現預期的結果。The first path has a high-pass characteristic and the second path has a low-pass characteristic. The desired result is a combination of the low-pass and high-pass signals and produces an undistorted signal at the VCO 120 output. Studies have shown that if the first and second paths have proper gain matching, the desired results can be achieved.

圖2圖示了圖1的頻率調變系統100的VCO 120。VCO 120包括負gm發生器250、電感器240和壓控可變電容器235,其中壓控可變電容器235之間的節點Vtune 係用於為鎖相環(PLL)230調變(TUNE) 壓控可變電容器235的電容值。耦合於壓控可變電容器235、電感器240和負gm產生器250的是VCO校準電容器庫220。VCO校準電容庫(BANK) 220可以包括一些電阻器271、包括金屬-絕緣體-金屬(MIM)的多個可切換電容器275 和互補式金氧半導體 (CMOS) 電容器 277,如圖所示。任何類型的電容器或電容器組合可用以實現 VCO 校準電容器庫220。FIG. 2 illustrates the VCO 120 of the frequency modulation system 100 of FIG. 1 . The VCO 120 includes a negative gm generator 250, an inductor 240, and a voltage-controlled variable capacitor 235, wherein the node Vtune between the voltage-controlled variable capacitors 235 is used to tune (TUNE) the voltage-controlled The capacitance value of the variable capacitor 235 . Coupled to voltage controlled variable capacitor 235 , inductor 240 and negative gm generator 250 is VCO calibration capacitor bank 220 . A VCO calibration capacitor bank (BANK) 220 may include a number of resistors 271, a plurality of switchable capacitors 275 including metal-insulator-metal (MIM), and complementary metal oxide semiconductor (CMOS) capacitors 277, as shown. Any type of capacitor or combination of capacitors can be used to implement the VCO calibration capacitor bank 220 .

VCO校準電容器庫220可以被校準並選擇到所要的頻段,然後通過控制由如圖所示的兩條路徑的輸入施加到Vtune節點的電壓,根據雙路徑方法鎖定頻率。第一路徑具有高通特性,數位信號從基帶調變器110流出,由DAC 140轉換,並通過低通濾波器135到達Vtune節點。 第二路徑具有低通特性,電壓信號流經電荷泵117和環路濾波器119至Vtune節點。通過控制到Vtune節點的第一和第二路徑的電壓,VCO 120的頻率可被調整。The VCO calibration capacitor bank 220 can be calibrated and selected to the desired frequency band, then frequency locked according to the dual path method by controlling the voltage applied to the Vtune node by the input of the two paths as shown. The first path has a high-pass characteristic. The digital signal flows out of the baseband modulator 110 , is converted by the DAC 140 , and reaches the Vtune node through the low-pass filter 135 . The second path has a low-pass characteristic, and the voltage signal flows through the charge pump 117 and the loop filter 119 to the Vtune node. By controlling the voltages of the first and second paths to the Vtune node, the frequency of the VCO 120 can be adjusted.

然而,習知技術即使採用雙路徑方法,仍然使用大量的類比電路。這些類比電路具有高的電流消耗,佔用相對較大的寶貴芯片空間,並且通常包含會產生噪聲的有源(ACTIVE)元件。However, even with the dual-path approach, the prior art still uses a large number of analog circuits. These analog circuits have high current consumption, occupy relatively large amounts of valuable chip space, and often contain active components that generate noise.

本發明揭露一種基於鎖相迴路兩路調變的頻率調變系統,包括:一電壓控制振蕩器 (VCO),包括:頻率偏差電容器庫,包括第一複數個可切換電容器;及VCO 校準電容器庫,包括第二複數個可切換電容器;第一路徑被耦合以將從基帶調製器輸出的數位控制信號饋送到該第一複數個可切換電容,並架構以控制該第一複數個可切換電容有幾個該可切換電容被導通以及有幾個該可切換電容被關閉; 及第二條路徑包括串聯電荷泵、一種基於鎖相迴路兩路調變的頻率調變系統,包括:一電壓控制振蕩器 (VCO),包括:頻率偏差電容器庫,包括第一複數個可切換電容器;及VCO 校準電容器庫,包括第二複數個可切換電容器;第一路徑被耦合以將從基帶調製器輸出的數位控制信號饋送到該第一複數個可切換電容,並架構以控制該第一複數個可切換電容有幾個該可切換電容被導通以及有幾個該可切換電容被關閉; 及第二條路徑包括串聯電荷泵、環路濾波器和VCO 的壓控變容器並架構以控制該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉;其中上述之VCO校準電容器庫決定了該VCO頻率,該頻率偏差電容器庫決定了數據調變。The present invention discloses a frequency modulation system based on phase-locked loop two-way modulation, including: a voltage-controlled oscillator (VCO), including: a frequency deviation capacitor bank, including a first plurality of switchable capacitors; and a VCO calibration capacitor bank , comprising a second plurality of switchable capacitors; a first path coupled to feed a digital control signal output from a baseband modulator to the first plurality of switchable capacitors, and configured to control the first plurality of switchable capacitors to have Several of the switchable capacitors are turned on and several of the switchable capacitors are turned off; and the second path includes a series charge pump, a frequency modulation system based on a two-way modulation of a phase-locked loop, comprising: a voltage controlled oscillator VCO, comprising: a bank of frequency deviation capacitors comprising a first plurality of switchable capacitors; and a bank of VCO calibration capacitors comprising a second plurality of switchable capacitors; a first path coupled to convert the digital output from the baseband modulator a control signal is fed to the first plurality of switchable capacitors, and configured to control how many of the first plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off; and a second path A voltage-controlled varactor comprising a series charge pump, a loop filter, and a VCO and structured to control how many of the switchable capacitors are turned on and how many of the switchable capacitors are turned off in the second plurality of switchable capacitors; wherein The VCO calibration capacitor bank described above determines the VCO frequency, and the frequency deviation capacitor bank determines data modulation.

本發明也揭露一種操作雙路直接頻率調製系統的方法和VCO 的壓控變容器並架構以控制該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉;其中上述之VCO校準電容器庫決定了該VCO頻率,該頻率偏差電容器庫決定了數據調變 。The present invention also discloses a method of operating a dual-channel direct frequency modulation system and a voltage-controlled varactor of the VCO and its structure to control how many of the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are switched on. Capacitors are turned off; wherein the above-mentioned VCO calibration capacitor bank determines the VCO frequency, and the frequency deviation capacitor bank determines data modulation.

本發明也揭露一種操作雙路直接頻率調製系統的方法,該系統包括壓控變容器、壓控振盪器 (VCO) 校準電容器庫,該校準電容器庫包括第一複數個可切換電容器;及VCO 頻率偏差電容器庫,包括第二複數個可切換電容器,所述方法包含以下步驟: 將該壓控變容器設置為預定義值;將該頻率偏差電容器庫設置為中間值; 校準該VCO並在校准後找到對應的VCO頻段; 記錄計數器內在預定時間內之週期數,以求出第一個計數; 在預設時間內,關閉(OF)F或導通(ON)該第一複數個可切換電容器中的一個在以找出第二個計數; 根據該第一計數、該第二計數和/或該第一計數與該第二計數的差值找出頻偏電容器庫中關閉或導通電容的調變數;及 在所要的頻段區間內調變數據信號,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。 The present invention also discloses a method of operating a dual direct frequency modulation system including a voltage controlled varactor, a voltage controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors; and a VCO frequency A bank of bias capacitors comprising a second plurality of switchable capacitors, the method comprising the steps of: Set the voltage-controlled variable capacitor to a predefined value; set the frequency deviation capacitor bank to an intermediate value; Calibrate the VCO and find the corresponding VCO frequency band after calibration; Record the number of cycles in the counter within the predetermined time to find the first count; within a preset time, turn off (OF) F or turn on (ON) one of the first plurality of switchable capacitors to find a second count; finding the modulation number of the off or on capacitance in the frequency offset capacitor bank according to the first count, the second count and/or the difference between the first count and the second count; and The data signal is modulated in the desired frequency range by adjusting how many of the switchable capacitors in the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off according to the data signal.

依據本發明操作雙路直接頻率調製系統的方法第二實施例包含以下步驟: 第二複數個可切換電容器將該壓控變容器設置為預定義值; 將該頻率偏差電容器庫設置為該頻率偏差電容器庫的中間值並在校準後固定一相應 VCO頻段; 設定所有該第二複數個可切換電容器為OFF並在預定時間內計算週期數以求出第二個計數; 根據第一計數與第二計數的差值確定頻偏電容器庫中電容數的ON 或OFF調變次數,以獲得預定之頻率偏差值; 在所要的頻段區間內調變數據信號,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被ON以及有幾個該可切換電容被OFF。 A second embodiment of the method of operating a dual channel direct frequency modulation system according to the present invention comprises the following steps: a second plurality of switchable capacitors sets the varicap to a predefined value; Setting the frequency deviation capacitor bank to the middle value of the frequency deviation capacitor bank and fixing a corresponding VCO frequency band after calibration; setting all of the second plurality of switchable capacitors to OFF and counting the number of cycles within a predetermined time to obtain a second count; Determine the number of ON or OFF modulations of the capacitance in the frequency offset capacitor bank according to the difference between the first count and the second count, so as to obtain a predetermined frequency deviation value; The data signal is modulated in the desired frequency range, according to the data signal, by adjusting how many of the switchable capacitors are turned ON and how many of the switchable capacitors are turned OFF in the second plurality of switchable capacitors.

本發明的目的是實現全數位化控制的兩路頻率調變及其相關校準。 在本發明的方法中,不是使用 DAC 將高通信號輸入壓控變容器,而是使用數位控制的切換電容器庫來實現所需的頻率偏差(deviation)。 由於 VCO 的頻率與 L 乘以 C 的平方根成反比,其中 L 是電感器,C 是電容器。 當L或C任一值發生變化時,振盪頻率都會發生變化。The purpose of the present invention is to realize two-way frequency modulation with full digital control and related calibration. In the method of the present invention, instead of using a DAC to feed a high-pass signal into a voltage-controlled varactor, a digitally controlled bank of switched capacitors is used to achieve the desired frequency deviation. Since the frequency of the VCO is inversely proportional to the square root of L times C, where L is the inductor and C is the capacitor. When any value of L or C changes, the oscillation frequency will change.

圖3圖示了根據本發明較佳實施例的雙路徑頻率調變系統300。類似於圖1的頻率調變系統100。雙路徑直接頻率調變系統300包括第二路徑,其中,基帶調變器(base band moduation)310輸出到Δ-∑調變器130。預分頻器123接收來自Δ-∑調變器130及分頻器125的輸出。 預分頻器123經由相位頻率檢測器115、電荷泵117和環路濾波器117依序串聯耦接再輸入到VCO 120。自晶體振盪器的參考時鐘(Ref Clock)也經由相位頻率檢測器115、電荷泵117和環路濾波器117依序串聯耦接再輸入到VCO 120。VCO 320輸出到分頻器125,分頻器125再輸出至本地振盪器 (LO)信號 LO 輸出。FIG. 3 illustrates a dual-path frequency modulation system 300 according to a preferred embodiment of the present invention. Similar to the frequency modulation system 100 of FIG. 1 . The dual-path direct frequency modulation system 300 includes a second path in which a base band modulation (base band modulation) 310 outputs to a delta-sigma modulator 130 . The prescaler 123 receives outputs from the delta-sigma modulator 130 and the frequency divider 125 . The prescaler 123 is sequentially coupled in series via the phase frequency detector 115 , the charge pump 117 and the loop filter 117 and then input to the VCO 120 . The reference clock (Ref Clock) from the crystal oscillator is also serially coupled through the phase frequency detector 115 , the charge pump 117 and the loop filter 117 and then input to the VCO 120 . The VCO 320 outputs to the frequency divider 125, which in turn outputs to the local oscillator (LO) signal LO out.

圖 3頻率調變系統300與圖1的調頻系統100之間的主要區別在於圖3頻率調變系統300的第一路徑是從基帶調變器310輸出的數位控制信號直接饋送到VCO 320的次級可切換電容器庫的輸入。在本發明實施例中第一路徑中不需要DAC或低通濾波器。The main difference between the frequency modulation system 300 of FIG. 3 and the frequency modulation system 100 of FIG. 1 is that the first path of the frequency modulation system 300 of FIG. level switchable capacitor bank input. No DAC or low-pass filter is required in the first path in an embodiment of the present invention.

圖4說明圖3的頻率調變系統300的VCO 320。VCO 320包括負gm之產生器250、電感器240和壓控可變電容器235。Vtune節點245是兩個壓控可變電容器235之間的電壓節點。壓控可變電容器壓控可變電容器235係用於鎖相環(PLL) 230的鎖定FIG. 4 illustrates the VCO 320 of the frequency modulation system 300 of FIG. 3 . VCO 320 includes negative gm generator 250 , inductor 240 and voltage controlled variable capacitor 235 . Vtune node 245 is the voltage node between two voltage-controlled variable capacitors 235 . Voltage-controlled variable capacitor The voltage-controlled variable capacitor 235 is used for the locking of the phase-locked loop (PLL) 230

由於半導體工藝、電壓和溫度會導致電感器和電容器值的變化,並且某些補償電路,例如切換電容器庫係用於減少在 VCO 320設計中的這些變化,如圖 4 所示。Inductor and capacitor values vary due to semiconductor process, voltage, and temperature, and some compensation circuitry, such as switched capacitor banks, is used to reduce these variations in the VCO 320 design, as shown in Figure 4.

切換電容器庫係通過VCO校準電容器庫220實現。VCO校準電容器庫220可包括電阻器271、多個可切換電容器由MIM電容器275和CMOS電容器277構成如圖所示耦接。The switched capacitor bank is implemented by the VCO calibration capacitor bank 220 . VCO calibration capacitor bank 220 may include resistor 271 , a plurality of switchable capacitors consisting of MIM capacitor 275 and CMOS capacitor 277 coupled as shown.

另一可切換電容器耦合到壓控可變電容器235、電感器 240 和負gm產生器250是頻偏電容器庫(frequency deviation capacitor bank) 210。頻偏電容器庫 210 可以包括電阻器 261、多個可切換電容器由MIM電容器265和CMOS電容器267構成以如圖所示耦接。電容器265、267、275和277不限於MIM和/或CMOS類型,並且任何類型的電容器或電容器組合組都可以用於實現VCO校準電容器組220和頻率偏差電容器庫210。Another switchable capacitor coupled to voltage controlled variable capacitor 235, inductor 240 and negative gm generator 250 is frequency deviation capacitor bank 210. The frequency bias capacitor bank 210 may include a resistor 261, a plurality of switchable capacitors consisting of MIM capacitors 265 and CMOS capacitors 267 coupled as shown. Capacitors 265 , 267 , 275 , and 277 are not limited to MIM and/or CMOS types, and any type of capacitor or combination of capacitors may be used to implement VCO calibration capacitor bank 220 and frequency offset capacitor bank 210 .

第一路徑具有高通特性,數位信號從基帶調變器310直接流到頻偏電容器庫210的開關元件267。第二路徑具有低通特性,電壓流過 通過電荷泵117和環路濾波器119到壓控可變電容器壓控可變電容器235。通過控製到Vtune電路230的第二路徑的電壓,可以控制VCO 320的頻率。 從基帶調變器310輸出到頻偏電容器組210的開關器件267的數位控制信號可以通過接通和/或多個可開關電容器265中的至少一個和/或其中之一來用於數據調變。The first path has a high-pass characteristic, and the digital signal flows directly from the baseband modulator 310 to the switching element 267 of the frequency offset capacitor bank 210 . The second path has a low-pass characteristic, and the voltage flows through the charge pump 117 and the loop filter 119 to the voltage-controlled variable capacitor voltage-controlled variable capacitor 235 . By controlling the voltage of the second path to Vtune circuit 230, the frequency of VCO 320 can be controlled. The digital control signal output from the baseband modulator 310 to the switching device 267 of the frequency offset capacitor bank 210 can be used for data modulation by turning on and/or at least one and/or one of the plurality of switchable capacitors 265 .

基於圖3所示的兩路頻率調變系統300,使用兩個單獨的電容器庫210、220來實現兩個路徑。 VCO校準電容器組220可被校準並調諧到期望的頻段。 頻偏電容器組210用於在所需頻段內調變數據信號,因此優選地具有比VCO校準電容器組220更高的解析度和更高的靈敏度。頻偏電容器組210和VCO校準電容器庫220通過每一個個別關閉或打開任意數量的可切換電容器267和/或277來分別單獨地調整之。Based on the two-way frequency modulation system 300 shown in FIG. 3, two separate capacitor banks 210, 220 are used to implement the two paths. VCO calibration capacitor bank 220 may be calibrated and tuned to a desired frequency band. The frequency offset capacitor bank 210 is used to modulate the data signal in the required frequency band, and thus preferably has higher resolution and higher sensitivity than the VCO calibration capacitor bank 220 . The frequency offset capacitor bank 210 and the VCO calibration capacitor bank 220 are individually adjusted by each individually turning on or off any number of switchable capacitors 267 and/or 277 .

-預設的演算法來搜索接通和斷開電容器的數量,從而實現期望的頻率或範圍。 數位計數電路對 VCO 頻率進行計數是區分所需頻率和測量頻率之間頻率差異的有效方法,儘管還有其他方法可以實現此目標,例如使用查找表,以及本公開但不限於使用數位計數電路。決定了計數的頻率解析度。 高頻解析度還需要一個大計數器。 VCO 設計中的這種頻率補償通常非常粗略,打開或關閉一個電容器通常會改變幾十MHz 或更大的頻率。 電容器庫用於VCO校準的電容器組在此稱為VCO校準電容器組220,如圖2所示。- Preset algorithms to search for the number of on and off capacitors to achieve the desired frequency or range. Counting the VCO frequency with a digital counting circuit is an effective way to distinguish the frequency difference between the desired frequency and the measured frequency, although there are other ways to achieve this, such as using a lookup table, and this disclosure is not limited to using a digital counting circuit. Determines the frequency resolution of the count. High frequency resolution also requires a large counter. This frequency compensation in VCO designs is usually very coarse, turning a capacitor on or off typically changes frequency by tens of MHz or more. Capacitor Bank The capacitor bank used for VCO calibration is referred to herein as VCO calibration capacitor bank 220 , as shown in FIG. 2 .

然而,在無線通信中,VCO通常在千兆赫頻率範圍內操作,而數據速率通常小於幾Mbps,與載波頻率相比,由於頻率調變導致的頻率偏差可以忽略不計。However, in wireless communication, VCOs usually operate in the gigahertz frequency range, while the data rate is usually less than a few Mbps, and the frequency deviation due to frequency modulation is negligible compared to the carrier frequency.

在這種新穎的方法中,第二電容器組,稱為頻偏電容器庫210被添加到VCO以控制頻率偏差。 由於與VCO校準電容器庫220相比,由頻偏電容器組210的變化引起的頻率變化小得多,因此頻偏電容器庫210的電容器值小得多。 頻偏電容器組210中的電容器可以與VCO校準電容器庫220中的電容器類型相同。如果頻偏電容器庫210的電容器變化追踪VCO校準電容器庫220中的電容器,則流程圖300 如圖5所示。 圖5是可用於求得頻偏電容器組210中所需的開和關電容器的一個示範例。流程圖300包括:In this novel approach, a second bank of capacitors, called Frequency Offset Capacitor Bank 210, is added to the VCO to control frequency offset. Since the frequency change caused by changes in the frequency offset capacitor bank 210 is much smaller compared to the VCO calibration capacitor bank 220, the capacitor values of the frequency offset capacitor bank 210 are much smaller. The capacitors in the frequency offset capacitor bank 210 may be of the same type as the capacitors in the VCO calibration capacitor bank 220 . If the capacitor change of the frequency offset capacitor bank 210 tracks the capacitors in the VCO calibration capacitor bank 220 , the flowchart 300 is as shown in FIG. 5 . FIG. 5 is an example that can be used to find the required on and off capacitors in the frequency offset capacitor bank 210 . Flowchart 300 includes:

步驟 301 : 將 Vtune 設定一預定義值,通常是 Vdd/2。Step 301: Set Vtune to a predefined value, usually Vdd/2.

步驟302: 將頻偏電容器庫210 設定為中間值。Step 302: Set the frequency offset capacitor bank 210 to an intermediate value.

步驟303:校準 VCO 並在校準後查找相應的 VCO 頻段。記錄計數器內在預定時間內之週期數,以求出第一個計數,這讓所選的特定通道能選取最佳VCO頻段。Step 303: Calibrate the VCO and find the corresponding VCO frequency band after calibration. The first count is obtained by recording the number of cycles in the counter within a predetermined time period, which allows selection of the optimum VCO frequency band for the particular channel selected.

步驟304:向上或向下移VCO頻段,在預定義時間計算週期數,以找出第二個計數。第一個計數和第二個計數之間的差值(週期數計數)是由VCO校準電容器庫220內一個切換電容器265 所造成,在此,VCO校準電容器庫220的電容器值預期跟隨並正比於頻偏電容器庫 210之電容器265的電容器值。Step 304: Shift the VCO band up or down and count the number of cycles at a predefined time to find the second count. The difference between the first count and the second count (cycle number count) is caused by a switched capacitor 265 within the VCO calibration capacitor bank 220, where the capacitor value of the VCO calibration capacitor bank 220 is expected to follow and be proportional to The capacitor value of the capacitor 265 of the frequency offset capacitor bank 210 .

步驟305:在預定義的頻率偏差下,頻率偏差電容器庫中的開或關電容器數量可被計算或通過查找表求出,查找表的求值是依據第一個計數、第二個計數和/或第一個計數和第二計數之間的差值。Step 305: Under the predefined frequency deviation, the number of on or off capacitors in the frequency deviation capacitor bank can be calculated or obtained through a lookup table, and the evaluation of the lookup table is based on the first count, the second count and/or Or the difference between the first count and the second count.

步驟306:供調變的數位 1 或 0透過開啟或關閉步驟305計算的電容器數量來實現。Step 306: The digit 1 or 0 for modulation is realized by turning on or off the capacitor quantity calculated in step 305.

上述校準方案的本質是使用大電容來估計小電容,從而可以使用更少的時間和簡單的計數器。 缺點是如果頻率的變化不能很好地跟踪到 VCO 校準電容器庫,則頻率的準確性和傳輸信號的質量將互受到影響而妥協。The essence of the above calibration scheme is to use a large capacitance to estimate a small capacitance, so that less time and simple counters can be used. The disadvantage is that if the change in frequency cannot be tracked well to the VCO calibration capacitor bank, the accuracy of the frequency and the quality of the transmitted signal will be compromised by each other.

為了解決這個問題,本發明提出了第二種校準方案,如圖6所示流程圖400包括以下步驟:In order to solve this problem, the present invention proposes a second calibration scheme, as shown in Figure 6, the flowchart 400 includes the following steps:

步驟401: 將 Vtune 設定為預定義值,通常為 Vdd/2。Step 401: Set Vtune to a predefined value, usually Vdd/2.

步驟402:將頻率偏差電容器庫210設置為中值,對 VCO進行校準並找到校準後相應的 VCO 頻段。Step 402: Set the frequency deviation capacitor bank 210 to a median value, calibrate the VCO and find the corresponding VCO frequency band after calibration.

步驟403:固定VCO頻段,將頻率偏差電容器庫210設置為最低值 ,即頻偏電容器庫210中所有電容器都在OFF(關閉)狀態,在預定時間內計算週期數以求出第三個計數。Step 403: Fix the VCO frequency band, set the frequency deviation capacitor bank 210 to the lowest value, that is, all capacitors in the frequency deviation capacitor bank 210 are in the OFF state, and calculate the number of cycles within a predetermined time to obtain the third count.

步驟404:將頻率偏差電容器庫 210設置為其最高值,即頻偏電容器庫210中所有電容器都在ON狀態。在預定時間內計算週期數以求出第四個計數。Step 404: Set the frequency deviation capacitor bank 210 to its highest value, that is, all capacitors in the frequency deviation capacitor bank 210 are in the ON state. Count the number of cycles within a predetermined time to find the fourth count.

步驟405:步驟403 和 步驟404(第三計數和第四計數之間的差值)的計數值差代表所要頻率,並且從此差值中可以推斷出所要的頻率偏差異數可被減少,即,頻率偏差庫210中的電容器數量應打開或關閉。Step 405: The difference in the count value of step 403 and step 404 (the difference between the third count and the fourth count) represents the desired frequency, and from this difference it can be deduced that the desired frequency offset difference can be reduced, i.e., The number of capacitors in frequency deviation bank 210 should be on or off.

值得注意的是在一些實施例中,步驟403和404可以互換(步驟303和304也可以)。 步驟403和404使電容變化最大,從而可以使用較少的計數時間和較小的計數器。 因此,在不脫離本發明公開的情況下,不需要將頻偏電容器中的所有電容器都打開或關閉。頻偏電容器庫210中的電容器的部分開啟或關閉將增加計數器的計數時間和複雜度,但校準原則仍然成立。It should be noted that in some embodiments, steps 403 and 404 can be interchanged (steps 303 and 304 can also be used). Steps 403 and 404 maximize the capacitance change so that less counting time and smaller counters can be used. Therefore, not all of the frequency bias capacitors need to be switched on or off without departing from the present disclosure. Partially turning on or off the capacitors in the frequency offset capacitor bank 210 will increase the counting time and complexity of the counter, but the calibration principles still hold.

在頻偏電容器庫210校準之後,打開或關閉特定電容,頻率的改變就已知。由於 VCO 頻率對電容器的非線性特性,特定的補償可以應用。對於FSK和MSK信號通訊中,通過在符號周期期間,打開和關閉頻偏電容器庫210中的幾個電容器來實現調變,並且在符號周期期間,打開和關閉動作不會改變。 例如,如果頻偏電容器庫210包括50個電容器265並且每個電容器265對應於上述校準的20kHz頻率變化,則頻偏電容器庫210可以設置為其值的一半,那麼以 500 kHz為例 ,偏差當需要符號1時,可以打開 25 個電容器,而當符號 0時,可以關閉 25 個電容器。After the frequency offset capacitor bank 210 is calibrated, the change in frequency is known by turning on or off a particular capacitor. Due to the non-linear characteristics of VCO frequency versus capacitor, specific compensation can be applied. For FSK and MSK signal communication, the modulation is realized by turning on and off several capacitors in the frequency offset capacitor bank 210 during the symbol period, and the turn-on and turn-off actions will not change during the symbol period. For example, if the frequency offset capacitor bank 210 includes 50 capacitors 265 and each capacitor 265 corresponds to the above-mentioned calibrated 20kHz frequency variation, then the frequency offset capacitor bank 210 can be set to half of its value, so taking 500 kHz as an example, the deviation when When a symbol 1 is required, 25 capacitors can be turned on, and when a symbol 0 is required, 25 capacitors can be turned off.

在FSK/MSK情況下,在符號周期內,頻偏電容器庫 210中電容器的開啟或關閉數量是一固定數。 但是,如果在符號周期內,電容器值可以改變,則其他類型的頻率調變,例如 GFSK 和 GMSK可以實現。 在 GFSK/GMSK 的情況下,在一個符號周期內,開或關電容器的數量是一個變化的數字。 這個變化的數字取決於高斯濾波器的輸出,而一個符號周期內電容變化的頻率取決於採樣率。In the case of FSK/MSK, the number of on or off capacitors in the frequency offset capacitor bank 210 is a fixed number within a symbol period. However, if the capacitor value can be changed within a symbol period, other types of frequency modulation such as GFSK and GMSK can be achieved. In the case of GFSK/GMSK, the number of on or off capacitors is a varying number during one symbol period. The number of changes depends on the output of the Gaussian filter, while the frequency of capacitance changes within a symbol period depends on the sampling rate.

本發明揭露了一種基於兩路調變的頻率調變裝置和方法。由於系統的非線性特性, 頻偏電容器庫 210的校準方法提高了頻偏精度、同時,揭露了用於匹配頻偏電容器庫的GFSK數位輸出的方法。 傳統上路徑中的 DAC 被頻偏電容器庫取代,從而降低了電流消耗、減小了組件尺寸,並通過消除有源組件來消除系統中的噪聲(NOISE)。The invention discloses a frequency modulation device and method based on two-way modulation. Due to the nonlinear characteristics of the system, the calibration method of the frequency offset capacitor bank 210 improves the frequency offset accuracy, and at the same time, discloses a method for matching the GFSK digital output of the frequency offset capacitor bank. The traditional DAC in the path is replaced by a bank of frequency offset capacitors, which reduces current consumption, reduces component size, and eliminates noise (NOISE) in the system by eliminating active components.

以上所述僅為本發明之一較佳實施例而已,並非用以限定本發明之申請專利範圍;凡其他未脫離本發明所揭示之精神下所完成之等效改變或修飾,均應包含在下述之申請專利範圍內。The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the following within the scope of the above-mentioned patent application.

100、300:調變系統 140:數位類比轉換器(DAC) 123:預分頻器 130:Δ-∑調變器 120、320:VCO 110、310:基帶調變器 119:環路濾波器 119、230:鎖相環(PLL) 115:相位頻率檢測器(PFD) 117:電荷泵 210:頻偏電容器庫 240:電感器 265、267、275、277:電容器 261:電阻器 235:壓控可變電容器 250:負gm之產生 100, 300: modulation system 140:Digital-to-analog converter (DAC) 123: Prescaler 130: Δ-Σ modulator 120, 320: VCO 110, 310: baseband modulator 119: loop filter 119, 230: Phase-locked loop (PLL) 115: Phase Frequency Detector (PFD) 117: Charge pump 210: Frequency Offset Capacitor Bank 240: Inductor 265, 267, 275, 277: Capacitors 261: Resistor 235:Voltage-controlled variable capacitor 250: Generation of negative gm

圖1是習之技術兩個路徑直接頻率調變系統方塊圖。Figure 1 is a block diagram of Xizhi's two-path direct frequency modulation system.

圖2說明了圖1頻率調變系統的VCO電路 。Figure 2 illustrates the VCO circuit for the frequency modulation system of Figure 1.

圖3根據本發明的實施例,說明兩個路徑頻率調變系統。FIG. 3 illustrates a two path frequency modulation system according to an embodiment of the present invention.

圖4說明了圖3頻率調變 系統的VCO電路。Figure 4 illustrates the VCO circuit for the frequency modulation system of Figure 3.

圖5是圖2的校準和操作兩個路徑頻率調變系統的流程圖。FIG. 5 is a flowchart of calibrating and operating the two-path frequency modulation system of FIG. 2 .

圖6是圖2的校準和操作兩個路徑頻率調變系統的流程圖。FIG. 6 is a flowchart of calibrating and operating the two-path frequency modulation system of FIG. 2 .

300:調變系統 300: modulation system

140:數位類比轉換器(DAC) 140:Digital-to-analog converter (DAC)

123:預分頻器 123: Prescaler

130:△-Σ調變器 130: △-Σ modulator

320:VCO 320:VCO

310:基帶調變器 310: Baseband modulator

119:環路濾波器 119: loop filter

230:鎖相環(PLL) 230: Phase-locked loop (PLL)

115:相位頻率檢測器(PFD) 115: Phase Frequency Detector (PFD)

117:電荷泵 117: Charge pump

210:頻偏電容器庫 210: Frequency Offset Capacitor Bank

250:負gm之產生器 250: Negative gm generator

235:壓控可變電容器 235:Voltage-controlled variable capacitor

Claims (10)

一種基於鎖相迴路兩路調變的頻率調變系統 ,包括: 一電壓控制 振蕩器 (VCO),包括: 頻率偏差電容器庫,包括第一複數個可切換電容器;及 VCO 校準電容器庫,包括第二複數個可切換電容器; 第一路徑被耦合以將從基帶調製器輸出的數位控制信號饋送到該第一複數個可切換電容,並架構以控制該第一複數個可切換電容有幾個該可切換電容被導通以及有幾個該可切換電容被關閉; 及 第二條路徑包括串聯電荷泵、環路濾波器和VCO 的壓控變容器並架構以控制該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉; 其中上述之VCO校準電容器庫決定了該VCO頻率,該頻率偏差電容器庫決定了數據調變 。 A frequency modulation system based on phase-locked loop two-way modulation, including: A Voltage Controlled Oscillator (VCO), consisting of: a bank of frequency deviation capacitors comprising a first plurality of switchable capacitors; and VCO calibration capacitor bank, including a second complex of switchable capacitors; The first path is coupled to feed the digital control signal output from the baseband modulator to the first plurality of switchable capacitors, and is configured to control how many of the first plurality of switchable capacitors are turned on and have Several of the switchable capacitors are turned off; and The second path includes a charge pump in series, a loop filter, and a voltage-controlled varactor of the VCO and is structured to control how many of the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are is closed; The above-mentioned VCO calibration capacitor bank determines the VCO frequency, and the frequency deviation capacitor bank determines the data modulation. 如請求項1 所述 之基於鎖相迴路兩路調變的頻率調變系統 ,其中上述之頻率偏差電容器庫被架構在所要的頻段區間內調變數據信號,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。The frequency modulation system based on the two-way modulation of the phase-locked loop as described in claim 1, wherein the above-mentioned frequency deviation capacitor bank is structured to modulate the data signal in the desired frequency band interval, and the data signal is adjusted by adjusting the first Several of the switchable capacitors in the two plurality of switchable capacitors are turned on and some of the switchable capacitors are turned off. 如請求項2 所述 之基於鎖相迴路兩路調變的頻率調變系統 ,其中上述之頻率偏差電容器庫被架構在所要的頻段區間內調變數據信號供頻率鍵移(FSK) 及/或最小鍵移(MSK),在符號周期之前,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉,在符號周期之區間,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。The frequency modulation system based on phase-locked loop two-way modulation as described in claim 2, wherein the above-mentioned frequency deviation capacitor bank is structured to modulate data signals in the desired frequency band for frequency key shift (FSK) and/or The minimum key shift (MSK), before the symbol period, according to the data signal is by adjusting how many of the switchable capacitors in the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off, in the symbol The cycle interval is adjusted according to the data signal by adjusting how many of the switchable capacitors are turned on and how many of the switchable capacitors are turned off. 如請求項2所述 之基於鎖相迴路兩路調變的頻率調變系統 ,其中上述之頻率偏差電容器庫被架構在所要的頻段區間內調變數據信號供高斯頻率鍵移(GFSK) 及/或G最小鍵移 (GMSK),在符號周期之前,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉,在符號周期之區間,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。The frequency modulation system based on the two-way modulation of the phase-locked loop as described in claim 2, wherein the above-mentioned frequency deviation capacitor bank is structured to modulate the data signal in the desired frequency range for Gaussian frequency key shift (GFSK) and/or or G minimum key shift (GMSK), before the symbol period, according to the data signal, by adjusting how many of the switchable capacitors in the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off, During the interval of the symbol period, according to the data signal, how many of the switchable capacitors in the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off are adjusted. 如請求項2 所述 之基於鎖相迴路兩路調變的頻率調變系統 ,更包含包括一計數單元,該計數單元被架構以求出該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。The frequency modulation system based on phase-locked loop two-way modulation as described in claim 2 further includes a counting unit, which is structured to calculate how many of the second plurality of switchable capacitors are Switched capacitors are turned on and several of the switchable capacitors are turned off. 如請求項2 所述 之基於鎖相迴路兩路調變的頻率調變系統 ,更包含包括一計數單元,該計數單元被架構以求出該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。The frequency modulation system based on phase-locked loop two-way modulation as described in claim 2 further includes a counting unit, which is structured to calculate how many of the second plurality of switchable capacitors are Switched capacitors are turned on and several of the switchable capacitors are turned off. 一種操作雙路直接頻率調製系統的方法,該系統包括壓控變容器、壓控振盪器 (VCO) 校準電容器庫,該校準電容器庫包括第一複數個可切換電容器;及VCO 頻率偏差電容器庫,包括第二複數個可切換電容器,所述方法包含以下步驟: 將該壓控變容器設置為預定義值; 將該頻率偏差電容器庫設置為中間值; 校準該VCO並在校準後找到對應的VCO頻段; 記錄計數器內在預定時間內之週期數,以求出第一個計數; 在預設時間內,關閉(OF)F或導通(ON)該第一複數個可切換電容器中的一個在以找出第二個計數; 根據該第一計數、該第二計數和/或該第一計數與該第二計數的差值找出頻偏電容器庫中關閉或導通電容的調變數;及 在所要的頻段區間內調變數據信號,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。 A method of operating a dual direct frequency modulation system comprising a voltage controlled varactor, a voltage controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors; and a VCO frequency deviation capacitor bank, Including a second plurality of switchable capacitors, the method comprises the steps of: Set the variac to a predefined value; Set the frequency deviation capacitor bank to the middle value; Calibrate the VCO and find the corresponding VCO frequency band after calibration; Record the number of cycles in the counter within the predetermined time to find the first count; within a preset time, turn off (OF) F or turn on (ON) one of the first plurality of switchable capacitors to find a second count; finding the modulation number of the off or on capacitance in the frequency offset capacitor bank according to the first count, the second count and/or the difference between the first count and the second count; and The data signal is modulated in the desired frequency range by adjusting how many of the switchable capacitors in the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off according to the data signal. 如請求項7 所述 之方法,其中上述之頻率偏差電容器庫被架構在所要的頻段區間內調變數據信號供頻率鍵移(FSK) 及/或最小鍵移(MSK),在符號周期之前,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉,在符號周期之區間,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被導通以及有幾個該可切換電容被關閉。The method as claimed in claim 7, wherein the above-mentioned frequency deviation capacitor bank is configured to modulate the data signal in the desired frequency band interval for frequency key shift (FSK) and/or minimum key shift (MSK), before the symbol period, According to the data signal, by adjusting how many of the switchable capacitors in the second plurality of switchable capacitors are turned on and how many of the switchable capacitors are turned off, in the interval of the symbol period, according to the data signal, by adjusting the Several of the switchable capacitors in the second plurality of switchable capacitors are turned on and some of the switchable capacitors are turned off. 如請求項7 所述 之方法,更包含使用查找表求出調變數。The method as described in Claim 7 further includes using a lookup table to obtain the modulation number. 一種操作雙路直接頻率調製系統的方法,該系統包括壓控變容器、壓控振盪器 (VCO) 校準電容器庫,該校準電容器庫包括第一複數個可切換電容器;及VCO 頻率偏差電容器庫,包括第二複數個可切換電容器,所述方法包含以下步驟: 第二複數個可切換電容器將該壓控變容器設置為預定義值; 將該頻率偏差電容器庫設置為該頻率偏差電容器庫的中間值並在校準後固定一相應 VCO頻段; 設定所有該第二複數個可切換電容器為OFF並在預定時間內計算週期數以求出第二個計數; 根據第一計數與第二計數的差值確定頻偏電容器庫中電容數的ON 或OFF調變次數,以獲得預定之頻率偏差值; 在所要的頻段區間內調變數據信號,依據該數據信號是通過調整該第二複數個可切換電容中有幾個該可切換電容被ON以及有幾個該可切換電容被OFF。 A method of operating a dual direct frequency modulation system comprising a voltage controlled varactor, a voltage controlled oscillator (VCO) calibration capacitor bank including a first plurality of switchable capacitors; and a VCO frequency deviation capacitor bank, Including a second plurality of switchable capacitors, the method comprises the steps of: a second plurality of switchable capacitors sets the varicap to a predefined value; Setting the frequency deviation capacitor bank to the middle value of the frequency deviation capacitor bank and fixing a corresponding VCO frequency band after calibration; setting all of the second plurality of switchable capacitors to OFF and counting the number of cycles within a predetermined time to obtain a second count; Determine the number of ON or OFF modulations of the capacitance in the frequency offset capacitor bank according to the difference between the first count and the second count, so as to obtain a predetermined frequency deviation value; The data signal is modulated in the desired frequency range, according to the data signal, by adjusting how many of the switchable capacitors are turned ON and how many of the switchable capacitors are turned OFF in the second plurality of switchable capacitors.
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