TW202303867A - Electronic package and manufacturing method thereof - Google Patents
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Description
本發明係有關一種半導體封裝製程,尤指一種具散熱機制之電子封裝件及其製法。 The invention relates to a semiconductor packaging process, especially an electronic package with a heat dissipation mechanism and its manufacturing method.
隨著近年來可攜式電子產品的蓬勃發展,各類相關產品之開發亦朝向高密度、高性能以及輕、薄、短、小之趨勢,為此,業界發展出各式整合多功能的封裝態樣,以期能符合電子產品輕薄短小與高密度的要求。例如,目前無線通訊技術已廣泛應用於各式各樣的消費性電子產品以利接收或發送各種無線訊號,其中,平面天線(Patch Antenna)因具有體積小、重量輕與製造容易等特性而廣泛利用在手機(cell phone)、個人數位助理(Personal Digital Assistant,簡稱PDA)等電子產品之無線通訊模組中。 With the vigorous development of portable electronic products in recent years, the development of various related products is also moving towards the trend of high density, high performance, light, thin, short, and small. For this reason, the industry has developed various integrated multi-functional packages. In order to meet the requirements of light, thin, short and high density of electronic products. For example, wireless communication technology has been widely used in various consumer electronic products to receive or send various wireless signals. Among them, the planar antenna (Patch Antenna) is widely used because of its small size, light weight and easy manufacturing. It is used in wireless communication modules of electronic products such as cell phone and personal digital assistant (PDA).
圖1係為習知電子裝置1之剖面示意圖。該電子裝置1係包括一結合有複數銲球13之線路結構10、複數配置於該線路結構10上且電性連接該線路結構10之半導體晶片11,12、一包覆該些半導體晶片11,12之封裝層16、及設於該封裝層16外表面之天線結構17,以令該天線結構藉由介電層14結合於該封裝層16上,且該線路結構10藉由該些銲球13安裝於一電路板(圖略)上。
FIG. 1 is a schematic cross-sectional view of a conventional
惟,於習知電子裝置1中,該些半導體晶片11,12於運轉時所產生的熱需透過該封裝層16,才能將熱傳導至外部環境(或者透過該線路結構10與該天線結構17之介電層14傳導至外部環境),因而容易聚熱,無法達到散熱之需求。
However, in the conventional
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved at present.
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:封裝層;第一電子元件,係埋設於該封裝層中,其中,該第一電子元件係具有相對之作用面與非作用面,且該非作用面上形成有至少一凹槽,以令該凹槽延伸連通該封裝層之側面,使該凹槽外露於該封裝層,供作為空氣通道;以及金屬層,係設於該第一電子元件之非作用面上。 In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a packaging layer; a first electronic component embedded in the packaging layer, wherein the first electronic component has an opposite active surface and the non-active surface, and at least one groove is formed on the non-active surface, so that the groove extends and communicates with the side of the packaging layer, so that the groove is exposed to the packaging layer for use as an air channel; and the metal layer is It is arranged on the non-active surface of the first electronic component.
本發明亦提供一種電子封裝件之製法,係包括:以封裝層包覆第一電子元件,使該第一電子元件埋設於該封裝層中,其中,該第一電子元件係具有相對之作用面與非作用面,且該非作用面上形成有至少一凹槽,以令該凹槽延伸連通該封裝層之側面,使該凹槽外露於該封裝層,供作為空氣通道;以及形成金屬層於該第一電子元件之非作用面上。 The present invention also provides a method for manufacturing an electronic package, which includes: covering a first electronic component with a packaging layer, so that the first electronic component is embedded in the packaging layer, wherein the first electronic component has an opposite active surface and the non-active surface, and at least one groove is formed on the non-active surface, so that the groove extends and communicates with the side of the encapsulation layer, so that the groove is exposed to the encapsulation layer for use as an air channel; and forming a metal layer on the The non-active surface of the first electronic component.
前述之電子封裝件及其製法中,該金屬層係沿該凹槽之壁面延伸佈設。 In the aforementioned electronic package and its manufacturing method, the metal layer is extended and arranged along the wall of the groove.
前述之電子封裝件及其製法中,該第一電子元件之作用面上係堆疊第二電子元件。 In the aforementioned electronic package and its manufacturing method, the active surface of the first electronic component is stacked with the second electronic component.
前述之電子封裝件及其製法中,復包括於該封裝層中形成複數導電元件,以令該複數導電元件外露於該封裝層。例如,復包括將該複數導電元件 接置於電路板上,以令該空氣通道位於該電路板與該第一電子元件之非作用面之間。 In the aforementioned electronic package and its manufacturing method, it further includes forming a plurality of conductive elements in the packaging layer, so that the plurality of conductive elements are exposed on the packaging layer. For example, complex includes the complex conductive elements connected to the circuit board so that the air channel is located between the circuit board and the non-active surface of the first electronic component.
前述之電子封裝件及其製法中,該凹槽之局部或全部係佈設有導熱元件。 In the aforementioned electronic package and its manufacturing method, part or all of the groove is provided with a heat conduction element.
前述之電子封裝件及其製法中,該非作用面上形成有至少一遮蓋該凹槽之散熱層。 In the aforementioned electronic package and its manufacturing method, at least one heat dissipation layer covering the groove is formed on the non-active surface.
由上可知,本發明之電子封裝件及其製法中,主要藉由該第一電子元件之非作用面上形成有至少一凹槽之設計,以直接將該第一電子元件所產生之熱導入該空氣通道中,故相較於習知技術,該第一電子元件於運轉時所產生的熱無需經過該封裝層,即可將熱傳導至外部環境,因而不會發生聚熱問題,以滿足散熱之需求。 It can be seen from the above that in the electronic package and its manufacturing method of the present invention, at least one groove is formed on the non-active surface of the first electronic component to directly guide the heat generated by the first electronic component. In the air channel, compared with the conventional technology, the heat generated by the first electronic component during operation can be conducted to the external environment without passing through the encapsulation layer, so that the problem of heat accumulation will not occur, so as to meet the requirements of heat dissipation. needs.
1:電子裝置 1: Electronic device
10:線路結構 10: Line structure
11,12:半導體晶片 11,12: Semiconductor wafer
13:銲球 13: solder ball
14:介電層 14: Dielectric layer
16,26:封裝層 16,26: encapsulation layer
17,27:天線結構 17,27: Antenna structure
2,3,4:電子封裝件 2,3,4: Electronic Packages
20:承載結構 20: Bearing structure
20a:第一側 20a: First side
20b:第二側 20b: Second side
200:線路層 200: line layer
21:第一電子元件 21: The first electronic component
21a:作用面 21a: Action surface
21b:非作用面 21b: Non-active surface
210:導電凸塊 210: conductive bump
211:底膠 211: primer
212:電極墊 212: electrode pad
22:第二電子元件 22: Second electronic component
23:導電元件 23: Conductive element
25:金屬層 25: metal layer
250:凹槽 250: Groove
26a:表面 26a: surface
26c:側面 26c: side
260:穿孔 260: perforation
35:導熱元件 35: Heat conduction element
45:散熱層 45: heat dissipation layer
8:電路板 8: Circuit board
S:空氣通道 S: air channel
圖1係為習知電子裝置之剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional electronic device.
圖2A至圖2F係為本發明之電子封裝件之製法之剖視示意圖。 2A to 2F are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.
圖2E-1係為對應圖2E之橫剖面示意圖。 FIG. 2E-1 is a schematic cross-sectional view corresponding to FIG. 2E.
圖3A及圖3B係為對應圖2F之其它不同實施例之剖視示意圖。 3A and 3B are schematic cross-sectional views of other different embodiments corresponding to FIG. 2F .
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限 定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this manual are only used to match the content disclosed in the manual, for the understanding and reading of those who are familiar with this technology, and are not used to limit The limit conditions for the implementation of the present invention are set, so it has no technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size shall not affect the effect and the purpose of the present invention. Still fall within the scope covered by the technical content disclosed in the present invention. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the applicable scope of the present invention if there is no substantial change in the technical content.
圖2A至圖2F圖係為本發明之電子封裝件2之製法的剖面示意圖。
2A to 2F are schematic cross-sectional views of the manufacturing method of the
如圖2A所示,提供一封裝模組,其包含有承載結構20、嵌埋於該承載結構20中之第二電子元件22、及設於該承載結構20上之天線結構27。
As shown in FIG. 2A , a packaging module is provided, which includes a carrying
所述之承載結構20係例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構,其係於絕緣材上形成複數線路層200,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL)。
The carrying
於本實施例中,該承載結構20具有相對之第一側20a與第二側20b,且形成該線路層200之材質係為銅,而該絕緣材係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
In this embodiment, the carrying
所述之第二電子元件22係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如為半導體晶片,且該被動元件係例如為電阻、電容及電感。
The second
於本實施例中,該第二電子元件22係為半導體晶片,其可藉由覆晶方式、打線方式、直接接觸該線路層200或其它適當方式電性連接該線路層200,並無特別限制。
In this embodiment, the second
所述之天線結構27係結合於該承載結構20第二側20b上。
The
於本實施例中,藉由濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、無電電鍍、化鍍或貼膜(foiling)等方式製作厚度輕薄之該天線結構27。例如,該天線結構27之製程可先於該承載結構20上形成圖案化凹槽,再於該凹槽中形成導電材以作為該天線結構27;或者,該天線結構27之製程亦可直接於該承載結構20上形成圖案化導電材(未先形成凹槽),以作為該天線結構27。
In this embodiment, the light and
如圖2B所示,設置第一電子元件21於該承載結構20之第一側20a上,且該第一電子元件21電性連接該線路層200。
As shown in FIG. 2B , a first
於本實施例中,該第一電子元件21係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。例如,該第一電子元件21係具有相對之作用面21a與非作用面21b,且該第一電子元件21可以其作用面21a之電極墊212藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該線路層200上並電性連接該線路層200,再以底膠211包覆該些導電凸塊210;或者,該第一電子元件21之電極墊212可藉由複數銲線(圖略)以打線方式電性連接該線路層200;亦或,該第一電子元件21之電極墊212可直接電性連接該線路層200。然而,有關該第一電子元件21電性連接該承載結構20之方式不限於上述。
In this embodiment, the first
如圖2C所示,形成一封裝層26於該承載結構20之第一側20a上,以包覆該第一電子元件21。接著,於該封裝層26中形成複數穿孔260,以令該線路層200之部分表面外露於該些穿孔260。
As shown in FIG. 2C , an
於本實施例中,該封裝層26係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound),但不限於上述。
In this embodiment, the
再者,可藉由整平製程,使該封裝層26之表面26a齊平該第一電子元件21之非作用面21b,以令該第一電子元件21之非作用面21b外露於該封裝層
26之表面26a。例如,該整平製程係藉由研磨方式,移除該第一電子元件21之部分材質與該封裝層26之部分材質。
Furthermore, the
如圖2D所示,形成導電元件23於該些穿孔260中,以令該導電元件23電性連接該線路層200。
As shown in FIG. 2D ,
於本實施例中,該導電元件23係為如銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)導電體,但不限於此。例如,該導電元件23凸出該封裝層26之表面26a,以令複數導電元件23外露於該封裝層26之表面26a。
In this embodiment, the
如第2E圖所示,於該第一電子元件21之非作用面21b上形成至少一凹槽250,並於該非作用面21b形成金屬層25,且該金屬層25沿該凹槽250之壁面延伸佈設,使該第一電子元件21之非作用面21b上形成空氣通道S,進而形成本發明之電子封裝件2。
As shown in Figure 2E, at least one
於本實施例中,係以蝕刻方式一併移除該第一電子元件21之非作用面21b與該封裝層26之部分材質,如圖2E-1所示之橫剖面示意圖,以形成複數連通該封裝層26相對兩側面26c之凹槽250,使該空氣通道S可供散熱之用。須注意,該金屬層25不會填滿該凹槽250。
In this embodiment, part of the material of the
再者,該金屬層25係以電鍍、濺鍍或其它塗佈方式形成於該電子元件21之非作用面21b與該凹槽250之壁面上。
Moreover, the
於後續製程中,如圖2F所示,將該電子封裝件2以該些導電元件23接置於一電路板8上,且令該金屬層25接觸該電路板8。
In the subsequent process, as shown in FIG. 2F , the
因此,本發明之製法藉由該第一電子元件21之非作用面21b上形成至少一凹槽250,以直接將該第一電子元件21所產生之熱導入由該凹槽250所構成之空氣通道S中,故當該電子封裝件2接置於該電路板8上時,該第一電子元件21於運轉時所產生的熱無需經過該封裝層26,即可將熱經由該空氣通道S傳導
至外部環境(換言之,該第一電子元件21與該電路板8之間可藉由該空氣通道S進行散熱),因而不會發生聚熱問題,以滿足散熱之需求,且大幅提升散熱之效能。
Therefore, in the manufacturing method of the present invention, at least one
再者,如圖3A所示之本發明另一實施例之電子封裝件3,可於該凹槽250之局部或全部形成至少一如銅柱之導熱元件35,且該導熱元件35接觸結合該金屬層25,但仍形成有該空氣通道S,以當該電子封裝件3接置於該電路板8上時,該導熱元件35接觸該電路板8,以利於散熱。進一步,如圖3B所示之本發明又一實施例之電子封裝件4,可於該第一電子元件21之非作用面21b上之金屬層25與該導熱元件35上形成散熱層45,以令該散熱層45遮蓋該凹槽250,但仍形成有該空氣通道S,以當該電子封裝件4接置於該電路板8上時,該散熱層45接觸該電路板8,以利於散熱。
Furthermore, as shown in FIG. 3A , in the electronic package 3 according to another embodiment of the present invention, at least one heat-conducting
本發明亦提供一種電子封裝件2,3,4,其包括:一封裝層26、一第一電子元件21以及一金屬層25。
The present invention also provides an
所述之第一電子元件21係埋設於該封裝層26中,其中,該第一電子元件21係具有相對之作用面21a與非作用面21b,且該非作用面21b上形成有至少一凹槽250,以令該凹槽250延伸連通該封裝層26之側面26c,使該凹槽250外露於該封裝層26,供作為空氣通道S。
The first
所述之金屬層25係設於該第一電子元件21之非作用面21b上。
The
於一實施例中,該金屬層25係沿該凹槽250之壁面延伸佈設。
In one embodiment, the
於一實施例中,該第一電子元件21之作用面21a上係堆疊第二電子元件22。
In one embodiment, the second
於一實施例中,所述之電子封裝件2,3,4復包括複數嵌埋於該封裝層26中之導電元件23,且該複數導電元件23係外露於該封裝層26。例如,該複數導電元件23係接置於電路板8上,以令該空氣通道S位於該電路板8與該第一電子元件21之非作用面21b之間。
In one embodiment, the
於一實施例中,該凹槽250之局部或全部係佈設有複數導熱元件35。
In one embodiment, part or all of the
於一實施例中,該非作用面21b上形成有至少一遮蓋該凹槽250之散熱層45。
In one embodiment, at least one
綜上所述,本發明之電子封裝件及其製法,係藉由該第一電子元件之非作用面上形成有凹槽之設計,以直接將該第一電子元件所產生之熱導入該空氣通道中,故該第一電子元件於運轉時所產生的熱無需經過該封裝層,即可將熱傳導至外部環境,因而不會發生聚熱問題,以滿足散熱之需求。 In summary, the electronic package and its manufacturing method of the present invention are designed with grooves formed on the non-active surface of the first electronic component to directly guide the heat generated by the first electronic component into the air Therefore, the heat generated by the first electronic component during operation can be conducted to the external environment without passing through the encapsulation layer, so that the problem of heat accumulation will not occur, so as to meet the requirement of heat dissipation.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.
2:電子封裝件 2: Electronic package
21:第一電子元件 21: The first electronic component
21b:非作用面 21b: Non-active surface
23:導電元件 23: Conductive element
25:金屬層 25: metal layer
250:凹槽 250: Groove
26:封裝層 26: encapsulation layer
8:電路板 8: Circuit board
S:空氣通道 S: air channel
Claims (14)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110125663A TWI796726B (en) | 2021-07-13 | 2021-07-13 | Electronic package and manufacturing method thereof |
| CN202110838654.1A CN115621219A (en) | 2021-07-13 | 2021-07-23 | Electronic package and its manufacturing method |
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| TW110125663A TWI796726B (en) | 2021-07-13 | 2021-07-13 | Electronic package and manufacturing method thereof |
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| TWI796726B TWI796726B (en) | 2023-03-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI257159B (en) * | 2004-12-06 | 2006-06-21 | Advanced Semiconductor Eng | Chip package structure |
| TW200707676A (en) * | 2005-08-09 | 2007-02-16 | Chipmos Technologies Inc | Thin IC package for improving heat dissipation from chip backside |
| TWI352409B (en) * | 2007-04-13 | 2011-11-11 | Chipmos Technologies Inc | Qfn package structure with chips having pattern |
| TWI443785B (en) * | 2011-07-27 | 2014-07-01 | 矽品精密工業股份有限公司 | Semiconductor wafer, wafer, semiconductor package having the same, and method of manufacturing the same |
| FR3061600B1 (en) * | 2017-01-03 | 2020-06-26 | Stmicroelectronics (Grenoble 2) Sas | ELECTRONIC DEVICE COMPRISING A GROOVED CHIP |
| US11387164B2 (en) * | 2019-08-28 | 2022-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
| CN112992691B (en) * | 2021-04-23 | 2021-09-03 | 度亘激光技术(苏州)有限公司 | Semiconductor device and soldering method thereof |
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