TW202235700A - Composite substrate for growing epitaxial growth and method of manufacturing the same - Google Patents

Abstract

A composite substrate for epitaxial growth is provided in the present invention, including a substrate, at least one anti-stress layer directly bonding the substrate, a crystalline silicon layer directly bonding the anti-stress layer and with micro patterns formed thereon, and an epitaxial layer formed on the surface having the micro patterns of the crystalline silicon layer.

Description

Composite substrate for epitaxy growth and manufacturing method thereof

The present invention is generally related to a composite substrate for epitaxial growth and its manufacturing method, more specifically, it relates to a composite substrate with an anti-stress layer for epitaxial growth and its manufacturing method.

In recent years, gallium nitride (GaN) materials have received attention and applications in various fields in the industry, such as the future 5G market, electric vehicles, radar satellite communications, radio transmission, and medical technology. Because gallium nitride materials have the characteristics of high energy band, high breakdown electric field, high thermal conductivity, high saturation electron velocity and small device volume, these characteristics make gallium nitride considered to be quite suitable for high-power and high-speed transistor applications. Ideal materials are widely used in high-frequency components such as high electron mobility transistors (high electron mobility transistors, HEMTs) or light-emitting diodes (LEDs).

Silicon substrate has its competitive advantage in price and cost, so the circuit design scheme of growing gallium nitride on silicon substrate is being vigorously researched and developed. However, the inborn lattice constant and thermal expansion coefficient of gallium nitride and silicon substrate are too different, so the heteroepitaxy method of growing gallium nitride directly on the silicon substrate will cause too large lattice mismatch (about 17 %) and thermal expansion coefficient mismatch (about 54%), a large tensile stress will be generated during the growth period, forming a high-density spiral dislocation, which will cause the wafer to warp or even crack, which will lead to the formation of GaN device leakage increases and reduces carrier mobility and operating efficiency.

In view of the above known problems of GaN epitaxy growth on silicon substrates, the present invention proposes to use a composite substrate with a high-strength and high-lattice-matched anti-stress layer for GaN epitaxy growth, and Regularly arranged trapezoidal micropatterns are formed on the epitaxy growth surface to achieve the effect of bending defects during the epitaxy process, so as to obtain a GaN layer structure with low warpage, low stress and high epitaxy quality.

One aspect of the present invention is to provide a composite substrate for epitaxial growth, the structure of which includes a substrate, at least one anti-stress layer directly bonded to the substrate, and a crystalline silicon layer directly bonded to the stress-resistant layer combined, micropatterns are formed thereon, and an epitaxial layer is formed on the side of the crystalline silicon layer with micropatterns.

Another aspect of the present invention is to provide a method for manufacturing a composite substrate for epitaxial growth, the steps of which include providing a first substrate and a second substrate, bonding a first anti-stress layer on the first substrate, Bonding a second anti-stress layer on the second substrate, bonding the bonded first substrate and the first anti-stress layer and the bonded second substrate and the second anti-stress layer in the performing high-temperature heat treatment in an oxygen environment, so that the first substrate is bonded to the first anti-stress layer, and the second substrate is bonded to the second anti-stress layer, and the second anti-stress layer is bonded to the first anti-stress layer. The layers are bonded by performing high-temperature heat treatment in an oxygen-containing environment, so that the first anti-stress layer and the second anti-stress layer work together as an anti-stress layer, and a photolithography process is performed to form a regular arrangement on the surface of the second substrate. micropatterns.

These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is depicted in various drawings and drawings.

Exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings for readers to understand and achieve technical effects. Readers will understand that the description herein is by way of illustration only and is not intended to limit the present case. Various embodiments of the present application and various features that do not conflict with each other in the embodiments can be combined or rearranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention will be understood by those skilled in the art and are intended to be included within the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad way so that "on" not only means "directly on "on" something, but also includes the meaning of "on" something with an intervening feature or layer in between, and "on" or "over" not only means "on" something or "above" and may also include its meaning "on" or "over" something without intervening features or layers in between (ie, directly on something).

In addition, for descriptive convenience, spatially relative terms such as "under", "beneath", "lower", "above", "upper", etc. may be used herein to describe an element or feature relationship to one or more elements or features as shown in the drawings.

In the following description, the terms "substrate", "substrate" and "wafer" are used interchangeably and may include any semiconductor structure having circuitry formed therein or on its surface. These structures may include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped or undoped semiconductors, silicon epitaxial layers supported by semiconductor substrates, or other semiconductor structures, etc. . The semiconductor does not have to be silicon, it can also be silicon germanium, germanium, or gallium arsenide. When referring to a substrate hereinafter, there may have been process steps in or above the semiconductor substrate to form structures such as layers, regions, or junctions.

As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers may extend horizontally, vertically and/or along sloped surfaces. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below.

First, please refer to FIG. 1 , which is a schematic cross-sectional view of laminating a sapphire substrate and a silicon substrate according to a preferred embodiment of the present invention. In the steps in FIG. 1 , a supporting substrate 100 is firstly provided as a supporting base of the overall structure and provides better heat dissipation properties. In this embodiment, the supporting substrate 100 can be a silicon substrate or a silicon wafer, such as crystalline silicon with a <100> or <111> lattice orientation. In other embodiments, the supporting substrate 100 can also be other substrates with good heat dissipation, such as silicon carbide or silicon germanium. On the other hand, a sapphire substrate or wafer 102 is provided to serve as a base layer and an anti-stress layer for subsequent epitaxial growth. The strength of the sapphire substrate is high (Young's modulus greater than 350 Gpa), and the lattice mismatch with the silicon support substrate 100 is low (less than 13%, and the lattice mismatch with the silicon substrate or wafer is 16 %), so it can be used as an excellent anti-stress layer. The sapphire substrate can have any crystal plane, such as a crystal plane with a lattice direction of <100>, for epitaxial growth.

In the step shown in FIG. 1 , the support substrate 100 is bonded to the sapphire substrate 102 . Before performing the lamination step, the support substrate 100 and the sapphire substrate 102 are first subjected to SC1 and SC2 wet chemical cleaning processes, which may include using a solution of ammonia water and hydrogen peroxide and a solution of hydrochloric acid and hydrogen peroxide to clean the surface of the substrate to remove the surface particles and metal impurities. After the cleaning step, the support substrate 100 is aligned with the sapphire substrate 102 and tightly bonded in a vacuum environment. The bonded substrates are then subjected to high-temperature heat treatment in an oxygen-containing environment, such as thermal annealing at a high temperature of 950° C. to 1250° C. in an oxygen-containing environment for 2 to 5 hours. In this way, bonding occurs between the silicon support substrate 100 and the sapphire substrate 102 , and the bonding energy is greater than 0.2 mJ/cm ² , forming a tightly bonded composite substrate or composite wafer.

In other embodiments, as shown in FIG. 2, before the supporting substrate 100 is bonded with the sapphire substrate 102, a high temperature oxidation treatment may be performed first, so that a silicon oxide layer 104 is formed on the surface of the supporting substrate 100, and its thickness is between 1~3μm, the film thickness uniformity is less than 3%. The existence of this silicon oxide layer 104 will help to improve the bonding force between the subsequent support substrate 100 and the sapphire substrate 102, and can also adjust the overall warpage of the composite substrate after subsequent bonding by controlling the thickness of the silicon oxide layer 104. Spend. In this embodiment, the formed silicon oxide layer 104 is bonded to the sapphire substrate 102 and then the above high temperature heat treatment is performed to complete the bonding between the support substrate 100 and the sapphire substrate 102 .

In addition, in other embodiments, as shown in FIG. 3, after the support substrate 100 and the sapphire substrate are bonded to form a composite wafer, the back surface of the support substrate 100 may be subjected to high-temperature oxidation treatment, thus forming another silicon oxide layer 105 As a stress compensation layer for composite substrates. Also, the warpage of the composite substrate can be adjusted by controlling the thickness of the silicon oxide layer 105 on the back surface.

As mentioned above, due to the large lattice mismatch and thermal expansion coefficient mismatch between the GaN epitaxial layer and the silicon substrate, a large tensile stress will be generated during its growth, causing the wafer to warp. By setting an intermediary sapphire layer/substrate between the GaN epitaxial layer and the silicon substrate, since the sapphire layer and the GaN epitaxial layer have low lattice mismatch and thermal expansion coefficient mismatch, it can achieve The function of a buffer layer reduces the stress generated by epitaxy. Furthermore, since the sapphire layer has higher strength and strain resistance, it can suppress the influence of remaining stress on the substrate warpage.

Next, please refer to FIG. 4 , which is a schematic cross-sectional view of connecting the anti-stress layers on two silicon substrates to form a common anti-stress layer according to another embodiment of the present invention. In the embodiment of the present invention, the anti-stress layer and the epitaxial base layer can be formed by abutting two sets of composite substrates. As shown in Figure 4, two sets of composite substrates are provided after bonding the supporting substrate and the sapphire substrate as shown in Figure 3, which respectively include the first substrate 100a, the first sapphire substrate (or wafer) 102a and the second substrate 100b and the second sapphire substrate (or wafer) 102b, wherein the first sapphire substrate 102a and the second sapphire substrate 102b have been planarized after bonding, such as a chemical mechanical planarization (CMP) process, so that the thickness is reduced Thin to 2~10μm. In this embodiment, the first substrate 100 a and the second substrate 100 b are preferably silicon substrates or wafers with a <111> lattice orientation.

Next, the same as the steps in Figure 1, before the bonding step, the SC1 and SC2 wet chemical cleaning processes are performed on the two sets of composite substrates to remove the fine particles and metal impurities on the surface. After the cleaning step, the first sapphire substrate 102a and the second sapphire substrate 102b are aligned and closely bonded in a vacuum environment. After the bonded substrates are subjected to high-temperature heat treatment in an oxygen-containing environment, for example, thermal annealing treatment at a high-temperature oxygen-containing environment at 950° C. to 1250° C. lasts for 2 to 5 hours. In this way, a chemical bond is produced between the two sapphire substrates, the bonding energy of which is greater than 0.2 mJ/cm ² , forming a tightly bonded composite substrate or composite wafer. In this embodiment, the bonded first sapphire substrate 102 a and the second sapphire substrate 102 b together serve as an anti-stress layer, and one of the substrates (such as the first substrate 100 a ) serves as a supporting substrate. The other substrate (eg, the second substrate 100 b ) is thinned by a planarization process, so that its thickness is between 2-300 μm. At the same time, the surface of the second substrate 100 b has a <111> crystal lattice direction, which can be used as an epitaxial foundation layer for GaN-HEMT epitaxial growth.

The advantage of this embodiment is that a composite substrate containing silicon substrate/sapphire substrate can be used to produce a three-layer structure of supporting substrate/anti-stress layer/epitaxy base layer through a very simple bonding process, as shown in Figure 5 , the lowermost first substrate 100a serves as a supporting substrate, the bonded first sapphire substrate 102a and second sapphire substrate 102b in the middle serve as an anti-stress layer, and the uppermost thinned second substrate 100b serves as an epitaxial base layer .

Referring back to FIG. 5, after the two composite substrates are bonded, regularly arranged and evenly distributed micropatterns 106 are formed on the thinned second substrate 100b, and the height of the pattern can be 0.2-5 μm. As shown in the figure, the cross sections of the micropatterns 106 are evenly distributed on the second sapphire substrate 102b, and the second substrate 100b after the formation of the micropatterns 106 does not expose the second sapphire substrate 102b below. In this embodiment, the micropattern 106 with a triangular cross-section can be directly formed by etching the second substrate 100 b having a <111> lattice orientation by an isotropic etching process.

In the embodiment of the present invention, micropatterns 106, such as triangular cross-section micropatterns, are formed on the epitaxial base surface, because these micropatterns have slopes in the <111> lattice direction, which can achieve the desired lateral direction. Epitaxial growth (epitaxial lateral overgrowth, ELOG) function. Such an epitaxy method can bend the generated defects during the epitaxy process to avoid increased defect diffusion. At the same time, the micropattern 106 with a triangular cross-section can also absorb the stress during epitaxial growth at the epitaxial interface, which helps to produce a GaN epitaxial layer with low defect density and high epitaxial quality.

In other embodiments, the micro-pattern 106 can also be formed through a photolithography process to form a triangular cross-sectional pattern different from that shown above. As shown in FIG. 6, the step can include forming a A patterned photoresist (not shown), the photoresist has been defined with a micro pattern 106 through steps such as exposure and development. Anisotropic dry etching is then performed using the photoresist as a mask to transfer the micropattern 106 on the photoresist to the second substrate 100b, and then remove the photoresist. In other embodiments, screen printing or laser engraving may also be used to form the micropattern 106 on the surface of the sapphire substrate 102 .

Referring again to FIG. 6, in this embodiment, the difference from the previous embodiments is that due to the use of photoresist and anisotropic etching processes, the micropattern 106 has a rectangular cross section, that is, it has straight side walls, and Unlike the triangular cross section in the previous embodiments. Furthermore, the micropattern 106 will expose the underlying second sapphire substrate 102b, and an oxidation process may be performed after the second substrate 100b is patterned to form a conformal silicon oxide layer 108 on its surface. In this embodiment, the epitaxial growth starts from the surface of the second sapphire substrate 102b having a lattice direction of <100>, and since the silicon oxide layer 108 is formed on the surface of the second silicon substrate 100b, the epitaxial layer No growth will occur from the surface of the second substrate 100b.

Now refer to Figure 7. In this embodiment, different from the previous embodiments, the formed micropattern 106 presents a trapezoidal shape that tapers from bottom to top in a cross-sectional view. In terms of manufacturing process, it is also possible to firstly form a patterned photoresist (not shown) on the surface of the second substrate 100 b through photolithography, and the photoresist has been defined with micropatterns 106 through steps such as exposure and development. An isotropic dry etching process or a wet etching process is performed using the photoresist as a mask to transfer the micropattern 106 on the photoresist to the second substrate 100b, and then the photoresist is removed. Due to the isotropic dry etching process, the formed micropattern 106 has slopes in the lattice direction. Similar to the foregoing embodiments, an oxidation process may be performed after the second substrate 100 b is patterned to form a conformal silicon oxide layer 108 on the surface. In this embodiment, since the micropattern 106 has an inclined surface, it can achieve the desired effect of lateral epitaxial growth, and can bend the generated defects during the epitaxial process to avoid increased defect diffusion. At the same time, since in this embodiment, there are undercut features 106a at the bottom of the micropattern 106, holes are easily formed at the positions of these undercut features 106a during subsequent epitaxial growth, which helps to reduce the stress during epitaxial growth. , to produce a GaN epitaxial layer with low defect density and high epitaxial quality.

In addition to the above-mentioned embodiments, in other embodiments, the micropattern 106 can also be formed through a hard mask. For example, as shown in FIG. 8 , firstly, an oxidation reaction or a nitriding reaction is performed on the silicon second substrate 100b to form a high-temperature silicon oxide or silicon nitride masking layer 110 . Afterwards, a patterned photoresist (not shown) is formed on the surface of the shielding layer 110 , and the photoresist has been defined with micropatterns 106 through steps such as exposure and development. Then use the photoresist as a mask to perform a dry etching or wet etching process, transfer the micropattern 106 on the photoresist to the masking layer 110, and expose the silicon second substrate 100b under the masking layer 110 through the transferred micropattern 106 , the etching operation is stopped when the second substrate 100b is exposed, and then the photoresist is removed. Next, an isotropic dry etching or wet etching process is performed using the masking layer 110 as an etching mask to transfer the micropattern 106 to the second substrate 100b. It should be noted that in this embodiment, the formed micropattern 106 does not completely extend through the second substrate 100b, that is, it does not expose the underlying second sapphire substrate 102b. In addition, the cross-section of the micropattern 106 in this embodiment is in the shape of an inverted trapezoid. Furthermore, another shielding layer 112 can be formed on the bottom surface of the micropattern 106 after the formation of the micropattern 106 , which can also be formed through an oxidation reaction or a nitridation reaction. The step of forming the masking layer 112 may include: performing an oxidation reaction or a nitriding reaction on the silicon second substrate 100b again to form a silicon oxide or silicon nitride material on its surface (including the slope and the bottom surface of the micropattern 106 ). Masking layer 112 . Next, perform a photolithography process to remove the masking layer 112 on the slope of the micropattern 106, for example, use a photoresist to cover the masking layer 110 and the masking layer 112 on the bottom surface of the micropattern 106, and then perform an etching process, so that only the masking layer 112 on the micropattern 106 is left. Masking layer 112 on the bottom surface of 106.

The advantage of this embodiment is that the slope of the inverted trapezoidal micropattern 106 is the exposed silicon substrate in the <111> lattice direction, and the top and bottom planes of the <100> lattice direction are covered by the masking layers 110 and 112, respectively. Shielding, in subsequent epitaxy growth, the epitaxy will only grow from the exposed silicon <111> slope, which can achieve the desired side epitaxy growth effect, and the epitaxy growth of the top and bottom The shielding layers 110 and 112 can cover the surface of the original silicon second substrate 100 b in the <100> lattice direction, preventing epitaxial deposition from the lattice direction. Such an epitaxy method can bend the generated defects during the epitaxy process to avoid increased defect diffusion. At the same time, the micro-pattern 106 with inverted trapezoidal cross-section can absorb the stress during epitaxial growth at the epitaxial interface, which helps to produce a GaN epitaxial layer with low defect density and high epitaxial quality.

Please refer to FIG. 9 , which is a schematic top view of an example of regularly arranged micropatterns 106 formed on the surface of the second silicon substrate 100 b according to a preferred embodiment of the present invention. In the embodiment of the present invention, the micropattern 106 can be linear or polygonal in the top view, and it can be evenly and regularly distributed on the surface of the second substrate 100b, the width of the pattern can be 0.5-5 μm, and the distance between the patterns can be 0.5~10μm.

Now refer to Figure 10. After the micropattern 106 is formed on the surface of the second substrate 100b, an epitaxy process is performed to form an epitaxial layer 114 on the surface of the second substrate 100b with the micropattern 106. More specifically, taking the embodiment in FIG. 6 as an example, a gallium nitride (GaN) epitaxial layer 114 can be grown on the surface of the second substrate 100b by metal organic chemical vapor deposition (MOCVD), and the formed The epitaxial layer 114 may include a polar, semi-polar or non-polar GaN epitaxial layer. In practice, gallium nitride devices can be fabricated on the composite substrate provided by the present invention, and its structural sequence may include nucleation layer, buffer layer, high reflection layer, channel layer and/or barrier layer, etc. layer structure. Since the focus of the present invention is not on the manufacture of GaN devices, only an epitaxial layer 114 is shown in the embodiment. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: supporting substrate 100a: first substrate 100b: second substrate 102: Sapphire substrate 102a: first sapphire substrate 102b: second sapphire substrate 104: Silicon oxide layer 105: Silicon oxide layer 106: Micro pattern 106a: Undercut feature 108: silicon oxide 110: masking layer 112: masking layer 114: epitaxial layer

This specification contains drawings and constitutes a part of this specification, so that readers can have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain its principles. In these diagrams: Figure 1 is a schematic cross-sectional view of bonding a sapphire substrate to a silicon substrate according to a preferred embodiment of the present invention; Figure 2 is a schematic cross-sectional view of bonding a sapphire substrate to a silicon oxide layer formed on a silicon substrate according to a preferred embodiment of the present invention; Figure 3 is a schematic cross-sectional view of forming a silicon oxide stress compensation layer on the back of a silicon substrate according to a preferred embodiment of the present invention; Figure 4 is a schematic cross-sectional view of a common anti-stress layer formed by butting the anti-stress layers on two silicon substrates according to another embodiment of the present invention; Figure 5 is a schematic cross-sectional view of regularly arranged micropatterns formed on the surface of a silicon substrate on the anti-stress layer according to a preferred embodiment of the present invention; Figure 6 is a schematic cross-sectional view of regularly arranged micropatterns formed on the surface of a silicon substrate on the anti-stress layer according to another embodiment of the present invention; Figure 7 is a schematic cross-sectional view of regularly arranged micropatterns formed on the surface of a silicon substrate on the anti-stress layer according to another embodiment of the present invention; Figure 8 is a schematic cross-sectional view of regularly arranged micropatterns formed on the surface of a silicon substrate on the anti-stress layer according to another embodiment of the present invention; Figure 9 is a top schematic view of an example of regularly arranged micropatterns formed on the surface of a silicon substrate on the anti-stress layer according to a preferred embodiment of the present invention; and FIG. 10 is a schematic cross-sectional view of growing an epitaxial layer on a micropattern formed on the surface of a silicon substrate according to a preferred embodiment of the present invention. It should be noted that all the diagrams in this manual are illustrations in nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the diagram may be exaggerated or reduced. Generally speaking, the The same reference symbols will be used to designate corresponding or similar component features in modified or different embodiments.

100a: first substrate

100b: second substrate

102a: first sapphire substrate

102b: second sapphire substrate

106: Micro pattern

108: Silicon oxide layer

114: epitaxial layer

Claims (18)

A composite substrate for epitaxy growth, comprising: a substrate; At least one anti-stress layer is directly and tightly bonded to the substrate; A crystalline silicon layer, which is directly and tightly bonded to the anti-stress layer, and has micropatterns formed thereon; and An epitaxial layer is formed on the surface of the crystalline silicon layer with micropatterns. The composite substrate for epitaxial growth as described in item 1 of the scope of the patent application, wherein the substrate is a silicon substrate, a silicon carbide substrate or a silicon germanium substrate. The composite substrate for epitaxial growth as described in item 2 of the scope of the patent application, wherein a silicon oxide layer is formed between the substrate and the stress-resisting layer. The composite substrate for epitaxy growth as described in item 1 of the scope of the patent application, wherein the anti-stress layer is a sapphire substrate. The composite substrate for epitaxial growth as described in item 1 of the scope of the patent application, wherein the anti-stress layer includes: a first sapphire substrate, directly bonded to the substrate; and A second sapphire substrate, the two sides of which are respectively directly and closely bonded to the first sapphire substrate and the crystalline silicon layer. The composite substrate for epitaxial growth as described in item 1 of the scope of the patent application, wherein the micropattern of the crystalline silicon layer is linear or polygonal in the top view angle, and inverted trapezoidal in the cross-sectional angle of view, tapered downward, upward Tapered trapezoid, or inverted triangle. The composite substrate for epitaxial growth as described in item 1 of the scope of the patent application, wherein the above-mentioned anti-stress layer is exposed from the above-mentioned micropattern. The composite substrate for epitaxial growth as described in item 7 of the scope of the patent application further includes a silicon oxide layer formed on the crystalline silicon layer and not formed on the anti-stress layer. In the composite substrate for epitaxial growth described in item 1 of the scope of the patent application, a stress compensation layer made of silicon oxide is further formed on the back surface of the substrate. The composite substrate for epitaxial growth as described in item 1 of the scope of the patent application, wherein the epitaxial layer is a gallium nitride layer. A method for manufacturing a composite substrate for epitaxial growth, comprising: providing a first substrate and a second substrate; bonding a first anti-stress layer on the first substrate, and bonding a second anti-stress layer on the second substrate; performing high-temperature heat treatment on the bonded first substrate and the first stress-resistant layer and the bonded second substrate and the second stress-resistant layer in an oxygen-containing environment, so that the first substrate and the first The anti-stress layer is bonded, and the second substrate is bonded to the second anti-stress layer; Bonding the second anti-stress layer and the first anti-stress layer by performing high-temperature heat treatment in an oxygen-containing environment, so that the first anti-stress layer and the second anti-stress layer together serve as an anti-stress layer; and A photolithography process is performed to form regularly arranged micropatterns on the surface of the second substrate. The method for manufacturing a composite substrate for epitaxial growth as described in claim 11 of the patent application further includes performing an epitaxial process on the surface of the second substrate having the above-mentioned micropattern to form an epitaxial layer. The method for manufacturing a composite substrate for epitaxial growth as described in item 12 of the scope of the patent application, wherein the epitaxial process is a lateral epitaxial growth process. The method for manufacturing a composite substrate for epitaxial growth as described in claim 11 of the patent application further includes performing a high-temperature oxidation treatment on the first substrate before bonding the first anti-stress layer to the first substrate, A silicon oxide layer is formed on the surface of the first substrate and bonded with the first anti-stress layer. The method for manufacturing a composite substrate for epitaxial growth as described in item 11 of the scope of the patent application further includes bonding the first anti-stress layer to the second anti-stress layer before bonding the first anti-stress layer to the second anti-stress layer The second anti-stress layer is planarized so that the first anti-stress layer and the second anti-stress layer have specific thicknesses. The method for making a composite substrate for epitaxial growth as described in item 11 of the scope of the patent application further includes forming a shielding layer on the surface of the second substrate before forming the above-mentioned micropattern on the surface of the second substrate. The etching process first forms the micropattern on the surface of the masking layer, and then uses the masking layer as an etching mask to perform an etching process to etch the second substrate exposed from the micropattern, so that the micropattern extends to the second substrate middle. The method for manufacturing a composite substrate for epitaxial growth as described in claim 16 of the patent application further includes forming the above-mentioned shielding layer by oxidation reaction or nitriding reaction. The method for manufacturing a composite substrate for epitaxial growth as described in claim 11 further includes performing a planarization treatment on the second substrate before forming the micropattern, so that the second substrate has a specific thickness.

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