[go: up one dir, main page]

TW202203413A - Electrostatic discharge protection device and circuit - Google Patents

Electrostatic discharge protection device and circuit Download PDF

Info

Publication number
TW202203413A
TW202203413A TW109122188A TW109122188A TW202203413A TW 202203413 A TW202203413 A TW 202203413A TW 109122188 A TW109122188 A TW 109122188A TW 109122188 A TW109122188 A TW 109122188A TW 202203413 A TW202203413 A TW 202203413A
Authority
TW
Taiwan
Prior art keywords
pnp
region
electrostatic discharge
doped
base
Prior art date
Application number
TW109122188A
Other languages
Chinese (zh)
Other versions
TWI732615B (en
Inventor
林文新
黃曄仁
邱俊榕
李建興
Original Assignee
世界先進積體電路股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 世界先進積體電路股份有限公司 filed Critical 世界先進積體電路股份有限公司
Priority to TW109122188A priority Critical patent/TWI732615B/en
Application granted granted Critical
Publication of TWI732615B publication Critical patent/TWI732615B/en
Publication of TW202203413A publication Critical patent/TW202203413A/en

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

An electrostatic discharge protection device including a substrate, a first PNP element, a second PNP element and an isolation region. The substrate has a P-type conductivity. The first and second PNP elements are formed in the substrate. The isolation region isolates the first and second PNP elements.

Description

靜電放電保護裝置及電路Electrostatic discharge protection device and circuit

本發明係有關於一種靜電放電保護裝置,特別是有關於一種具有串接式PNP元件的靜電放電保護裝置。The present invention relates to an electrostatic discharge protection device, in particular to an electrostatic discharge protection device with series-connected PNP elements.

因靜電放電所造成之元件損害對積體電路產品來說已經成為最主要的可靠度問題之一。尤其是隨著尺寸不斷地縮小至深次微米之程度,金氧半導體之閘極氧化層也越來越薄,積體電路更容易因靜電放電現象而遭受破壞。在一般的工業標準中,積體電路產品之輸出入接腳(I/O pin)必需能夠通過2000伏特以上之人體模式靜電放電測試以及200伏特以上之機械模式靜電放電測試。因此,在積體電路產品中,靜電放電防護元件必需設置在所有輸出入銲墊(pad)附近,以保護內部之核心電路(core circuit)不受靜電放電電流之侵害。Component damage caused by electrostatic discharge has become one of the most important reliability issues for integrated circuit products. In particular, as the size continues to shrink to the depth of sub-micron, the gate oxide layer of the metal oxide semiconductor is getting thinner and thinner, and the integrated circuit is more likely to be damaged by the phenomenon of electrostatic discharge. In general industry standards, the I/O pins of integrated circuit products must be able to pass the human body model electrostatic discharge test above 2000 volts and the mechanical model electrostatic discharge test above 200 volts. Therefore, in integrated circuit products, ESD protection components must be arranged near all the input and output pads to protect the internal core circuits from ESD currents.

本發明之一實施例提供一種靜電放電保護裝置,包括一基底、一第一PNP元件、一第二PNP元件以及一隔離區。基底具有一P型導電性。第一PNP元件包括一第一井區、一第一摻雜區以及一第二摻雜區。第一井區形成於基底之中,並具有一N型導電性。第一摻雜區形成於第一井區之中,並具有P型導電性。第二摻雜區形成於第一井區之中,並具有P型導電性。第二PNP元件包括一第二井區、一第三摻雜區以及一第四摻雜區。第二井區形成於基底之中,並具有N型導電性。第三摻雜區形成於第二井區之中,並具有P型導電性。第四摻雜區形成於第二井區之中,並具有P型導電性。隔離區形成於基底中,並分隔第一PNP元件及第二PNP元件。An embodiment of the present invention provides an electrostatic discharge protection device including a substrate, a first PNP element, a second PNP element, and an isolation region. The substrate has a P-type conductivity. The first PNP element includes a first well region, a first doping region and a second doping region. The first well region is formed in the substrate and has an N-type conductivity. The first doped region is formed in the first well region and has P-type conductivity. The second doped region is formed in the first well region and has P-type conductivity. The second PNP element includes a second well region, a third doping region and a fourth doping region. The second well region is formed in the substrate and has N-type conductivity. The third doped region is formed in the second well region and has P-type conductivity. The fourth doped region is formed in the second well region and has P-type conductivity. An isolation region is formed in the substrate and separates the first PNP element and the second PNP element.

為讓本發明之目的、特徵和優點能更明顯易懂,下文特舉出實施例,並配合所附圖式,做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本發明。另外,實施例中圖式標號之部分重覆,係為了簡化說明,並非意指不同實施例之間的關聯性。In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. The present specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, and not for limiting the present invention. In addition, parts of the reference numerals in the drawings in the embodiments are repeated for the purpose of simplifying the description, and do not mean the correlation between different embodiments.

第1圖為本發明之靜電放電保護裝置之示意圖。如圖所示,靜電放電保護裝置100包括一基底110、PNP元件120及130。基底110具有P型導電性。在一可能實施例中,基底110可為一半導體基板,例如矽基板。此外,上述半導體基板亦可為元素半導體,包括鍺(germanium);化合物半導體,包括碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide);合金半導體,包括矽鍺合金(SiGe)、磷砷鎵合金(GaAsP)、砷鋁銦合金(AlInAs)、砷鋁鎵合金(AlGaAs)、砷銦鎵合金(GaInAs)、磷銦鎵合金(GaInP)及/或磷砷銦鎵合金(GaInAsP)或上述材料之組合。此外,基底110也可以是絕緣層上覆半導體(semiconductor on insulator)。在一實施例中,基底110可為未摻雜之基板。然而,在其它實施例中,基底110亦可為輕摻雜之基板,例如輕摻雜之P型基板。FIG. 1 is a schematic diagram of the electrostatic discharge protection device of the present invention. As shown, the ESD protection device 100 includes a substrate 110 , PNP elements 120 and 130 . The substrate 110 has P-type conductivity. In a possible embodiment, the base 110 may be a semiconductor substrate, such as a silicon substrate. In addition, the above-mentioned semiconductor substrate can also be an elemental semiconductor, including germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, and indium phosphide ), indium arsenide and/or indium antimonide; alloy semiconductors, including silicon germanium (SiGe), gallium arsenide phosphorous (GaAsP), aluminum indium arsenide (AlInAs), aluminum arsenic gallium Alloy (AlGaAs), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphate (GaInP) and/or Gallium Indium Arsenide Phosphorus (GaInAsP) or a combination of the above materials. In addition, the substrate 110 may also be a semiconductor on insulator. In one embodiment, the substrate 110 may be an undoped substrate. However, in other embodiments, the substrate 110 can also be a lightly doped substrate, such as a lightly doped P-type substrate.

PNP元件120包括一井區121、摻雜區122及123。井區121形成於基底110之中,並具有N型導電性。本發明並不限定如何形成井區121。在一可能實施例中,可藉由離子佈植步驟形成井區121。舉例而言,於預定形成井區121之區域佈植磷離子或砷離子以形成井區121。在其它實施例中,井區121係為一高壓N型井區(high voltage N well;HVNW)。The PNP device 120 includes a well region 121 , doped regions 122 and 123 . The well region 121 is formed in the substrate 110 and has N-type conductivity. The present invention does not limit how the well region 121 is formed. In one possible embodiment, the well region 121 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions are implanted in the region where the well region 121 is to be formed to form the well region 121 . In other embodiments, the well 121 is a high voltage N well (HVNW).

摻雜區122及123形成於井區121之中,並具有P型導電性。在本實施例中,摻雜區122及123的雜質濃度高於基底110的雜質濃度。在一可能實施例中,藉由植入P型雜質以形成P+型摻雜區122及123。P型雜質包括例如硼、鎵、鋁、銦、或其結合的雜質。在一可能實施例中,摻雜區122作為PNP元件120的一集極(collector)、摻雜區123作為PNP元件120的一射極(emitter)、井區121作為PNP元件120的一基極(base)。The doped regions 122 and 123 are formed in the well region 121 and have P-type conductivity. In this embodiment, the impurity concentrations of the doped regions 122 and 123 are higher than the impurity concentration of the substrate 110 . In a possible embodiment, P+ type doped regions 122 and 123 are formed by implanting P type impurities. P-type impurities include impurities such as boron, gallium, aluminum, indium, or a combination thereof. In a possible embodiment, the doped region 122 serves as a collector of the PNP element 120 , the doped region 123 serves as an emitter of the PNP element 120 , and the well region 121 serves as a base of the PNP element 120 (base).

在其它實施例中,PNP元件120更包括一摻雜區124、隔離區125與126。摻雜區124具有N型導電性,並作為井區121的電接觸點。在本實施例中,摻雜區124的雜質濃度高於井區121的雜質濃度。在一可能實施例中,藉由植入N型雜質以形成N+型摻雜區124。在一些實施例中,摻雜區122~124係藉由一圖案化罩幕(未顯示)配合執行一植入步驟所形成。In other embodiments, the PNP device 120 further includes a doped region 124 , and isolation regions 125 and 126 . The doped regions 124 have N-type conductivity and serve as electrical contacts for the well regions 121 . In this embodiment, the impurity concentration of the impurity region 124 is higher than that of the well region 121 . In a possible embodiment, the N+ type doped region 124 is formed by implanting N type impurities. In some embodiments, the doped regions 122-124 are formed by performing an implantation step in conjunction with a patterned mask (not shown).

隔離區125與126形成於基底110的表面並延伸進入井區121之中。在本實施例中,隔離區125位於摻雜區122及123之間,用以分隔摻雜區122及123。隔離區126位於摻雜區123及124之間,用以分隔摻雜區123及124。在一些實施例中,隔離區125與126可為場氧化物(field oxide;FOX)。在一些實施例中,隔離區125與126可為局部矽氧化(local oxidation of silicon;LOCOS)或淺溝槽隔離(shallow trench isolation;STI)結構。在其它實施例中,隔離區125與126的材料可為氧化矽、氮化矽、氮氧化矽、其他合適的介電材料、或上述之組合。Isolation regions 125 and 126 are formed on the surface of the substrate 110 and extend into the well region 121 . In this embodiment, the isolation region 125 is located between the doped regions 122 and 123 for separating the doped regions 122 and 123 . The isolation region 126 is located between the doped regions 123 and 124 for separating the doped regions 123 and 124 . In some embodiments, isolation regions 125 and 126 may be field oxides (FOX). In some embodiments, the isolation regions 125 and 126 may be local oxidation of silicon (LOCOS) or shallow trench isolation (STI) structures. In other embodiments, the isolation regions 125 and 126 may be made of silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof.

PNP元件130至少包括一井區131、摻雜區132及133。井區131形成於基底110之中,並具有N型導電性。由於井區131的特性與井區121的特性相似,故不再贅述。在本實施例中,井區131並未接觸井區121。在一些實施例中,井區131的雜質濃度相似於井區121的雜質濃度,但並非用以限制本發明。在其它實施例中,井區131的雜質濃度可能低於或高於井區121的雜質濃度。舉例而言,井區121及131之一者係為高壓N型井區,而另一者為一般井區。在此例中,高壓N型井區的雜質濃度低於一般井區的雜質濃度。因此,高壓N型井區可承受較高的電壓。The PNP device 130 at least includes a well region 131 , doped regions 132 and 133 . The well region 131 is formed in the substrate 110 and has N-type conductivity. Since the characteristics of the well area 131 are similar to those of the well area 121, the details are omitted. In this embodiment, the well area 131 does not contact the well area 121 . In some embodiments, the impurity concentration of the well region 131 is similar to the impurity concentration of the well region 121, but is not intended to limit the present invention. In other embodiments, the impurity concentration of the well region 131 may be lower or higher than the impurity concentration of the well region 121 . For example, one of the wells 121 and 131 is a high pressure N-type well, and the other is a general well. In this example, the impurity concentration of the high-voltage N-type well region is lower than that of the general well region. Therefore, the high-voltage N-type well region can withstand higher voltages.

摻雜區132及133形成於井區131之中。摻雜區132及133具有P型導電性。在本實施例中,摻雜區132及133的雜質濃度高於基底110的雜質濃度。在一可能實施例中,摻雜區132及133的雜質濃度相似於摻雜區122及123的雜質濃度。由於摻雜區132及133的特性相似於摻雜區122及123的特性,故不再贅述。在一可能實施例中,摻雜區132作為PNP元件130的一集極、摻雜區133作為PNP元件130的一射極、井區131作為PNP元件130的一基極。Doped regions 132 and 133 are formed in the well region 131 . The doped regions 132 and 133 have P-type conductivity. In this embodiment, the impurity concentrations of the doped regions 132 and 133 are higher than the impurity concentration of the substrate 110 . In a possible embodiment, the impurity concentrations of the doped regions 132 and 133 are similar to the impurity concentrations of the doped regions 122 and 123 . Since the characteristics of the doped regions 132 and 133 are similar to those of the doped regions 122 and 123 , they will not be described again. In a possible embodiment, the doped region 132 serves as a collector of the PNP element 130 , the doped region 133 serves as an emitter of the PNP element 130 , and the well region 131 serves as a base of the PNP element 130 .

在其它實施例中,PNP元件130更包括一摻雜區134、隔離區135與136。摻雜區134具有N型導電性,並作為井區131的電接觸點。在本實施例中,摻雜區134的雜質濃度高於井區131的雜質濃度,並相似於摻雜區124的雜質濃度。由於摻雜區134的特性相似於摻雜區124的特性,故不再贅述。In other embodiments, the PNP device 130 further includes a doped region 134 and isolation regions 135 and 136 . The doped regions 134 have N-type conductivity and serve as electrical contacts for the well regions 131 . In this embodiment, the impurity concentration of the impurity region 134 is higher than that of the well region 131 and is similar to the impurity concentration of the impurity region 124 . Since the characteristics of the doped region 134 are similar to those of the doped region 124, the details are not repeated here.

隔離區135與136形成於基底110的表面並延伸進入井區131之中。在本實施例中,隔離區135位於摻雜區132及133之間,用以分隔摻雜區132及133。隔離區136位於摻雜區133及134之間,用以分隔摻雜區133及134。由於隔離區135及136的特性相似於隔離區125及126的特性,故不再贅述。Isolation regions 135 and 136 are formed on the surface of the substrate 110 and extend into the well region 131 . In this embodiment, the isolation region 135 is located between the doped regions 132 and 133 for separating the doped regions 132 and 133 . The isolation region 136 is located between the doped regions 133 and 134 for separating the doped regions 133 and 134 . Since the characteristics of the isolation regions 135 and 136 are similar to the characteristics of the isolation regions 125 and 126 , detailed descriptions are omitted.

在本實施例中,靜電放電保護裝置100更包括一隔離區152。隔離區152形成於基底110的表面,並延伸進入井區121及131。隔離區152用以分隔PNP元件120及130。在此例中,隔離區152位於摻雜區124與132之間。在一可能實施例中,隔離區152直接接觸摻雜區124及132。In this embodiment, the ESD protection device 100 further includes an isolation region 152 . The isolation region 152 is formed on the surface of the substrate 110 and extends into the well regions 121 and 131 . The isolation region 152 is used to separate the PNP devices 120 and 130 . In this example, isolation region 152 is located between doped regions 124 and 132 . In a possible embodiment, isolation region 152 is in direct contact with doped regions 124 and 132 .

在其它實施例中,靜電放電保護裝置100更包括一摻雜區140。摻雜區140形成於基底110中,並具有P型導電性。在一可能實施例中,摻雜區140的雜質濃度相似於摻雜區122的雜質濃度。由於摻雜區140的特性相似於摻雜區122的特性,故不再贅述。在本實施例中,摻雜區140作為基底110的電接觸點。In other embodiments, the ESD protection device 100 further includes a doped region 140 . The doped region 140 is formed in the substrate 110 and has P-type conductivity. In a possible embodiment, the impurity concentration of the doped region 140 is similar to the impurity concentration of the doped region 122 . Since the characteristics of the doped region 140 are similar to those of the doped region 122, the details are omitted. In this embodiment, the doped region 140 serves as an electrical contact point for the substrate 110 .

在一些實施例中,靜電放電保護裝置100更包括隔離區151及153。隔離區151形成於基底110的表面,並延伸進入井區121及基底110。在本實施例中,隔離區151用以分隔摻雜區140及PNP元件120。另外,隔離區153形成於基底110的表面,並延伸進入井區131及基底110。隔離區153用以分隔PNP元件130與其它元件(未顯示)。In some embodiments, the ESD protection device 100 further includes isolation regions 151 and 153 . The isolation region 151 is formed on the surface of the substrate 110 and extends into the well region 121 and the substrate 110 . In this embodiment, the isolation region 151 is used to separate the doped region 140 and the PNP device 120 . In addition, the isolation region 153 is formed on the surface of the substrate 110 and extends into the well region 131 and the substrate 110 . The isolation region 153 is used to separate the PNP device 130 from other devices (not shown).

本發明並不限定隔離區151~153的尺寸。在一可能實施例中,隔離區152的寬度(水平方向)大於隔離區151及153的寬度。舉例而言,摻雜區124與132之間的距離大於摻雜區140與122之間的距離。摻雜區124與132之間的距離也大於摻雜區134與另一摻雜區(未顯示)之間的距離。在其它實施例中,隔離區125、126、135及136的寬度小於隔離區151的寬度。在此例中,隔離區125、126、135及136的寬度相似。The present invention does not limit the size of the isolation regions 151 to 153 . In a possible embodiment, the width (horizontal direction) of the isolation region 152 is larger than the widths of the isolation regions 151 and 153 . For example, the distance between doped regions 124 and 132 is greater than the distance between doped regions 140 and 122 . The distance between doped regions 124 and 132 is also greater than the distance between doped region 134 and another doped region (not shown). In other embodiments, the widths of the isolation regions 125 , 126 , 135 and 136 are smaller than the width of the isolation region 151 . In this example, isolation regions 125, 126, 135, and 136 are similar in width.

在一可能實施例中,靜電放電保護裝置100更包括走線161~163。走線161電性連接摻雜區140及122。在一可能實施例中,走線161耦接至一電壓源VL。走線162電性連接摻雜區123、124及132。走線163電性連接摻雜區133及134。在一可能實施例中,走線163耦接至一電壓源VH。在正常操作下(無靜電放電事件),電壓源VH用以接收一高操作電壓,電壓源VL可能接收一低操作電壓,如接地電壓。In a possible embodiment, the electrostatic discharge protection device 100 further includes wirings 161 - 163 . The traces 161 are electrically connected to the doped regions 140 and 122 . In a possible embodiment, the trace 161 is coupled to a voltage source VL. The traces 162 are electrically connected to the doped regions 123 , 124 and 132 . The traces 163 are electrically connected to the doped regions 133 and 134 . In a possible embodiment, the trace 163 is coupled to a voltage source VH. Under normal operation (no ESD events), the voltage source VH is used to receive a high operating voltage, and the voltage source VL may receive a low operating voltage, such as a ground voltage.

當一靜電放電事件發生於電壓源VH並且電壓源VL接地時, PNP元件130及120依序導通。因此,一靜電放電電流由電壓源VH流經摻雜區133、井區131、摻雜區132、摻雜區123、井區121、摻雜區122流入電壓源VL。此時,由於井區131的電壓上升,故一電流流入基底110,使得基底110的電壓上升,因而導通PNP元件130及120之間的一具有P型基底的NPN元件。在此例中,井區131、121及基底110構成一P型基底的NPN元件。井區131作為該P型基底的NPN元件的集極、井區121作為該具有P型基底的NPN元件的射極,基底110作為該具有P型基底的NPN元件的基極。由於具有P型基底的NPN元件導通,故可減少PNP元件130及120的導通電阻的阻抗。因此,靜電放電保護裝置100可承受更高的電流,並增加靜電放電保護裝置100的維持電壓(holding voltage),以避免靜電放電保護裝置100在正常工作(無靜電放電事件)下被閂鎖(latch up)。此外,具有P型基底的NPN元件可以為寄生元件(parasitic element),或因摻雜而產生之NPN元件,本發明並不以此為限。When an electrostatic discharge event occurs at the voltage source VH and the voltage source VL is grounded, the PNP elements 130 and 120 are turned on in sequence. Therefore, an electrostatic discharge current flows from the voltage source VH through the doped region 133 , the well region 131 , the doped region 132 , the doped region 123 , the well region 121 , and the doped region 122 into the voltage source VL. At this time, since the voltage of the well region 131 rises, a current flows into the substrate 110 , so that the voltage of the substrate 110 rises, thereby turning on an NPN element with a P-type substrate between the PNP elements 130 and 120 . In this example, the well regions 131, 121 and the substrate 110 constitute a P-type substrate NPN device. The well region 131 serves as the collector of the NPN element with the P-type substrate, the well region 121 serves as the emitter of the NPN element with the P-type substrate, and the substrate 110 serves as the base of the NPN element with the P-type substrate. Since the NPN element having the P-type substrate is turned on, the resistance of the on-resistance of the PNP elements 130 and 120 can be reduced. Therefore, the ESD protection device 100 can withstand a higher current and increase the holding voltage of the ESD protection device 100 to prevent the ESD protection device 100 from being latched up (with no ESD event) during normal operation (no ESD event). latch up). In addition, the NPN element with the P-type substrate may be a parasitic element, or an NPN element generated by doping, and the present invention is not limited thereto.

第2圖為第1圖之靜電放電保護裝置的等效電路示意圖。如圖所示,靜電放電保護裝置100包括PNP元件120、130以及一具有P型基底的NPN元件200。PNP元件120的射極E1係為第1圖的摻雜區123。PNP元件120的集極C1係為第1圖的摻雜區122。PNP元件120的基極B1係為第1圖的井區121。在本實施例中,PNP元件120的射極E1與基極B1之間具有一電阻R121。在此例中,電阻R121係為井區121的等效電阻。另外,PNP元件120的集極C1透過走線(如第1圖的走線161),電性連接至電壓源VL。FIG. 2 is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device of FIG. 1 . As shown, the ESD protection device 100 includes PNP elements 120 and 130 and an NPN element 200 having a P-type substrate. The emitter E1 of the PNP element 120 is the doped region 123 in FIG. 1 . The collector C1 of the PNP element 120 is the doped region 122 in FIG. 1 . The base B1 of the PNP element 120 is the well 121 in FIG. 1 . In this embodiment, a resistor R121 is provided between the emitter E1 and the base B1 of the PNP element 120 . In this example, the resistance R121 is the equivalent resistance of the well region 121 . In addition, the collector C1 of the PNP element 120 is electrically connected to the voltage source VL through a wire (such as the wire 161 in FIG. 1 ).

PNP元件130的射極E2係為第1圖的摻雜區133。PNP元件130的集極C2係為第1圖的摻雜區132。PNP元件130的基極B2係為第1圖的井區131。在本實施例中,PNP元件130的射極E2與基極B2之間具有一電阻R131。在此例中,電阻R131係為井區131的等效電阻。另外,PNP元件130的集極C2透過走線(如第1圖的走線162),電性連接至PNP元件120的射極E1。PNP元件130的射極E2透過走線(如第1圖的走線163),電性連接至電壓源VH。The emitter E2 of the PNP element 130 is the doped region 133 in FIG. 1 . The collector C2 of the PNP element 130 is the doped region 132 in FIG. 1 . The base B2 of the PNP element 130 is the well 131 in FIG. 1 . In this embodiment, there is a resistor R131 between the emitter E2 and the base B2 of the PNP element 130 . In this example, the resistance R131 is the equivalent resistance of the well region 131 . In addition, the collector C2 of the PNP element 130 is electrically connected to the emitter E1 of the PNP element 120 through a wire (such as the wire 162 in FIG. 1 ). The emitter E2 of the PNP element 130 is electrically connected to the voltage source VH through a trace (such as the trace 163 in FIG. 1 ).

由於第1圖的井區121作為具有P型基底的NPN元件200的射極E3,故可視為具有P型基底的NPN元件200的射極E3電性連接至PNP元件120的基極B1。另外,由於第1圖的井區131作為具有P型基底的NPN元件200的集極C3,故可視為具有P型基底的NPN元件200的集極C3電性連接至PNP元件130的基極B2。在本實施例中,具有P型基底的NPN元件200的基極B3與電壓源VL之間具有一電阻R110。在此例中,電阻R110係為基底110的等效電阻。Since the well region 121 in FIG. 1 serves as the emitter E3 of the NPN element 200 with the P-type substrate, it can be considered that the emitter E3 of the NPN element 200 with the P-type substrate is electrically connected to the base B1 of the PNP element 120 . In addition, since the well region 131 in FIG. 1 serves as the collector C3 of the NPN element 200 with the P-type base, it can be considered that the collector C3 of the NPN element 200 with the P-type base is electrically connected to the base B2 of the PNP element 130 . In this embodiment, there is a resistor R110 between the base electrode B3 of the NPN element 200 having the P-type substrate and the voltage source VL. In this example, the resistor R110 is the equivalent resistance of the substrate 110 .

當一靜電放電事件發生在電壓源VH並且電壓源VL接地時,由於PNP元件130的射極E2的電壓上升,故PNP元件130導通。此時,PNP元件120的射極E1的電壓上升,故PNP元件120接著導通。因此,一靜電放電電流由電壓源VH,經PNP元件130及120,流入電壓源VL。此時,由於PNP元件130及120導通,故具有P型基底的NPN元件200也導通,因而減小PNP元件130及120導通時的等效阻抗,使得靜電放電保護裝置100具有較高的維持電壓。When an electrostatic discharge event occurs at the voltage source VH and the voltage source VL is grounded, the PNP element 130 is turned on because the voltage of the emitter E2 of the PNP element 130 rises. At this time, since the voltage of the emitter E1 of the PNP element 120 rises, the PNP element 120 is then turned on. Therefore, an electrostatic discharge current flows from the voltage source VH, through the PNP elements 130 and 120, into the voltage source VL. At this time, since the PNP elements 130 and 120 are turned on, the NPN element 200 with the P-type substrate is also turned on, thereby reducing the equivalent impedance when the PNP elements 130 and 120 are turned on, so that the electrostatic discharge protection device 100 has a higher sustaining voltage .

第3圖為本發明之靜電放電保護裝置的另一示意圖。第3圖相似第1圖,不同之處在於,第3圖的靜電放電保護裝置300更包括一PNP元件170。PNP元件170包括一井區171、摻雜區172及173。井區171形成於基底110之中,並具有N型導電性。由於井區171的特性與井區121的特性相似,故不再贅述。在本實施例中,隔離區153分隔井區131及171。在一些實施例中,井區121、131及171的雜質濃度均相同,但並非用以限制本發明。在其它實施例中,井區121、131及171之一者的雜質濃度可能低於或高於井區121、131及171之另一者的雜質濃度。舉例而言,井區121、131及171之一者為高壓N型井區,而井區121、131及171之另一者並非高壓N型井區。FIG. 3 is another schematic diagram of the electrostatic discharge protection device of the present invention. FIG. 3 is similar to FIG. 1 , except that the electrostatic discharge protection device 300 of FIG. 3 further includes a PNP element 170 . The PNP device 170 includes a well region 171 , doped regions 172 and 173 . The well region 171 is formed in the substrate 110 and has N-type conductivity. Since the characteristics of the well area 171 are similar to those of the well area 121, the details are omitted. In this embodiment, the isolation region 153 separates the well regions 131 and 171 . In some embodiments, the impurity concentrations of the well regions 121 , 131 and 171 are all the same, but are not intended to limit the present invention. In other embodiments, the impurity concentration of one of the well regions 121 , 131 and 171 may be lower or higher than the impurity concentration of the other of the well regions 121 , 131 and 171 . For example, one of the wells 121, 131 and 171 is a high pressure N-type well, while the other of the wells 121, 131 and 171 is not a high pressure N-type.

摻雜區172及173形成於井區171之中。摻雜區172及173具有P型導電性。在本實施例中,摻雜區172及173的雜質濃度高於基底110的雜質濃度。在一可能實施例中,摻雜區172及173的雜質濃度相似於摻雜區122及123的雜質濃度。由於摻雜區172及173的特性相似於摻雜區122及123的特性,故不再贅述。在本實施例中,摻雜區172作為PNP元件170的一集極、摻雜區173作為PNP元件170的一射極、井區171作為PNP元件170的一基極。Doped regions 172 and 173 are formed in the well region 171 . The doped regions 172 and 173 have P-type conductivity. In this embodiment, the impurity concentrations of the doped regions 172 and 173 are higher than the impurity concentration of the substrate 110 . In a possible embodiment, the impurity concentrations of the doped regions 172 and 173 are similar to the impurity concentrations of the doped regions 122 and 123 . Since the properties of the doped regions 172 and 173 are similar to those of the doped regions 122 and 123 , they are not described again. In this embodiment, the doped region 172 serves as a collector of the PNP element 170 , the doped region 173 serves as an emitter of the PNP element 170 , and the well region 171 serves as a base of the PNP element 170 .

在其它實施例中,PNP元件170更包括一摻雜區174及隔離區175與176。摻雜區174形成於井區171中,並具有N型導電性。在一可能實施例中,摻雜區174的雜質濃度相似於摻雜區124的雜質濃度。由於摻雜區174的特性相似於摻雜區124的特性,故不再贅述。在本實施例中,摻雜區174作為井區171的電接觸點。In other embodiments, the PNP device 170 further includes a doped region 174 and isolation regions 175 and 176 . The doped region 174 is formed in the well region 171 and has N-type conductivity. In a possible embodiment, the impurity concentration of the doped region 174 is similar to the impurity concentration of the doped region 124 . Since the characteristics of the doped region 174 are similar to those of the doped region 124, the details are not repeated here. In this embodiment, the doped region 174 serves as an electrical contact point for the well region 171 .

隔離區175與176形成於基底110的表面並延伸進入井區171之中。在本實施例中,隔離區175位於摻雜區172及173之間,用以分隔摻雜區172及173。隔離區176位於摻雜區173及174之間,用以分隔摻雜區173及174。由於隔離區175與176的特性相似於隔離區125與126的特性,故不再贅述。Isolation regions 175 and 176 are formed on the surface of the substrate 110 and extend into the well region 171 . In this embodiment, the isolation region 175 is located between the doped regions 172 and 173 for separating the doped regions 172 and 173 . The isolation region 176 is located between the doped regions 173 and 174 for separating the doped regions 173 and 174 . Since the characteristics of the isolation regions 175 and 176 are similar to the characteristics of the isolation regions 125 and 126 , detailed descriptions are omitted.

在本實施例中,隔離區153用以分隔PNP元件130及170。在此例中,隔離區153位於摻雜區134與172之間。在一可能實施例中,隔離區153直接接觸摻雜區134及172。在其它實施例中,靜電放電保護裝置300更包括一隔離區154。隔離區154形成於基底110的表面,並延伸進入井區171及基底110。隔離區154用以分隔PNP元件170與其它元件(未顯示)。本發明並不限定隔離區151~154的尺寸。在一可能實施例中,隔離區154的寬度相似於隔離區151的寬度。在其它實施例中,隔離區152及153的寬度相似,並大於隔離區151及154的寬度。在此例中,隔離區125、126、135、136、175及176的寬度相似,並小於隔離區151的寬度。In this embodiment, the isolation region 153 is used to separate the PNP elements 130 and 170 . In this example, isolation region 153 is located between doped regions 134 and 172 . In a possible embodiment, isolation region 153 is in direct contact with doped regions 134 and 172 . In other embodiments, the ESD protection device 300 further includes an isolation region 154 . The isolation region 154 is formed on the surface of the substrate 110 and extends into the well region 171 and the substrate 110 . Isolation region 154 is used to separate PNP device 170 from other devices (not shown). The present invention does not limit the size of the isolation regions 151 to 154 . In a possible embodiment, the width of the isolation region 154 is similar to the width of the isolation region 151 . In other embodiments, the widths of isolation regions 152 and 153 are similar and larger than the widths of isolation regions 151 and 154 . In this example, the widths of isolation regions 125 , 126 , 135 , 136 , 175 and 176 are similar and smaller than the width of isolation region 151 .

在一可能實施例中,靜電放電保護裝置300更包括走線164。走線164電性連接摻雜區173及174,並耦接電壓源VH。此外,走線163電性連接摻雜區133、134及172。在本實施例中,走線161~164用以將PNP元件120、130及170串接在一起。當串接的PNP元件愈多時,靜電放電保護裝置300的觸發電壓愈高,故可避免靜電放電保護裝置300在正常操作(即無靜電放電事件)被觸發。本發明並不限定PNP元件的數量。在其它實施例中,靜電放電保護裝置300具有更多的PNP元件。In a possible embodiment, the ESD protection device 300 further includes a wiring 164 . The trace 164 is electrically connected to the doped regions 173 and 174 and is coupled to the voltage source VH. In addition, the traces 163 are electrically connected to the doped regions 133 , 134 and 172 . In this embodiment, the traces 161 to 164 are used to connect the PNP elements 120 , 130 and 170 in series. When more PNP elements are connected in series, the trigger voltage of the ESD protection device 300 is higher, so that the ESD protection device 300 can be prevented from being triggered during normal operation (ie, no ESD event). The present invention does not limit the number of PNP elements. In other embodiments, the ESD protection device 300 has more PNP elements.

當一靜電放電事件發生於電壓源VH並且電壓源VL耦接至地時,PNP元件170、130及120依序導通。因此,一靜電放電電流經PNP元件170、130及120流入電壓源VL。在本實施例中,PNP元件170與130之間具有一第一具有P型基底的NPN元件,PNP元件130與120之間具有一第二具有P型基底的NPN元件,PNP元件170與120之間具有一第三具有P型基底的NPN元件。在此例中,當PNP元件170、130及120導通時,PNP元件170與130之間的第一具有P型基底的NPN元件以及PNP元件170與120之間具有的第三具有P型基底的NPN元件也會導通。When an electrostatic discharge event occurs at the voltage source VH and the voltage source VL is coupled to ground, the PNP elements 170 , 130 and 120 are turned on in sequence. Therefore, an electrostatic discharge current flows into the voltage source VL through the PNP elements 170 , 130 and 120 . In this embodiment, a first NPN element with a P-type substrate is arranged between the PNP elements 170 and 130 , a second NPN element with a P-type substrate is arranged between the PNP elements 130 and 120 , and the one between the PNP elements 170 and 120 is There is a third NPN element with a P-type substrate in between. In this example, when the PNP elements 170 , 130 and 120 are turned on, the first NPN element with a P-type substrate between the PNP elements 170 and 130 and the third NPN element with a P-type substrate between the PNP elements 170 and 120 The NPN element will also conduct.

在本實施例中,第一具有P型基底的NPN元件係由井區171、131及基底110所構成。井區171作為第一具有P型基底的NPN元件的集極,井區131作為第一具有P型基底的NPN元件的射極,基底110作為第一具有P型基底的NPN元件的基極。另外,第二具有P型基底的NPN元件係由井區131、121及基底110所構成。在此例中,井區131作為第二具有P型基底的NPN元件的集極,井區121作為第二具有P型基底的NPN元件的射極,基底110作為第二具有P型基底的NPN元件的基極。第三具有P型基底的NPN元件係由井區171、121及基底110所構成。在此例中,井區171作為第三具有P型基底的NPN元件的集極,井區121作為第三具有P型基底的NPN元件的射極,基底110作為第三具有P型基底的NPN元件的基極。In this embodiment, the first NPN element having a P-type substrate is composed of well regions 171 and 131 and the substrate 110 . The well region 171 serves as the collector of the first NPN element with a P-type substrate, the well region 131 serves as the emitter of the first NPN element with a P-type substrate, and the substrate 110 serves as the base of the first NPN element with a P-type substrate. In addition, the second NPN element with a P-type substrate is composed of the well regions 131 and 121 and the substrate 110 . In this example, the well region 131 serves as the collector of the second NPN element with a P-type substrate, the well region 121 serves as the emitter of the second NPN element with a P-type substrate, and the substrate 110 serves as the second NPN element with a P-type substrate. the base of the element. The third NPN device with a P-type substrate is composed of well regions 171 and 121 and the substrate 110 . In this example, the well region 171 serves as the collector of the third NPN element with a P-type substrate, the well region 121 serves as the emitter of the third NPN element with a P-type substrate, and the substrate 110 serves as the third NPN element with a P-type substrate. the base of the element.

當PNP元件170、130及120導通時,第一具有P型基底的NPN元件減少PNP元件170及130導通時的等效阻抗,並且第三具有P型基底的NPN元件減少PNP元件170及120導通時的等效阻抗。因此,靜電放電保護裝置300具有較高的維持電壓,並可承受較大的電流。When the PNP elements 170, 130 and 120 are turned on, the first NPN element with a P-type base reduces the equivalent impedance of the PNP elements 170 and 130 when they are turned on, and the third NPN element with a P-type base reduces the conduction of the PNP elements 170 and 120 Equivalent impedance when . Therefore, the ESD protection device 300 has a higher sustain voltage and can withstand a higher current.

第4圖為第3圖的靜電放電保護裝置300的等效電路示意圖。如圖所示,靜電放電保護裝置300包括PNP元件120、130、170以及具有P型基底的NPN元件200、400、500。由於PNP元件120、130及具有P型基底的NPN元件200的特性與第2圖的PNP元件120、130及具有P型基底的NPN元件200的特性相同,故不再贅述。FIG. 4 is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device 300 of FIG. 3 . As shown, the ESD protection device 300 includes PNP elements 120, 130, 170 and NPN elements 200, 400, 500 having a P-type substrate. Since the characteristics of the PNP elements 120 and 130 and the NPN element 200 with a P-type substrate are the same as those of the PNP elements 120 and 130 and the NPN element 200 with a P-type substrate in FIG.

在本實施例中,PNP元件170的射極E4係為第3圖的摻雜區173。PNP元件170的集極C4係為第3圖的摻雜區172。PNP元件170的基極B4係為第3圖的井區171。在本實施例中,PNP元件170的射極E4與基極B4之間具有一電阻R171。在此例中,電阻R171係為井區171的等效電阻。另外,PNP元件170的集極C4透過走線(如第3圖的走線163),電性連接至PNP元件130的射極E2。PNP元件170的射極E4透過走線(如第3圖的走線164),電性連接至電壓源VH。In this embodiment, the emitter E4 of the PNP element 170 is the doped region 173 in FIG. 3 . The collector C4 of the PNP element 170 is the doped region 172 in FIG. 3 . The base B4 of the PNP element 170 is the well 171 in FIG. 3 . In this embodiment, a resistor R171 is provided between the emitter E4 and the base B4 of the PNP element 170 . In this example, the resistance R171 is the equivalent resistance of the well region 171 . In addition, the collector C4 of the PNP element 170 is electrically connected to the emitter E2 of the PNP element 130 through a wire (such as the wire 163 in FIG. 3 ). The emitter E4 of the PNP element 170 is electrically connected to the voltage source VH through a trace (such as the trace 164 in FIG. 3 ).

由於第3圖的井區131作為具有P型基底的NPN元件400的射極E5,故可視為具有P型基底的NPN元件400的射極E5電性連接至PNP元件130的基極B2。另外,第3圖的井區171作為具有P型基底的NPN元件400的集極C5,故可視為具有P型基底的NPN元件400的集極C5電性連接至PNP元件170的基極B4。在本實施例中,具有P型基底的NPN元件400的基極B5與電壓源VL之間具有一電阻R110B。在此例中,電阻R110B係為基底110的等效電阻。Since the well region 131 in FIG. 3 serves as the emitter E5 of the NPN element 400 with the P-type substrate, it can be considered that the emitter E5 of the NPN element 400 with the P-type substrate is electrically connected to the base B2 of the PNP element 130 . In addition, the well region 171 in FIG. 3 serves as the collector C5 of the NPN element 400 with the P-type substrate, so it can be considered that the collector C5 of the NPN element 400 with the P-type substrate is electrically connected to the base B4 of the PNP element 170 . In this embodiment, there is a resistor R110B between the base B5 of the NPN element 400 having the P-type substrate and the voltage source VL. In this example, the resistor R110B is the equivalent resistance of the substrate 110 .

由於第3圖的井區121作為具有P型基底的NPN元件500的射極E6,故可視為具有P型基底的NPN元件500的射極E6電性連接至PNP元件120的基極B1。另外,第3圖的井區171作為具有P型基底的NPN元件500的集極C6,故可視為具有P型基底的NPN元件500的集極C6電性連接至PNP元件170的基極B4。在本實施例中,具有P型基底的NPN元件500的基極B6與電壓源VL之間具有一電阻R110C。在此例中,電阻R110C係為基底110的等效電阻。Since the well region 121 in FIG. 3 serves as the emitter E6 of the NPN element 500 with the P-type substrate, it can be considered that the emitter E6 of the NPN element 500 with the P-type substrate is electrically connected to the base B1 of the PNP element 120 . In addition, the well region 171 in FIG. 3 serves as the collector C6 of the NPN element 500 with the P-type substrate, so it can be considered that the collector C6 of the NPN element 500 with the P-type substrate is electrically connected to the base B4 of the PNP element 170 . In this embodiment, there is a resistor R110C between the base B6 of the NPN element 500 having the P-type substrate and the voltage source VL. In this example, the resistor R110C is the equivalent resistance of the substrate 110 .

在本實施例中,由於具有P型基底的NPN元件400和500與電壓源VL的距離比具有P型基底的NPN元件200與電壓源VL的距離遠,故電阻R110B及R110C的阻抗比電阻R110A的阻抗大。於一實施例中,可藉由調控基底110的濃度,控制電阻R110A、R110B及R110C的阻抗。於較佳實施例中,電阻R110B及R110C的電壓小於約0.7V使得具有P型基底的NPN元件400及500導通。In the present embodiment, since the distance between the NPN elements 400 and 500 having the P-type substrate and the voltage source VL is greater than the distance between the NPN element 200 having the P-type substrate and the voltage source VL, the impedances of the resistors R110B and R110C are higher than that of the resistor R110A resistance is large. In one embodiment, the resistance of the resistors R110A, R110B and R110C can be controlled by adjusting the concentration of the substrate 110 . In a preferred embodiment, the voltages of the resistors R110B and R110C are less than about 0.7V so that the NPN devices 400 and 500 with the P-type substrate are turned on.

當一靜電放電事件發生在電壓源VH並且電壓源VL接地時,由於PNP元件170的射極E4的電壓上升,故PNP元件170導通。此時,PNP元件130的射極E2的電壓上升,故PNP元件130接著導通。由於PNP元件120的射極E1的電壓上升,故PNP元件120也導通。因此,一靜電放電電流由電壓源VH,經PNP元件170、130及120,流入電壓源VL。此時,由於PNP元件170、130及120導通,故具有P型基底的NPN元件400及500也導通,因而減小PNP元件170、130及120導通時的等效阻抗,並使靜電放電保護裝置300具有較高的維持電壓。When an electrostatic discharge event occurs at the voltage source VH and the voltage source VL is grounded, the PNP element 170 is turned on because the voltage at the emitter E4 of the PNP element 170 rises. At this time, since the voltage of the emitter E2 of the PNP element 130 rises, the PNP element 130 is then turned on. Since the voltage of the emitter E1 of the PNP element 120 rises, the PNP element 120 is also turned on. Therefore, an electrostatic discharge current flows from the voltage source VH, through the PNP elements 170, 130 and 120, into the voltage source VL. At this time, since the PNP elements 170, 130 and 120 are turned on, the NPN elements 400 and 500 with the P-type substrate are also turned on, thereby reducing the equivalent impedance when the PNP elements 170, 130 and 120 are turned on, and making the electrostatic discharge protection device 300 has a higher sustain voltage.

第5A~5C圖為第1圖的靜電放電保護裝置100的製造方法。首先,請參考第5A圖,提供一基底110。在一可能實施例中,基底110可包括絕緣層上有矽(SOI)基底、塊狀矽(Bulk silicon)基底、或基底上有矽磊晶層之形式。在本實施例中,基底110具有P型導電性。FIGS. 5A-5C are the manufacturing method of the electrostatic discharge protection apparatus 100 of FIG. 1. FIG. First, referring to FIG. 5A, a substrate 110 is provided. In one possible embodiment, the substrate 110 may include a silicon-on-insulator (SOI) substrate, a bulk silicon (Bulk silicon) substrate, or a silicon-on-substrate epitaxial layer. In this embodiment, the substrate 110 has P-type conductivity.

接著,基底110內形成隔離區151~153,用以定義出PNP元件120及130的位置,並形成隔離區125、126、135及136。在本實施例中,隔離區151~153、125、126、135及136係以場氧化層為例,但並非用以限制本發明。在其它實施例中,亦可採用其他隔離結構,例如淺溝槽隔離結構。在一可能實施例中,隔離區152的尺寸大於隔離區151及153的尺寸。在此例中,隔離區151及153的尺寸大於隔離區125、126、135及136的尺寸。隔離區125、126、135及136的尺寸彼此相似。Next, isolation regions 151 to 153 are formed in the substrate 110 to define the positions of the PNP elements 120 and 130 , and the isolation regions 125 , 126 , 135 and 136 are formed. In this embodiment, the isolation regions 151 ˜ 153 , 125 , 126 , 135 and 136 are taken as an example of a field oxide layer, but are not intended to limit the present invention. In other embodiments, other isolation structures, such as shallow trench isolation structures, may also be used. In a possible embodiment, the size of the isolation region 152 is larger than the size of the isolation regions 151 and 153 . In this example, the size of the isolation regions 151 and 153 is larger than the size of the isolation regions 125 , 126 , 135 and 136 . The sizes of the isolation regions 125, 126, 135 and 136 are similar to each other.

請參考第5B圖,形成井區121及131於基底110內。井區121位於隔離區151與152之間,井區131位於隔離區152與153之間。在本實施例中,隔離區152分隔井區121及131。在一可能實施例中,井區121延伸至隔離區151與152的下方。因此,隔離區151與152覆蓋井區121的部分。同樣地,井區131延伸至隔離區152與153的下方。因此,隔離區152與153覆蓋井區131的部分。在本實施例中,井區121及131具有N型導電性。Referring to FIG. 5B , well regions 121 and 131 are formed in the substrate 110 . Well area 121 is located between isolation areas 151 and 152 , and well area 131 is located between isolation areas 152 and 153 . In this embodiment, the isolation region 152 separates the well regions 121 and 131 . In a possible embodiment, the well region 121 extends below the isolation regions 151 and 152 . Therefore, isolation regions 151 and 152 cover portions of well region 121 . Likewise, well region 131 extends below isolation regions 152 and 153 . Accordingly, isolation regions 152 and 153 cover portions of well region 131 . In this embodiment, the well regions 121 and 131 have N-type conductivity.

接著,請參考第5C圖,於基底110內形成摻雜區140、於井區120內形成摻雜區122及123,並於井區130內形成摻雜區132及133。在一實施例中,可以藉由植入P型雜質以形成摻雜區140、122、123、132及133。P型雜質包括例如硼、鎵、鋁、銦、或其結合的雜質。摻雜濃度可視製程技術及元件特性而定,於此並不加以限定。在本實施例中,摻雜區140、122、123、132及133的摻雜濃度高於基底110的摻雜濃度。在一實施例中,摻雜區140、122、123、132及133是藉由一圖案化罩幕(未顯示)配合執行一植入步驟形成。在本實施例中,摻雜區122位於隔離區151與125之間。摻雜區123位於隔離區125與126之間。摻雜區132位於隔離區152與135之間。摻雜區133位於隔離區135與136之間。Next, referring to FIG. 5C , doped regions 140 are formed in the substrate 110 , doped regions 122 and 123 are formed in the well region 120 , and doped regions 132 and 133 are formed in the well region 130 . In one embodiment, the doped regions 140 , 122 , 123 , 132 and 133 may be formed by implanting P-type impurities. P-type impurities include impurities such as boron, gallium, aluminum, indium, or a combination thereof. The doping concentration may be determined by process technology and device characteristics, and is not limited herein. In this embodiment, the doping concentration of the doped regions 140 , 122 , 123 , 132 and 133 is higher than that of the substrate 110 . In one embodiment, the doped regions 140, 122, 123, 132, and 133 are formed by performing an implantation step in conjunction with a patterned mask (not shown). In this embodiment, the doped region 122 is located between the isolation regions 151 and 125 . The doped region 123 is located between the isolation regions 125 and 126 . Doped region 132 is located between isolation regions 152 and 135 . Doped region 133 is located between isolation regions 135 and 136 .

接著,於井區120內形成摻雜區124,並於井區130內形成摻雜區134。在一實施例中,可以藉由植入N型雜質以形成摻雜區124及134。N型雜質包括例如磷、砷、氮、銻、或其結合的雜質。摻雜濃度可視製程技術及元件特性而定,於此並不加以限定。在本實施例中,摻雜區124及134的摻雜濃度高於井區121及131的摻雜濃度。在一實施例中,摻雜區124及134是藉由一圖案化罩幕(未顯示)配合執行一植入步驟形成。在本實施例中,摻雜區124位於隔離區126與152之間。摻雜區134位於隔離區136與153之間。Next, a doped region 124 is formed in the well region 120 , and a doped region 134 is formed in the well region 130 . In one embodiment, the doped regions 124 and 134 may be formed by implanting N-type impurities. N-type impurities include, for example, phosphorus, arsenic, nitrogen, antimony, or a combination thereof. The doping concentration may be determined by process technology and device characteristics, and is not limited herein. In this embodiment, the doping concentrations of the doped regions 124 and 134 are higher than the doping concentrations of the well regions 121 and 131 . In one embodiment, doped regions 124 and 134 are formed by performing an implantation step in conjunction with a patterned mask (not shown). In this embodiment, the doped region 124 is located between the isolation regions 126 and 152 . Doped region 134 is located between isolation regions 136 and 153 .

摻雜區122、123及井區121構成PNP元件120,而摻雜區132、133及井區131構成PNP元件130。此外,PNP元件120與130之間具有一具有P型基底的NPN元件。舉例而言,井區121、131及基底110構成一NPN元件。藉由NPN元件的存在,當PNP元件120及130導通時,PNP元件120及130具有較高的維持電壓,並最佳化PNP元件120及130的導通阻抗。此外,PNP元件120及130可承受更高的靜電放電電流。The doped regions 122 , 123 and the well region 121 constitute the PNP device 120 , and the doped regions 132 , 133 and the well region 131 constitute the PNP device 130 . In addition, there is an NPN element with a P-type substrate between the PNP elements 120 and 130 . For example, the well regions 121, 131 and the substrate 110 constitute an NPN device. With the existence of the NPN elements, when the PNP elements 120 and 130 are turned on, the PNP elements 120 and 130 have a higher sustain voltage, and the on-resistance of the PNP elements 120 and 130 is optimized. Additionally, PNP elements 120 and 130 can withstand higher ESD currents.

除非另作定義,在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外,除非明白表示,詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致,而不應解釋為理想狀態或過分正式之語態。Unless otherwise defined, all terms (including technical and scientific terms) herein are commonly understood by those of ordinary skill in the art to which this invention belongs. Furthermore, unless expressly stated otherwise, the definitions of words in general dictionaries should be construed as consistent with their meanings in articles in the related technical field, and should not be construed as ideal states or overly formal voices.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾。舉例來說,本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, apparatus, or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100、300:靜電放電保護裝置 110:基底 120、130、170:PNP元件 121、131、171:井區 122~124、132~134、140、172~174:摻雜區 151~154、125、126、135、136、175、176:隔離區 161~164:走線 VH、VL:電壓源 R121、R131、R110、R110A、R110B、R110C:電阻 200、400、500:NPN元件100, 300: Electrostatic discharge protection device 110: Base 120, 130, 170: PNP elements 121, 131, 171: Well area 122~124, 132~134, 140, 172~174: Doping region 151~154, 125, 126, 135, 136, 175, 176: Quarantine 161~164: Route VH, VL: voltage source R121, R131, R110, R110A, R110B, R110C: Resistors 200, 400, 500: NPN elements

第1圖為本發明之靜電放電保護裝置之示意圖。 第2圖為第1圖之靜電放電保護裝置的等效電路示意圖。 第3圖為本發明之靜電放電保護裝置之另一示意圖。 第4圖為第3圖之靜電放電保護裝置的等效電路示意圖。 第5A~5C圖為本發明之靜電放電保護裝置之製造方法示意圖。FIG. 1 is a schematic diagram of the electrostatic discharge protection device of the present invention. FIG. 2 is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device of FIG. 1 . FIG. 3 is another schematic diagram of the electrostatic discharge protection device of the present invention. FIG. 4 is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device of FIG. 3 . 5A to 5C are schematic diagrams of the manufacturing method of the electrostatic discharge protection device of the present invention.

100:靜電放電保護裝置100: Electrostatic discharge protection device

110:基底110: Base

120、130:PNP元件120, 130: PNP element

121、131:井區121, 131: Well area

122~124、132~134、140:摻雜區122~124, 132~134, 140: Doping region

151~153、125、126、135、136:隔離區151~153, 125, 126, 135, 136: Quarantine

161~163:走線161~163: Route

VH、VL:電壓源VH, VL: voltage source

Claims (17)

一種靜電放電保護裝置,包括: 一基底,具有一P型導電性; 一第一PNP元件,包括: 一第一井區,形成於該基底之中,並具有一N型導電性; 一第一摻雜區,形成於該第一井區之中,並具有該P型導電性; 一第二摻雜區,形成於該第一井區之中,並具有該P型導電性; 一第二PNP元件,包括: 一第二井區,形成於該基底之中,並具有該N型導電性; 一第三摻雜區,形成於該第二井區之中,並具有該P型導電性; 一第四摻雜區,形成於該第二井區之中,並具有該P型導電性;以及 一第一隔離區,形成於該基底中,並分隔該第一PNP元件及該第二PNP元件。An electrostatic discharge protection device, comprising: a substrate having a P-type conductivity; A first PNP element comprising: a first well region formed in the substrate and having an N-type conductivity; a first doped region formed in the first well region and having the P-type conductivity; a second doped region formed in the first well region and having the P-type conductivity; A second PNP element comprising: a second well region formed in the substrate and having the N-type conductivity; a third doped region formed in the second well region and having the P-type conductivity; a fourth doped region formed in the second well region and having the P-type conductivity; and A first isolation region is formed in the substrate and separates the first PNP element and the second PNP element. 如請求項1之靜電放電保護裝置,其中該第一PNP元件更包括: 一第五摻雜區,形成於該第一井區之中,並具有該N型導電性; 一第二隔離區,形成於該第一井區之中,並位於該第一及第二摻雜區之間;以及 一第三隔離區,形成於該第一井區之中,並位於該第二及第五摻雜區之間。The electrostatic discharge protection device of claim 1, wherein the first PNP element further comprises: a fifth doped region formed in the first well region and having the N-type conductivity; a second isolation region formed in the first well region between the first and second doped regions; and A third isolation region is formed in the first well region and located between the second and fifth doped regions. 如請求項2之靜電放電保護裝置,其中該第二PNP元件更包括: 一第六摻雜區,形成於該第二井區之中,並具有該N型導電性; 一第四隔離區,形成於該第二井區之中,並位於該第三及第四摻雜區之間;以及 一第五隔離區,形成於該第二井區之中,並位於該第四及第六摻雜區之間。The electrostatic discharge protection device of claim 2, wherein the second PNP element further comprises: a sixth doped region formed in the second well region and having the N-type conductivity; a fourth isolation region formed in the second well region between the third and fourth doped regions; and A fifth isolation region is formed in the second well region and located between the fourth and sixth doped regions. 如請求項3之靜電放電保護裝置,其中該第一隔離區延伸進入該第一及第二井區,並位於該第三及第五摻雜區之間。The ESD protection device of claim 3, wherein the first isolation region extends into the first and second well regions and is located between the third and fifth doped regions. 如請求項3之靜電放電保護裝置,其中該第一隔離區的寬度大於該第二隔離區的寬度。The electrostatic discharge protection device of claim 3, wherein the width of the first isolation region is greater than the width of the second isolation region. 如請求項1之靜電放電保護裝置,更包括: 一第七摻雜區,形成於該基底之中,並具有該P型導電性; 一第一走線,電性連接該第一及第七摻雜區; 一第二走線,電性連接該第二、第三及第五摻雜區;以及 一第三走線,電性連接該第四及第六摻雜區。Such as the electrostatic discharge protection device of claim 1, further including: a seventh doped region formed in the substrate and having the P-type conductivity; a first trace electrically connecting the first and seventh doped regions; a second trace electrically connected to the second, third and fifth doped regions; and A third wiring is electrically connected to the fourth and sixth doping regions. 如請求項1之靜電放電保護裝置,其中該第一井區的雜質濃度不同於該第二井區的雜質濃度。The electrostatic discharge protection device of claim 1, wherein the impurity concentration of the first well region is different from the impurity concentration of the second well region. 如請求項1之靜電放電保護裝置,更包括: 一第三PNP元件,包括: 一第三井區,形成於該基底之中,並具有該N型導電性; 一第八摻雜區,形成於該第三井區之中,並具有該P型導電性; 一第九摻雜區,形成於該第三井區之中,並具有該P型導電性; 一第十摻雜區,形成於該第三井區之中,並具有該N型導電性; 一第六隔離區,形成於該第三井區之中,並位於該第八及第九摻雜區之間; 一第七隔離區,形成於該第三井區之中,並位於該第九及第十摻雜區之間;以及 一第八隔離區,形成於該基底之中,並延伸進入該第二及第三井區; 其中該第八隔離區位於該第六及第八摻雜區之間。Such as the electrostatic discharge protection device of claim 1, further including: A third PNP element comprising: a third well region formed in the substrate and having the N-type conductivity; an eighth doping region formed in the third well region and having the P-type conductivity; a ninth doped region formed in the third well region and having the P-type conductivity; a tenth doped region formed in the third well region and having the N-type conductivity; a sixth isolation region formed in the third well region and located between the eighth and ninth doped regions; a seventh isolation region formed in the third well region and located between the ninth and tenth doped regions; and an eighth isolation region formed in the substrate and extending into the second and third well regions; Wherein the eighth isolation region is located between the sixth and eighth doping regions. 如請求項6之靜電放電保護裝置,其中該第一、第二及第三井區之一者的雜質濃度不同於該第一、第二及第三井區之另一者的雜質濃度。The electrostatic discharge protection device of claim 6, wherein an impurity concentration of one of the first, second and third well regions is different from an impurity concentration of the other of the first, second and third well regions. 如請求項6之靜電放電保護裝置,更包括: 一第七摻雜區,形成於該基底之中,並具有該P型導電性; 一第一走線,電性連接該第一及第七摻雜區; 一第二走線,電性連接該第二、第三及第五摻雜區; 一第三走線,電性連接該第四、第六及第八摻雜區;以及 一第四走線,電性連接該第九及第十摻雜區。As claimed in claim 6, the electrostatic discharge protection device further includes: a seventh doped region formed in the substrate and having the P-type conductivity; a first trace electrically connecting the first and seventh doped regions; a second trace electrically connected to the second, third and fifth doped regions; a third trace electrically connected to the fourth, sixth and eighth doped regions; and A fourth wire is electrically connected to the ninth and tenth doped regions. 一種靜電放電保護電路,包括: 一第一PNP元件,具有一第一集極、一第一射極以及一第一基極,該第一射極耦接一第一電壓源; 一第二PNP元件,具有一第二集極、一第二射極以及一第二基極,該第二集極耦接該第一射極,該第二射極耦接一第二電壓源;以及 一第一NPN元件,具有一第三集極、一第三射極以及一第三基極,該第三集極耦接該第二基極,該第三射極耦接該第一基極,該第三基極耦接該第一電源線。An electrostatic discharge protection circuit, comprising: a first PNP element, having a first collector, a first emitter and a first base, the first emitter is coupled to a first voltage source; A second PNP element has a second collector, a second emitter and a second base, the second collector is coupled to the first emitter, the second emitter is coupled to a second voltage source ;as well as A first NPN element has a third collector, a third emitter and a third base, the third collector is coupled to the second base, the third emitter is coupled to the first base , the third base is coupled to the first power line. 如請求項11之靜電放電保護電路,其中當一靜電放電事件發生在該第二電壓源並且該第一電壓源接地時,該第一PNP元件及該第二PNP元件依序導通。The electrostatic discharge protection circuit of claim 11, wherein when an electrostatic discharge event occurs at the second voltage source and the first voltage source is grounded, the first PNP element and the second PNP element are turned on in sequence. 如請求項12之靜電放電保護電路,其中當一靜電放電事件發生在該第二電壓源並且該第一電壓源接地時,該第一NPN元件導通,用以減少該第一PNP元件及該第二PNP元件的導通阻抗。The electrostatic discharge protection circuit of claim 12, wherein when an electrostatic discharge event occurs at the second voltage source and the first voltage source is grounded, the first NPN element is turned on for reducing the first PNP element and the second voltage source. The on-resistance of the two PNP components. 如請求項11之靜電放電保護電路,其中該第一射極與該第一基極之間具有一第一等效阻抗,該第二射極與該第二基極之間具有一第二等效阻抗,該第三基極與該第一電壓源之間具有一第三等效阻抗。The electrostatic discharge protection circuit of claim 11, wherein there is a first equivalent impedance between the first emitter and the first base, and a second equivalent impedance between the second emitter and the second base effective impedance, and there is a third equivalent impedance between the third base and the first voltage source. 如請求項14之靜電放電保護電路,更包括: 一第三PNP元件,具有一第四集極、一第四射極以及一第四基極,該第四集極耦接該第二射極,該第四射極耦接該第二電壓源; 一第二NPN元件,具有一第五集極、一第五射極以及一第五基極,該第五集極耦接該第四基極,該第五射極耦接該第二基極,該第五基極耦接該第一電壓源;以及 一第三NPN元件,具有一第六集極、一第六射極以及一第六基極,該第六集極耦接該第二電壓源,該第六射極耦接該第一基極,該第六基極耦接該第一電壓源。Such as the electrostatic discharge protection circuit of claim 14, further including: A third PNP element has a fourth collector, a fourth emitter and a fourth base, the fourth collector is coupled to the second emitter, the fourth emitter is coupled to the second voltage source ; A second NPN element has a fifth collector, a fifth emitter and a fifth base, the fifth collector is coupled to the fourth base, and the fifth emitter is coupled to the second base , the fifth base is coupled to the first voltage source; and A third NPN element has a sixth collector, a sixth emitter and a sixth base, the sixth collector is coupled to the second voltage source, and the sixth emitter is coupled to the first base , the sixth base is coupled to the first voltage source. 如請求項15之靜電放電保護電路,其中當一靜電放電事件發生在該第二電壓源並且該第一電壓源接地時,該第一PNP元件、該第二PNP元件及該第三PNP元件依序導通。The electrostatic discharge protection circuit of claim 15, wherein when an electrostatic discharge event occurs at the second voltage source and the first voltage source is grounded, the first PNP element, the second PNP element and the third PNP element depend on sequence turn on. 如請求項15之靜電放電保護電路,其中該第四基極與該第二電壓源之間具有一第四等效阻抗,該第五基極與該第二電壓源之間具有一第五等效阻抗,該第六基極與該第二電壓源之間具有一第六等效阻抗。The electrostatic discharge protection circuit of claim 15, wherein there is a fourth equivalent impedance between the fourth base and the second voltage source, and a fifth and so on between the fifth base and the second voltage source effective impedance, and there is a sixth equivalent impedance between the sixth base and the second voltage source.
TW109122188A 2020-07-01 2020-07-01 Electrostatic discharge protection device and circuit TWI732615B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW109122188A TWI732615B (en) 2020-07-01 2020-07-01 Electrostatic discharge protection device and circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109122188A TWI732615B (en) 2020-07-01 2020-07-01 Electrostatic discharge protection device and circuit

Publications (2)

Publication Number Publication Date
TWI732615B TWI732615B (en) 2021-07-01
TW202203413A true TW202203413A (en) 2022-01-16

Family

ID=77911380

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109122188A TWI732615B (en) 2020-07-01 2020-07-01 Electrostatic discharge protection device and circuit

Country Status (1)

Country Link
TW (1) TWI732615B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI888717B (en) * 2022-04-06 2025-07-01 聯華電子股份有限公司 Electrostatic discharge protection structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI823291B (en) * 2022-03-15 2023-11-21 世界先進積體電路股份有限公司 Protection circuit
US11894674B2 (en) 2022-05-11 2024-02-06 Vanguard International Semiconductor Corporation Protection circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679888B1 (en) * 2016-08-30 2017-06-13 Globalfoundries Inc. ESD device for a semiconductor structure
US10573635B2 (en) * 2018-07-23 2020-02-25 Amazing Microelectronics Corp. Transient voltage suppression device with improved electrostatic discharge (ESD) robustness

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI888717B (en) * 2022-04-06 2025-07-01 聯華電子股份有限公司 Electrostatic discharge protection structure

Also Published As

Publication number Publication date
TWI732615B (en) 2021-07-01

Similar Documents

Publication Publication Date Title
US7715159B2 (en) ESD protection circuit
CN100364089C (en) Substrate-triggered electrostatic protection circuit using triple-well structure
CN102832211B (en) High voltage resistor with PIN diode isolation
CN101630673B (en) Electrostatic discharge protection circuit
TWI732615B (en) Electrostatic discharge protection device and circuit
US5854504A (en) Process tolerant NMOS transistor for electrostatic discharge protection
CN107346786B (en) GGNMOS transistors, multi-finger GGNMOS devices and circuits
US10163892B2 (en) Silicon controlled rectifiers (SCR), methods of manufacture and design structures
CN101645447B (en) Electrostatic Discharge Protection Circuit Components
US11049853B2 (en) ESD protection device with breakdown voltage stabilization
TWI744187B (en) Semiconductor circuit and manufacturing method for the same
US10211290B2 (en) Electrostatic discharge protection
CN101803022B (en) Electrostatic damage protection element, electrostatic damage protection circuit, semiconductor device and manufacturing method
CN107275324A (en) Electrostatic discharge protection device and method
US20130146978A1 (en) Transistor assisted esd diode
CN114068516B (en) Electrostatic discharge protection device and circuit
Amato et al. Bidirectional DIAC Devices with Two-Stage Triggering
US11837600B2 (en) Electrostatic discharge protection apparatus and its operating method
CN102738141B (en) Semiconductor structure and manufacturing method and operating method thereof
US11527529B2 (en) Electrostatic discharge protection device
CN102237341B (en) Electrostatic discharge protection element and manufacturing method thereof
TWI553821B (en) Electrostatic discharge protection structure
CN114975419A (en) Electrostatic discharge protection circuit structure
US7075156B1 (en) Collector structure for electrostatic discharge protection circuits
TW201010043A (en) ESD protection device