TW202203313A - Methods of fabricating semiconductor structure - Google Patents

Abstract

A method for fabricating semiconductor structure includes the steps of providing a substrate having a device region and a peripheral region surrounding the device region, forming a first dielectric layer on the device region and the peripheral region of the substrate, forming a mask layer on the first dielectric layer on the device region, forming a second dielectric layer on the device region and the peripheral region of the substrate, performing a lift-off process to remove the mask layer and the second dielectric layer on the mask layer such that the first dielectric layer on the device region is exposed, and performing a polishing process to the first dielectric layer and the second dielectric layer on the first dielectric layer thereby obtaining a polished surface.

Description

Method of making a semiconductor structure

The present invention relates to a method for fabricating a semiconductor structure, in particular to a method for planarizing a semiconductor structure.

3D IC packaging and 3D IC integration are important technologies for advanced semiconductor manufacturing to achieve smaller package size and more functional integration. The basic method is to use bonding technology to stack chips. Bonding, and forming electrical connection structures (such as through silicon vias, TSVs) between the wafers to transmit signals between the wafers. Such technology can effectively utilize space and increase the number of components that can be accommodated per unit area. In addition, since the stack structure can effectively shorten the distance of current signal transmission, signal delay can be reduced.

Wafer level bonding is a technique in which two wafers are first bonded and then diced to obtain three-dimensional stacked chips. Fusion bonding is one of the widely used wafer bonding techniques in the art, which forms wafer bonding by forming a bond between the surfaces of two wafers. The fusion bonding process usually involves aligning and contacting two wafers at room temperature to form a weak bond between the surfaces of the two wafers (this step is also called pre-bonding), followed by thermal annealing ( thermal anneal) to convert weak bonds into covalent bonds, thereby forming strong and strong bonds.

Since fusion bonding involves wafer surface contact, the flatness of the wafer surface is related to the quality of the bond. The chemical mechanical polishing (CMP) process is often used to planarize the wafer surface, but it is still difficult to avoid the edge roll off phenomenon in the peripheral region of the wafer. When the roll-off is severe or the roll-off is extended, it can lead to poor joints in the adjacent areas.

The main purpose of the present invention is to provide a method for fabricating a semiconductor structure. By forming a second dielectric layer on the first dielectric layer in the peripheral region of the wafer as a polishing buffer layer, the rolling of the first dielectric layer in the peripheral region can be reduced. This reduces the level, thereby improving the yield of wafer-level bonding.

According to an embodiment of the present invention, a method for fabricating a semiconductor structure includes the following steps. First, a substrate is provided, including an element area and a peripheral area surrounding the element area. Then, a first dielectric layer is formed on the device region and the peripheral region, and then a mask layer is formed on the first dielectric layer in the device region. Next, a second dielectric layer is formed on the device region and the peripheral region, and then a lift-off process is performed to simultaneously remove the mask layer and the second dielectric layer on the mask layer and expose out of the first dielectric layer of the device region. Subsequently, a polishing process is performed on the first dielectric layer and the second dielectric layer on the first dielectric layer to obtain a polished surface.

In order to enable those of ordinary skill in the technical field to which the present invention pertains to further understand the present invention, the preferred embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, the composition of the present invention and the desired effect will be described in detail. . It should be noted that, in the following embodiments, other embodiments may be completed by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

In order to make the reader easy to understand and the drawings are concise, the drawings in the present disclosure only depict a part of the display device, and specific elements in the drawings are not drawn according to actual scale. In addition, the number and size of each element in the figures are for illustration only, and are not intended to limit the scope of the present disclosure. In the drawings, the same or similar elements may be denoted by the same reference numerals. As for the top-bottom relationship of the relative elements in the drawings described in the text, those in the art should understand that it refers to the relative positions of the objects, so they can all be turned over to present the same components, which should all belong to the disclosure of this specification. range.

In this specification, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, or directly on the other element or layer. Connected to another element or layer, or there may be other elements or layers in between. In contrast, when an element is referred to as being "directly on" or "directly connected to another element or layer", there are no intervening elements or layers present.

In this specification, "wafer", "substrate" or "substrate" means any structure comprising an exposed surface on which material can be deposited to fabricate integrated circuit structures, such as wiring, according to embodiments of the present invention Floor. It should be understood that "substrate" includes semiconductor wafers, but is not limited thereto. "Substrate" in the process also means a semiconductor structure that includes a layer of material fabricated thereon.

The description of the "spacing" or "distance" between elements, or the "width" or "length" of elements in this document is the projection of the element on the XY plane, the YZ plane or the XZ plane along the X and Y directions. or the Z direction to define. The same "parallel" or "non-parallel" means that the projection of the extension line of the element on the XY plane, the YZ plane or the XZ plane is "parallel" or "nonparallel".

Please refer to Figures 1 to 10. FIG. 1 is a flow chart of the steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention. FIG. 2 is a schematic plan view of a plane (XY plane) defined by the X direction and the Y direction of the semiconductor structure according to an embodiment of the present invention. Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 and Fig. 10 are the planes defined by the semiconductor structure along the AA' tangent in the X and Z directions (XZ Schematic diagram of the cross-section of the plane). FIG. 8 is a schematic plan view of the semiconductor structure in the XY plane.

The fabrication method 100 of the semiconductor structure of the present embodiment firstly performs step 102 to provide a substrate including an element region and a peripheral region surrounding the element region. Please refer to FIG. 2, the substrate 10 may be made of semiconductor materials, such as silicon substrate, epitaxial silicon substrate, silicon carbide substrate, III-V substrate, silicon-on-insulator (SOI), but not limited thereto . In some embodiments, the substrate may also be composed of a non-semiconductor material, such as a glass, plastic or sapphire substrate. In some embodiments, the substrate 10 is, for example, a wafer, and the distance from the center C of the substrate 10 to the edge 10a of the substrate 10 is a radius R. The substrate 10 includes a main surface 10 b parallel to the XY plane, and includes a device area 12 and a peripheral area 14 . The peripheral region 14 is interposed between and surrounding the element regions 12 at the edges 10 a of the substrate 10 . The device region 12 of the substrate 10 may include a plurality of wafer regions (not shown), and the wafer regions may include integrated circuit components and/or circuit structures, such as transistors, diodes, resistors, capacitors, inductors, decoders , drivers, amplifiers, timers, buffers, interconnect structures, etc., but not limited thereto. A boundary area B1 is included between the element area 12 and the peripheral area 14 .

In some embodiments, the peripheral region 14 has a width W, and the device region 12 is substantially a region centered on the center C and encircled by a radius R1, wherein the radius R1 is substantially equal to the radius R minus the width W. For example, the substrate 10 is, for example, a 12-inch wafer, the radius R of which is about 150 millimeters (mm), the width W of the peripheral region 14 is about 2 mm, and the radius R1 of the device region 12 is about 148 mm. It should be understood that the above dimensions are only examples, and the width of the peripheral region 14 and the radius R1 of the device region 12 can be adjusted according to actual conditions.

In some embodiments, as shown in FIG. 3, an integrated circuit structure 18 may be formed on the main surface 10a of the device region 12 of the substrate 10, and the integrated circuit structure 18 may include integrated circuit elements and/or circuit structures, Examples include, but are not limited to, transistors, diodes, resistors, capacitors, inductors, decoders, drivers, amplifiers, timers, buffers, interconnect structures, and the like. A distance D1 is included between the edge 18a of the integrated circuit structure 18 and the edge 10a of the substrate 10 . According to an embodiment of the present invention, the distance D1 is greater than or equal to the width W of the peripheral region 14 , for example, greater than or equal to 2 mm. In other words, the edge 18 a of the integrated circuit structure 18 may be substantially aligned with the boundary region B1 of the device region 12 and the peripheral region 14 , or within the device region 12 .

Next, step 104 is performed to form a first dielectric layer on the device region and the peripheral region of the substrate. Referring to FIG. 3, the first dielectric layer 20 is formed on the substrate 10 in an all-round way, completely covering the element area 12 of the substrate 10 and the integrated circuit structure 18 disposed on the element area 12, and covering at least part of the peripheral area 14. The first dielectric layer 20 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric material, or a combination thereof, but not limited to this. According to an embodiment of the present invention, the first dielectric layer 20 includes a dielectric material that can be used for wafer bonding, such as silicon oxide. The first dielectric layer 20 at this time may have a predetermined thickness T0. According to some embodiments of the present invention, the thickness T0 is preferably between about 5000 angstroms (Å) to 15000 angstroms (Å). In one embodiment, the thickness T0 is about 10000±1000 angstroms (Å). The first dielectric layer 20 may be formed by a chemical vapor deposition (CVD) process.

Next, step 106 is performed to form a mask layer on the first dielectric layer in the device region. Referring to FIG. 4 , the mask layer 22 is formed on the first dielectric layer 20 in the device region 12 and exposes the first dielectric layer 20 in the peripheral region 14 . The mask layer 22 is preferably selected from a material with etching selectivity between the mask layer 22 and the first dielectric layer 20 . According to an embodiment of the present invention, the mask layer 22 is, for example, a photoresist layer. The method of forming the mask layer 22 is, for example, coating a photoresist material on the substrate 10 in a comprehensive manner, and then removing it by a photoresist edge bead removal (EBR) process or a wafer edge exposure (WEE) process The photoresist material covering the peripheral region 14 exposes the first dielectric layer 20 of the peripheral region 14 . In other embodiments, a patterning process such as a lithography and etching process can be used to remove the mask layer 22 on the peripheral region 14 .

As shown in FIG. 4, the mask layer 22 may have a thickness T1. According to some embodiments of the present invention, the thickness T1 is preferably greater than or equal to 5 times the thickness T2 of the second dielectric layer 24 (refer to FIG. 5 ), eg, greater than or equal to 10 micrometers (µm). A distance D2 is included between the edge 22a of the mask layer 22 and the edge 10a of the substrate 10 . According to an embodiment of the present invention, the distance D2 is greater than or equal to the distance D1. In other words, the width W, the distance D1 and the distance D2 satisfy the relationship W≦D1≦D2.

Next, step 108 is performed to form a second dielectric layer on the device region and the peripheral region. Referring to FIG. 5 , the second dielectric layer 24 is comprehensively formed on the device region 12 and the peripheral region 14 of the substrate 10 , covering the mask layer 22 and the first dielectric layer 20 exposed from the mask layer 22 . s surface. The second dielectric layer 24 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, low-k dielectric materials, or any of the above combination, but not limited to this. According to an embodiment of the present invention, the second dielectric layer 24 and the first dielectric layer 20 may comprise the same material, such as silicon oxide.

It should be noted that the second dielectric layer 24 is preferably formed by a low step coverage process, so that the deposition rate of the second dielectric layer 24 on the sidewalls 22a of the mask layer 22 is lower than that of the second dielectric layer 24. The deposition rate of the second dielectric layer 24 on the exposed surface of the first dielectric layer 20 . Therefore, the thickness T3 of the portion of the second dielectric layer 24 covering the sidewall 22 a of the mask layer 22 is smaller than the thickness T2 of the portion covering the first dielectric layer 20 . According to some embodiments of the present invention, the thickness T2 is preferably between 1.5 micrometers (µm) and 2.5 micrometers (µm), and the thickness T3 is preferably less than or equal to 500 angstroms (Å). For example, in one embodiment, the thickness T2 is about 1.9±0.2 micrometers (µm), and the thickness T3 is about 500±50 angstroms (Å). The second dielectric layer 24 may be formed using a sputtering process. In some examples, when the step coverage of the second dielectric layer 24 is sufficiently low, the sidewalls 22 a of the mask layer 22 may not be completely covered by the second dielectric layer 24 .

Next, referring to FIG. 6 , an etching process P1 may be selectively performed on the second dielectric layer 24 to remove part of the second dielectric layer 24 until part of the sidewall of the mask layer 22 is removed from the second dielectric layer 24 The opening 26 is exposed. According to an embodiment of the present invention, the etching process P1 may include a wet etching process.

Next, step 110 is performed to perform a lift-off process to simultaneously remove the mask layer and the second dielectric layer on the mask layer, and expose the first dielectric layer in the device region. Referring to FIG. 7 , according to an embodiment of the present invention, the lift-off process P2 includes performing a solvent treatment on the mask layer 22 through the opening 26 to lift the mask layer 22 from the first dielectric layer 20 (lift- off), the first dielectric layer 20 of the element region 12 is exposed. The solvent treatment preferably uses a solvent that has a high etching rate for the mask layer 22 and a low etching rate for the first dielectric layer 20 or has no etching property for the first dielectric layer 20, so as to reduce the amount of the first dielectric layer during the solvent treatment process. Loss of the electrical layer 20 . In one embodiment, when the mask layer 22 is a photoresist layer, the lift-off process P2 can use the solvent used in the photoresist rinsing process. In other embodiments, depending on the material of the mask layer 22 , a suitable gas or liquid etchant may be used to lift off the mask layer 22 .

It is worth noting that the second dielectric layer 24 deposited on the mask layer 22 will be removed at the same time when the mask layer 22 is lifted off, so only the first dielectric layer 20 is left after the lift-off process P2 the second dielectric layer 24 thereon. According to an embodiment of the present invention, as shown in FIG. 8 , the remaining second dielectric layer 24 forms a dielectric layer convex ring 24A (dot-marked area) across the boundary between the device area 12 and the peripheral area 14 Area B1 and surrounds the element area 12 . A distance D2' may be included between the sidewall 24a of the second dielectric layer 24 and the edge 10a of the substrate 10 . According to an embodiment of the present invention, the distance D2' may be substantially equal to the distance D2.

Next, step 112 is performed to perform a polishing process on the first dielectric layer and the second dielectric layer on the first dielectric layer to obtain a polished surface. Referring to FIG. 9 and FIG. 10 , then a polishing process P3 is performed on the first dielectric layer 20 and the remaining second dielectric layer 24 (dielectric layer convex ring 24A), so that the first dielectric layer 18 on the integrated circuit structure 18 is polished. A dielectric layer 20 is ground from the thickness T3 to the target thickness T4, and a ground surface S is obtained. According to an embodiment of the present invention, in the polishing process P3, the first dielectric layer 20 and the second dielectric layer 24 may have substantially the same removal rate. In other embodiments, the removal rate of the second dielectric layer 24 may be slightly greater than the removal rate of the first dielectric layer 20 . In the embodiment shown in FIG. 9 , the second dielectric layer 24 can be completely removed in the grinding process P3 , that is, the grinding surface S is completely formed by the first dielectric layer 20 . In other embodiments, a portion of the second dielectric layer 24 may be left on the first dielectric layer 20 in the peripheral region 14 after the polishing process P3, and the polishing surface S may be made of the first dielectric layer 20 and the second dielectric layer. 24 together constitute.

As shown in FIG. 10, the grinding surface S includes a flat area S1 and a roll-off area S2, and a boundary area B2 is therebetween. The flat area S1 is substantially parallel to the main surface 10b of the substrate 10, and the roll-off area S2 rolls down and slides from the boundary area B2 to the main surface 10b of the substrate 10 and deviates from the extension surface of the flat area S1. The flat area S1 roughly corresponds to the element area 12 , and the roll-off area S2 roughly corresponds to the peripheral area 14 . According to an embodiment of the present invention, a distance D3 is included between the boundary region B2 of the flat region S1 and the roll-off region S2 and the edge 10a of the substrate 10, and the roll-off region S2 includes a slope D4.

In the present invention, the convex ring 24A of the dielectric layer is used as the polishing buffer layer of the first dielectric layer 20 in the polishing process P3, which can reduce the degree of roll-off of the roll-off area S2 after the polishing process P3, such as making the flat area S1 The boundary area B2 with the roll-off area S2 is closer to the edge 10a of the substrate 10 (ie, the distance D3 is reduced), and/or the slope D4 of the roll-off area S2 is reduced. According to an embodiment of the present invention, the distance D3 is smaller than the distance D1, or smaller than or equal to the width W of the peripheral area 14, so as to ensure that the flat area S1 can completely cover the area where the integrated circuit structure 18 is provided, or can completely cover the area of the device area 12. The range and extension cover part of the peripheral region 14 to increase the margin of the dicing process after wafer bonding.

For example, the substrate 10 is, for example, a 12-inch wafer, the width W of the peripheral region 14 is about 2 mm, and the distance D1 is greater than or equal to 2 mm. Through the method provided by the present invention, the distance D3 can be made less than 2 mm. In one embodiment, the distance between the position where the roll-off area S2 is 148.5 mm from the center C of the substrate 10 and the extending surface of the flat area S1 in the vertical direction may be less than 5 micrometers (µm).

Please refer to FIG. 11 , which is a schematic cross-sectional view of a bonded semiconductor structure according to an embodiment of the present invention. Subsequently, another substrate 30 can be bonded by using the ground surface S of the first dielectric layer 20 as a bonding surface. The substrate 30 may be, for example, another wafer. The surface of the substrate 30 facing the substrate 10 may include a material for forming a bond with the first dielectric layer 20, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low dielectric constant (low-dielectric constant) k) Dielectric material, or a combination of the above, but not limited thereto. Before bonding with the substrate 30 , the ground surface S of the first dielectric layer 20 may be subjected to a surface treatment (eg, plasma activation) to promote the formation of bonds between the first dielectric layer 20 and the substrate 30 .

In summary, the present invention utilizes the second dielectric layer (the convex ring of the dielectric layer) as the polishing buffer layer of the first dielectric layer in the polishing process, which can reduce the roll-off degree of the first dielectric layer in the peripheral region and improve the polishing surface. The flatness is favorable for subsequent bonding with another substrate. In addition, an embodiment of the present invention utilizes a photoresist as a mask layer, and can conveniently use a photoresist edge cleaning (EBR) process or a wafer edge exposure (WEE) process to adjust the coverage area of the mask layer to control the second dielectric layer (Dielectric layer convex ring) covers the range of the first dielectric layer, and can use a photoresist cleaning solvent to perform a lift-off process. In addition, an embodiment of the present invention utilizes a sputtering process to form the second dielectric layer, which can reduce the thickness of the second dielectric layer covering the sidewalls of the mask layer, so as to facilitate the removal of the solvent or etchant in the process to etch from the sidewalls of the mask layer . It should be understood that the fabrication method of the semiconductor structure of the present invention is not limited to the planarization of the surface of the wafer-level bonding, but can also be applied to other planarization steps of the semiconductor structure, such as for a faster grinding removal rate and/or surface shape The concave area forms a polishing buffer layer to improve the planarization effect of the polishing process. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base 10a: Edge 10b: Main surface 12: Component area 14: Surrounding area 18: Integrated circuit structure 18a: Edge 20: First Dielectric Layer 22: mask layer 22a: Edge 24: Second Dielectric Layer 26: Opening 30: Base 100: Method 102: Steps 104: Steps 106: Steps 108: Steps 110: Steps 112: Steps 24A: Dielectric layer convex ring 24a: Sidewall AA': Tangent B1: Junction area B2: Junction area C: Center D1: Distance D2: Distance D2': distance D3: Distance D4: Slope P1: Etching process P2: lift off process P3: Grinding Process R: radius R1: radius S: Grinding surface S1: Flat area S2: Roll-off area T0: Thickness T1: Thickness T2: Thickness T3: Thickness T4: Target thickness W: width X: direction Y: direction Z: direction

In order to make the above-mentioned and other objects, features, advantages and embodiments of the present invention more clearly understood, the detailed description of the accompanying drawings is as follows: FIG. 1 is a flow chart showing the steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention. FIG. 2 is a schematic plan view of a semiconductor structure according to an embodiment of the present invention. Figures 3 to 10 are schematic cross-sectional views along the AA' tangent in Figure 2, for explaining the steps of the method for fabricating the semiconductor structure in Figure 1, wherein: Figure 3 shows the formation of an integrated circuit structure and a first dielectric layer on the substrate; FIG. 4 illustrates forming a mask layer on the first dielectric layer; FIG. 5 illustrates forming a second dielectric layer on the first dielectric layer and the mask layer; FIG. 6 shows an etching process for the second dielectric layer; FIG. 7 shows a lift-off process for the semiconductor structure; Figure 8 shows a schematic plan view of the semiconductor structure after the lift-off process; FIG. 9 illustrates performing a grinding process on the semiconductor structure; and FIG. 10 is a schematic cross-sectional view of the semiconductor structure after the polishing process. FIG. 11 is a schematic cross-sectional view of a bonded semiconductor structure according to an embodiment of the present invention.

10: Base

10a: Edge

10b: Main surface

12: Component area

14: Surrounding area

18: Integrated circuit structure

18a: Edge

20: First Dielectric Layer

22: mask layer

24: Second Dielectric Layer

24A: Dielectric layer convex ring

24a: Sidewall

C: Center

D2': distance

P2: lift off process

X: direction

Z: direction

Claims (13)

A method of fabricating a semiconductor structure, comprising: providing a substrate including an element area and a peripheral area surrounding the element area; forming a first dielectric layer on the device region and the peripheral region; forming a mask layer on the first dielectric layer in the device region; forming a second dielectric layer on the device region and the peripheral region; performing a lift-off process to simultaneously remove the mask layer and the second dielectric layer on the mask layer, and expose the first dielectric layer in the device region; and A polishing process is performed on the first dielectric layer and the second dielectric layer on the first dielectric layer to obtain a polished surface. The method for fabricating a semiconductor structure described in claim 1, wherein before performing the lift-off process, further comprising performing an etching process on the second dielectric layer to form an opening to expose the sidewall of the mask layer. The method for fabricating a semiconductor structure as described in claim 1, wherein the lift-off process includes performing a solvent treatment on the mask layer through the opening. The method for fabricating a semiconductor structure as described in claim 1, wherein the mask layer comprises a photoresist layer. The method for fabricating a semiconductor structure as described in claim 1, wherein the materials of the first dielectric layer and the second dielectric layer respectively comprise silicon oxide. The method for fabricating a semiconductor structure as described in claim 1, wherein the second dielectric layer is formed by a sputtering process. The method for fabricating a semiconductor structure as described in claim 1, wherein the thickness of the second dielectric layer on the sidewall 2 of the mask layer is smaller than the thickness of the second dielectric layer on the first dielectric layer layer thickness. The method for fabricating a semiconductor structure as described in item 1 of the claimed scope, before forming the first dielectric layer, further comprising forming an integrated circuit structure in the device region of the substrate, the integrated circuit structure to the The distance from an edge of the substrate is smaller than the distance from the mask layer to the edge of the substrate. The method for fabricating a semiconductor structure as described in claim 1, wherein the grinding surface includes a flat region and a roll-off region adjacent to the flat region, wherein the flat region and the roll-off region are connected to the flat region by a boundary region. The distance from an edge of the substrate is smaller than the distance from the semiconductor structure to the edge of the substrate. The method for fabricating a semiconductor structure as described in claim 1, wherein after the lift-off process, the second dielectric layer on the first dielectric layer overlaps a boundary region between the device region and the peripheral region directly above. The method for fabricating a semiconductor structure as described in claim 1, wherein the second dielectric layer on the first dielectric layer is completely removed in the polishing process. The method for fabricating a semiconductor structure as described in claim 1, before forming the second dielectric layer, further comprising performing an edge removal (EBR) process on the mask layer to remove the peripheral region. the mask layer. The method for fabricating a semiconductor structure as described in item 1 of the claimed scope, wherein after the polishing process, further comprising using the polished surface as a bonding surface to bond another substrate.

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