TW202203042A - Memory device, electronic device, and associated read method - Google Patents

Abstract

A memory device, an electronic device, and associated read method capable of performing a synchronized read operation to multiple memory modules are provided. The electronic device includes a host control device, a first memory module and a second memory module, and the host control device executes a read operation to the first and the second memory modules simultaneously. When a refresh collision occurs in the first memory module, the first memory module reports the refresh confliction to the host control device. After a synchronized data preparation duration passes, the first and the second memory modules respectively transmit a first synchronized read data and a second synchronized read data to the host in a synchronized read duration. The synchronized data preparation duration is longer than a predefined read latency.

Description

Memory device, electronic device and reading method related thereto

The present invention relates to a memory device, an electronic device and a reading method related thereto, and more particularly, to a memory device, an electronic device and a reading method related thereto that can perform synchronous reading of a plurality of memory modules take method.

The increasing popularity of portable electronic devices, coupled with the trend of audio and video applications, has led to an unabated demand for memory modules. Therefore, the storage capacity of the memory module is getting larger and larger. However, with different applications, some electronic devices do not need to use large-capacity memory modules. In addition, a large-capacity memory module requires a larger number of pins, which is a limitation when designing an embedded system.

Please refer to FIG. 1 , which is a schematic diagram of a memory module in an electronic device using dynamic random access memory (DRAM). The electronic device 10a includes a main control device 13a and a memory module 11a. The main control device 13a may be a controller or a digital signal process (DSP) in an embedded system, and the memory module (DRAM) 11a uses a dynamic random access memory (DRAM) Dynamic Random Access Memory, referred to as DRAM) technology. The main control device 13a selects the memory module (DRAM) 11a by using the chip selection signal CS#, and transmits the control signal CTL to the memory module (DRAM) 11a. According to the control signal CTL and the system clock signal SCLK, between the main control device 13a and the memory module (DRAM) 11a, the 64-bit system input and output signal lines SIO[64:1] are used to transmit the memory address and read Data DATm. The memory address includes a column address ADRr and a row address ADRc of the memory module (DRAM) 11a.

With the development of memory technology, the capacity of the memory module (DRAM) 11a using the DRAM technology may be too large, and the number of wires may be too large. Therefore, a memory module using a pseudo static random access memory (Pseudo Static Random Access Memory, referred to as PSRAM for short) is currently developed on the market.

Please refer to FIG. 2 , which is a schematic diagram of a memory module in an electronic device using a virtual static random access memory PSRAM. The electronic device 10b includes a main control device 13b and a memory module (PSRAM) 11b. The memory module (PSRAM) 11b adopts the PSRAM technology of virtual static random access memory. After the main control device 13b selects the memory module (PSRAM) 11b by using the chip selection signal CS#, it transmits the control signal CTL to the memory module (PSRAM) 11b. According to the control of the control signal CTL, the system clock signal SCLK and the data flashing mask signal (Read Data strobe/Write Data Mask, DQSM for short), between the main control device 13 and the memory module (PSRAM) 11b, the The 8-bit system input and output signal line SIO[8:1] transmits memory address and read data. For convenience of explanation, the same symbols are used herein to represent the signal line and the signal transmitted by the signal line. For example, the control signal CTL is transmitted using the control signal line CTL.

Comparing Figures 1 and 2, it can be seen that the number of system input and output signal lines SIO in the two figures is very different. In addition, the number of control signals CTL required by the main control device 13a in FIG. 1 is larger than that required by the main control device 13b in FIG. 2 . Therefore, when the memory module (PSRAM) 11b is used, the main control device 13 needs fewer pins. In addition, the memory module (PSRAM) 11b using PSRAM technology has also become a trend of embedded systems.

When using PSRAM technology, the memory module needs to be continuously refreshed to maintain the stored data. If a read command from the main control device is just received while the memory module is being updated, the memory module cannot immediately perform the read operation because the memory module is being updated. Such a phenomenon that the read operation cannot be performed immediately because the memory module is being updated is called a refresh collision.

When the memory module (PSRAM) 11b adopts the virtual static random access memory PSRAM technology, when the main control device 13b performs a read operation on the memory module (PSRAM) 11b, it may be caused by the memory module ( The state of the PSRAM) 11b itself is different and there are two situations as follows: a read operation under normal circumstances, or a read operation under an update conflict. In the following, Fig. 3A is used to illustrate the waveform of the read operation of the memory module (PSRAM) 11b in a normal situation (when no update conflict occurs), and Fig. 3B is used to illustrate the read operation of the memory module (PSRAM) 11b. The waveform for which an update conflict occurred while operating.

In Figures 3A and 3B, from top to bottom are the chip select signal CS#, the system clock signal SCLK, the data flash mask signal DQSM, and the system input and output signal lines SIO[8:1]. In this article, the horizontal axis of the waveform graph is time.

Please refer to FIG. 3A , which is a waveform diagram of a general read operation performed by the master device using the PSRAM memory module. First, the main control device 13b pulls down the chip select signal CS# corresponding to the memory module (PSRAM) 11b from a high level to a low level at a time point t1. Next, after the memory module 11b pulls down the data flash control mask signal DQSM to a low level at time t2, the main control device 13b uses the system input and output signal lines SIO[8:1] to sequentially issue the read commands mCMDrd, The row address (ADRr) and the row address (column address) ADRc are sent to the memory module (PSRAM) 11b.

In this paper, the period during which the master control device 13b transmits the read command mCMDrd (time t3 to time t4) is defined as the read command transmission period Tcmd; the period during which the master control device 13b transmits the memory address (time t4 to time t7) is defined as is the address transmission period Tadr; the period during which the main control device 13b transmits the column address ADRr (time t4~time t6) is defined as the column address period Tadr_r; the period during which the main control apparatus 13b transmits the row address ADRc (time t6~time t7) ) is defined as the row address period Tadr_c. For the convenience of description, the read command mCMDrd is represented by the dot-shaped mesh bottom; the column address ADRr is represented by the horizontal mesh bottom; and the row address ADRc is represented by the vertical mesh bottom.

In the memory module (PSRAM) 11b, a read latency count (LC for short) can be defined. The read delay count LC represents the time required for reading the read data DATm from the memory array to the internal buffer after the memory module (PSRAM) 11b obtains the row address from the control device 13b. This article assumes that the read delay count LC is three times the system clock period Tclk (LC=Tclk*3).

After the memory module (PSRAM) 11b receives the read command mCMDrd, the column address ADRr and the row address (column address) ADRc, the read data DATm can be copied from the memory array to the internal after waiting for a period of time. The buffer is ready. As shown in FIG. 3A, if the memory module (PSRAM) 11b does not have an update collision, the period required by the memory module (PSRAM) 11b to copy the read data DATm from the memory array to the internal buffer , depending on the preset read delay (dftLC =LC*1). The default read delay dftLC represents the number of read delay counts LC required to wait for data read when the memory module (PSRAM) 11b has no update conflict. The predetermined read delay (dftLC=LC*1) is calculated after the memory module (PSRAM) 11b receives the column address mADRr (ie, time t5).

Once the preset read delay (dftLC=LC*1) ends (time t8), the memory module (PSRAM) 11b uses the data flash at the next rising edge of the system clock signal SCLK (ie, time t9). The mask signal DQSM successively generates two read strobe pulse signals mstrb1 and mstrb2. When the read flash pulse signals mstrb1 and mstrb2 are generated, the memory module 11b also transmits the read data DATm in the internal buffer to the main control device 13b by using the system input and output signal lines SIO[8:1].

Please refer to FIG. 3B , which is a waveform diagram of an update conflict in the memory module when the master device uses the PSRAM memory module to perform a read operation. Since the waveforms in Figures 3A and 3B are roughly similar, the sequence of changes in the chip select signal CS#, system clock signal SCLK, data flash mask signal DQSM, and system input and output signal SIO[8:1] will not be repeated here. .

Comparing Figures 3A and 3B, it can be seen that in Figure 3A, the memory module (PSRAM) 11b waits for the preset read delay (dftLC=LC*1), and then can transmit the read data DATm to the main control device 13b. In FIG. 3B, the memory module (PSRAM) 11b has to wait until the read delay rfcLC (eg, rfcLC=LC*2) is updated (time point t9), and then can transmit the read data DATm to the master device 13b. The update read delay rfcLC represents the number of read delay counts LC required for data reading after the update conflict occurs in the memory module (PSRAM) 11b when an update conflict occurs. For ease of illustration, this paper assumes that the update read delay rfcLC is the length of two read delay counts (rfcLC =LC*2). In practical applications, the number of read delay counts LC included in updating the read delay rfcLC is not limited to this.

In Figure 3B, the data flash mask signal DQSM rises from a low level to a high level at time t10, and is used to issue read flash pulse signals m1strb1 and m1strb2 during the period from time t10 to time t11. The memory module (PSRAM) 11b can notify the main control device 13b that the read data DATm has been prepared in the internal buffer through the change of the data flash mask signal DQSM. Next, the memory module (PSRAM) 11b transmits the read data previously stored in the internal buffer to the system input and output signal lines SIO[8:1] for access by the main control device 13b. Since the read operation performed by the master device 13b on the memory module (PSRAM) 11b may be continuous, the memory module (PSRAM) 11b transmits the read data previously stored in the internal buffer to the system input and output Simultaneously with the signal lines SIO[8:1], the memory module (PSRAM) 11b will continue to read data from the memory array and transmit it to the internal buffer.

In some applications, an electronic device may need to use multiple memory modules using PSRAM technology at the same time. For such an electronic device including multiple virtual static random access memory (PSRAM) memory modules at the same time, the main control device may not be able to correctly access the multiple memory modules due to the different statuses of whether the update conflict occurs in the memory modules themselves. The module obtains the read data synchronously.

The present invention relates to a memory device capable of synchronously reading multiple memory modules, an electronic device and a reading method related thereto. When the memory device includes a plurality of memory modules, and an update conflict occurs in one of the memory modules, the main control device in the electronic device can still obtain the read data from the memory module synchronously.

According to a first aspect of the present invention, a memory device electrically connected to a main control device is provided. The main control device performs a read operation on the first memory device during the read operation period (Trd), and the memory device includes a first memory module (PSRAM1) and a second memory module (PSRAM2). The first memory module (PSRAM1) generates an update conflict during a read operation. The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive the first read command (m1CMDrd) and the second read command sent by the main control device during the read command transmission period (Tcmd) (m2CMDrd). The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive the first memory address (m1ADDr, m1ADDc) and the second memory address (m2ADDr, m2ADDc) during the address transfer period (Tadr) . The read command transfer period (Tcmd) is earlier than the address transfer period (Tadr). After the synchronization data preparation period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) simultaneously transmit the first synchronization read data (Tdat_sync) during the synchronization data read period (Tdat_sync). DATm1) and the second synchronous read data (DATm2) to the master device, wherein the synchronous data preparation period (Tsdatpr) is greater than a predetermined read delay (dftLC=LC*1).

According to a second aspect of the present invention, an electronic device is provided. The electronic device includes: a memory device and a main control device. The memory device includes: a first memory module (PSRAM1) and a second memory module (PSRAM2). The first memory module (PSRAM1) generates an update conflict during a read operation. The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive the first read command (m1CMDrd) and the second read command sent by the main control device during the read command transmission period (Tcmd) (m2CMDrd). The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive the first memory address (m1ADDr, m1ADDc) and the second memory address (m2ADDr, m1ADDc) during the address transfer period (Tadr) . The read command transfer period (Tcmd) is earlier than the address transfer period (Tadr). After the synchronization data preparation period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) simultaneously transmit the first synchronization read data (Tdat_sync) during the synchronization data read period (Tdat_sync). DATm1) and the second synchronous read data (DATm2) to the master device, wherein the synchronous data preparation period (Tsdatpr) is greater than a predetermined read delay (dftLC=LC*1).

According to a third aspect of the present invention, a reading method applied to an electronic device is provided. The electronic device includes a main control device, a first memory module (PSRAM1) and a second memory module (PSRAM2). The main control device performs a read operation on the first memory module (PSRAM1) and the second memory module (PSRAM2) during the read operation period (Trd). The first memory module (PSRAM1) generates an update conflict during a read operation, and the read method includes the following steps. First, the first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive the first read command (m1CMDrd) and the second read command ( m2CMDrd). Secondly, the first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive the first memory address (m1ADRr, ADRc) and the second memory address (m2ADRr, m2ADRc). The read command transfer period (Tcmd) is earlier than the address transfer period (Tadr). After the synchronization data preparation period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) simultaneously transmit the first synchronization read data (Tdat_sync) during the synchronization data read period (Tdat_sync). DATm1) and the second synchronous read data (DATm2) to the master device, wherein the synchronous data preparation period (Tsdatpr) is greater than a predetermined read delay (dftLC=LC*1).

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

Please refer to FIG. 4 , which is a schematic diagram of an electronic device including two virtual static random access memory (PSRAM) memory modules. The electronic device 20 includes a main control device 23 and a memory device 25 , and the memory device 25 includes memory modules ( PSRAM1 ) 21 and ( PSRAM2 ) 22 .

The system input/output signal line SIO[16:1] of the main control device 23 includes 16 bits, and 8 of the 16 bits are the system input/output signal line SIO[8:1] and the memory module (PSRAM1) 21 is connected; the other 8 system input and output signal lines SIO[16:9] are connected with the memory module (PSRAM2) 22. The main control device 23 has two data flashing mask signal lines DQSM[2:1], wherein the data flashing mask signal line DQSM[1] is connected to the memory module (PSRAM1) 21, and the data flashing mask signal line DQSM[1] is connected to the memory module (PSRAM1) 21. Line DQSM[2] is connected to the memory module (PSRAM2) 22.

The main control device 23 selects the memory modules (PSRAM1) 21 and (PSRAM2) 22 by using the chip selection signal CS#. According to the system clock signal SCLK, the main control device 23 transmits the memory bits corresponding to the memory modules (PSRAM1) 21 and (PSRAM2) 22 respectively using the system input and output signal lines SIO[8:1] and SIO[16:9] address to the memory modules (PSRAM1) 21 and (PSRAM2) 22, and the memory modules (PSRAM1) 21 and (PSRAM2) 22 use the system input and output signal lines SIO[8:1] and SIO[16:9] respectively. The read data DATm1 and DATm2 are sent to the main control device 23 . The memory address of the memory module (PSRAM1) 21 includes a column address m1ADRr and a row address m1ADRc, and the memory address of the memory module (PSRAM2) 22 includes a column address m2ADRr and a row address m2ADRc.

Please refer to FIG. 5 , which is a schematic diagram of the master control device performing a read operation on the memory modules PSRAM1 and PSRAM2 in a preset data synchronization manner. The waveforms in Fig. 5 are, from top to bottom, the chip select signal CS# and the system clock signal SCLK that are simultaneously transmitted to the memory modules (PSRAM1) 21 and (PSRAM2) 22, and are transmitted to the memory module (PSRAM1) 21 The data flash mask signal DQSM[1] and the system I/O signal SIO[8:1], and the data flash mask signal DQSM[2] and the system I/O signal transmitted to the memory module (PSRAM2) 22 SIO[16:9]. When the data flash mask signals DQSM[1] and DQSM[2] are not driven, they may be in a floating state. Alternatively, the undriven data flash mask signals DQSM[1] and DQSM[2] can be maintained at a high level by a pull-up resistor, or the undriven data flash mask signal can be kept at a high level by a pull-down resistor DQSM[1], DQSM[2] are maintained at low level. In this paper, it is assumed that the undriven data flash mask signals DQSM[1] and DQSM[2] are maintained at a low level.

To simplify the description, in the following waveform diagrams, several time parameters are defined. These time parameters include: read operation period Trd, chip selection period Tcs, set period Tset, read command transfer period Tcmd, address transfer period Tadr, synchronization data preparation period Tsdatpr, and synchronization data read period Tdat_sync. Next, the definitions of these time parameters are briefly introduced.

The read operation period Trd is the time it takes for the main control device 23 to perform the read operation on the memory modules ( PSRAM1 ) 21 and ( PSRAM2 ) 22 . The chip selection period Tcs is a period during which the main control device 23 pulls down the chip selection signal CS# when the main control device 23 performs a read operation on the memory modules (PSRAM1) 21 and (PSRAM2) 22 . The setting period Tset is the time difference between when the main control device 23 pulls down the chip selection signal CS# and before the main control device 23 starts to transmit the read commands m1CMDrd and m2CMDre. The read command transmission period Tcmd is the time required for the master control device 23 to transmit the read commands m1CMDrd and m2CMDre to the memory modules (PSRAM1) 21 and (PSRAM2) 22.

During the address transfer Tadr, the main control device 23 synchronously transfers the memory address (including the column address m1ADRr and the row address m1ADRc) corresponding to the memory module (PSRAM1) 21 to the memory module (PSRAM1) 21, and the time required to transmit the memory address (including the column address m2ADRr and the row address m2ADRc) corresponding to the memory module (PSRAM2) 22 to the memory module (PSRAM2) 22 . The address transfer period Tadr further includes a column address period Tadr_r and a row address period Tadr_c. During the column address period Tadr_r, the master device 23 transmits the column address m1ADRr corresponding to the memory module (PSRAM1) 21 to the memory module (PSRAM1) 21, and synchronously transmits the column address m1ADRr corresponding to the memory module (PSRAM2) 22 Column address m2ADRr to memory module (PSRAM2) 22. During the row address period Tadr_c, the master device 23 transmits the row address m1ADRc corresponding to the memory module (PSRAM1) 21 to the memory module (PSRAM1) 21, and synchronously transmits the row address m1ADRc corresponding to the memory module (PSRAM2) 22 The row address m2ADRc of the memory module (PSRAM2) 22.

In addition, the synchronization data preparation period Tsdatpr is a period of time before the synchronization data reading period Tdat_sync starts after the master device 23 transmits the memory address to the memory modules (PSRAM1) 21 and (PSRAM2) 22. Wherein, the length of Tsdatpr during synchronization data preparation may vary significantly with different embodiments. During the synchronous data read period Tdat_sync is, the memory module (PSRAM1) 21 transmits the synchronous read data DATm1 from the internal buffer to the main control device 23 and the memory module via the system input and output signal lines SIO[8:1] (PSRAM2) The period during which the 22 transmits the synchronous read data DATm2 from the internal buffer to the master device via the system input/output signal lines SIO[16:9]. The end period Tend is the time difference between the end point of the wafer selection period Tcs and the end point of the read operation period Trd.

In Fig. 5, the time point t1 to the time point t11 is the read operation period Trd; the time point t1 to the time point t10 is the chip selection period Tcs; the time point t1 to the time point t2 is the setting period Tset; the time point t2 to the time point t3 is the read command transmission period Tcmd; time point t4 to time point t7 is the address transmission period Tadr; time point t7 to time point t9 is the synchronization data preparation period Tsdatpr; time point t9 to time point t11 is the synchronization data reading period Tdat_sync; time point t10 to time point t11 is the end period Tend. Wherein, the synchronization data reading period Tdat_sync is less than one read delay count LC. In the default data synchronization mode, the memory modules (PSRAM1) 21 and (PSRAM2) 22 only need to spend the period from time point t5 to time point t9 to start transmitting the data in the internal memory to the system input and output signal line SIO [16:1]. Therefore, the period from the time point t5 to the time point t9 can be defined as the general reading period Trdnm.

Since the memory modules (PSRAM1) 21 and (PSRAM2) 22 do not have frequent update conflicts, the memory modules (PSRAM1) 21 and (PSRAM2) 22 usually perform normal read operations as shown in Figure 5. . However, in some cases, one of the memory modules (PSRAM1) 21 and (PSRAM2) 22 may have an update conflict, so that the master control device 23 cannot correctly read the data stored in the memory due to inconsistent reading speeds. The situation of the data in the memory modules (PSRAM1) 21 and (PSRAM2) 22 occurs.

To this end, the present disclosure proposes a memory module (PSRAM1) 21, (PSRAM2) 22 that can dynamically adjust one read delay count LC or two read delay counts in response to the occurrence of an update conflict. The data in the memory modules (PSRAM1) 21 and (PSRAM2) 22 are read by means of LC. For ease of description, the following assumes a situation in which an update conflict occurs inside the memory module (PSRAM1) 21, and a situation in which the memory module (PSRAM2) 22 can perform a normal read operation.

When no update conflict occurs in all memory modules (PSRAM1) 21 and (PSRAM2) 22, the master control device and the memory modules (PSRAM1) 21 and (PSRAM2) 22 count LC with one read delay. way to read data. Conversely, if any one of the memory modules (for example, the memory module (PSRAM1) 21 ) has an update conflict, the master control device 23 can still be synchronized from the memory module through the reporting and notification mechanism. Data is read in (PSRAM1) 21 and (PSRAM2) 22. The present disclosure provides various embodiments, and the basic flow of these embodiments is shown in FIG. 6 .

Please refer to FIG. 6 , which is a flowchart of the synchronous read operation performed by the main control device on the memory modules PSRAM1 and PSRAM2 in the electronic device according to the embodiment of the present invention. First, the main control device 23 pulls down the chip select signal CS# and sends read commands m1CMDrd, m2CMDrd to the memory modules (PSRAM1) 21, (PSRAM2) 22 (step S51). Next, it is determined whether any one of the memory modules (PSRAM1) 21 and (PSRAM2) 22 has an update conflict (step S53). The method of step S53 may be determined by the main control device 23 after detection, or reported by the memory module (PSRAM1) 21 in which the update conflict occurs. Regarding the determination method of step S53, different embodiments will be described later.

If the judgment result of step S53 is negative, it means that all memory modules (PSRAM1) 21 and (PSRAM2) 22 can complete the reading operation in the way of general data reading as shown in FIG. 5 . Therefore, the memory modules (PSRAM1) 21 and (PSRAM2) 22 prepare to read data in the pre-set data synchronization method (Tsdatpr<LC) during the synchronization data preparation period Tsdatpr (step S55), and then during the synchronization data reading period Tdat_sync The synchronous read data DATm1 and DATm2 are transmitted to the main control device 23 (step S59).

On the other hand, the determination result of step S53 is affirmative, which means that one or more memory modules (PSRAM1) 21 have an update conflict. At this time, the one or more memory modules (PSRAM1) 21 that generate the update conflict cannot complete the data retrieval within the preset read delay (dftLC=LC*1). Since the memory module ( PSRAM1 ) 21 which has an update conflict requires a long read period, the read data can be copied from the memory array to the internal buffer. Therefore, the memory module ( PSRAM2 ) 22 that does not have an update conflict must suspend the speed of its read operation so as to be consistent with the read speed of the memory module ( PSRAM1 ) 21 . Therefore, the main control device 23 needs to notify the memory module (PSRAM2) 22 that does not have an update conflict to prepare to read data in a special data synchronization manner. When the special data synchronization method is used to read data, the memory modules (PSRAM1) 21 and (PSRAM2) 22 need to wait for a long synchronization data preparation period Tsdatpr (Tsdatpr>LC) (step S57), and then read the synchronization data. During the fetch period Tdat_sync transmits the synchronous read data DATm1 and DATm2 to the main control device 23 .

According to the concept of the present disclosure, the main control device 23 can automatically sense the occurrence of an update conflict in the memory module ( PSRAM1 ) 21 . Alternatively, when the memory module ( PSRAM1 ) 21 encounters an update conflict, it can actively report the situation to the main control device 23 . The memory module ( PSRAM1 ) 21 can notify the main control device 23 of the update conflict that occurs in the memory module ( PSRAM1 ) through two report modes, an immediate report mode (mode A) and a delayed report mode (mode B). The immediate report mode (mode A) means that if the memory module (PSRAM1) 21 has an internal update conflict, the memory module (PSRAM1) 21 will immediately notify the host device after the chip select signal CS# is pulled low 23 about an update conflict within it. The delayed return mode (mode B) means that if the memory module (PSRAM1) 21 has an internal update conflict, after the memory module (PSRAM1) 21 receives the column address m1ADRr from the main control device 23, the memory module Only the group (PSRAM1) 21 notifies the master device 23 of the situation where an update conflict occurs within it.

Next, FIG. 7A is used to describe the read process when the memory module (PSRAM1) 21 notifies the master control device 23 of an update conflict situation in the immediate report mode (mode A); and, FIG. 7B is used to describe when The memory module ( PSRAM1 ) 21 informs the master device 23 of the read process when an update conflict occurs inside the memory module ( PSRAM1 ) in a delayed report mode (mode B). In Figures 7A and 7B, the sequence of processes is from top to bottom, and from left to right, the main control device 23, the memory module (PSRAM1) 21, and the memory module (PSRAM2) 22 perform the processes respectively. process. In Figures 7A and 7B, the direction of the arrow represents the transmission direction of the signal, and the direction of the dashed arrow represents the optional execution or non-execution according to different embodiments.

Please refer to FIG. 7A, which is based on the concept of the present disclosure, when the memory module PSRAM1 notifies the master device in the immediate report mode (mode A) when an update conflict occurs, the memory modules PSRAM1 and PSRAM2 perform a synchronous read operation flow chart. First, the main control device 23 pulls down the chip select signal CS# corresponding to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (S301a). Next, the memory module (PSRAM1) 21 confirms that an update conflict occurs (step S101a). Next, the memory module ( PSRAM1 ) 21 notifies the main control device 23 of the situation that an update conflict occurs internally (step S103 a ). The details of how the memory module ( PSRAM1 ) 21 notifies the main control device 23 of an update conflict in the memory module ( PSRAM1 ) 21 may vary from embodiment to embodiment, which will be further described later.

After that, the main control device 23 transmits the read commands m1CMDrd and m2CMDrd to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (step S302a), and notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that special The data is read in synchronization mode (step S303a). Depending on the embodiment, step S302a and step S303a may be performed in combination, or step S302a and step S303a may be performed separately.

The method by which the master control device 23 notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that the memory modules (PSRAM1) 21 and (PSRAM2) 22 must be read in a special data synchronization manner may vary according to the embodiment, and will be further described later. Please also note that although step S303a can only be performed after step S103a is completed. However, step S303a is not limited to be executed immediately after step S103a is completed. For example, step S303a can also be executed after step S307a ends.

Next, the main control device 23 transmits the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc of the memory modules (PSRAM1) 21 and (PSRAM2) 22 successively by using the system input and output signals SIO[16:1] (step S305a, S307a). Among them, the system input and output signals SIO[8:1] are used to transmit the column address m1ADRr and the row address m1ADRc corresponding to the memory module (PSRAM1) 21; the system input and output signals SIO[16:9] are used to transmit and The memory module (PSRAM2) 22 corresponds to the column address m2ADRr and the row address m2ADRc.

After the memory module (PSRAM1) 21 waits for the update conflict to end (step S105a), it transmits the synchronous read data DATm1 to the master device 21 by using the system input and output signals SIO[8:1] (step S107a). While the memory module (PSRAM1) 21 transmits the read data DATm1, the memory module (PSRAM2) 22 also needs to wait for the synchronization data preparation period Tsdatpr to end (step S201a). Thereafter, the memory module (PSRAM2) 22 transmits the synchronous read data DATm2 to the main control device 23 by using the system input and output signals SIO[16:9] (step S203a).

Please refer to FIG. 7B , according to the concept of the present disclosure, when the memory module PSRAM1 notifies the master device in a delayed report mode (mode B) when an update conflict occurs, the memory modules PSRAM1 and PSRAM2 perform a synchronous read operation flow chart. First, the main control device 23 pulls down the chip select signal CS# of the memory modules (PSRAM1) 21 and (PSRAM2) 22 (S301b). Next, the main control device 23 sends the read commands m1CMDrd and m2CMDrd and the column addresses m1ADRr and m2ADRr to the memory modules (PSRAM1) 21 and (PSRAM2) 22 (steps S303b and S305b).

After the memory module (PSRAM1) 21 confirms that an update conflict occurs (step S101b), the memory module (PSRAM1) 21 notifies the main control device 23 of the internal update conflict (step S103b). At the same time, the main control device 23 transmits the row addresses m1ADRc and m2ADRc to the memory modules (PSRAM1) 21 and (PSRAM2) 22 using the system input and output signal lines SIO[16:1] (step S307b). After that, the main control device 23 notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that the data must be read in a special data synchronization manner (step S309a).

After the memory module (PSRAM1) 21 waits for the update conflict to end (step S105b), it transmits the synchronous read data DATm1 of the internal buffer to the master device 21 by using the system input and output signals SIO[8:1] (step S107b). On the other hand, after the memory module (PSRAM2) 22 waits for the synchronous data preparation period Tsdatpr to end (step S201b), it transmits the synchronous read data DATm2 of the internal buffer to the master using the system input and output signals SIO[16:9] device 21 (step S203b).

See also Figures 7A, 7B. It can be seen that the steps to be performed in these two flowcharts are roughly similar, and the main difference between the two is that the memory module (PSRAM1) 21 notifies the main control device 23 to generate an update conflict (step S103a, step S103a in FIG. Step S103b in Fig. 7B, and the main control device 23 notifies the memory modules (PSRAM1) 21 and (PSRAM2) 22 that the memory modules (PSRAM1) 21 and (PSRAM2) 22 must be read in a special data synchronization method (step S303a in Fig. 7A, step S309b in Fig. 7B) time is different. In the immediate report mode (mode A) (FIG. 7A), the memory module (PSRAM1) 21 updates the conflicting data before the master device 23 transmits the read commands m1CMDrd and m2CMDrd and the column addresses m1ADRr and m2ADRr. The main control device 23 is notified of the situation. In the delayed return mode (mode B) (FIG. 7B), the memory module (PSRAM1) 21 updates the conflicting data after the master device 23 transmits the read commands m1CMDrd and m2CMDrd and the column addresses m1ADRr and m2ADRr. The main control device 23 is notified of the situation.

Memory modules can be divided into single bank and multibank. The memory module of the single memory bank can know whether an update conflict occurs in the memory module of the single memory bank at the moment when the chip select signal CS# is pulled low. On the other hand, the memory module of the multi-memory bank must wait for the column addresses m1ADRr and m2ADRr to be received before judging whether an update conflict occurs. Therefore, the immediate return mode (Mode A) is applicable to the memory modules of a single memory bank, and the delayed return mode (Mode B) is applicable to the memory modules of the single memory bank and the multi-memory bank. The embodiments provided below will respectively illustrate how the memory module (PSRAM1) 21 uses the immediate report mode (Mode A) and the delayed report mode (Mode B) to report the update conflict.

According to the embodiment of the present disclosure, when the memory module (PSRAM1) 21 reports the update conflict situation to the master control device 23, the memory module (PSRAM1) 21 notifies the master control device 23 of the reporting time except that the reporting time can be changed according to different embodiments. The medium and means of the device 23 may also vary. For example, the memory module ( PSRAM1 ) 21 can use different signal lines and various combinations of control waveforms for the signals to notify the main control device 23 .

Next, the waveform diagrams corresponding to the embodiments that can be adopted by the reading method based on the concept of the present disclosure will be described herein. First, Figures 8A and 8B use the existing data flash mask signal DQSM as a transmission medium, respectively illustrating the methods of adopting the immediate return mode (mode A) and the delayed return mode (mode B). Related embodiments using different signal lines as transmission media will be provided later.

Please refer to FIG. 8A , which is an embodiment of a synchronous read operation between the memory module and the master device using the data flash mask signal DQSM and the immediate report mode (mode A) according to the concept of the present disclosure. Waveform diagram. In this figure, the time point t1 to the time point t15 is the read operation period Trd; the time point t1 to the time point t14 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t8 is the address transfer period Tadr; time point t8 to time point t13 is the synchronization data preparation period Tsdatpr; time point t13 to time point t15 is the synchronization data reading period Tdat_sync; time point t14 to time point t15 is the end period Tend.

After the main control device 23 pulls down the chip select signal CS# to a low level at time t1, the memory module (PSRAM1) 21 starts at time t2 by pulling the data flash mask signal DQSM[1] to a low level. In the high mode, the main control device 23 is notified that an update conflict has occurred internally. The memory module (PSRAM1) 21 maintains the data flash mask signal DQSM[1] at a high level from the time point t2 to the time point t7, and starts to pull down the data flash mask signal DQSM[1] to a low level at the time point t7. low level. The period from the time point t2 to the time point t7 can be defined as the update conflict notification period Trfrp of the master control device 23 when the memory module (PSRAM1) 21 having an update conflict will notify the master device 23 of the update conflict.

On the other hand, the memory module (PSRAM2) 22 keeps the data flash mask signal DQSM[2] at a low level until time point t10. At the time point t2, the main control device 23 has grasped the memory module (PSRAM1) 21 by the high-level data flash mask signal DQSM[1] and the low-level data flash mask signal DQSM[2] respectively. , (PSRAM2) 22 state. Among them, the high-level data flash mask signal DQSM[1] represents that the memory module PSRAM1 has an update conflict, and the low-level data flash mask signal DQSM[2] represents that the memory module (PSRAM2) 22 does not An update conflict has occurred.

Next, during the period from time point t3 to time point t4 (the read command transmission period Tcmd), the main control device 23 uses the system input and output signals SIO[8:1] to issue a special read command m1CMDrd_sp to the memory module (PSRAM1) 21, and The special read command m2CMDrd_sp is sent to the memory module (PSRAM2) 22 using the system input and output signals SIO[16:9]. Once the memory module (PSRAM2) 22 receives the special read command m2CMDrd_sp, it can know that this read operation should be slowed down. Here, the special read commands m1CMDrd_sp and m2CMDrd_sp are represented by the dotted mesh bottom and the thick outer frame. According to this, at time t4, the memory module (PSRAM2) 22 has learned through the special read command m2CMDrd_sp issued by the main control device 23 that it should not be performed at the speed of the normal read operation at present, and additionally wait for the memory module Group (PSRAM1) 21 completes its update conflict.

As mentioned above, the memory modules (PSRAM1) 21 and (PSRAM2) 22 start to count the read delays after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG. 8A that the memory modules (PSRAM1) 21 and (PSRAM2) 22 both count the read delay counts from the time point t5. Among them, the memory module (PSRAM1) 21 needs two read delay counts (LC*2), until the time point t12, the read data can be obtained from the internal memory array to the internal buffer, and the memory module ( The PSRAM2)22 only needs one read delay count (LC*1), and from the time point t9, the read data can be obtained from the internal memory array to the internal buffer. Next, how and when the memory modules (PSRAM1) 21 and (PSRAM2) 22 transmit and synchronously read the data DATm1 and DATm2 from the internal buffer are respectively described.

The update conflict of the memory module (PSRAM1) 21 ends at the time point t12, and at the next rising edge of the system clock signal SCLK (ie, the time point t13), the data flash mask signal DQSM[1] is successively used to generate reads. Flashing pulse signals m1strb1, m1strb2. Here, the time point t5 to the time point t13 are defined as the update conflict reading period Trdrf. The update conflict read period Trdrf represents the read delay count (LC*2) required for the memory module to wait for the update to complete, plus the period required to wait for the rising edge of the next system clock signal SCLK (time t12 to time t13 ). That is, Trdrf=LC*2+(t13-t12). In FIG. 8A, the memory module (PSRAM1) 21 starts to transmit the synchronous read data DATm1 from the time point t13.

Since the memory module (PSRAM2) 22 is ready to read data in the internal buffer when a read delay count ends (ie, time t9 ), and the next rising edge of the system clock signal SCLK (ie, time point t9 ) At t10), the data flash mask signal DQSM[2] is used to transmit the read flash pulse signals m2strb1', m2strb2' to the main control device 23 successively. Therefore, the memory module (PSRAM2) 22 starts to transmit the read data from the internal buffer to the system input and output signals SIO[16:9] from the time point t10. Since the read data transmitted by the memory module (PSRAM2) 22 from the time point t10 to the time point t11 is not used by the main control device 23, the memory module (PSRAM2) 22 transmits the read data from the time point t10 to the time point t11. The read data may be called discard data drpDATm2, and the period during which the memory module (PSRAM2) 22 transmits the discard data drpDATm2 may be defined as the data discard period Tdrp2.

After that, after the memory module (PSRAM2) 22 remains idle for a period of time (time t11 to time t13), it will start to generate again from time t13 and transmit the read flash pulse signal with the data flash mask signal DQSM[2] m2strb1, m2strb2. In addition, the memory module (PSRAM2) 22 also starts from the time point t13, and again transmits the read data from the internal buffer to the system input and output signals SIO[16:9]. According to the concept of the present disclosure, the read data transmitted by the memory module (PSRAM2) 22 from the time point t13 is synchronized with the time point of the read data transmitted by the memory module (PSRAM1) 21 from the time point t13. The read data transmitted by the modules (PSRAM1) 21 and (PSRAM2) 22 from the time point t13 are called synchronous read data DATm1 and DATm2.

According to the concept of the present disclosure, the main control device 23 does not use the discarded data drpDATm2 sent by the memory module (PSRAM2) 22 from the time point t10 to the time point t11, but uses the memory module (PSRAM2) 22 from the time point t13 to the time point t11. The synchronous read data DATm2 transmitted during the time point t15. Therefore, the period from the time point t10 to t11 is defined as the data discard period Tdrp2. The internal buffer of the memory module (PSRAM2) 22 uses the system input and output signals SIO[16:9] to transmit the discarded data drpDATm2 after reading the flash pulse signals m2strb1', m2strb2', and the content of the discarded data drpDATm2 after reading the flash The content of the synchronous read data DATm2 transmitted after the pulse signals m2strb1 and m2strb2 is exactly the same.

Even if the memory module ( PSRAM2 ) 22 transmits the read data from the time point t10 to the time point t11 , the read data needs to be retransmitted from the time point t13 after that. Therefore, from the time point t9 to the time point t13, the memory module (PSRAM2) 22 is a period of time required to wait for the update conflict of the memory module (PSRAM1) 21 to end. Since the period from the time point t9 to the time point t13 is not the period required for the memory module (PSRAM2) 22 to perform its own read operation (with no update conflict), but the memory (with the actual update conflict) The period for which the read operation is suspended after the update conflict of the module (PSRAM1) 21 is completed. Therefore, the time point t9 to the time point t13 is defined here as the memory module (PSRAM2) 22 (with no update conflict) is waiting for the update conflict of the memory module (PSRAM1) 21 (with the update conflict) to end. Additional waiting period Taddwt (additional waiting duration) for simultaneous data reading.

As can be seen from FIG. 8A, the memory module (PSRAM1) 21 transmits the read data from the time point t13 to the time point t15, and the memory module (PSRAM2) 22 transmits the read data from the time point t13 to the time point t15. . Therefore, the period from the time point t13 to the time point t15 can be referred to as the synchronous data read period Tdat_sync, and the read data transmitted by the memory modules (PSRAM1) 21 and (PSRAM2) 22 are referred to as the synchronous read data DATm1 and DATm2.

In some applications, the memory module (PSRAM2) 22 can be designed to suspend the transmission of the read data from the internal buffer to the system I/O signal once the memory module (PSRAM1) 21 is known to have an update conflict. SIO[16:9], until the time point t13, the memory module (PSRAM2) 22 starts to transmit the read flash pulse signals m2strb1, m2strb2 and the synchronous read data DATm2. That is, the data flash mask signal DQSM[2] corresponding to the memory module (PSRAM2) 22 maintains a low level during the period from the time point t2 to the time point t13, and the system input corresponding to the memory module (PSRAM2) 22 The output signal SIO[16:9] does not output data from the memory module (PSRAM2) 22 during the period from the time point t8 to the time point t13.

Please refer to FIG. 8B, which is a kind of synchronous read operation using the data flash mask signal DQSM and the delayed return mode (mode B) between the memory modules PSRAM1, PSRAM2 and the main control device according to the concept of the present disclosure Example waveforms. In this figure, the time point t1 to the time point t17 is the read operation period Trd; the time point t1 to the time point t16 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t9 is the address transmission period Tadr; time point t9 to time point t15 is the synchronization data preparation period Tsdatpr; time point t15 to time point t17 is the synchronization data reading period Tdat_sync; time point t16 to time point t17 is the end period Tend.

After the main control device 23 pulls down the chip selection signal CS# to a low level at the time t1, the memory modules (PSRAM1) 21 and (PSRAM2) 22 flash the data flash mask signals DQSM[1], DQSM[ at the time t2. 2] Keep it low. Then, during the period from time point t3 to time point t4, the main control device 23 sends read commands m1CMDrd and m2CMDrd to the memory modules (PSRAM1) 21 and (PSRAM2) 22 through the system input and output signal lines SIO[16:1]. Next, from the time point t4 to the time point t6, the main control device 23 transmits the column address m1ADRr corresponding to the memory module (PSRAM1) 21 by using the system input and output signals SIO[8:1], and uses the system input and output signals SIO[ 16:9] The column address m2ADRr corresponding to the memory module (PSRAM2) 22 is transmitted. During the period from the time point t6 to the time point t9, the main control device 23 transmits the row address m1ADRc corresponding to the memory module (PSRAM1) 21 by using the system input and output signals SIO[8:1], and uses the system input and output signals SIO[16: 9] Send the row address m2ADRc corresponding to the memory module (PSRAM2) 22.

As mentioned above, when the memory module (PSRAM1) 21 adopts the delayed return mode (mode B), the main control device 23 is notified after the memory module (PSRAM1) 21 receives the column address m1ADRr. Therefore, the memory module (PSRAM1) 21 notifies the main control device 23 that an update conflict occurs in the memory module (PSRAM1) 21 by pulling up the level of the data flash mask signal DQSM[1] during the time point t7 and the time point t8 situation. The period from the time point t7 to the time point t8 can be defined as the new conflict notification period Trfrp required by the master control device 23 when the memory module (PSRAM1) 21 having an update conflict will notify the master device 23 of the update conflict.

Next, from the time point t9 to the time point t10 (the extended read command period Tcmdext), the main control device 23 respectively transmits the extended read command m1CMDext to the memory module (PSRAM1) 21 by using the data flash mask signal DQSM[1], and using the data flash mask signal DQSM[2] to transmit the extended read command m2CMDext to the memory module (PSRAM2) 22. Accordingly, at time t10, the memory module (PSRAM2) 22 has been informed by the main control device 23 that the current read operation should not be performed at the speed of the normal read operation, and an additional waiting time for the memory module (PSRAM1) is required. )21 internal completion update conflict.

As mentioned above, after the memory modules (PSRAM1) 21 and (PSRAM2) 22 receive the column addresses m1ADRr and m2ADRr, the read delay count LC is started. Therefore, it can be seen from FIG. 8B that the memory modules (PSRAM1) 21 and (PSRAM2) 22 both count the read delay counts from the time point t5. Among them, the memory module (PSRAM1) 21 needs two read delay counts (LC*2) to obtain the read data from the internal memory array to the internal buffer, while the memory module (PSRAM2) 22 only needs to After a read latency count (LC), read data can be obtained from the internal memory array to the internal buffer. Next, how and when the memory modules (PSRAM1) 21 and (PSRAM2) 22 transmit and read the data DATm1 and DATm2 synchronously will be described respectively.

The memory module (PSRAM1) 21 ends its update conflict at the time point t14, and at the next rising edge of the system clock signal SCLK (ie, time point t15), the data flash mask signal DQSM[1] is successively used to generate reads Flashing pulse signals m1strb1, m1strb2. Therefore, the internal buffer of the memory module (PSRAM1) 21 starts to transmit the synchronous read data DATm1 by using the system input and output signals SIO[16:9] from the time point t15. Here, the time point t5 to the time point t15 is defined as the update conflict reading period Trdrf.

Since the memory module (PSRAM2) 22 can finish reading when one read delay count ends (ie, time point t11 ), and at the next rising edge of the system clock signal SCLK (ie, time point t12 ), the data flashes successively with data The control mask signal DQSM[2] generates read flash pulse signals m2strb1', m2strb2'. Therefore, the memory module (PSRAM2) 22 transmits the read data from the internal buffer from the time point t12 to the time point t13.

After that, the memory module (PSRAM2) 22 will remain idle for a period of time (from time point t13 to time point t15 ), and then start from time point t15 to generate read flash pulse signals m2strb1 and m2strb2 with the data flash mask signal DQSM[2] again . In addition, the memory module (PSRAM2) 22 will also transmit the synchronous read data DATm2 with the system input and output signals SIO[16:9] again starting from the time point t15.

Similar to Section 8A, the main control device 23 does not use the read data transmitted by the memory module (PSRAM2) 22 from the time point t12 to the time point t13, but uses the memory module (PSRAM2) 22 from the time point t15 to the time point Synchronous read data DATm2 transmitted during t17. Therefore, the read data transmitted by the memory module (PSRAM2) 22 from the time point t12 to the time point t13 can be referred to as the discarded data drpDATm2, and the period during which the memory module (PSRAM2) 22 transmits the discarded data drpDATm2 can be defined as Data discard period Tdrp2. The discarded data drpDATm2 transmitted from the time point t12 to the time point t13 by the system input and output signal SIO[16:9] and the synchronous read data DATm2 transmitted from the time point t15 to the time point t17 are both buffered by the internal buffer of the memory module (PSRAM2) 22 The content of the two is exactly the same.

The time point t11 to the time point t15 is equivalent to a waiting period for the memory module ( PSRAM2 ) 22 to wait for the update conflict of the memory module ( PSRAM1 ) 21 to end, which is an additional waiting period. Since the period from the time point t11 to the time point t15 is not the period required for the memory module (PSRAM2) 22 to perform its own read operation (with no update conflict), but the memory (with the actual update conflict) The period for which the read operation is suspended after the update conflict of the module (PSRAM1) 21 is completed. Therefore, the time point t11 to the time point t15 is defined here as the additional waiting period Taddwt of the memory module (PSRAM2) 22 (when no update conflict occurs).

It can be seen from FIG. 8B that the memory module (PSRAM1) 21 transmits the synchronous read data DATm1 during the period from time point t15 to time point t17, and the memory module (PSRAM2) 22 transmits the synchronization data during the period from time point t15 to time point t17. Read data DATm2. Therefore, the period from the time point t15 to the time point t17 is the synchronization data reading period Tdat_sync. During the synchronous data read period Tdat_sync, the internal buffers of the memory modules (PSRAM1) 21 and (PSRAM2) 22 can synchronously transmit the read data through the system input and output signals SIO[8:1], SIO[16:9] sent to the main control device 23 .

Please also note that in practical application, the method of Figure 8B can also be combined with other changes. For example, because the memory module ( PSRAM1 ) 21 itself has an update conflict, the main control device 23 only needs to notify the memory module ( PSRAM2 ) 22 that does not have the update conflict. Therefore, in some applications, the master device 23 may only issue the extended read command m2CMDext to the memory module (PSRAM2) 22, but not issue the extended read command m1CMDext to the memory module (PSRAM1) 21.

In addition, in some applications, the memory module (PSRAM2) 22 may only transmit the synchronous read data DATm2 without transmitting the discarded data drpDATm2 using the system I/O signals SIO[16:9]. Therefore, the memory module PSRAM2 stops transmitting any data from the time point t10 to the time point t15, and the data flash mask signal DQSM[2] is maintained at a low level from the time point t2 to the time point t15. The changes in these applications are not detailed here.

See also Figures 8A and 8B. Since the immediate report mode (mode A) described in FIG. 8A reports the update conflict situation to the master device 23 earlier than the delayed report mode (mode B) described in FIG. 8B, the update conflict notification period of FIG. 8A Trfrp is longer than the update conflict notification period Trfrp of Figure 8B. In addition, the lengths of the additional waiting period Taddwt and the update conflict reading period Trdrf are not different due to the different reporting modes used. Furthermore, in practical applications, different memory modules may also be matched with different return modes.

In the embodiment shown in Figs. 8A and 8B, the existing data flash mask signal lines DQSM[1] and DQSM[2] are used as the memory modules PSRAM1 and PSRAM2 to report the occurrence of the update conflict. medium. In some applications, additionally provided signal lines can be used as a medium for the memory modules PSRAM1 and PSRAM2 to report the occurrence of update conflicts. Figures 9A, 9B and 10 show that the memory modules (PSRAM1) 51, (PSRAM2) 52 and the main control device 53 are provided with a memory bank busy signal (bank read busy, abbreviated as BRBB), and the memory bank busy signal line is used BRBB is used as an example for the memory modules (PSRAM1) 51 and (PSRAM2) 52 to report update conflicts to the master device 53 . Among them, Figures 9A and 9B show that the memory bank busy signal line BRBB is set between the main control device 53 and the memory modules (PSRAM1) 51 and (PSRAM2) 52, and the drive will be changed according to the state of the read operation. end situation.

In FIGS. 9A and 9B , the electronic device 50 includes a main control device 53 and memory modules 51 and 52 . The main control device 53 is electrically connected to the memory modules (PSRAM1) 51 and (PSRAM2) 52 through CS# and the system clock signal SCLK at the same time. In addition, the main control device 53 is electrically connected to the memory module 51 through the system input and output signals SIO[8:1] and the data flash mask signal DQSM[1], and is also electrically connected to the memory module 51 through the system input and output signals SIO[16:9] . The data flashing mask signal DQSM[2] is electrically connected to the memory module (PSRAM2) 52. Furthermore, the memory bank busy signal line BRBBh of the main control device 53, the memory bank busy signal line BRBBm1 of the memory module (PSRAM1) 51, and the memory bank busy signal line BRBBm2 of the memory module (PSRAM2) 52 are electrically connected together together. According to an embodiment of the present invention, the memory bank busy signal lines BRBBh, BRBBm1, and BRBBm2 can be connected to each other using common wiring. Alternatively, the memory bank busy signal lines BRBBh, BRBBm1 and BRBBm2 can be used as shown in Figs. 9A and 9B, together with the bidirectional interface circuits 501, 511, 521 and the pull-up resistor 50a. The pull-up resistor 50a is electrically connected between the supply voltage Vcc and the memory bank busy signal line BRBBh. In Figs. 9A and 9B, the signal driving directions on the memory bank busy signal lines BRBBh, BRBBm1, and BRBBm2 are marked with dotted lines.

When the memory bank busy signal lines BRBBh, BRBBm1, BRBBm2 are used in conjunction with the bidirectional interface circuits 501, 511, 521 and the pull-up resistor 50a, the memory module (for example, the memory module (PSRAM1) 51) that has an update conflict can be Based on the wired OR (wired OR) wiring method, the effect of simultaneously notifying the main control device 53 and other memory modules (eg, the memory module (PSRAM2) 52 ) that does not have an update conflict is achieved. In Figures 9A and 9B, the bidirectional interface circuit 501 of the main control device 53 includes an output inverter 501a and an input inverter 501b with opposite connection modes; the bidirectional interface circuit 511 of the memory module (PSRAM1) 51 includes a connection mode The output inverter 511a and the input inverter 511b are opposite; the bidirectional interface circuit 521 of the memory module (PSRAM2) 52 includes the output inverter 521a and the input inverter 521b connected in opposite ways.

Please refer to FIG. 9A , which is a schematic diagram of setting a memory bank busy signal line BRBB between the memory module and the main control device, and the main control device drives the memory bank busy signal BRBB. When the main control device 53 is used as the driving end of the memory bank busy signal line, the driving signal sent by the main control device 53 is first transmitted to the memory bank busy signal line BRBBh by the output inverter 501a in the bidirectional interface circuit 501, and then respectively through the memory bank The bank busy signal line BRBBm1 and the input inverter 511b of the bidirectional interface circuit 511 are transmitted to the memory module (PSRAM1) 51, and are transmitted to the memory via the memory bank busy signal line BRBBm2 and the input inverter 521b of the bidirectional interface circuit 521 Module (PSRAM2) 52 .

Please refer to FIG. 9B , which is a schematic diagram of setting a memory bank busy signal line BRBB between the memory module and the main control device, and the memory module driving the memory bank busy signal BRBB. When the memory bank busy signal line uses the memory module (PSRAM1) 51 as the driving end, the memory module (PSRAM1) 51 first transmits the driving signal to the memory bank busy signal line through the output inverter 511a in the bidirectional interface circuit 511 BRBBm1 is then transmitted to the main control device 53 via the memory bank busy signal line BRBBh and the input inverter 501b of the bidirectional interface circuit 501, and is transmitted to the main control device 53 via the memory bank busy signal line BRBBm2 and the input inverter 521b of the bidirectional interface circuit 521, respectively. Memory module (PSRAM2) 52 .

Under the default condition, if the main control device 53 and the memory modules (PSRAM1) 51 and (PSRAM2) 52 do not generate driving signals, the pull-up resistor 50a is used to maintain the memory bank busy signals BRBBh, BRBBm1 and BRBBm2 at high level. Herein, it is assumed that the drive capability of the memory modules (PSRAM1) 51 and (PSRAM2) 52 to the memory bank busy signals BRBBm1 and BRBBm2 is greater than the drive capability of the main control device 53 to the memory bank busy signal BRBBh. Moreover, the driving capability of the memory bank busy signal BRBBh sent by the main control device 53 is greater than the driving capability of the pull-up resistor 50a.

Next, using the wiring diagrams shown in Figures 9A and 9B and Figure 10 to illustrate that the memory module uses the memory bank busy signals BRBB (PSRAM1) 51 and (PSRAM2) 52 to report the occurrence of an update conflict and the occurrence of an update conflict to the main control device 53. No example.

Please refer to FIG. 10, which is a waveform of an embodiment of a synchronous read operation using the memory bank busy signal line BRBB and the immediate report mode (mode A) between the memory module and the main control device according to the concept of the present disclosure picture. In this figure, the time point t1 to the time point t15 is the read operation period Trd; the time point t1 to the time point t14 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t8 is the address transfer period Tadr; time point t8 to time point t13 is the synchronization data preparation period Tsdatpr; time point t13 to time point t15 is the synchronization data reading period Tdat_sync; time point t14 to time point t15 is the end period Tend.

After the master device 53 pulls down the chip select signal CS# to a low level at time t1, the memory module (PSRAM1) 51 notifies the master by pulling down the level of the memory bank busy signal BRBBm1 at time t2. The update conflict occurs inside the control device 53 . The memory module ( PSRAM1 ) 51 maintains the memory bank busy signal BRBBm1 at a low level from the time point t2 to the time point t7 , and starts to pull the memory bank busy signal BRBBm1 to a high level at the time point t7 . The period from the time point t2 to the time point t7 may be defined as the update conflict notification period Trfrp.

On the other hand, during the period from the time point t1 to the time point t7, the memory module PSRAM2 maintains the memory bank busy signal BRBBm2 at a high level. At this time, the signal driving situation between the memory bank busy signal lines BRBBh, BRBBm1, and BRBBm2 will be as shown in Section 9B. That is, the memory bank busy signal BRBBm1 sent by the memory module ( PSRAM1 ) 51 will drive the memory bank busy signal BRBBh of the main control device and the memory bank busy signal BRBBm2 corresponding to the memory module ( PSRAM2 ) 22 .

Although in FIG. 10, the memory bank busy signal BRBBm2 sent by the memory module (PSRAM2) 52 is at a high level, since the memory module (PSSRAM1) 51 is actively driven from the time point t2, the memory The memory bank busy signal line BRBBm2 of the bulk module PSRAM2 also starts at time t2, and the level is lowered. In addition, the memory module (PSRAM2) 52 can immediately know that other memory modules (ie, the memory module (PSRAM1) 51 ) have an update conflict by the phenomenon that the level of the memory bank busy signal BRBBm2 is lowered. condition.

In Fig. 10, the effect of notifying the memory module PSRAM2 is achieved by means of hardware wiring as shown in Figs. 9A and 9B. Therefore, in FIG. 10, the main control device 53 does not need to notify the memory module PSRAM2 by means of the special read command m2CMDrd_sp, the extended read command m2CMDext, etc. as shown in FIGS. 8A and 8B.

In some applications, the memory bank busy signal lines BRBBh, BRBBm1, and BRBBm2 can also be used without the bidirectional interface circuit and the pull-up circuit. For these applications, the method as shown in FIGS. 8A and 8B can be used to notify the memory module (PSRAM2) 52 from the main control device 53 .

As mentioned above, the memory modules (PSRAM1) 51 and (PSRAM2) 52 start to count the read delays after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG. 10 that the memory modules (PSRAM1) 51 and (PSRAM2) 52 both count the read delay counts from the time point t5. Among them, the memory module (PSRAM1) 51 needs two read delay counts (LC*2) to prepare the read data in the internal buffer, while the memory module PSRAM2 only needs one read delay count (LC) is ready to read data in the internal buffer. Next, it is explained how and when the memory modules PSRAM1 and PSRAM2 transmit the synchronous read data DATm1 and DATm2 respectively.

The update conflict of the memory module (PSRAM1) 51 ends at the time point t12, and at the next rising edge of the system clock signal SCLK (ie, the time point t13), the data flash mask signal DQSM[1] is successively used to generate reads. Flashing pulse signals m1strb1, m1strb2. Therefore, the memory module (PSRAM1) 51 starts to transmit the synchronous read data DATm1 using the system input and output signals SIO[8:1] from the time point t13.

Since the memory module (PSRAM2) 52 can finish reading when one read delay count ends (ie, time point t9 ), and at the next rising edge of the system clock signal SCLK (ie, time point t10 ), flashing with data The mask signal DQSM[2] successively generates read flash pulse signals m2strb1', m2strb2'. Therefore, the memory module (PSRAM2) 52 starts to transmit the discarded data drpDATm2 using the system I/O signals SIO[16:9] from the time point t10. The period during which the memory module (PSRAM2) 52 transmits the discard data drpDATm2 is defined as the data discard period Tdrp2.

After that, the memory module (PSRAM2) 52 will remain idle for a period of time (from time point t11 to time point t13), and then starts to generate read flash pulse signals m2strb1 and m2strb2 with the data flash mask signal DQSM[2] again starting from time point t13 . The time point t9 to the time point t13 can be defined as the additional waiting period Taddwt spent by the memory module (PSRAM2) 22 for waiting for the update conflict of the memory module (PSRAM1) 51 to end. The memory module (PSRAM2) 52 will also transmit the synchronous read data DATm2 again from the time point t13.

According to the concept of the present disclosure, the main control device 53 does not use the discarded data drpDATm2 transmitted by the memory module (PSRAM2) 52 from the time point t9 to the time point t10, but uses the memory module (PSRAM2) 52 from the time point t13 to the time point t10. The synchronous read data DATm2 transmitted during the time point t15. The discarded data drpDATm2 and the synchronous read data DATm2 transmitted through the system input and output signals SIO[16:9] are both provided by the memory module (PSRAM2) 22, and their contents are identical.

Here, the time point t5 to the time point t13 is defined as, in response to the update conflict occurred in the memory module (PSRAM1) 51, waiting for the memory module (PSRAM1) 51 to copy the read data to the internal buffer for the update conflict read Period Trdrf. It can be seen from FIG. 10 that the memory module (PSRAM1) 51 transmits the synchronous read data DATm1 during the period from time point t13 to time point t15, and the memory module (PSRAM2) 52 (synchronization) is transmitted from time point t13 to time point t15. During the data read period Tdat_sync) transmits the synchronous read data DATm2. Therefore, the memory modules (PSRAM1) 51 and (PSRAM2) 52 can transmit the read data to the main control device 53 synchronously.

Figure 10 shows the waveform diagram of the memory modules (PSRAM1) 51, (PSRAM2) 52 and the main control device 53, using the memory bank busy signal lines BRBBh, BRBBm1, BRBBm2 to match the immediate report mode (mode A). In application, the delayed return mode (mode B) can also be used. The method of matching the delayed return mode (mode B) can be analogized to the descriptions in Figure 8B and Figure 10, so it will not be described in detail.

Furthermore, the present disclosure can also use existing signal lines (eg, chip select signal CS#, system clock signal SCLK, data flash mask signal DQSM, etc.) between the main control device and the memory modules PSRAM1 and PSRAM2, And the additionally arranged signal lines are matched with each other, thereby generating a specific waveform change, which is used for reporting the states of the memory modules (PSRAM1) 51 and (PSRAM2) 52 . For example, in Figure 11, it is assumed that the data flash mask signal DQSM[1] is used in conjunction with the changes of the memory bank busy signals BRBBm1 and BRBBh as the communication between the master device and the memory modules PSRAM1 and PSRAM2.

Please refer to FIG. 11, which is another embodiment of the synchronous read operation of the memory modules PSRAM1 and PSRAM2 after the memory module PSRAM1 notifies the master device in the immediate report mode (mode A) according to the concept of the present disclosure. Waveform diagram. In this figure, the time point t1 to the time point t13 is the read operation period Trd; the time point t1 to the time point t12 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t8 is the address transmission period Tadr; time point t8 to time point t11 is the synchronization data preparation period Tsdatpr; time point t11 to time point t13 is the synchronization data reading period Tdat_sync; time point t12 to time point t13 is the end period Tend.

After the main control device 53 pulls down the chip selection signal CS# at the time point t1, the memory module (PSRAM1) 51 simultaneously pulls down the level of the memory bank busy signal BRBBm1 at the time point t2 and blocks the data flash. By pulling the level of the mask signal DQSM[1] high, the master control device 53 is notified that an update conflict has occurred therein. The memory module (PSRAM1) 51 maintains the memory bank busy signal BRBBm1 at a low level and the data flash mask signal DQSM[1] at a high level during the period from the time point t2 to the time point t7 (the update conflict notification period Trfrp).

Since the memory module (PSRAM1) 51 keeps the memory bank busy signal BRBBm1 at a low level during the update conflict notification period, the memory bank busy signal BRBBh will be received from the memory module (PSRAM1) as shown in FIG. 9B Trfrp remains low during update conflict notification due to the influence of the memory bank busy signal BRBBm1 at 51 . The memory module (PSRAM1) 51 stops pulling the memory bank busy signal BRBBm1 high at time t7, and starts pulling the data flash mask signal DQSM[1] to a low level.

On the other hand, during the period from time t1 to time t7, the memory module (PSRAM2) 52 maintains the memory bank busy signal BRBBm2 at a high level, and maintains the data flash mask signal DQSM[2] at a low level. Although the memory module (PSRAM2) 52 maintains the memory bank busy signal BRBBm2 at a high level from the time point t2 to the time point t7, the memory bank busy signals BRBBh, BRBBm1 and BRBBm2 are connected in a wired OR manner. For this reason, the memory module (PSRAM1) 51 pulls down the memory bank busy signal BRBBm1 to a low level from the time point t2 to the time point t7, which will still be reflected in the memory bank busy signal BRBBm2, so that the bit of the memory bank busy signal BRBBm2 is still reflected. subject to fluctuations. Therefore, the memory module (PSRAM2) 52 can know the update conflict of the memory module (PSRAM1) 51 by the signal fluctuation of the memory bank busy signal BRBBm2.

Accordingly, the main control device 53 can know that the memory module (PSRAM1) 51 has an update conflict according to the memory bank busy signal BRBBh. In addition, the memory module (PSRAM2) 52 can also directly grasp the situation of the update conflict of the memory module (PSRAM1) 51 through the wired OR connection as shown in FIG. 9B. In other words, when the wired OR connection method is adopted, the memory module (PSRAM2) 52 can directly know that the memory module (PSRAM1) 51 has an update conflict through the memory bank busy signal BRBBm2, without going through the main control device. 53 learned indirectly.

As mentioned above, the memory modules (PSRAM1) 51 and (PSRAM2) 52 start to count the read delays after receiving the column addresses m1ADRr and m2ADRr. Therefore, it can be seen from FIG. 11 that the memory modules (PSRAM1) 51 and (PSRAM2) 52 both count the read delay counts from the time point t5. Among them, the memory module (PSRAM1) 51 takes two read delay counts (LC*2) to obtain the read data from the internal memory array to the internal buffer, and the memory module (PSRAM2) 52 Only one read latency count (LC) is required to obtain read data from the internal memory array to the internal buffer. Next, how and when the memory modules (PSRAM1) 51 and (PSRAM2) 52 transmit and read the data DATm1 and DATm2 synchronously will be described respectively.

The memory module (PSRAM1) 51 starts from the time point t5, and after updating the read delay rfcLC (for example, rfcLC=LC*2), the update conflict ends at the time point t10, and the memory module (PSRAM1) 51 ends at the time point t10. At the next rising edge of the system clock signal SCLK (ie, time point t11 ), the read flash pulse signals m1strb1 and m1strb2 are successively generated by the data flash mask signal DQSM[1]. Therefore, the memory module (PSRAM1) 51 starts to transmit the synchronous read data DATm1 from the time point t11.

On the other hand, the memory module (PSRAM2) 52 can prepare the read data in the internal buffer at time t9 after a preset read delay (dftLC=LC*1) from time t5. Due to an update conflict of the memory module (PSRAM1) 51, the memory module (PSRAM2) 52 knows that after the preset read delay (dftLC =LC*1) expires, the memory module (PSRAM2) 52 cannot execute the preset read delay (dftLC). The rising edge of the next system clock signal SCLK after the end of =LC*1) (time point t9) immediately transmits the read data. The time point t9 to the time point t11 can be defined as the additional waiting period Taddwt spent by the memory module (PSRAM2) 22 for waiting for the update conflict of the memory module (PSRAM1) 51 to end.

Here, the time point t5 to the time point t11 is defined as, in response to the update conflict occurred in the memory module (PSRAM1) 51, waiting for the memory module (PSRAM1) 51 to copy the read data to the internal buffer. Period Trdrf. As can be seen from FIG. 11, the memory module (PSRAM1) 51 transmits the synchronous read data DATm1 during the period from time point t11 to time point t13, and the memory module (PSRAM2) 52 transmits the synchronization data during the period from time point t11 to time point t13. Read data DATm2. The period from the time point t11 to the time point t13 can be defined as the synchronization data reading period Tdat_sync. Therefore, the memory modules (PSRAM1) 51 and (PSRAM2) 52 can use the system input and output signals SIO[8:1] and SIO[16:9] to transmit the read data in the internal buffer to the main control device synchronously 53.

9A and 9B, the additional memory bank busy signal BRBB is used with the bidirectional interface circuit and the pull-up resistor 50a, the present disclosure can also use the chip select signal CS# with the bidirectional interface circuit and the pull-up resistor 40a Use, as shown in Figures 12A and 12B.

In FIGS. 12A and 12B , the electronic device 40 includes a main control device 43 and memory modules (PSRAM1 ) 41 and (PSRAM2 ) 42 . The main control device 43 is electrically connected to the memory modules (PSRAM1) 41 and (PSRAM2) 42 through the chip selection signal CS# and the system clock signal SCLK at the same time. In addition, the main control device 43 is electrically connected to the memory module (PSRAM1) 41 through the system input and output signal SIO[8:1], the data flash mask signal DQSM[1], and is electrically connected to the memory module (PSRAM1) 41 through the system input and output signal SIO[16] :9], the data flashing mask signal DQSM[2] is electrically connected to the memory module (PSRAM2) 42. Here, it is assumed that the chip select signal CS# is used in conjunction with the bidirectional interface circuits 401, 411, 421 and the pull-up resistor 40a.

When the chip select signal CS# is used in conjunction with the bidirectional interface circuits 401, 411, 421 and the pull-up resistor 40a, the memory module (for example, the memory module (PSRAM1) 41) in which the update conflict occurs, can be based on a wire-OR ( wired OR) to achieve the effect of simultaneously notifying the main control device 43 and other memory modules (eg, the memory module (PSRAM2) 42) that have no update conflict. In Figures 12A and 12B, the bidirectional interface circuit 401 of the main control device 43 includes an output inverter 401a and an input inverter 401b with opposite connection modes; the bidirectional interface circuit 411 of the memory module (PSRAM1) 41 includes a connection mode The output inverter 411a and the input inverter 411b are opposite; the bidirectional interface circuit 421 of the memory module (PSRAM2) 42 includes the output inverter 421a and the input inverter 421b connected in opposite ways.

Please refer to FIGS. 12A and 12B, which are the chip selection signal CS# used as the communication interface for updating conflict between the memory module and the main control device, and the chip selection signal CS# is respectively transmitted by the main control device 43 and the memory module (PSRAM1) Schematic diagram of 41 driver. The driving manner of the chip select signal CS# in FIGS. 12A and 12B can be analogous to the driving manner of the memory bank busy signal BRBB in FIGS. 9A and 9B, so it will not be described in detail.

When the chip select signal CS# is connected in a wired OR manner as shown in Figs. 12A and 12B, the memory modules (PSRAM1) 41 and (PSRAM2) 42 may also select bits of the chip select signal CS#. likely to have an impact. Therefore, in some applications, the chip select signal CS# can be used as a communication purpose for performing a synchronous read operation. For example, FIG. 13 shows an embodiment in which the memory module (PSRAM1) 41 performs a synchronous read operation according to the immediate report mode (mode A) through the chip select signal CS#.

Please refer to FIG. 13, which shows that the chip selection signal CS# is used as the communication interface for the update conflict between the memory module and the main control device, and after the memory module notifies the main control device according to the immediate report mode (mode A), Waveform diagram of an embodiment of performing a synchronous read operation. In this figure, the time point t1 to the time point t13 is the read operation period Trd; the time point t1 to the time point t4 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t7 is the address transmission period Tadr; time point t7 to time point t12 is the synchronization data preparation period Tsdatpr; time point t12 to time point t13 is the synchronization data reading period Tdat_sync. The time point t5 to the time point t12 here is the update conflict reading period Trdrf. The time point t8 to the time point t12 can be defined as the additional waiting period Taddwt spent by the memory module (PSRAM2) 42 for waiting for the update conflict of the memory module (PSRAM1) 41 to end. The time point t5 to the time point t12 here is the update conflict reading period Trdrf.

Please also note that in this embodiment, if any one of the memory modules (eg, the memory module PSRAM1) has an update conflict, the memory module with the update conflict will pull the chip select signal CS# high , to force the end of the read operation. Therefore, the read operation period Trd shown in FIG. 13 does not include the end period Tend, and the length of the wafer selection period Tcs is much shorter than the wafer selection period Tcs of other embodiments. In FIG. 13, since the chip selection signal CS# is used for notification, the update conflict notification period Trfrp is almost as long as the wafer selection period Tcs.

In this embodiment, the memory module ( PSRAM1 ) 41 senses the moment when the main control device 43 pulls the chip selection signal CS# low at the time point t1 , that is, it knows that there is an update conflict in it. Therefore, at the time point t4, the memory module (PSRAM1) 41 pulls the chip select signal CS# high, and in this way notifies the main control device 43 that there is an update conflict therein. That is, before the time point t4, the main control device 43, as shown in FIG. 12A, serves as the driving end of the chip select signal CS#. During the period from the time point t4 to the time point t13, the memory module (PSRAM2) 42, as shown in FIG. 12B, serves as the driving end of the chip select signal CS#.

Since the main control device 43, the memory modules (PSRAM1) 41, and (PSRAM2) 42 are all connected to the chip selection signal CS#, the memory module (PSRAM2) 42 can also know the memory module (PSRAM1) at the time point t4. )41 The phenomenon of an update conflict inside. Therefore, the memory module (PSRAM2) 42 can know that the next rising edge (time t9) of the system clock signal SCLK after the preset read delay (dftLC=LC*1) ends (time t8) Immediately transmit the read data in the internal buffer to the main control device 43 .

As shown in FIG. 13, the memory module (PSRAM2) 42 starts to transmit the read immediately after the next rising edge (time t9) of the system clock signal SCLK after the preset read delay (dftLC=LC*1). The data is fetched to the main control device 43, but the read data sent by the memory module (PSRAM2) 42 during the data discarding period Tdrp2 will be discarded by the main control device 43, so it is called discarded data drpDATm2. Therefore, the memory module (PSRAM2) 42 still needs to start at the time point t12, again using the data flash mask signal DQSM[2] to issue the read flash pulse signals m2strb1, m2strb2, and using the system input and output signals SIO[16: 9] Send the synchronous read data DATm2 again. The discarded data drpDATm2 and the synchronous read data DATm2 transmitted through the data flash mask signal DQSM[2] are both provided by the memory module (PSRAM2) 42, and their contents are identical.

Figure 13 shows the waveform diagram of the memory module (PSRAM1) 41 and the main control device using the chip select signal CS# to match the immediate report mode (mode A). In practical applications, the memory module (PSRAM1) 41 A delayed reporting mode (mode B) can also be used with the master device 43 . The method of matching the delayed return mode (mode B) can be analogized to the descriptions in Figure 8B and Figure 13, so it will not be described in detail.

Please refer to FIG. 14, which is an embodiment in which a synchronous read operation is performed between the memory modules PSRAM1, PSRAM2 and the main control device using the chip select signal CS#, the system clock signal SCLK and the immediate report mode (mode A) The waveform diagram. In this figure, the time point t1 to the time point t12 is the read operation period Trd; the time point t1 to the time point t12 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t8 is the address transfer period Tadr; time point t8 to time point t13 is the synchronization data preparation period Tsdatpr; time point t13 to time point t15 is the synchronization data reading period Tdat_sync; time point t14 to time point t15 is the end period Tend. The time point t5 to the time point t13 here is the update conflict reading period Trdrf. The time point t5 to the time point t11 is the preset read delay (dftLC=LC*1) required for the memory module (PSRAM2) 42 to perform the read operation. The time point t11 to the time point t13 can be defined as the additional waiting period Taddwt spent by the memory module (PSRAM2) 42 for waiting for the update conflict of the memory module (PSRAM1) 41 to end.

In this embodiment, it is assumed that the memory device (PSRAM1) 41 notifies the main control device 43 and the memory device by pulling the chip select signal CS# high during a complete cycle of the system clock signal SCLK. The body module (PSRAM2) 42 has an effect on the situation where the update conflict occurs. In FIG. 14, it is assumed that the main control device 43 pulls up the chip select signal CS# during the period from the time point t9 to the time point t10 (a period corresponding to the entire period of the system clock period Tclk4). Therefore, the period from the time point t9 to the time point t10 can be defined as the read suspension notification period Tstp used by the master control device 43 to notify the memory module (PSRAM2) 42 that the read operation needs to be suspended. In this figure, it is assumed that the update conflict notification period Trfrp corresponds to the system clock period Tclk4 of the system clock signal SCLK.

In practical application, the method that the main control device 43 notifies the memory module (PSRAM2) 42 with the chip select signal CS# and the system clock signal and SCLK does not need to be limited. For example, the main control device 43 may select to pull the chip selection signal CS# high during any one of the system clock periods Tclk1 ˜ Tclk8 . Since the preset read delay (dftLC=LC*1) required for the read operation of the memory module PSRAM2 ends at time t11, if the position where the main control device 43 pulls the chip selection signal CS# high is earlier than time t11, Then, the memory module (PSRAM2) 42 can immediately know that the read data from the internal buffer should be temporarily stopped after the preset read delay (dftLC=LC*1) expires. If the main control device 43 pulls the chip selection signal CS# high before the time point t11, the memory module (PSRAM2) 42 will stop transmitting the data in the internal buffer after the time point t11. After the synchronization data preparation period Tsdatpr ends (time point t13), the memory module (PSRAM2) 42 starts to transmit the synchronization read data DATm2 from the internal buffer.

On the other hand, if the position at which the main control device 43 pulls the chip selection signal CS# high is later than the time point t11 . For example, the main control device 43 pulls the chip select signal CS# high during the system clock periods Tclk6, Tclk7, and Tclk8. Then, the memory module (PSRAM2) 42 needs to transmit the read data from the internal buffer twice to the system input and output signals SIO[16:9].

In FIG. 14, it is assumed that the memory module (PSRAM1) 41 uses the immediate report mode (mode A) to notify the master device 43, and the master device 43 uses the combination of the chip select signal CS# and the system clock signal SCLK to notify Memory module (PSRAM2) 42 . In practical application, the delayed return mode (mode B) can also be changed to match the combination of the chip selection signal CS# and the system clock signal SCLK. The method of matching with the delayed return mode (mode B) can be analogized to the description in FIG. 8B and will not be described in detail.

According to the concept of the present disclosure, the manner in which the memory module PSRAM2 knows that it needs to wait for the synchronization data preparation period Tsdatpr is quite flexible. For example, in practical application, the clock ignore signal lines ICK1 and ICK2 may be additionally set between the main control device and the memory modules PSRAM1 and PSRAM2. The clock ignore signal lines ICK1 and ICK2 are at low level most of the time, but when the main control device pulls the clock ignore signal ICK1 and ICK2 high, the memory modules PSRAM1 and PSRAM2 are at the clock ignore signal ICK1 and ICK2. During the pull-up period, the fluctuation of the system clock signal SCLK will be temporarily ignored.

Please refer to FIG. 15, which sets the clock ignore signal lines ICK1 and ICK2 between the main control device and the memory modules PSRAM1 and PSRAM2, and implements a synchronous read operation in the case of an update conflict of the memory module PSRAM1 Example of the waveform diagram. In this figure, time point t1 to time point t14 is the read operation period Trd; time point t1 to time point t13 is the chip selection period Tcs; time point t1 to time point t3 is the setting period Tset; time point t3 to time point t4 is the read command transmission period Tcmd; time point t4 to time point t8 is the address transmission period Tadr; time point t8 to time point t12 is the synchronization data preparation period Tsdatpr; time point t12 to time point t14 is the synchronization data reading period Tdat_sync; time point t12 to time point t13 is the end period Tend. The period from the time point t2 to the time point t7 here can be defined as the update conflict notification period Trfrp that the memory module PSRAM1 in which the update conflict occurs notifies the master device. The time point t5 to the time point t11 may be defined as the update conflict reading period Trdrf. The time point t5 to the time point t9 can be defined as the preset read delay (dftLC=LC*1) required for the read operation of the memory module PSRAM2. The time point t9 to the time point t11 can be defined as the additional waiting period Taddwt spent by the memory module PSRAM2 for waiting for the update conflict of the memory module PSRAM1 to end.

In FIG. 15, the master device temporarily pulls up the level of the clock ignore signal ICK2 during the period from the time point t10 to the time point t11. Here, the period from the time point t10 to the time point t11 can be defined as the clock skip period Tick. During the clock ignoring period Tick, the internal memory module PSRAM2 will stop receiving the system clock signal SCLK. Therefore, the memory module PSRAM2 suspends the operation of Tick during the clock ignoring period. After the clock ignore period Tick ends (time point t11), the main control device pulls the clock ignore signal ICK2 to a low level again, so that the memory module PSRAM2 receives the clock of the system clock signal SCLK again and continues to read operate. Therefore, at the time point t12, the memory modules PSRAM and PSRAM2 start to transmit the read data synchronously.

In the example of FIG. 15 , the main control device generates a clock ignore signal ICK2 to the memory module PSRAM2, so as to notify the memory module PSRAM2 to suspend receiving the system clock signal SCLK. In the embodiment of FIG. 16 , it is assumed that the master control device actually stops transmitting the system clock signal SCLK to the memory module PSRAM2 . Compared with Fig. 15, the method of Fig. 16 does not require additional wiring, and its cost is relatively low.

Please refer to FIG. 16, the master control device suspends the read operation of the memory modules PSRAM1 and PSRAM2 by suspending the supply of the system clock signal SCLK to the memory modules PSRAM1 and PSRAM2 after the update conflict occurs in the memory module PSRAM1. A schematic diagram of the synchronous read operation performed by the modules PSRAM1 and PSRAM2. In this figure, the time point t1 to the time point t13 is the read operation period Trd; the time point t1 to the time point t12 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t8 is the address transmission period Tadr; time point t8 to time point t11 is the synchronization data preparation period Tsdatpr; time point t11 to time point t13 is the synchronization data reading period Tdat_sync; time point t12 to time point t13 is the end period Tend. The period from the time point t2 to the time point t7 here can be defined as the update conflict notification period Trfrp that the memory module PSRAM1 in which the update conflict occurs notifies the master device. The time point t5 to the time point t11 may be defined as the update conflict reading period Trdrf. The time point t5 to the time point t9 can be defined as the preset read delay (dftLC=LC*1) required for the read operation of the memory module PSRAM2. The time point t9 to the time point t11 can be defined as the additional waiting period Taddwt spent by the memory module PSRAM2 for waiting for the update conflict of the memory module PSRAM1 to end.

In FIG. 16, the main control device stops transmitting the system clock signal SCLK to the memory modules PSRAM1 and PSRAM2 during the period from the time point t9 to the time point t11. During this period, because the memory module PSRAM1 performs an update conflict within the memory module PSRAM1, even if the memory module PSRAM1 does not receive the system clock signal SCLK, its operation will not be affected. On the other hand, during the period from the time point t9 to the time point t11, the memory module PSRAM2 stops operating because it does not receive the clock of the system clock signal SCLK. Beginning at time point t11, the master device restarts transmitting the system clock signal SCLK to the memory modules PSRAM1 and PSRAM2, and the memory module PSRAM2 will operate again. Therefore, at the time point t11, the memory modules PSRAM and PSRAM2 start to synchronously transmit the synchronous read data DATm1 and DATm2.

In the aforementioned embodiment, it is assumed that the master control device knows that an update conflict occurs inside the memory module PSRAM1 through the report of the memory module PSRAM1. In practical application, the main control device can also actively grasp the update conflict in the memory module PSRAM1 by other means.

The above-mentioned embodiments all complete the synchronous read operation in one chip selection period Tcs. In these embodiments, the synchronization data preparation period Tsdatpr is greater than the predetermined read delay (dftLC=LC*1), and the synchronization data preparation period (Tsdatpr) is smaller than the update read delay (rfcLC=2*LC). In practical application, two (or more) chip selection periods Tcs can also be used to complete the read operation of the memory modules PSRAM1 and PSRAM2 in a synchronous manner.

Please refer to FIG. 17 , which is a schematic diagram of the master control device issuing repeated read commands m1CMDrtry and m2CMDrtry to synchronize the memory modules PSRAM1 and PSRAM2 for read operations. In this figure, time point t1 to time point t21 is the reading operation period Trd; time point t1 to time point t12 is the chip selection period Tcs1; time point t12 to time point t14 is the chip selection interval Tint; time point t14 to time point t19 is the chip selection period Tcs2 ; Time t1 to time t3 is the setting period Tset; time t3 to time t4 is the read command transmission period Tcmd; time t4 to time t6 is the address transmission period Tadr; time t6 to time t18 is the synchronization data preparation period Tsdatpr; time t19 From the time point t21 to the time point t21 is the synchronization data reading period Tdat_sync; from the time point t20 to the time point t21 is the end period Tend.

In this embodiment, the read operation period Trd includes a chip selection period Tcs1, a chip selection pitch Tint, a chip selection period Tcs2, and an end period Tend in sequence. The chip select signal CS# is at a low level during the chip select periods Tcs1 and Tcs2, and the chip select signal CS# is at a high level during the chip select pitch Tint and the end period Tend.

During the chip selection period Tcs1, the main control device successively receives the read data from the memory module PSRAM2 during the data discarding period Tdrp2, and the memory module PSRAM1 successively receives the read data from Tdrp1 during the data discarding period. If the main control device finds that the time from the internal buffers of the memory modules PSRAM1 and PSRAM2 to the system input and output signals SIO[8:1] and SIO[16:9] is inconsistent during the chip selection period Tcs1 , it means that the master device cannot use the read data correctly. Therefore, the read data can be regarded as discard data drpDATm1, drpDATm2. In addition, the main control device can actively know that the memory module PSRAM1 has an update conflict, but the memory module PSRAM2 does not have an update conflict by using the inconsistent data transmission timing. The time point t5 to the time point t11 here is the update conflict reading period Trdrf.

Based on the above, in the chip selection period Tcs1, the read data transmitted by the memory modules PSRAM1 and PSRAM2 to the main control device includes the read data transmitted by the memory module PSRAM1 from the time point t11 to the time point t13, and The read data transmitted by the memory module PSRAM2 from the time point t8 to the time point t9 will be ignored by the main control device. In the chip selection period Tcs1 , the read data transmitted from the memory modules PSRAM1 and PSRAM2 to the main control device are regarded as discarded data drpDATm1 and drpDATm2 .

The middle of the wafer selection period Tcs1 and Tcs2 is the wafer selection pitch Tint. At the chip selection pitch Tint, the main control device pulls the chip selection signal CS# to a high level, and maintains the system clock signal SCLK at a low level. In the chip selection period Tcs2, from the time point t14 to the time point t15 (the repeated read command period Tcmd_rtry), the main control device sends the repeated read commands m1CMDrtry and m2CMDrtry to the memory modules PSRAM1 and PSRAM2. The repeated read commands m1CMDrtry and m2CMDrtry represent that the master control device requires the memory modules PSRAM1 and PSRAM2 to wait for the read delay rfcLC (for example, rfcLC=LC*2) to be updated again before performing the read operation. The time point t14 to the time point t19 here is the period during which the memory modules PSRAM1 and PSRAM2 perform the read operation for the second time, so it is defined as the repeated read period T2rd.

Since the memory modules PSRAM1 and PSRAM2 have already received the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc during the address transfer period Tadr of the chip selection period Tcs1 (the period from the time point t4 to the time point t6 ). Therefore, during the chip selection period Tcs2, the main control device does not need to transmit the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc to the memory modules PSRAM1 and PSRAM2 again.

After the memory modules PSRAM1 and PSRAM2 receive the repeated read commands m1CMDrtry and m2CMDrtry, they wait to update the read delay rfcLC (for example, rfcLC=LC*2). After the time point t18, the synchronous generation of the read flash pulse signals m1strb1 and m2strb1 is started. During the period from time point t18 to time point t20, the memory module PSRAM1 uses the data flash mask signal DQSM[1] to transmit the read flash pulse signals m1strb1 and m1strb2 to the main control device, and uses the system input and output signals SIO[8:1] ] Send the synchronous read data DATm1 from the internal buffer to the master device. At the same time, the memory module PSRAM2 uses the data flash mask signal DQSM[2] to transmit the read flash pulse signals m2strb1, m2strb2 to the main control device, and uses the system input and output signals SIO[16:9] to buffer from the internal The device transmits the synchronous read data DATm2 to the master device.

In Figure 17, the discarded data drpDATm1 and the synchronous read data DATm1 transmitted through the system input and output signals SIO[8:1] are both transmitted from the internal buffer of the memory module PSRAM1, so the contents of the two are exactly the same . Similarly, the discarded data drpDATm2 and the synchronous read data DATm2 transmitted through the system I/O signals SIO[16:9] are both transmitted from the internal buffer of the memory module PSRAM2, so the contents of the two are exactly the same.

In the embodiment of FIG. 17, the synchronization data preparation period Tsdatpr simultaneously covers a part of the wafer selection periods Tcs1 and Tcs2. Therefore, the synchronization data preparation period Tsdatpr is longer than the update read delay rfcLC (Tsdatpr>rfcLC=2*LC). In addition, in the embodiment of FIG. 18, the synchronization data preparation period Tsdatpr is slightly shorter than the update read delay rfcLC (Tsdatpr<rfcLC=2*LC).

When the memory module PSRAM of the PSRAM technology is used, the master device can enable the notification function of the precycle pulse of the pilot pulse signal mpre of the data flash mask signal DQSM by setting the register. The pilot pulse signal mpre refers to the high level of the system clock signal SCLK before the data flash mask signal DQSM sends out the read flash pulse signals mstrb1 and mstrb2, the memory module PSRAM pre-blocks the data flash The level of the mask signal DQSM is pulled high for a short period of time, so as to notify the main control device that the read data will be sent out later. That is, before the read flash pulse signals mstrb1 and mstrb2 are transmitted, the pilot pulse signal mpre is used in advance to inform the main control device that the subsequent transmission of the read data is about to begin.

In the embodiment shown in FIG. 17 , the main control device can determine that an update conflict occurs in the memory module PSRAM1 by means of active sensing. Therefore, in this embodiment, the conflict notification period Trfrp is not updated. In practical application, the embodiment of FIG. 17 can also be performed in combination with an immediate reporting mode (mode A) and a delayed reporting mode (mode B). That is, the main control device is still notified by the memory module PSRAM1 in which the update conflict occurs.

FIG. 18 is another embodiment in which the main control device actively senses the update conflict of the memory module PSRAM1. Please refer to FIG. 18, which is the chip selection signal CS# and the system clock signal SCLK between the memory modules PSRAM1, PSRAM2 and the main control device, according to the time difference between the generation of the pilot pulse signals m1pre, m2pre, to determine the memory A waveform diagram of an embodiment of how to perform a synchronous read operation after an update conflict occurs in the bulk module PSRAM1. In this figure, the time point t1 to the time point t15 is the read operation period Trd; the time point t1 to the time point t14 is the chip selection period Tcs; the time point t1 to the time point t3 is the setting period Tset; the time point t3 to the time point t4 is the read command transmission period Tcmd; time point t4 to time point t7 is the address transmission period Tadr; time point t7 to time point t13 is the synchronization data preparation period Tsdatpr; time point t13 to time point t15 is the synchronization data reading period Tdat_sync; time point t14 to time point t15 is the end period Tend. The time point t5 to the time point t13 here is the update conflict reading period Trdrf. The time point t5 to the time point t9 can be defined as the preset read delay (dftLC=LC*1) required for the read operation of the memory module PSRAM2. The time point t9 to the time point t13 can be defined as the additional waiting period Taddwt spent by the memory module PSRAM2 for waiting for the update conflict of the memory module PSRAM1 to end.

In the example of FIG. 18 , it is assumed that the functions of the memory modules PSRAM1 and PSRAM2 for generating the pilot pulse signals m1pre and m2pre are both enabled. Due to an update conflict of the memory module PSRAM1, the period during which the memory module PSRAM1 generates the pilot pulse signal m1pre is later than the period during which the memory module PSRAM2 generates the pilot pulse signal m2pre. The memory module PSRAM1 uses the data flash mask signal DQSM[1] to transmit the pilot pulse signal m1pre during the period from the time point t11 to the time point t12; and the memory module PSRAM2 uses the data flash control during the period from the time point t8 to the time point t9. The mask signal DQSM[2] transmits the pilot pulse signal m2pre.

It can be seen from FIG. 18 that during the period from time t8 to time t9, the main control device only receives the pilot pulse signal m2pre generated by the memory module PSRAM2 using the data flashing mask signal line DQSM[2]. The main control device needs to wait until the time point t11 to the time point t12 to receive the pilot pulse signal m1pre generated by the memory module PSRAM1 using the data flash mask signal line DQSM[1]. Accordingly, based on the pilot pulse signals m1pre and m2pre generated in sequence (asynchronously), the main control device can know that there is a time difference in the process that the memory modules PSRAM1 and PSRAM2 can provide the corresponding read data. That is, since the main control device firstly receives the pilot pulse signal m2pre transmitted from the memory module PSRAM2, the main control device can judge accordingly that the memory module PSRAM2 does not have an update conflict; on the other hand, the main control device When the pilot pulse signal m1pre transmitted from the memory module PSRAM1 is received later, it can be determined that the memory module PSRAM1 has an update conflict. In this embodiment, since the main control device actively learns that the memory module PSRAM1 has an update conflict, it is not notified by the memory module PSRAM1. Therefore, this embodiment does not include the update conflict notification period Trfrp.

In Fig. 18, during the period from time point t8 to time point t9, the main control device can generate only the pilot pulse signal m2pre corresponding to the memory module PSRAM2, and there is no pilot pulse signal corresponding to the memory module PSRAM1. From the phenomenon generated by m1pre, it is known that the memory module PSRAM1 takes a long time to perform the read operation, and then it is judged that the memory module PSRAM1 has an update conflict. Here, during the period from the time point t5 to the time point t11, the memory module PSRAM2 has to wait to update the read delay rfcLC (for example, rfcLC=LC*2). After that, the memory module PSRAM1 sends the pilot pulse signal m1pre during the period from the time point t11 to the time point t12.

Therefore, in FIG. 18, it is assumed that the main control device pulls the chip select signal CS# high during the system clock period Tclk6 as a notification to the memory module PSRAM2 to wait for the memory module PSRAM1 to complete the update conflict. In practical application, the main control device can also choose to pull the chip select signal CS# high during the system clock cycles Tclk7 and Tclk8 to notify the memory module PSRAM2 that the read operation speed needs to be slowed down.

Please note that, as mentioned in FIG. 18, the main control device determines the update collision of the memory module PSRAM1 by using the pilot pulse signals m1pre and m2pre, although the chip selection signal CS# is pulled high according to the system clock cycle. In this way, the memory module PSRAM2 is notified that its read operation needs to be delayed, but the actual application is not limited to this. Therefore, as mentioned in the other embodiments mentioned above, the methods of setting the memory bank busy signal BRBB, the clock ignore signal ICK, etc. can also be modified and applied to the main control device to judge the memory by using the pilot pulse signals m1pre and m2pree. The body module PSRAM1 has an update collision.

Incidentally, the main control device only chooses to use one of the system clock cycles Tclk6, Tclk7, Tclk8 to pull the chip selection signal CS# high, if the main control device pulls the chip selection signal CS# high. The period is longer than one system clock period Tclk, which may cause the memory module PSRAM2 to mistakenly think that the master device is ready to forcibly end the current read operation. Therefore, in order to prevent the memory module PSRAM2 from malfunctioning, this embodiment assumes that the main control device notifies the memory module PSRAM2 that the read operation period needs to be extended by pulling the chip select signal CS# high by one system clock period Tclk .

It can be seen from the foregoing embodiments that the application of the present disclosure is quite flexible. First, the master device can passively know that there is an update conflict inside the memory module PSRAM1 through the report of the memory module PSRAM1 (Figures 8A, 8B, 10, 11, 13, 14, 15, and 16); the master device By comparing the generation time points of the flash pulse signals m1strb1 and m2strb1, it can actively determine the update conflict in the memory module PSRAM1 (Fig. 17); or, the main control device can detect the pilot pulse signals m1pre, The m2pre method actively determines that an update conflict occurs in the memory module PSRAM1 (Fig. 18). In addition, the report mode of the memory module PSRAM1 can be further classified into an immediate report mode (mode A) and a delayed report mode (mode B) according to the report time.

Furthermore, the above-mentioned different embodiments also illustrate that if the memory module PSRAM1 has an update conflict, the memory module PSRAM1 can notify the main control device through different types of signal lines. For example: data flash mask signal DQSM[1], DQSM[2], memory bank busy signal BRBBh, BRBBm1, BRBBm2, chip select signal CS#, or the waveform of chip select signal CS# and system clock signal SCLK combination, etc. In practical application, the memory module PSRAM1 notifies the main control device of the type of the signal line and the control of its waveform, etc., and is not limited to the foregoing embodiment.

In addition, according to different embodiments, the memory module PSRAM2 can indirectly learn from the master control device that the memory module PSRAM1 has an update conflict; or, the memory module PSRAM2 can directly learn the memory from the memory module PSRAM1 The update conflict occurs in the module PSRAM1.

In the above-mentioned embodiment, the method that the memory module PSRAM2 indirectly learns from the main control device that the memory module PSRAM1 has an update conflict includes: the main control device issues special read commands m1CMDrd_sp, m2CMDrd_sp (FIG. 8A), When the control device issues extended read commands m1CMDext, m2CMDext (Fig. 8B), the main control device changes the level of the chip selection signal CS# (Figs. 13A, 13B), the main control device changes the chip selection signal CS# and the system The combination of the pulse signal SCLK (Fig. 14), the master control device sets the additionally set clock ignore signal lines ICK1 and ICK2 (Fig. 15), the master control device suspends the transmission of the system clock signal SCLK (Fig. 16), Repeat the read commands m1CMDrtry, m2CMDrtry (Fig. 17). In the foregoing embodiment, the way that the memory module PSRAM2 can be directly obtained from the memory module PSRAM1 to generate an update conflict situation for the memory module PSRAM1 includes: as shown in FIGS. 9A and 9B, a wired OR ) to set the memory bank busy signal line BRBB; and, as shown in FIGS. 12A and 12B , to set the chip select signal CS# in a wired OR manner.

It can be seen from the foregoing description that the reading method of the present disclosure can be applied to electronic devices in a fairly flexible manner. In practical application, the memory module PSRAM2 indirectly learns from the main control device how the memory module PSRAM1 generates an update conflict, and the memory module PSRAM2 directly learns from the memory module PSRAM1 that the memory module PSRAM1 generates an update conflict The method is not limited to the foregoing embodiments.

When the concept of the present disclosure is adopted, the master control device can know whether there is an update conflict between memory modules, and then notify other memory modules in the system to delay the time when it transmits and read data, and ensures that the master control device can synchronize from multiple memory modules. The memory module receives the read data. The memory module using PSRAM technology described in this article, its PSRAM technology includes but not limited to OctaRAM, HyperRAM, Xccela PSRAM, etc., and the transmission protocol used by PSRAM technology can be Serial Peripheral Interface Bus (SPI for short) , Double Sequence Peripheral Interface (Dual-SPI), Quadruple Sequence Peripheral Interface (QSPI), etc. In addition, although the waveform diagram in this article assumes that a read delay count LC is equivalent to three times the system clock period (LC=3*Tclk), the actual application is not limited to this.

Please also note that although in the foregoing description, it is assumed that the electronic device includes only two memory modules PSRAM1 and PSRAM2, the practical application of the present disclosure is not limited to this. For example, an electronic device may contain four or eight memory modules. Or, a situation in which a plurality of memory modules included in the electronic device need to be updated and conflicted in turn occurs. Then, the aforementioned reading method can still be based on a similar control method. After all the memory modules in which the update conflict occurs have completed the update conflict, all the memory modules are controlled to transmit the read data synchronously. The aforementioned embodiments can be applied to these different types of electronic devices after modification.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

11a, DRAM, 11b, 21, 22, PSRAM1, PSRAM2, 51, 52, 41, 42: Memory modules 13a, 13b, 23, 53, 43: Master control device CS#: Chip Select Signal (Line) SCLK: system clock signal (line) SIO[64:1], SIO[8:1], SIO[16:9]: System input and output signal lines DQSM, DQSM[2:1], DQSM[1], DQSM[2]: Data flash mask signal (line) CTL: Control Signal (Line) 10a, 10b, 20, 50, 40: Electronic devices t1~t21: time point Trd: During a read operation Tcs: During wafer selection Tset: set period LC: Read Latency Count Tclk, Tclk1~Tclk10: System clock cycle Tend: end period Tadr_r: Column address period Tadr_c: row address period mstrb1,mstrb2,m1strb1,m1strb2,m2strb1,m2strb2,m2strb1',m2strb2': read the flash pulse signal mCMDrd: read command ADRr, m1ADRr, m2ADRr: column address ADRc, m1ADRc, m2ADRc: row address DATm: read data synchronously Tcmd: During read command transmission Tadr: During address transfer 25: Memory device Tsdatpr: During synchronization data preparation Tdat_sync: During synchronous data reading DATm1, DATm2: read data synchronously m1CMDrd, m2CMDrd: read command Trdnm: During normal reading S51,S53,S55,S57,S59,S301a,S302a,S303a,S305a,S307a,S101a,S103a,S105a,S107a,S201a,S203a,S301b,S303b,S305b,S307b,S309b,S101b,S10bb,S105bb,S10bb S201b, S203b: Steps Trdrf: Update conflict during read Trfrp: Update conflict notification period Taddwt: extra waiting period drpDATm2: discard data Tdrp2: Data discard period m1CMDrd_sp, m2CMDrd_sp: special read commands m2CMDext: Extend read instruction Tcmdext: Extend read command period 501,511,521,401,421,411: Bidirectional Interface Circuits 501a, 521a, 511a, 401a, 421a, 411a: Output inverter 501b, 521b, 511b, 401b, 421b, 411b: Input inverter BRBBh, BRBBm1, BRBBm2: memory bank busy signal (line) 50a, 40a: Pull-up resistors Vcc: Supply voltage Tstp: Suspend read notification period Tick: During the clock ignore period ICK1,ICK2: Clock ignore signal m1CMDrtry, m2CMDrtry: repeat read command Tcmd_rtry: During repeated read instructions T2rd: During repeated read Tint: Chip selection pitch m1pre, m2pre: pilot pulse signal

FIG. 1 is a schematic diagram of a memory module in an electronic device using dynamic random access memory (DRAM). FIG. 2 is a schematic diagram of a memory module in an electronic device using a virtual static random access memory PSRAM. FIG. 3A is a waveform diagram of a general read operation performed by the main control device using the PSRAM memory module. FIG. 3B is a waveform diagram of an update conflict occurring inside the memory module when the master control device uses the PSRAM memory module to perform a read operation. FIG. 4 is a schematic diagram of an electronic device including two memory modules using virtual static random access memory PSRAM. FIG. 5 is a schematic diagram of the master control device performing a read operation on the memory modules PSRAM1 and PSRAM2 in a preset data synchronization manner. FIG. 6 is a flowchart of the synchronous read operation performed by the main control device on the memory modules PSRAM1 and PSRAM2 in the electronic device according to the embodiment of the present invention. Fig. 7A shows the flow of the synchronous read operation of the memory modules PSRAM1 and PSRAM2 after the memory module PSRAM1 notifies the master device in the immediate report mode (mode A) when an update conflict occurs according to the concept of the present disclosure picture. FIG. 7B shows the flow of the synchronous read operation of the memory modules PSRAM1 and PSRAM2 after the memory module PSRAM1 notifies the master device in the delayed report mode (mode B) when an update conflict occurs, according to the concept of the present disclosure. picture. Fig. 8A is a waveform of an embodiment of a synchronous read operation between the memory module PSRAM1 and the master device using the data flash mask signal DQSM and the immediate report mode (mode A) according to the concept of the present disclosure picture. FIG. 8B is a waveform of an embodiment of a synchronous read operation using the data flash mask signal DQSM and the delayed return mode (mode B) between the memory module PSRAM1 and the master device according to the concept of the present disclosure picture. FIG. 9A is a schematic diagram of setting a memory bank busy signal line BRBB between the memory modules PSRAM1 and PSRAM2 and the main control device, and the main control device drives the memory bank busy signal BRBB. FIG. 9B is a schematic diagram of setting the memory bank busy signal line BRBB between the memory modules PSRAM1 and PSRAM2 and the main control device, and the memory module PSRAM1 drives the memory bank busy signal BRBB. FIG. 10 is an embodiment of a synchronous read operation using the memory bank busy signal line BRBB and the immediate report mode (mode A) between the memory modules PSRAM1, PSRAM2 and the main control device according to the concept of the present disclosure. Waveform diagram. FIG. 11 is a waveform diagram of another embodiment in which the memory modules PSRAM1 and PSRAM2 perform a synchronous read operation after the memory module PSRAM1 notifies the main control device in the immediate report mode (mode A) according to the concept of the present disclosure. . FIG. 12A is a schematic diagram of the chip selection signal CS# being used as a communication interface for updating conflict between the memory modules PSRAM1, PSRAM2 and the main control device, and the chip selection signal CS# is driven by the main control device. FIG. 12B is a schematic diagram of the chip selection signal CS# being used as a communication interface for updating conflict between the memory modules PSRAM1, PSRAM2 and the master device, and the chip selection signal CS# is driven by the memory module PSRAM1. Fig. 13 shows the chip selection signal CS# as the communication interface of the update conflict between the memory modules PSRAM1, PSRAM2 and the main control device, and the memory module PSRAM1 notifies the main control device according to the immediate report mode (mode A) Then, the waveform diagram of the embodiment of the synchronous read operation is shown. Fig. 14 shows the waveforms of an embodiment in which a synchronous read operation is performed between the memory modules PSRAM1, PSRAM2 and the main control device using the chip select signal CS#, the system clock signal SCLK and the immediate report mode (mode A) picture. FIG. 15 is an embodiment of a synchronous read operation in which the clock ignore signals ICK1 and ICK2 are set between the main control device and the memory modules PSRAM1 and PSRAM2 to perform a synchronous read operation in the case of an update conflict in the memory module PSRAM1. Waveform diagram. FIG. 16 is a schematic diagram of the synchronous read operation of the memory modules PSRAM1 and PSRAM2 by suspending the generation of the system clock signal SCLK after the master control device knows that the memory module PSRAM1 has an update conflict. FIG. 17 is a schematic diagram of the master control device issuing a repeated read command to synchronize the memory modules PSRAM1 and PSRAM2 to perform the read operation. Fig. 18 shows the chip selection signal CS# and the system clock signal SCLK between the memory modules PSRAM1, PSRAM2 and the main control device. According to the time difference between the pilot pulse signals m1pre and m2pre, the memory module is determined. A waveform diagram of an embodiment of how to perform a synchronous read operation after an update conflict occurs in the group PSRAM1.

S51, S53, S55, S57, S59: Steps

Claims (14)

A memory device is electrically connected to a main control device, wherein the main control device performs a read operation on the memory device during a read operation period, and the memory device comprises: a first memory module that generates an update conflict during the read operation; and, a second memory module, wherein, The first memory module and the second memory module simultaneously receive a first read command and a second read command sent by the main control device during a read command transmission period; The first memory module and the second memory module receive a first memory address and a second memory address respectively during an address transfer period, wherein the read command transfer period is earlier than the bit during address transmission; and, After a synchronization data preparation period, the first memory module and the second memory module transmit a first synchronization read data and a second synchronization read data respectively during a synchronization data read period at the same time to the master device, wherein the synchronization data preparation period is greater than a predetermined read delay. The memory device of claim 1, wherein, The master device informs the second memory module that the read operation must be performed in a special data synchronization manner; or The first memory module notifies the second memory module that the read operation must be performed in the special data synchronization mode. The memory device of claim 1, wherein, the first memory module reports the update conflict situation to the host device before the read command transmission period begins; or The first memory module reports the update conflict situation to the master device during the address transfer period. The memory device of claim 1, wherein the first memory module is formed by a chip select signal line, a data flash mask signal line, a dedicated signal line, a system clock signal line, and A clock ignores one or a combination of the signal lines, and reports the update conflict situation to the master device. The memory device of claim 1, wherein the second memory module transmits a discarded data during the preparation of the synchronized data, wherein the contents of the discarded data are the same as the contents of the second synchronized read data. The memory device of claim 1, wherein, The synchronization data preparation period is less than an update read delay, wherein the read operation period includes: A chip selection period for selecting the first memory module and the second memory module at the same time, wherein the chip selection period includes a setting period, the read command transmission period, the address transmission period, the The synchronization data preparation period and a part of the synchronization data reading period. The memory device of claim 1, wherein the synchronization data preparation period is greater than an update read delay, wherein the read operation period includes: A first chip selection period for selecting the first memory module and the second memory module at the same time, wherein the first chip selection period includes a setting period, the read command transmission period, the address the transmission period and a portion of the synchronization data preparation period; a chip selection pitch; A second chip selection period for selecting the first memory module and the second memory module at the same time, wherein the second chip selection period includes a command repeated transmission period and another part of the synchronization data preparation period with a portion of the synchronous data read period; and An end period, wherein the end period includes another part of the synchronization data reading period. The memory device of claim 7, wherein, The first memory module transmits a first discard data during the synchronization data preparation period, and the second memory module transmits a second discard data during the synchronization data preparation period, The content of the first discarded data is the same as the content of the first synchronously read data, and the content of the second discarded data is the same as the content of the second synchronously read data. The memory device of claim 8, wherein, The first chip selection period includes the read command transfer period and the address transfer period, and The second chip selection period includes a command repeated transmission period, the synchronization data preparation period and the synchronization data read period. The memory device of claim 1, wherein, The master control device determines that the first memory module has the update conflict during the synchronization data preparation period, and the master control device notifies the second memory module that a special data must be used during the synchronization data preparation period The read operation is performed synchronously. The memory device of claim 10, wherein, The first memory module sends out a first pilot pulse signal in response to the read operation, and the second memory module sends out a second pilot pulse signal in response to the read operation, wherein, The main control device determines that the update conflict occurs in the first memory module according to the comparison between the first pilot pulse signal and the second pilot pulse signal. The memory device of claim 1, wherein the read operation period includes the read command transmission period, the address transmission period, the synchronization data preparation period and the synchronization data read period. An electronic device comprising: a memory device comprising: a first memory module that generates an update conflict during a read operation; and a second memory module; and a main control device electrically connected to the first memory module and the second memory module, wherein the main control device is used for the first memory module and the second memory module during the read operation period The body module performs a read operation at the same time, wherein, The first memory module and the second memory module simultaneously receive a read command sent by the main control device during a read command transmission period; The first memory module and the second memory module receive a first memory address and a second memory address respectively during an address transfer period, wherein the read command transfer period is earlier than the bit during the transmission of the address; and After a synchronization data preparation period, the first memory module and the second memory module transmit a first synchronization read data and a second synchronization read data respectively during a synchronization data read period at the same time to the master device, wherein the synchronization data preparation period is greater than a predetermined read delay. A reading method applied to an electronic device, wherein the electronic device comprises a main control device, a first memory module and a second memory module, wherein the main control device is simultaneously in a reading operation During the period, a read operation is simultaneously performed on the first memory module and the second memory module, the first memory module generates an update conflict during the read operation, and the read method is Contains the following steps: The first memory module and the second memory module simultaneously receive a first read command and a second read command sent by the main control device during a read command transmission period; The first memory module and the second memory module receive a first memory address and a second memory address respectively during an address transfer period, wherein the read command transfer period is earlier than the bit during the transmission of the address; and After a synchronization data preparation period, the first memory module and the second memory module transmit a first synchronization read data and a second synchronization read data respectively during a synchronization data read period at the same time to the master device, wherein the synchronization data preparation period is greater than a predetermined read delay.

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