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TW202201372A - Source driver and driving circuit thereof - Google Patents

Source driver and driving circuit thereof Download PDF

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Publication number
TW202201372A
TW202201372A TW109129127A TW109129127A TW202201372A TW 202201372 A TW202201372 A TW 202201372A TW 109129127 A TW109129127 A TW 109129127A TW 109129127 A TW109129127 A TW 109129127A TW 202201372 A TW202201372 A TW 202201372A
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Taiwan
Prior art keywords
buffer
circuit
node voltage
source driver
driving circuit
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TW109129127A
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Chinese (zh)
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TWI741759B (en
Inventor
馬佑昇
程智修
林俊甫
詹作晟
楊仁傑
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聯詠科技股份有限公司
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Priority to US17/111,449 priority Critical patent/US11217152B1/en
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Publication of TWI741759B publication Critical patent/TWI741759B/en
Publication of TW202201372A publication Critical patent/TW202201372A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The present invention provides a source driver for driving a light emitting diode panel. The source driver includes a buffer including an output terminal; and a plurality of driving circuits coupled to the buffer. Each of the plurality of driving circuits includes a constant current transistor including a gate controlled by a node voltage of the output terminal of the buffer; and a compensation unit for compensating the node voltage of the output terminal of the buffer when at least one driving circuit of the plurality of driving circuits turns on or off.

Description

源極驅動器及其驅動電路Source driver and its driving circuit

本發明係指一種用於驅動一發光二極體面板之源極驅動器及其驅動電路，尤指一種可於驅動電路開啟或關閉時，減少電壓耦合對通道電流的影響，以減少通道電流變化及亮度變化之源極驅動器及其驅動電路。The present invention relates to a source driver for driving a light-emitting diode panel and a driving circuit thereof, especially to a source driver that can reduce the influence of voltage coupling on channel current when the driving circuit is turned on or off, so as to reduce channel current variation and A source driver and its driving circuit for changing brightness.

在發光二極體（Light-emitting diode，LED）驅動中，無源選址（Passive Matrix）驅動模式將陣列中每一欄（column）的發光二極體像素的陽極（P-electrode）連接到發光二極體源極驅動器的通道，同時將每一列（row）的發光二極體像素的陰極（N-electrode）連接到掃描線（Scan Line）透過掃描開關接地。當某一特定欄和特定列被導通的時候，其交叉點的發光二極體像素即會被點亮。In light-emitting diode (LED) driving, the passive matrix driving mode connects the anode (P-electrode) of each column of LED pixels in the array to the The channel of the light-emitting diode source driver simultaneously connects the cathode (N-electrode) of the light-emitting diode pixel of each row (row) to the scan line (Scan Line) through the scan switch to ground. When a specific column and a specific column are turned on, the light-emitting diode pixels at their intersections are lit.

然而，在發光二極體源極驅動器端通道開啟時會有兩種耦合路徑影響其他通道，而影響發光二極體像素的亮度。有鑑於此，習知技術實有改進之必要。However, when the light-emitting diode source driver side channel is turned on, there are two coupling paths that affect other channels, thereby affecting the brightness of the light-emitting diode pixel. In view of this, it is necessary to improve the prior art.

因此，本發明之主要目的即在於提供一種可於驅動電路開啟或關閉時，減少電壓耦合對通道電流的影響，以減少通道電流變化及亮度變化之源極驅動器及其驅動電路。Therefore, the main purpose of the present invention is to provide a source driver and its driving circuit which can reduce the influence of voltage coupling on channel current when the driving circuit is turned on or off, so as to reduce channel current variation and brightness variation.

本發明揭露一種源極驅動器，用於驅動一發光二極體面板，該源極驅動器包含有一緩衝器，包含一輸出端；複數個驅動電路，耦接於該緩衝器，該複數個驅動電路中各驅動電路包含有：一恆流電晶體，具有一閘極，該閘極由該緩衝器之該輸出端之一節點電壓所控制；以及一補償單元，用來於該複數個驅動電路中至少一驅動電路開啟或關閉時，補償該緩衝器之該輸出端之該節點電壓。The present invention discloses a source driver for driving a light-emitting diode panel, the source driver includes a buffer including an output end; a plurality of driving circuits are coupled to the buffer, among the plurality of driving circuits Each drive circuit includes: a constant current transistor with a gate, the gate is controlled by a node voltage of the output end of the buffer; and a compensation unit for at least one of the plurality of drive circuits When a driving circuit is turned on or off, the node voltage of the output end of the buffer is compensated.

本發明另揭露一種驅動電路，用於驅動一發光二極體面板之一源極驅動器，該驅動電路包含有一恆流電晶體，具有一閘極，該閘極由一緩衝器之一輸出端之一節點電壓所控制；以及一補償單元，用來於複數個驅動電路中至少一驅動電路開啟或關閉時，補償該緩衝器之該輸出端之該節點電壓。The present invention further discloses a driving circuit for driving a source driver of a light-emitting diode panel. The driving circuit includes a constant current transistor and has a gate, and the gate is connected by an output end of a buffer. A node voltage is controlled; and a compensation unit is used for compensating the node voltage of the output end of the buffer when at least one of the plurality of drive circuits is turned on or off.

請參考第1圖，第1圖為一無源選址（Passive Matrix）驅動發光二極體（Light-emitting diode，LED）面板10之示意圖。如第1圖所示，發光二極體面板10包含一源極驅動器102、一掃描電路104、通道C[1]~C[m]、掃描線S[1]~S[n]、掃描電容CS1 ~CSn 、發光二極體電容CLED11 ~CLEDmn 以及相對應發光二極體。源極驅動器102用來驅動通道C[1]~C[m]，而掃描電路104用來透過相對應開關將掃描線S[1]~S[n]接地，掃描電容CS1 ~CSn 使掃描線S[1]~S[n]未接地時不在發光二極體形成壓差，當掃描電路104將掃描線S[1]~S[n]中特定掃描線接地且源極驅動器102驅動通道C[1]~C[m]中特定通道時，即可導通交叉點的發光二極體。Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a passive matrix driving light-emitting diode (LED) panel 10 . As shown in FIG. 1, the light emitting diode panel 10 includes a source driver 102, a scan circuit 104, channels C[1]-C[m], scan lines S[1]-S[n], and scan capacitors C S1 ~C Sn , light-emitting diode capacitors C LED11 ~C LEDmn and corresponding light-emitting diodes. The source driver 102 is used to drive the channels C[1]-C[m], and the scan circuit 104 is used to ground the scan lines S[1]-S[n] through the corresponding switches, and the scan capacitors C S1 -C Sn make the scan lines S[1]-S[n] grounded. When the scan lines S[1]~S[n] are not grounded, no voltage difference is formed on the light-emitting diodes. When the scan circuit 104 grounds a specific scan line in the scan lines S[1]~S[n] and the source driver 102 drives When a specific channel is selected among channels C[1]~C[m], the light-emitting diodes at the intersections can be turned on.

舉例來說，當掃描電路104將掃描線S[1]接地且源極驅動器102驅動通道C[1]時，即可在發光二極體電容CLED11 形成跨壓導通相對應發光二極體。然而，源極驅動器102驅動通道C[1]時電壓變化藉由發光二極體燈板電容耦合路徑耦合其他未驅動而浮接（floating）的通道輸出（如透過節點(1)＞(2)＞(3) ＞(4)＞(5) 耦合通道C[2]），且此時掃描線S[1]接地，使得發光二極體電容CLED21 ~CLEDm1 的跨壓受影響，發光二極體導通電流因此受影響。如此一來，若同時開啟通道數量越多，發光二極體燈板電容耦合越強，跨壓受影響越大，電流變化越大，亮度變化越大。For example, when the scan circuit 104 grounds the scan line S[1] and the source driver 102 drives the channel C[1], the corresponding light-emitting diodes can be formed in the light-emitting diode capacitor C LED11 to be conductive across voltage. However, when the source driver 102 drives the channel C[1], the voltage change is coupled through the capacitive coupling path of the LED lamp panel to other undriven and floating channel outputs (eg, through the node (1)>(2) >(3) >(4)>(5) Coupling channel C[2]), and the scan line S[1] is grounded at this time, so that the cross-voltage of the light-emitting diode capacitors C LED21 ~C LEDm1 is affected, and the light-emitting diode capacitors C LED21 ~ C LEDm1 The pole body conduction current is thus affected. In this way, if more channels are turned on at the same time, the stronger the capacitive coupling of the light-emitting diode panel will be, the greater the impact on the cross voltage will be, the greater the current change will be, and the greater the brightness change will be.

另一方面，請參考第2圖，第2圖為第1圖所示之源極驅動器102之示意圖。如第2圖所示，一緩衝器200之一輸出端之一節點電壓VB控制驅動電路DC[1]~DC[m]以對通道C[1]~C[m]進行驅動。舉例來說，在驅動電路DC[1]中，一脈衝寬度調變（Pulse Width Modulation，PWM）電路202根據一脈衝寬度調變訊號控制一脈衝寬度調變電晶體MPWM之開啟或關閉，以開啟或關閉通道C[1]，由脈衝寬度調變訊號的脈衝寬度及一恆流電晶體MPS（恆流電流源）所提供穩定通道電流大小決定發光亮度。當脈衝寬度調變電晶體MPWM關閉時，一節點電壓VN[1]會瞬間上升至一系統電壓VDD或脈衝寬度調變電晶體MPWM開啟時一放大器204進行負回授節點電壓VN[1]會瞬間下拉至一參考電壓VREF，進而透過恆流電晶體MPS的一寄生電容CGD 干擾恆流電晶體MPS閘極之節點電壓VB。在此情況下，因通道電流會受其他通道的動作影響，同時動作通道數量越多，耦合越強，恆流電流源受影響越大，通道電流變化大，亮度變化越大。On the other hand, please refer to FIG. 2 , which is a schematic diagram of the source driver 102 shown in FIG. 1 . As shown in FIG. 2, a node voltage VB of an output terminal of a buffer 200 controls the driving circuits DC[1]-DC[m] to drive the channels C[1]-C[m]. For example, in the driving circuit DC[1], a Pulse Width Modulation (PWM) circuit 202 controls a PWM transistor MPWM to be turned on or off according to a PWM signal to turn on Or close the channel C[1], and the luminous brightness is determined by the pulse width of the PWM signal and the stable channel current provided by a constant current transistor MPS (constant current source). When the pulse width modulation transistor MPWM is turned off, a node voltage VN[1] will instantly rise to a system voltage VDD or when the pulse width modulation transistor MPWM is turned on, an amplifier 204 performs negative feedback and the node voltage VN[1] will be Instantly pull down to a reference voltage VREF, and then disturb the node voltage VB of the gate of the constant current transistor MPS through a parasitic capacitance C GD of the constant current transistor MPS. In this case, the channel current will be affected by the actions of other channels. At the same time, the greater the number of active channels, the stronger the coupling, the greater the impact of the constant current source, the greater the channel current change, and the greater the brightness change.

舉例而言，請參考第3圖，第3圖為第2圖所示之源極驅動器102之操作示意圖。如第3圖上半所示，以掃描線S[1]導通為例，當僅有通道C[1]開啟時，脈衝寬度調變電晶體MPWM導通，節點電壓VN[1]下拉至參考電壓VREF，節點電壓VB被些微向下耦合，一通道電流IC[1] 瞬時電流僅些微增加。另一方面，如第3圖下半所示，通道C[1]~C[m]全部同時開啟時，節點電壓VB被嚴重向下耦合，通道電流IC[1] ~IC[m] 瞬時電流皆大幅上升，再加上第1圖所示之燈板電容路徑耦合，電流將大幅增加，使亮度發生變化。For example, please refer to FIG. 3 , which is a schematic diagram of the operation of the source driver 102 shown in FIG. 2 . As shown in the upper half of Figure 3, taking the scan line S[1] as an example, when only the channel C[1] is turned on, the pulse width modulation transistor MPWM is turned on, and the node voltage VN[1] is pulled down to the reference voltage VREF, the node voltage VB is coupled down slightly, a channel current I C[1] instantaneous current increases only slightly. On the other hand, as shown in the lower half of Figure 3, when all channels C[1]~C[m] are turned on at the same time, the node voltage VB is severely coupled downward, and the channel currents I C[1] ~I C[m] Instantaneous currents all rise sharply, coupled with the capacitive path coupling of the lamp panel as shown in Figure 1, the current will increase sharply, resulting in changes in brightness.

另一方面，請參考第4圖，第4圖為第2圖所示之源極驅動器102之另一操作示意圖。如第4圖上半所示，以掃描線S[1]導通為例，通道C[1]~C[m-1]維持開啟，通道C[m]關閉且相對應脈衝寬度調變電晶體MPWM關閉，節點電壓VN[m]上升至系統電壓VDD，節點電壓VB被向上耦合，通道電流IC[1] ~IC[m-1] 瞬時電流些微減少。另一方面，如第4圖下半所示，通道C[1]維持開啟，通道C[2]~C[m]關閉，節點電壓VB被嚴重向上耦合，通道電流IC[1] 瞬時電流大幅衰減，使亮度發生變化。On the other hand, please refer to FIG. 4 , which is another schematic diagram of the operation of the source driver 102 shown in FIG. 2 . As shown in the upper half of Figure 4, taking the scan line S[1] as an example, the channels C[1]~C[m-1] remain open, the channel C[m] is closed and the corresponding PWM transistor The MPWM is turned off, the node voltage VN[m] rises to the system voltage VDD, the node voltage VB is coupled up, and the channel currents I C[1] ~ I C[m-1] are slightly reduced instantaneously. On the other hand, as shown in the lower half of Figure 4, channel C[1] remains on, channels C[2]~C[m] are off, node voltage VB is severely coupled upward, and channel current I C[1] instantaneous current Attenuates drastically, causing changes in brightness.

相較之下，請參考第5圖，第5圖為本發明實施例一源極驅動器502之示意圖，源極驅動器502可取代第2圖所示之源極驅動器102用於第1圖所示之源極驅動器102。源極驅動器502與源極驅動器102大致相似，因此功能與結構相似之元件以相同符號表示，源極驅動器502與源極驅動器102之主要差別在於，源極驅動器502中各驅動電路DC[1]~DC[m]另包含一補償單元504，用來於至少一驅動電路開啟或關閉時，補償緩衝器200之輸出端之節點電壓VB。具體而言，補償單元504於至少一驅動電路開啟時，抬升緩衝器200之輸出端之節點電壓VB，於至少一驅動電路關閉時，降低緩衝器200之輸出端之節點電壓VB。舉例來說，驅動電路DC[1]中補償單元504可包含補償電路IP[1] 、IN[1] 分別用來抬升及降低節點電壓VB，於第5圖中繪示補償電路IP[1] 、IN[1] 為電流源。此外，補償單元504可針對相對應驅動電路開啟或關閉對補償相對應恆流電晶體MPS之閘極之節點電壓VB，但亦可針對其它驅動電路開啟或關閉對補償相對應恆流電晶體MPS之閘極之節點電壓VB。In contrast, please refer to FIG. 5. FIG. 5 is a schematic diagram of a source driver 502 according to an embodiment of the present invention. The source driver 502 can be used in the source driver 102 shown in FIG. 1 instead of the source driver 102 shown in FIG. 2. the source driver 102 . The source driver 502 is roughly similar to the source driver 102, so the components with similar functions and structures are represented by the same symbols. The main difference between the source driver 502 and the source driver 102 is that each driving circuit in the source driver 502 ~DC[m] further includes a compensation unit 504 for compensating the node voltage VB of the output end of the buffer 200 when at least one driving circuit is turned on or off. Specifically, the compensation unit 504 boosts the node voltage VB of the output end of the buffer 200 when at least one driving circuit is turned on, and lowers the node voltage VB of the output end of the buffer 200 when the at least one driving circuit is turned off. For example, the compensation unit 504 in the driving circuit DC[1] may include compensation circuits IP[1] and IN[1] for raising and lowering the node voltage VB respectively. The compensation circuit IP is shown in FIG. 5 . [1] and I N[1] are current sources. In addition, the compensation unit 504 can be turned on or off for the corresponding driving circuit to compensate the node voltage VB of the gate of the corresponding constant current transistor MPS, but can also be turned on or off for other driving circuits to compensate the corresponding constant current transistor MPS The node voltage VB of the gate.

詳細來說，請參考第6圖，第6圖為第5圖所示之源極驅動器502之操作示意圖。如第6圖所示，通道C[1]~C[m]全部同時開啟時（即於至少一驅動電路及相對應通道開啟時），補償電路IP[1] ~IP[m] 與通道同步輸出，可調整補償電路IP[1] ~IP[m] 輸出時間長度，以抬升節點電壓VB補償受節點電壓VN[1]~VN[m]耦合後降低的電壓（相較於第3圖下半，本發明實施例可將節點電壓VB變化由虛線降低至實線，以將通道電流IC[1] ~IC[m] 變化由虛線降低至實線）。須注意，若開啟的通道越多，來自燈板電容路徑的耦合越強，但同時多通道的補償電路IP[1] ~IP[m] 對節點電壓VB的補償量也越多，因此可相互補償，以減少通道電流變化及亮度變化。For details, please refer to FIG. 6 , which is a schematic diagram of the operation of the source driver 502 shown in FIG. 5 . As shown in Figure 6, when all channels C[1]~C[m] are turned on at the same time (that is, when at least one driver circuit and the corresponding channel are turned on), the compensation circuits IP[1] ~ IP[m] and Channel synchronization output, the output time length of the compensation circuit I P[1] ~ IP[m] can be adjusted to raise the node voltage VB to compensate for the reduced voltage after being coupled by the node voltages VN[1]~VN[m] (compared to In the lower half of Fig. 3, the embodiment of the present invention can reduce the change of the node voltage VB from the dotted line to the solid line, so as to reduce the change of the channel currents I C[1] ~ I C[m] from the dotted line to the solid line). It should be noted that the more channels are turned on, the stronger the coupling from the capacitor path of the lamp panel will be, but at the same time the multi-channel compensation circuits IP[1] ~ IP[m] will compensate the node voltage VB more, so Compensate each other to reduce channel current variation and brightness variation.

另一方面，請參考第7圖，第7圖為第5圖所示之源極驅動器502之另一操作示意圖。如第7圖所示，通道C[1]維持開啟而通道C[2]~C[m]關閉時（即於至少一驅動電路及相對應通道關閉時），補償電路IN[2] ~IN[m] 在通道關閉後輸出，可調整補償電路IN[2] ~IN[m] 輸出時間長度，以降低節點電壓VB受節點電壓VN[2]~VN[m]耦合後抬升的電壓（相較於第4圖下半，本發明實施例可將節點電壓VB變化由虛線降低至實線，以將通道電流IC[1] 變化由虛線降低至實線）。須注意，若關閉的通道越多，來自燈板電容路徑的耦合越強，但同時多通道的補償電路IN[2] ~IN[m] 對節點電壓VB的補償量也越多，因此可相互補償，以減少通道電流變化及亮度變化。On the other hand, please refer to FIG. 7 , which is another schematic diagram of the operation of the source driver 502 shown in FIG. 5 . As shown in Fig. 7, when channel C[1] remains on and channels C[2]~C[m] are off (that is, when at least one driver circuit and the corresponding channel are off), the compensation circuit I N[2] ~ I N[m] is output after the channel is turned off, and the output time length of the compensation circuit I N[2] ~I N[m] can be adjusted to reduce the node voltage VB and increase after being coupled by the node voltage VN[2]~VN[m] (compared to the lower half of FIG. 4, the embodiment of the present invention can reduce the change of the node voltage VB from the dotted line to the solid line, so as to reduce the change of the channel current IC [1] from the dotted line to the solid line). It should be noted that the more channels are closed, the stronger the coupling from the capacitor path of the lamp panel is, but at the same time, the compensation amount of the multi-channel compensation circuit I N[2] ~ IN[m] to the node voltage VB is also more. Therefore, Compensate each other to reduce channel current variation and brightness variation.

值得注意的是，本發明實施例於至少一驅動電路開啟或關閉時，補償緩衝器200之輸出端之節點電壓VB，以減少電壓耦合對通道電流的影響，以減少通道電流變化及亮度變化。本領域具通常知識者當可據以進行修飾或變化，而不限於此。舉例來說，於第5圖中繪示補償電路IP[1] 、IN[1] 為電流源，但補償電路IP[1] 、IN[1] 可以金屬氧化半導體場效電晶體開關、二極體、源極隨耦器、運算放大器、電流源等電路以上任一者來實現。It is worth noting that the embodiment of the present invention compensates the node voltage VB of the output end of the buffer 200 when the at least one driving circuit is turned on or off, so as to reduce the influence of voltage coupling on the channel current, thereby reducing the channel current variation and brightness variation. Those with ordinary knowledge in the art can make modifications or changes accordingly, but are not limited to this. For example, the compensation circuits IP[1] and IN[1] are shown as current sources in FIG. 5, but the compensation circuits IP[1] and IN[1] can be MOSFETs Switches, diodes, source-followers, operational amplifiers, current sources and other circuits can be implemented by any of the above circuits.

另一方面，補償單元亦可包含其它元件。舉例來說，請參考第8圖，第8圖為本發明實施例一源極驅動器802之操作示意圖，源極驅動器802可取代第2圖所示之源極驅動器102用於第1圖所示之源極驅動器102。源極驅動器802與源極驅動器502大致相似，因此功能與結構相似之元件以相同符號表示，源極驅動器802與源極驅動器502之主要差別在於，源極驅動器802中各驅動電路DC[1]~DC[m]所包含之一補償單元804另包含一電阻RVB 耦接於緩衝器200之輸出端與恆流電晶體MPS之閘極之間，以大量降低則來自節點電壓VN對節點電壓VB的耦合（此電阻RVB 可具有電阻電容濾波器（RC filter）之作用，隔離節點電壓VN對節點電壓VB的耦合），減少通道開啟或關閉時電壓耦合對其他通道的影響。在此情況下，相較於第3圖下半，如第8圖右上方所示，本發明實施例可將節點電壓VB變化由虛線降低至實線（較第6圖之實線變化更小），以將通道電流IC[1] ~IC[m] 變化由虛線降低至實線（較第6圖之實線變化更小），以進一步減少亮度變化。此外，相較於第4圖下半，如第8圖右下方所示，本發明實施例可將節點電壓VB變化由虛線降低至實線（較第7圖之實線變化更小），以將通道電流IC[1] 變化由虛線降低至實線（較第7圖之實線變化更小），以進一步減少亮度變化。On the other hand, the compensation unit may also include other elements. For example, please refer to FIG. 8. FIG. 8 is a schematic diagram of the operation of a source driver 802 according to an embodiment of the present invention. The source driver 802 can be used as the source driver 102 shown in FIG. 1 instead of the source driver 102 shown in FIG. 2. the source driver 102 . The source driver 802 is roughly similar to the source driver 502, so the components with similar functions and structures are represented by the same symbols. The main difference between the source driver 802 and the source driver 502 is that each driver circuit in the source driver 802 A compensation unit 804 included in ~DC[m] further includes a resistor R VB coupled between the output end of the buffer 200 and the gate of the constant current transistor MPS, to greatly reduce the voltage from the node VN to the node voltage Coupling of VB (this resistor R VB can function as a resistor-capacitor filter (RC filter) to isolate the coupling of node voltage VN to node voltage VB) to reduce the influence of voltage coupling on other channels when the channel is turned on or off. In this case, compared with the lower half of Fig. 3, as shown in the upper right of Fig. 8, the embodiment of the present invention can reduce the change of the node voltage VB from the dotted line to the solid line (the change is smaller than that of the solid line in Fig. 6). ) to reduce the change of the channel current I C[1] ~ I C[m] from the dotted line to the solid line (smaller change than the solid line in Figure 6) to further reduce the brightness change. In addition, compared with the lower half of Fig. 4, as shown in the lower right of Fig. 8, the embodiment of the present invention can reduce the change of the node voltage VB from the dotted line to the solid line (the change is smaller than that of the solid line in Fig. 7), so as to The channel current IC [1] change is reduced from the dashed line to the solid line (smaller change than the solid line in Figure 7) to further reduce the brightness change.

另一方面，脈衝寬度調變電路202可以任意形式實現。舉例來說，請參考第9圖，第9圖為本發明實施例一驅動電路DC之操作示意圖，驅動電路DC可為第8圖所示驅動電路DC[1]~DC[m]中任一者。如第9圖所示，脈衝寬度調變電路202根據一脈衝寬度調變訊號PWM控制一脈衝寬度調變電晶體MPWM之開啟或關閉。脈衝寬度調變電路202透過一反相器接收脈衝寬度調變訊號PWM產生一反向訊號，以及一開關耦接於系統電壓VDD與脈衝寬度調變電晶體MPWM之閘極之間，用來受該反向訊號控制，於脈衝寬度調變訊號PWM為低準位時，控制脈衝寬度調變電晶體MPWM之閘極為高準位（系統電壓VDD）而關閉。脈衝寬度調變電路202透過另一開關耦接於放大器204之一輸出端與脈衝寬度調變電晶體MPWM之一閘極之間，用來受脈衝寬度調變訊號PWM控制，以於脈衝寬度調變訊號PWM為一高準位時，形成一負回授將脈衝寬度調變電晶體PWM之一源極電壓（即一節點電壓VN）固定在一參考電壓VREF。於脈衝寬度調變訊號PWM由低準位切換至高準位時，一控制訊號PR控制一補償電路IP （提供電流）抬升節點電壓VB進行補償，於脈衝寬度調變訊號PWM由高準位切換至低準位時，一控制訊號PF控制一補償電路IN （汲取電流）降低節點電壓VB進行補償，其餘操作可參考以上敘述，於此不再贅述。On the other hand, the pulse width modulation circuit 202 can be implemented in any form. For example, please refer to FIG. 9, which is a schematic diagram of the operation of a driving circuit DC according to an embodiment of the present invention, and the driving circuit DC can be any one of the driving circuits DC[1]~DC[m] shown in FIG. 8 By. As shown in FIG. 9, the pulse width modulation circuit 202 controls a pulse width modulation transistor MPWM to be turned on or off according to a pulse width modulation signal PWM. The pulse width modulation circuit 202 receives the pulse width modulation signal PWM through an inverter to generate an inversion signal, and a switch is coupled between the system voltage VDD and the gate of the pulse width modulation transistor MPWM for use in Controlled by the reverse signal, when the pulse width modulation signal PWM is at a low level, the gate of the control pulse width modulation transistor MPWM is at a high level (system voltage VDD) and is turned off. The pulse width modulation circuit 202 is coupled between an output terminal of the amplifier 204 and a gate of the pulse width modulation transistor MPWM through another switch, and is used for being controlled by the pulse width modulation signal PWM, so that the pulse width When the modulation signal PWM is at a high level, a negative feedback is formed to fix a source voltage (ie, a node voltage VN) of the pulse width modulation transistor PWM to a reference voltage VREF. When the pulse width modulation signal PWM is switched from a low level to a high level, a control signal PR controls a compensation circuit IP (supplying current) to raise the node voltage VB for compensation, and when the pulse width modulation signal PWM is switched from a high level When the level is low, a control signal PF controls a compensation circuit I N (current sink) to reduce the node voltage VB for compensation. The rest of the operations can be referred to the above description, which will not be repeated here.

綜上所述，本發明於至少一驅動電路開啟或關閉時，補償緩衝器之輸出端之節點電壓，以減少電壓耦合對通道電流的影響，進而減少通道電流變化及亮度變化。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。To sum up, the present invention compensates the node voltage of the output end of the buffer when at least one driving circuit is turned on or off, so as to reduce the influence of voltage coupling on the channel current, thereby reducing the channel current variation and brightness variation. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10:發光二極體面板 102, 502:源極驅動器 104:掃描電路 200:緩衝器 202:脈衝寬度調變電路 204:放大器 504:補償單元 C[1]~C[m]:通道 S[1]~S[n]:掃描線 CS1 ~CSn :掃描電容 CLED11 ~CLEDmn :發光二極體電容 (1)~(5): 節點 VB, VN, VN[1]~VN[m]:節點電壓 DC[1]~DC[m],DC:驅動電路 CGD :寄生電容 MPWM: 脈衝寬度調變電晶體 MPS:恆流電晶體 VDD:系統電壓 VREF:參考電壓 IC[1] ~IC[m] ,IC :通道電流 IP[1] ~IP[m] ,IN[1] ~IN[m] ,IP ,IN: 補償電路 RVB :電阻 PR,PF:控制訊號 PWM:脈衝寬度調變訊號10: LED panels 102, 502: Source driver 104: Scanning circuit 200: Buffer 202: PWM circuit 204: Amplifier 504: Compensation unit C[1]~C[m]: Channel S[ 1]~S[n]: Scanning line C S1 ~C Sn : Scanning capacitance C LED11 ~C LEDmn : Light emitting diode capacitance (1)~(5) : Node VB, VN, VN[1]~VN[m ]: node voltage DC[1]~DC[m], DC: drive circuit C GD : parasitic capacitance MPWM : pulse width modulation transistor MPS: constant current transistor VDD: system voltage VREF: reference voltage I C[1] ~I C[m] , I C : channel current I P[1] ~I P[m] , I N[1] ~I N[m] , I P , I N: compensation circuit R VB : resistance PR, PF: Control signal PWM: Pulse width modulation signal

第1圖為一無源選址驅動發光二極體面板之示意圖。 第2圖為第1圖所示之一源極驅動器之示意圖。 第3圖為第2圖所示之源極驅動器之操作示意圖。 第4圖為第2圖所示之源極驅動器之另一操作示意圖。 第5圖為本發明實施例一源極驅動器之示意圖。 第6圖為第5圖所示之源極驅動器操作示意圖。 第7圖為第5圖所示之源極驅動器之另一操作示意圖。 第8圖為本發明實施例另一源極驅動器之操作示意圖。 第9圖為本發明實施例另一驅動電路之操作示意圖。FIG. 1 is a schematic diagram of a passive address-driven LED panel. FIG. 2 is a schematic diagram of a source driver shown in FIG. 1 . FIG. 3 is a schematic diagram of the operation of the source driver shown in FIG. 2 . FIG. 4 is another schematic diagram of the operation of the source driver shown in FIG. 2 . FIG. 5 is a schematic diagram of a source driver according to an embodiment of the present invention. FIG. 6 is a schematic diagram of the operation of the source driver shown in FIG. 5 . FIG. 7 is another schematic diagram of the operation of the source driver shown in FIG. 5 . FIG. 8 is a schematic diagram of the operation of another source driver according to an embodiment of the present invention. FIG. 9 is a schematic diagram of the operation of another driving circuit according to an embodiment of the present invention.

502:源極驅動器502: Source driver

200:緩衝器200: Buffer

202:脈衝寬度調變電路202: Pulse width modulation circuit

204:放大器204: Amplifier

504:補償單元504: Compensation unit

C[1]~C[m]:通道C[1]~C[m]: Channel

VB,VN[1]~VN[m]:節點電壓VB, VN[1]~VN[m]: node voltage

DC[1]~DC[m]:驅動電路DC[1]~DC[m]: drive circuit

CGD :寄生電容C GD : Parasitic capacitance

MPWM:脈衝寬度調變電晶體MPWM: Pulse Width Modulation Transistor

MPS:恆流電晶體MPS: constant current transistor

VDD:系統電壓VDD: system voltage

VREF:參考電壓VREF: reference voltage

IP[1] ~IP[m] ,IN[1] ~IN[m] :補償電路I P[1] ~I P[m] , IN[1] ~ IN[m] : compensation circuit

Claims (23)

一種源極驅動器，用於驅動一發光二極體（Light-emitting diode，LED）面板，包含有： 一緩衝器，包含一輸出端；以及 複數個驅動電路，耦接於該緩衝器，該複數個驅動電路中各驅動電路包含有： 一恆流電晶體，具有一閘極，該閘極由該緩衝器之該輸出端之一節點電壓所控制；以及 一補償單元，用於補償該緩衝器之該輸出端之該節點電壓。A source driver for driving a light-emitting diode (Light-emitting diode, LED) panel, comprising: a buffer including an output; and A plurality of driving circuits are coupled to the buffer, and each driving circuit in the plurality of driving circuits includes: a constant current transistor having a gate controlled by a node voltage of the output terminal of the buffer; and a compensation unit for compensating the node voltage of the output end of the buffer. 如請求項1所述之源極驅動器，其中該補償單元於該複數個驅動電路中該至少一驅動電路開啟時，抬升該緩衝器之該輸出端之該節點電壓。The source driver as claimed in claim 1, wherein the compensation unit boosts the node voltage of the output end of the buffer when the at least one driver circuit among the plurality of driver circuits is turned on. 如請求項1所述之源極驅動器，其中該補償單元於該複數個驅動電路中該至少一驅動電路關閉時，降低該緩衝器之該輸出端之該節點電壓。The source driver as claimed in claim 1, wherein the compensation unit reduces the node voltage of the output end of the buffer when the at least one driver circuit among the plurality of driver circuits is turned off. 如請求項1所述之源極驅動器，其中該補償單元包含有： 一第一補償電路，用來於該複數個驅動電路中該至少一驅動電路開啟時，抬升該緩衝器之該輸出端之該節點電壓；以及 一第二補償電路，用來於該複數個驅動電路中該至少一驅動電路關閉時，降低該緩衝器之該輸出端之該節點電壓。The source driver as claimed in claim 1, wherein the compensation unit comprises: a first compensation circuit for raising the node voltage of the output end of the buffer when the at least one driving circuit among the plurality of driving circuits is turned on; and A second compensation circuit is used for reducing the node voltage of the output end of the buffer when the at least one driving circuit among the plurality of driving circuits is turned off. 如請求項4所述之源極驅動器，其中該第一補償電路及該第二補償電路中一者包含有一金屬氧化半導體場效電晶體開關、一二極體、一源極隨耦器、一運算放大器或一電流源以上任一者來實現。The source driver of claim 4, wherein one of the first compensation circuit and the second compensation circuit includes a metal oxide semiconductor field effect transistor switch, a diode, a source follower, a Either an operational amplifier or a current source is implemented. 如請求項1所述之源極驅動器，其中該補償單元於該各驅動電路開啟或關閉時，補償該緩衝器之該輸出端之該節點電壓。The source driver of claim 1, wherein the compensation unit compensates the node voltage of the output end of the buffer when the driving circuits are turned on or off. 如請求項1所述之源極驅動器，其中該複數個驅動電路中開啟或關閉之驅動電路之數量愈多，該複數個驅動電路中進行補償之補償單元之補償量愈多。The source driver according to claim 1, wherein the greater the number of the driving circuits that are turned on or off in the plurality of driving circuits, the greater the compensation amount of the compensation unit that performs compensation in the plurality of driving circuits. 如請求項1所述之源極驅動器，其中該補償單元另包含一電阻耦接於該緩衝器之該輸出端與該恆流電晶體之該閘極之間。The source driver of claim 1, wherein the compensation unit further comprises a resistor coupled between the output end of the buffer and the gate of the constant current transistor. 如請求項1所述之源極驅動器，其中各驅動電路另包含有一脈衝寬度調變電路，用來根據一脈衝寬度調變訊號控制一脈衝寬度調變電晶體之開啟或關閉。The source driver according to claim 1, wherein each driving circuit further comprises a pulse width modulation circuit for controlling a pulse width modulation transistor to be turned on or off according to a pulse width modulation signal. 如請求項9所述之源極驅動器，其中該脈衝寬度調變電路包含有： 一反相器，用來接收該脈衝寬度調變訊號，以產生一反向訊號：以及 一第一開關，耦接於一系統電壓與該脈衝寬度調變電晶體之一閘極之間，用來受該反向訊號控制，以於該脈衝寬度調變訊號為一低準位時，控制該脈衝寬度調變電晶體之一閘極為一高準位而關閉。The source driver of claim 9, wherein the pulse width modulation circuit comprises: an inverter for receiving the PWM signal to generate an inverted signal: and A first switch, coupled between a system voltage and a gate of the PWM transistor, is controlled by the reverse signal, so that when the PWM signal is at a low level, A gate of the pulse width modulation transistor is controlled to be closed at a high level. 如請求項9所述之源極驅動器，其中該脈衝寬度調變電路包含有： 一第二開關，耦接一放大器之一輸出端與該脈衝寬度調變電晶體之一閘極之間，用來受該脈衝寬度調變訊號控制，以於該脈衝寬度調變訊號為一高準位時，形成一負回授將該脈衝寬度調變電晶體之一源極電壓固定在一參考電壓。The source driver of claim 9, wherein the pulse width modulation circuit comprises: A second switch, coupled between an output terminal of an amplifier and a gate of the PWM transistor, is controlled by the PWM signal so that the PWM signal is at a high level At the level, a negative feedback is formed to fix a source voltage of the PWM transistor to a reference voltage. 如請求項9所述之源極驅動器，其中於該脈衝寬度調變訊號由一低準位切換至一高準位時，一第一控制訊號控制一第一補償電路抬升該緩衝器之該輸出端之該節點電壓，而於該脈衝寬度調變訊號由該高準位切換至該低準位時，一第二控制訊號控制一第二補償電路降低該緩衝器之該輸出端之該節點電壓。The source driver of claim 9, wherein when the PWM signal is switched from a low level to a high level, a first control signal controls a first compensation circuit to boost the output of the buffer The node voltage of the terminal, and when the PWM signal is switched from the high level to the low level, a second control signal controls a second compensation circuit to reduce the node voltage of the output terminal of the buffer . 一種驅動電路，用於驅動一發光二極體（Light-emitting diode，LED）面板之一源極驅動器，包含有： 一恆流電晶體，具有一閘極，該閘極由一緩衝器之一輸出端之一節點電壓所控制；以及 一補償單元，用於補償該緩衝器之該輸出端之該節點電壓。A driving circuit for driving a source driver of a light-emitting diode (Light-emitting diode, LED) panel, comprising: a constant current transistor having a gate controlled by a node voltage of an output terminal of a buffer; and a compensation unit for compensating the node voltage of the output end of the buffer. 如請求項13所述之驅動電路，其中該補償單元於該驅動電路開啟時，抬升該緩衝器之該輸出端之該節點電壓。The driving circuit of claim 13, wherein the compensation unit boosts the node voltage of the output end of the buffer when the driving circuit is turned on. 如請求項13所述之驅動電路，其中該補償單元於該驅動電路關閉時，降低該緩衝器之該輸出端之該節點電壓。The driving circuit of claim 13, wherein the compensation unit reduces the node voltage of the output end of the buffer when the driving circuit is turned off. 如請求項13所述之驅動電路，其中該補償單元包含有： 一第一補償電路，用來於該驅動電路開啟時，抬升該緩衝器之該輸出端之該節點電壓；以及 一第二補償電路，用來於該驅動電路關閉時，降低該緩衝器之該輸出端之該節點電壓。The driving circuit of claim 13, wherein the compensation unit comprises: a first compensation circuit for raising the node voltage of the output end of the buffer when the driving circuit is turned on; and A second compensation circuit is used for reducing the node voltage of the output end of the buffer when the driving circuit is turned off. 如請求項16所述之驅動電路，其中該第一補償電路及該第二補償電路中一者包含有一金屬氧化半導體場效電晶體開關、一二極體、一源極隨耦器、一運算放大器或一電流源以上任一者來實現。The driving circuit of claim 16, wherein one of the first compensation circuit and the second compensation circuit comprises a MOSFET switch, a diode, a source follower, an arithmetic Either an amplifier or a current source. 如請求項13所述之驅動電路，其中該補償單元於該驅動電路開啟或關閉時，補償該緩衝器之該輸出端之該節點電壓。The driving circuit of claim 13, wherein the compensation unit compensates the node voltage of the output end of the buffer when the driving circuit is turned on or off. 如請求項13所述之驅動電路，其中該補償單元另包含一電阻耦接於該緩衝器之該輸出端與該恆流電晶體之該閘極之間。The driving circuit of claim 13, wherein the compensation unit further comprises a resistor coupled between the output end of the buffer and the gate of the constant current transistor. 如請求項13所述之驅動電路，其另包含有一脈衝寬度調變電路，用來根據一脈衝寬度調變訊號控制一脈衝寬度調變電晶體之開啟或關閉。The driving circuit of claim 13, further comprising a pulse width modulation circuit for controlling a pulse width modulation transistor to be turned on or off according to a pulse width modulation signal. 如請求項20所述之驅動電路，其中該脈衝寬度調變電路包含有： 一反相器，用來接收該脈衝寬度調變訊號，以產生一反向訊號：以及 一第一開關，耦接於一系統電壓與該脈衝寬度調變電晶體之一閘極之間，用來受該反向訊號控制，以於該脈衝寬度調變訊號為一低準位時，控制該脈衝寬度調變電晶體之一閘極為一高準位而關閉。The driving circuit of claim 20, wherein the pulse width modulation circuit comprises: an inverter for receiving the PWM signal to generate an inverted signal: and A first switch, coupled between a system voltage and a gate of the PWM transistor, is controlled by the reverse signal, so that when the PWM signal is at a low level, A gate of the pulse width modulation transistor is controlled to be closed at a high level. 如請求項20所述之驅動電路，其中該脈衝寬度調變電路包含有： 一第二開關，耦接一放大器之一輸出端與該脈衝寬度調變電晶體之一閘極之間，用來受該脈衝寬度調變訊號控制，以於該脈衝寬度調變訊號為一高準位時，形成一負回授將該脈衝寬度調變電晶體之一源極電壓固定在一參考電壓。The driving circuit of claim 20, wherein the pulse width modulation circuit comprises: A second switch, coupled between an output terminal of an amplifier and a gate of the PWM transistor, is controlled by the PWM signal so that the PWM signal is at a high level At the level, a negative feedback is formed to fix a source voltage of the PWM transistor to a reference voltage. 如請求項20所述之驅動電路，其中於該脈衝寬度調變訊號由一低準位切換至一高準位時，一第一控制訊號控制一第一補償電路抬升該緩衝器之該輸出端之該節點電壓，而於該脈衝寬度調變訊號由該高準位切換至該低準位時，一第二控制訊號控制一第二補償電路降低該緩衝器之該輸出端之該節點電壓。The driving circuit of claim 20, wherein when the PWM signal is switched from a low level to a high level, a first control signal controls a first compensation circuit to raise the output end of the buffer the node voltage, and when the pulse width modulation signal is switched from the high level to the low level, a second control signal controls a second compensation circuit to reduce the node voltage of the output end of the buffer.
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